Size-Efficient Mitigation of Latch-Up and Latch-Up Propagation

Abstract

The set of transistor elements includes a substrate of a first doping type, and a first well and a second well, both of a second doping type and both formed on the substrate. The set of transistor elements also includes a first complementary transistor cell and a second complementary transistor cell. The set of transistor elements also includes an anti-propagation region of the first doping type between the first well and the second well.

Description

[Technical field]

[0001] The present invention relates to semiconductor structures, and more particularly to preventing and mitigating latch-up in semiconductor structures. [Background technology]

[0002] Semiconductor structures such as complementary metal oxide semiconductor cells are often fabricated in series within electronic devices such as processor chips. A typical metal oxide semiconductor device contains regions of silicon that are doped with either electron donor or electron acceptor elements to make the silicon electrically active. These semiconductors usually contain two regions, where a region doped with the same type of doping element is surrounded by a region doped with the opposite doping element.

[0003] Semiconductor devices are often paired with complementary semiconductor devices (i.e., devices with regions doped with the opposite element) to form complementary semiconductor cells. These cells can be patterned in series within an electronic device. The number of cells within a device can vary widely depending on the design of the device, but typically the cells within a series are patterned closely together to conserve space across the device (e.g., to reduce the overall size of the chip containing the cells).

[0004] However, when semiconductor cells are patterned in close proximity, the conductors of a first cell can interact with the complementary conductors of a neighboring cell, creating an unintended connection. One type of such connection is called latch-up. Latch-up can occur when a low impedance path between a power supply voltage source (i.e., VDD) and a ground source is formed between doped regions of a semiconductor cell. Such a path can be formed when current carriers (typically called electrons and holes) migrate (e.g., leak) from a region connected to their source, through the wells and substrate in which they are buried, to an adjacent region, and then migrate through this adjacent region.

[0005] Once latch-up occurs in a single cell, it can propagate to neighboring cells, potentially disrupting the functioning of many cells over time and causing irreversible damage from overcurrents.

[0006] Several design elements exist to address latch-up susceptibility and prevent its propagation once it has occurred. However, these solutions consume space within the semiconductor traces and can adversely increase the overall size of the electronic device. Therefore, the benefits of these solutions are often weighed against the cost of device size and other space-increasing considerations. For this reason, designs that are less susceptible to latch-up and latch-up propagation, while still being space-efficient, would be beneficial. Summary of the Invention

[0007] Some embodiments of the present disclosure can be exemplified as a set of transistor elements including a substrate of a first doping type. The set of transistor elements also includes a first well of a second doping type formed on the substrate. The set of transistor elements also includes a second well of a second doping type formed on the substrate. The set of transistor elements also includes a first plane parallel to and intersecting the first and second wells. The set of transistor elements also includes a second plane parallel to the first and second wells but not intersecting the first or second wells. The set of transistor elements also includes a first complementary transistor cell intersecting the first plane and a second complementary transistor cell intersecting the first plane. The set of transistor elements also includes an anti-propagation region of the first doping type intersecting the first plane between the first well and the second well.

[0008] Some embodiments of the present disclosure may be described as a set of transistor elements as described above, but further include a tap cell intersecting the first plane between the first complementary transistor cell and the anti-propagation region.

[0009] Some embodiments of the present disclosure, which may also be exemplified as the set of transistor elements described above, further include a first minority collector region of a first doping type formed on the first well and intersecting the first plane between the first complementary transistor cell and the anti-propagation region.

[0010] Some embodiments of the present disclosure may be exemplified as a set of transistor elements as described above, but further include a minority collector of a second doping type formed in the anti-propagation region.

[0011] Some embodiments of the present disclosure may also be exemplified as a set of transistor elements as described above, but further include a clamp contact located on the substrate and intersecting the second plane between the first well and the second well.

[0012] Some embodiments of the present disclosure may be exemplified as a set of transistor elements as described above, but further including a second anti-propagation region of a second doping type formed on the substrate and intersecting the second plane.

[0013] Some embodiments of the present disclosure may also be exemplified as a set of transistor elements including a substrate of a first doping type. The set of transistor elements also includes a well of a second doping type formed on the substrate. The set of transistor elements also includes a first plane parallel to and intersecting the well. The set of transistor elements also includes a second plane parallel to but not intersecting the well. The set of transistor elements also includes a first complementary transistor cell intersecting the first plane, and a second complementary transistor cell intersecting the first plane. The set of transistor elements also includes a minority collector region formed between the first complementary transistor cell and the second complementary transistor cell.

[0014] Some embodiments of the present disclosure may be described as a set of transistor elements as described above, but further include a tap cell intersecting the first plane between the first complementary transistor cell and the minority collector region.

[0015] Some embodiments of the present disclosure may also be described as a set of transistor elements as described above, but further including a second tap cell intersecting the first plane between the second complementary transistor cell and the minority collector region.

[0016] Some embodiments of the present disclosure may be exemplified as a set of transistor elements as described above, but further including a second well of a second doping type formed on the substrate, and an anti-propagation region of the first doping type. In these embodiments, the anti-propagation region intersects the first plane between the well and the second well, and a minority collector region may be of the second doping type and may be formed on the anti-propagation region.

[0017] Some embodiments of the present disclosure may also be exemplified as a set of transistor elements as described above, with the minority collector region being formed on a substrate and intersecting a second plane.

[0018] Some embodiments of the present disclosure may also be exemplified as a set of transistor elements as described above, but of a second doping type, further including an anti-propagation region formed on the substrate and intersecting the second plane. [Brief description of the drawings]

[0019] [Figure 1A] FIG. 1 is a schematic diagram illustrating an example embodiment of a set of transistor elements including an anti-propagation region and two tap cells. [Figure 1B] For clarity, a cross-section of the set of transistor elements of FIG. 1A is shown. [Figure 2A] FIG. 1 is a schematic diagram illustrating an example embodiment of a set of transistor elements including two tap cells and a minority collector set. [Figure 2B] For clarity, a cross-section of the set of transistor elements of FIG. 2A is shown. [Diagram 3] 1 is a schematic diagram illustrating an example embodiment of a set of transistor elements including minority collector regions formed within an anti-propagation region. [Figure 4A] FIG. 2 is a schematic diagram illustrating an example embodiment of a set of transistor elements including two anti-propagation regions. [Figure 4B] For clarity, FIG. 4B shows a cross-sectional view of the set of transistor elements of FIG. 4A. [Diagram 5] FIG. 1 is a diagram of a set of transistor elements incorporating multiple minority collector regions without anti-propagation regions. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Electronic devices often include semiconductor devices such as complementary semiconductor cells patterned together on a substrate to form logic circuits. These semiconductor devices are often constructed from silicon doped with electron acceptor elements (e.g., boron, aluminum, gallium) or electron donor elements (e.g., phosphorus, arsenic, antimony).

[0021] For example, a region of silicon doped with an electron acceptor (also called a p-doped region) may be separated from a second such p-doped region by a region of silicon that is undoped or doped with an electron donor (also called an n-doped region). One of the p-doped regions (also called a "source region") may be connected to a hole source (e.g., VDD), and the second p-doped region (also called a "drain region" or "output region") may be connected to an output. When an n-doped region is activated (e.g., by an adjacent metal gate), holes can flow from a voltage source through the first p-doped region, through the n-doped region, through the second p-doped region, and to the output.

[0022] In many circuit designs, the semiconductor devices described above are sometimes paired with complementary semiconductor devices in which the doping types of the regions are reversed (i.e., a complementary semiconductor consisting of two n-doped regions separated by an undoped or p-doped region). In this complementary semiconductor device, the first n-doped region (also called the "source region") is typically connected to a ground source (e.g., VSS), and the second n-doped region (also called the "drain region" or "output region") is typically connected to an output. These pairs of semiconductors are often referred to as complementary semiconductor cells (also referred to herein as "semiconductor cells"). Thus, in a typical semiconductor cell, charge carriers (either electrons or holes) are typically intended to flow from a voltage source (either an electron source or a ground source), through a set of doped silicon regions (either a pnp region (pFET) or an npn region (nFET)) to an output.

[0023] However, in some cases, unintended current paths can be created throughout a semiconductor cell. This can often occur when charge carriers leak out of their respective regions (e.g., from VDD and out of the first p-doped region) from their source (e.g., VDD or ground) and migrate throughout the surrounding regions of the cell (e.g., well and substrate). This migration can cause these charge carriers to create a low impedance path for current to flow.

[0024] When such a path is formed between the hole source and ground source of the cell through the two source regions of the cell's complementary semiconductor, a latch-up condition is said to occur. In a latch-up condition, the path between VDD and ground through the two source regions can be of low enough impedance that current flows continuously from VDD to ground. This is detrimental because the path between VDD and ground is uncontrolled. In other words, the connection cannot be easily broken by the normal methods of switching the cell on and off. Furthermore, the amount of current flowing through the path is uncontrollable. This can lead to the cell not only failing, but also enough current building up through the path to damage the cell and surrounding structures.

[0025] For these reasons, latch-up in a single cell can be detrimental. A further detriment is that latch-up is known to propagate to neighboring cells, potentially causing widespread problems and damage to the entire device.

[0026] Several designs can be incorporated into electronic devices to protect against the initiation and propagation of latch-up. For example, some devices contain tap cells that are periodically arranged in a semiconductor pattern. These tap cells add a set of contacts between complementary cells. For example, a typical tap cell may add a VDD contact to an n-doped region (e.g., an n-well or n-doped substrate) and a ground contact to a p-doped region (e.g., a p-well or p-doped substrate) between two standard semiconductor cells. The tap cell acts to clamp the potential of the two regions to which the contacts are attached, thereby preventing the source region from being forward biased and injecting minority carriers (e.g., electrons in a p-doped semiconductor and holes in an n-type semiconductor) into the well or substrate.

[0027] Theoretically, including one tap cell between each pair of semiconductor cells in the semiconductor cell pattern would provide significant protection against latch-up. However, because tap cells require space to place contacts between the cells, including such a number of tap cells would significantly increase the overall size of some devices, making them entirely impractical. Therefore, some device designs place tap cells periodically throughout the cell pattern. The frequency of tap cells in the pattern often depends on the fabrication rules of the design and the trade-off between adding space to the overall design and protection from latch-up.

[0028] For these and other reasons, a typical circuit cannot completely prevent the onset of latch-up. In other words, even with reasonable incorporation of tap cells into the design, a typical circuit can still experience latch-up in semiconductor cells. For this reason, a typical electronic device also includes designs to mitigate the propagation of latch-up throughout the device if it does occur. For example, some devices include guard rings of doped silicon around the entire design, often around the input / output circuitry. However, while the guard rings can interrupt the propagation, they usually consume a significant amount of design space. Thus, preventing latch-up propagation with a typical anti-propagation design also significantly increases the overall size of the electronic device.

[0029] To address the above problems, some embodiments of the present disclosure provide protection from latch-up initiation and propagation in a space-efficient manner. For example, some embodiments of the present disclosure reduce the susceptibility of latch-up propagation by incorporating anti-propagation regions between wells in which diffusion regions of adjacent semiconductor cells are formed.

[0030] In some embodiments of the present disclosure, these anti-propagation regions may be bordered on one or both sides by tap cells, which reduces the susceptibility to latch-up of the semiconductor cells on either side of the anti-propagation region.

[0031] Some embodiments of the present disclosure also include additional diffusion regions on the boundaries of these diffusion barrier regions. These diffusion regions may be of a different doping type than the surface on which they are formed (e.g., an n-doped region on a p-doped well substrate, or a p-doped region on an n-doped substrate or well), thereby serving as collector regions for minority carriers (e.g., holes in an n-doped semiconductor, or electrons in a p-doped semiconductor) that have leaked from neighboring semiconductor cells. In some cases, collecting these migrating minority carriers can prevent them from migrating to locations that might help form low impedance paths between source regions of semiconductor cells or between adjacent semiconductor cells. In other words, collecting these minority carriers can prevent latch-up from initiating within a cell (or between cells), as well as from propagating after initiation.

[0032] Some embodiments of the present disclosure also include additional source or ground contacts (similar to those in the tap cells) or additional diffusion regions disposed in the anti-propagation regions or between the tap cells. In these embodiments, the anti-propagation regions not only provide a physical impedance barrier to propagation, but can also play an electrically active role in preventing both latch-up and propagation.

[0033] FIG. 1A is a schematic diagram illustrating an example embodiment of a set of transistor elements 100 including an anti-propagation region and two tap cells. The set of transistor elements 100 includes a first complementary semiconductor cell 102, enclosed within dashed line 104 for clarity, and a second complementary semiconductor cell 106, enclosed within dashed line 108. The semiconductor cell 102 includes two transistors. For clarity, the gate conductor has been omitted. The first transistor is of a first semiconductor type (e.g., a pFET) and includes a source diffusion region 110 (also referred to herein as "region 110") and a drain diffusion region 112 (also referred to herein as "region 112"). The second transistor is of a semiconductor type (e.g., an nFET) and includes a source diffusion region 114 (also referred to herein as "region 114") and a drain diffusion region 116 (also referred to herein as "region 116"). Regions 110 and 112 are shown formed over a well 118 recessed in a substrate 120. Regions 114 and 116 are shown formed over substrate 120.

[0034] The substrate 120 and regions 110 and 112 are all shown with a dotted fill pattern indicating that they are doped with the same dopant (e.g., an electron acceptor element or an electron donor element). In other words, the substrate 120 and regions 110 and 112 are of the same doping type (e.g., p-doped or n-doped). Similarly, the well 118 and regions 114 and 116 are all shown with a diagonal filled pattern indicating that they are doped with the same dopant, but with a different dopant than the substrate 120 and regions 110 and 112. In other words, the well 118 and regions 114 and 116 have an opposite doping type than the substrate 120 and regions 110 and 112. Thus, the substrate 120 and regions 110 and 112 can be p-doped, in which case the well 118 and regions 114 and 116 would be n-doped.

[0035] Similar to semiconductor cell 104, semiconductor cell 106 includes a first semiconductor formed over well 122 and a second semiconductor formed over substrate 120. Well 122 is also shown with a diagonal fill pattern indicating that, like well 118, it is of the opposite doping type as substrate 120.

[0036] It is noted that the set of transistor elements 100 includes two wells 118 and 122, separated by an anti-propagation region 124, bounded by dashed line 126 for clarity. The anti-propagation region 124 effectively provides a high impedance to any path that would otherwise be formed between the diffusion regions of the semiconductor cells 102 and 106 formed on the wells 118 and 122. In other words, even if a forward bias condition, for example, a precursor to latch-up, occurs between the source diffusion region 110 and the well region 118, the anti-propagation region 124 can significantly reduce the likelihood that the forward bias condition will propagate through the wells 118 and 122 to the semiconductor cell 106.

[0037] The set of transistor elements 100 also includes two tap cells 128 and 130, bounded by dashed lines 132 and 134, respectively, for clarity. The tap cell 128 includes a contact 136 formed on the well 118 and a contact 138 formed on the substrate 120. The contact 136 is illustrated with a dot-fill pattern to indicate that it is connected to the same voltage source as the source diffusion region 110. For example, if the source diffusion region 110 was connected to VDD, then the contact 136 would also be connected to VDD. This clamps the well potential to the same as the diffusion region 110, preventing forward biasing and reducing the likelihood of latch-up of the semiconductor cell 102.

[0038] Contact 138 of tap cell 128 is shown with a solid diagonal line pattern to indicate that it is connected to the same voltage source as diffusion region 114. Thus, contact 138 can clamp the substrate potential to be the same as the potential of diffusion region 114, preventing forward bias. In other words, contact 138 can act to reduce the susceptibility of semiconductor cell 102 to latch-up in the same manner that contact 136 does.

[0039] Of note, tap cell 130 also includes contacts 140 and 142. Contact 140 can function similarly to contact 136, and contact 142 can function similarly to contact 138.

[0040] It should also be noted that including two separate tap cells between a pair of complementary semiconductor cells may, in some cases, occupy more space than having one tap cell between the pair of complementary semiconductor cells. However, depending on the ground rules of the case, it may be difficult to place a pair of semiconductor cells (e.g., semiconductor cells 102 and 106) very close to the edges of wells 118 and 122 near anti-propagation region 124. Thus, in some cases, it may be possible to fit the contacts required for the tap cells into the space on the well required between the semiconductor cells and the edges of the well. Thus, in some embodiments, the addition of tap cells 128 and 130 does not actually increase the required size of set 100 of transistor elements, but simply utilizes the space required by the ground rules. In this manner, the latch-up prevention benefits of tap cells 128 and 130 may not come at the cost of additional design space.

[0041] However, in some cases this may not be the case, in which adding both tap cells 128 and 130 to the edge of anti-propagation region 124 may actually increase the space required for set of transistor elements 100. In such cases, it may be beneficial to save space by including only one or neither of tap cells 128 and 130. In such cases, the small benefit that each tap cell provides in preventing latch-up of surrounding semiconductor cells may need to be weighed against the space-saving design considerations.

[0042] It should also be noted that FIG. 1A includes three planes for understanding. Plane 144 extends into and out of the paper on which FIG. 1A is printed, is parallel to wells 118 and 122, and intersects wells 118 and 122. Plane 146 extends into and out of the paper on which FIG. 1A is printed, is parallel to plane 144 and wells 118 and 122, but does not intersect wells 118 and 112. Intermediate plane 148 extends into and out of the paper on which FIG. 1A is printed, and is perpendicular to planes 144 and 146 and wells 118 and 122. Intermediate plane 148 intersects anti-propagation region 124.

[0043] For clarity, Figure 1B shows a cross section of set of transistor elements 100 intersected by plane 144. Plane 144 is therefore represented in Figure 1B by dashed outline.

[0044] 1B, wells 118 and 122 are separated by anti-propagation region 124 comprised of substrate 120. Thus, the portion of substrate 120 that is of a doping type opposite to that of wells 118 and 122 creates a high impedance path that charge carriers must travel to propagate between wells 118 and 122. In other words, if a latch-up event occurs in a cell (e.g., semiconductor cell 102) in one well, it may be highly unlikely to propagate to the other well.

[0045] As mentioned above, the inclusion of tap cells 128 and 130 and anti-propagation region 124 may cause set of transistor elements 100 to occupy more space in a design, but in some cases the benefits of reducing latch-up and latch-up propagation susceptibility may outweigh the negative effects of increased space requirements.

[0046] Similarly, in some cases the benefit of reduced latch-up may be sufficient to justify the inclusion of other transistor elements, even if this increases the space requirements.

[0047] 2A is a schematic diagram illustrating an example embodiment of a set of transistor elements 200 that includes, for example, two tap cells and a minority collector set. Similar to set of transistor elements 100, set of transistor elements 200 includes plane 202, plane 204, and intermediate plane 206. Set of transistor elements 200 also includes two complementary semiconductor cells, indicated by dashed outlines 212 and 214, and two tap cells, indicated by dashed outlines 216 and 218.

[0048] Unlike set of transistor elements 100, set of transistor elements 200 includes four minority collector regions 220, 222, 224, and 226. Minority collector regions 220 and 222 intersect plane 202 and are formed on wells 208 and 210, respectively, while minority collector regions 224 and 226 intersect plane 204 and are formed on substrate 228.

[0049] Minority collector regions 220 and 222 are of the same doping type as the diffusion regions of semiconductor cells 212 and 214 which are also formed on wells 208 and 210. Similarly, minority collector regions 224 and 226 are of the same doping type as the diffusion regions of semiconductor cells 212 and 214 which are also formed on substrate 228. However, minority collectors 220-226 are connected to voltage sources opposite to the voltage sources to which their corresponding diffusion regions are connected.

[0050] For example, minority collector region 220 is of the same doping type (e.g., p-doped) as source diffusion region 230 and opposite to source diffusion region 230. However, minority collector region 220 is connected to a voltage source opposite to that to which source diffusion region 230 is connected (i.e., the same voltage source to which source diffusion region 232 is connected). For example, if the source diffusion region is connected to VDD, minority collector region 220 is connected to ground. Because minority collector region 220 is biased to ground, it provides a harmless path for collecting minority carriers that may have been injected from region 232. Similarly, minority collector region 224 can collect carriers that may have been injected from source diffusion region 230 without being forward biased. Thus, minority collector regions 220-226 may reduce the susceptibility of set of transistor elements 200 to latch-up.

[0051] For clarity, Figure 2B shows a cross section of the set of transistor elements 200 intersected by a plane 202. As such, plane 202 is represented in Figure 2B by a dashed outline.

[0052] 2B, minority collector regions 220 and 222 may be similar in both doping and form factor to the diffusion regions of the semiconductor cells of set of transistor elements 200. However, as previously discussed, minority collector regions 220 and 222 are connected to a voltage source opposite these diffusion regions, allowing them to attract minority carriers without inducing a forward bias.

[0053] It is noted that Figures 2A and 2B show the set of transistor elements 200 including an anti-propagation region between wells 208 and 210. However, in some cases, space considerations of the set of transistor elements 200 may not justify the inclusion of an anti-propagation region. In other words, the increase in size of the set of transistor elements 200 caused by including an anti-propagation region may outweigh the benefit of reducing latch-up propagation between semiconductor cells 212 and 214. In such cases, the embodiment shown in Figures 2A and 2B may be adjusted to account for such space considerations. An example of such an embodiment is shown in Figure 5 below.

[0054] As previously mentioned, in some cases the benefits of the anti-propagation region may outweigh the space considerations of including it, and depending on the ground rules in these cases the anti-propagation region may necessarily be large enough to allow for additional structures to be built on top of it.

[0055] 3, for example, is a schematic diagram illustrating an example embodiment of a set of transistor elements 300 including a minority collector region formed within an anti-propagation region. Specifically, minority collector region 302 is formed within an anti-propagation region represented by dashed outline 304. The minority collector region is shown intersected by plane 306 and intermediate plane 308.

[0056] Similar to minority collector regions 224 and 226 of FIG. 2A, minority collector region 302 may function to collect minority carriers that leak into substrate 310. This may prevent these minority carriers from leaking into wells 312 or 314 and forming a low impedance path between complementary semiconductor source diffusion regions in the semiconductor cell. Specifically, minority collector region 302 may be of the same doping type as diffusion regions 316 and 318, for example. However, minority collector region 302 may be connected to an opposite voltage source. Thus, for example, if diffusion regions 316 and 318 are of n-doping type and connected to a ground source (e.g., VSS), minority collector region 302 may be of n-doping type but connected to a hole source (e.g., VDD).

[0057] 3, the space required to include an anti-propagation region in plane 306 may result in extra space being available in plane 320. Thus, set of transistor elements 300 also includes a clamp contact 322 formed on substrate 310. Clamp contact 322 intersects plane 320 and intermediate plane 308 as well as minority collector region 302. Thus, clamp contact 322 may also be described as intersecting plane 320 between wells 312 and 314.

[0058] Clamp contact 322 may take the form of a metal contact that is connected to the same type of voltage source as tap contact 324. In other words (if diffusion region 316 is connected to ground), clamp contact 322 and tap contact 324 will also be connected to ground.

[0059] In this manner, clamp contact 322 may function similarly to a tap cell. Specifically, clamp contact 322 acts as an ohmic contact and clamps the potential of substrate 310. In other words, clamp contact 322 can prevent substrate 310 from forward biasing with respect to diffusion regions 316 and 318. In this manner, clamp contact 322 can further reduce susceptibility to latch-up.

[0060] Notably, set of transistor elements 300 includes only a single minority collector region and a single clamp contact formed between wells 312 and 314. However, in some cases, space considerations may actually allow for multiple elements to be formed, for example, on the anti-propagation region between the wells. For example, in some embodiments, ground rules may require forming sufficient distance between wells 312 and 314 to form a second minority collector region (or clamp contact) in the anti-propagation region and intersect plane 306.

[0061] Also, note that in some embodiments of the present disclosure, a set of transistor elements may resemble set of transistor elements 300, but may include different transistor elements in mid-plane 308. For example, a clamping contact may intersect plane 306 and mid-plane 308, while a minority collector region, such as minority collector region 302, may intersect plane 320 and mid-plane 322.

[0062] Additionally, in some embodiments, ground rule, space considerations, and latch-up anti-propagation concerns may make it beneficial to include a second anti-propagation region within the set of transistor elements.

[0063] 4A, for example, is a schematic diagram illustrating an example embodiment of a set of transistor elements 400 including two anti-propagation regions. A first anti-propagation region is shown as outline 402, and a second anti-propagation region, anti-propagation region 404, is shown as a well formed in substrate 406. Anti-propagation region 404 may act as a high impedance path between semiconductor cells, shown as outlines 408 and 410, because it is of a different doping type than substrate 406. This high impedance path may serve to reduce the likelihood of a latch-up condition from one semiconductor cell propagating to the other semiconductor cell. Additionally, clamping contacts or minority collectors may be added to anti-propagation region 404 to further reduce susceptibility to latch-up.

[0064] The set of transistor elements 400 also includes minority collectors 412 and 414 formed within the anti-propagation region shown by outline 402. This may be beneficial in instances where anti-propagation region 404 requires increased space between semiconductor cells to allow for two components to be placed within the anti-propagation region shown by outline 402. In other words, in instances where ground rules require that space to be available, it may be beneficial to place multiple minority collectors (or clamp contacts) in the space.

[0065] Anti-propagation region 404 intersects plane 416 and intermediate plane 418. For clarity, Figure 4B shows a cross section of set of transistor elements 400 intersecting plane 416. Plane 416 is represented in Figure 4B by a dashed outline.

[0066] 4B illustrates the anti-propagation region 404 as a well that intersects with the mid-plane 418. Although the anti-propagation region 404 may not provide a complete physical barrier between the semiconductor cells 408 and 410, the anti-propagation region 404 will still increase the impedance between these cells 408 and 410. In particular, requiring charge carriers (e.g., minority or majority carriers) to be guided around the anti-propagation region 404 may increase the impedance of such a path to a degree that reduces susceptibility to latch-up propagation. For at least this reason, in some instances, the reduction in latch-up propagation may outweigh the potential harm of increasing the size of the set of transistor elements 400 to make room for the anti-propagation region 404.

[0067] 1A-4B each illustrate an embodiment in which at least one anti-propagation region is formed. However, as discussed above, in some cases, the benefits of including an anti-propagation region may be outweighed by the extra space required to include the anti-propagation region. For example, in some embodiments, the space required by an anti-propagation region may be such that the anti-propagation region is rarely used in a pattern. Thus, in some embodiments of the present disclosure, some of the other features discussed above may be utilized more frequently in a transistor pattern than the anti-propagation region.

[0068] Figure 5 is a diagram of a set 500 of transistor elements incorporating multiple minority collector regions 502 and 504 without anti-propagation regions. Set 500 also includes a well 506 and a substrate 508, neither of which include an anti-propagation region within the space shown in Figure 5. Set 500 also includes a first complementary transistor cell, indicated by outline 510, and a second complementary transistor cell, indicated by outline 512. The first complementary transistor cell includes source diffusion regions 514 and 516.

[0069] FIG. 5 also shows a plane 518 and a plane 520. The plane 518 is parallel to the well 506 and intersects with the well 506. The plane 518 also intersects with the first complementary transistor cell (e.g., the plane 518 intersects with the source diffusion region 514) and the second complementary transistor cell. Finally, the plane 518 also intersects with the minority collector region 502 between the first and second complementary transistor cells. Meanwhile, the plane 520 is parallel to the well 506 but does not intersect with the well 506. Rather, the plane 520 intersects with the first complementary transistor cell (e.g., the source diffusion region 516) and the second complementary transistor cell. Finally, the plane 520 intersects with the minority collector region 504 between the first and second complementary transistor cells.

[0070] The minority collector cells 502 and 504 may provide sufficient local latch-up protection in some cases. Furthermore, the space savings from not forming anti-propagation regions within the set of transistor elements 500 may outweigh the lack of propagation protection that such anti-propagation regions would provide. However, in some cases, additional local latch-up protection may be desired. In such cases, additional protection mechanisms may be added to the set of transistor elements 500, such as tap cells between the first and second transistor cells (e.g., on either side of the minority collector regions 502 and 504).

[0071] Throughout this disclosure, space considerations and rules have been mentioned at various times. Because embodiments of the present disclosure present many permutations of sets of transistor elements, various spacing rules may be utilized in some embodiments. These spacing rules may be determined in part by the details of the case. Some spacing rules may, for example, provide a preferred maximum distance between a transistor cell (or a diffusion region within a transistor cell, etc.) and a latch-up prevention element (such as a tap cell).

[0072] For example, embodiments of the present disclosure disclose at least four spacing categories: (1) the distance between a well transistor cell (i.e., a transistor cell formed on a well) and a minority collector region on that same well, (2) the distance between a substrate transistor cell and a minority collector region on the substrate, (3) the distance between a well transistor cell and a clamp contact on that same well, and (4) the distance between a substrate transistor cell and a clamp contact on the substrate. In some embodiments, the rules may specify the same maximum distance for all four spacing categories. However, in some cases, the rules may specify the same maximum distance for categories 1 and 3, and the same maximum distance for categories 2 and 4, but different maximum distances for categories 1 and 2, and categories 2 and 3. Similarly, in some embodiments, the rules may specify different maximum distances for all four categories.

[0073] For example, in some embodiments, the rules may set a first maximum distance between the source diffusion region 514 and the nearest clamp contact on the well 506, a second maximum distance between the source diffusion region 514 and the nearest minority collector region on the well 506 (i.e., minority collector region 502), a third maximum distance between the source diffusion region 516 and the nearest clamp contact on the substrate 508, and a fourth maximum distance between the source diffusion region 516 and the nearest minority collector region on the substrate 508 (i.e., minority collector region 504). In some of these embodiments, each of these four maximum distances may be different.

[0074] Additionally, in some embodiments, similar rules may set a maximum distance between a transistor and the nearest anti-propagation region. Continuing with the previous example, the rules may also set a fifth maximum distance between source diffusion region 514 and the nearest anti-propagation region that cuts into well 506 (e.g., an anti-propagation region that intersects plane 518), and a sixth maximum distance between source diffusion region 516 that cuts into substrate 508 and intersects plane 520. In these embodiments, the fifth and sixth differences may also be different.

[0075] It should be noted that FIGS. 1A-5 are simplified diagrams of a set of transistor elements. The embodiments of the present disclosure are presented in this simplified manner for understanding. As such, the figures of the present disclosure are not intended to be construed as literal depictions of every embodiment of the present disclosure. For example, although the diffusion regions and minority collector regions are presented as abstracted fin form factors (thus, the source diffusion region 110 may take the form of a FinFET), other transistor form factors (e.g., planar regions) are also contemplated as long as those form factors are not inconsistent with the scope of the embodiments of the present disclosure. Similarly, what are referred to herein as diffusion regions may in some embodiments actually be epitaxially doped regions.

[0076] Additionally, the size ratios of some elements in some of the drawings may be significantly distorted in order to adequately illustrate the embodiments. Similarly, to avoid unnecessarily cluttering the figures, some elements necessary for device functionality have been omitted from the figures. For this reason, electron source connections and ground connections have been omitted from the drawings, as have gates (e.g., metal gates) necessary to cause semiconductor cells to switch states. Additionally, oxide insulating layers between some elements (e.g., diffusion regions of different doping types) have been omitted.

[0077] The description of various embodiments of the present invention is presented for illustrative purposes, but is not intended to be exhaustive and is not limited to the disclosed embodiments. Many changes and modifications will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used in this specification are selected to best explain the principles of the embodiments, practical applications, or technical improvements to the technology found in the market, or to allow other skilled in the art to understand the embodiments disclosed herein.

Claims

1. a substrate of a first doping type; a first well of a second doping type formed on the substrate; a second well of the second doping type formed on the substrate; a first plane parallel to and intersecting the first and second wells; and a second plane parallel to the first and second wells but not intersecting the first or second wells; a first complementary transistor cell intersecting the first plane; a second complementary transistor cell intersecting the first plane; an anti-propagation region of the first doping type intersecting the first plane between the first well and the second well; A set of transistor elements comprising:

2. The set of transistor elements of claim 1 further comprising a first tap cell intersecting the first plane between the first complementary transistor cell and the anti-propagation region.

3. The set of transistor elements of claim 2 further comprising a second tap cell intersecting the first plane between the second complementary transistor cell and the anti-propagation region.

4. 3. The set of transistor elements of claim 2, further comprising a first minority collector region of said first doping type formed on said first well and intersecting said first plane between said first tap cell and said anti-propagation region.

5. a first minority collector region of the first doping type formed on the first well and intersecting the first plane between the first tap cell and the anti-propagation region; a second minority collector region of the first doping type formed on the second well and intersecting the second plane between the second tap cell and the anti-propagation region; The set of transistor elements according to claim 3 , further comprising:

6. 2. The set of transistor elements of claim 1, further comprising a first minority collector region of said first doping type formed over said first well and intersecting said first plane between said first complementary transistor cell and said anti-propagation region.

7. 2. The set of transistor elements of claim 1, further comprising a minority collector of said second doping type formed in said anti-propagation region.

8. The set of transistor elements of claim 1 further comprising a clamping contact located on the substrate and intersecting the second plane between the first well and the second well.

9. 2. The set of transistor elements of claim 1, further comprising a second anti-propagation region of said second doping type formed on said substrate and intersecting said second plane.

10. 2. The set of transistor elements of claim 1, further comprising a minority collector of said second doping type formed on said substrate and intersecting said second plane.

11. a substrate of a first doping type; a well of a second doping type formed on the substrate; a first plane parallel to and intersecting said well; a second plane parallel to but not intersecting the well; and a first complementary transistor cell intersecting the first plane; a second complementary transistor cell intersecting the first plane; a minority collector region formed between the first complementary transistor cell and the second complementary transistor cell; A set of transistor elements comprising:

12. a second well of the second doping type formed on the substrate; a propagation prevention region of the first doping type, the propagation prevention region intersecting the first plane between the well and the second well; The set of transistor elements according to claim 11 , further comprising:

13. The set of transistor elements as recited in claim 12 , wherein the minority collector region is formed between the first complementary transistor cell and the anti-propagation region.

14. The set of transistor elements of claim 11 further comprising a first tap cell intersecting the first plane between the first complementary transistor cell and the minority collector region.

15. The set of transistor elements of claim 14 further comprising a second tap cell intersecting the first plane between the second complementary transistor cell and the minority collector region.

16. The set of transistor elements of claim 15 further comprising a second minority collector region formed between the first tap cell and the second tap cell.

17. The set of transistor elements of claim 12 , wherein the minority collector region is of the second doping type and is formed on the anti-propagation region.

18. The set of transistor elements of claim 12 , further comprising a clamping contact disposed on the anti-propagation region.

19. The set of transistor elements of claim 12 further comprising a clamping contact disposed on the substrate and intersecting the second plane between the well and the second well.

20. The set of transistor elements of claim 12 further comprising a second anti-propagation region of the second doping type formed on the substrate and intersecting the second plane.

21. The set of transistor elements as recited in claim 11 , wherein the minority collector region is formed on the substrate and intersects the second plane.

22. The set of transistor elements of claim 11 further comprising an anti-propagation region of the second doping type formed on the substrate and intersecting the second plane.

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