System and method for trimming a photonic integrated circuit - Patents.com

Abstract

A system for trimming a photonic chip includes a fabrication unit and a system controller communicatively coupled to the fabrication unit. The system controller is configured to cause the fabrication unit to fabricate a photonic chip in an offset state. The system controller is further configured to generate one or more trimming patterns based on an optical performance of the photonic chip and a first target optical performance of the photonic chip. The system controller is further configured to provide a patterned resist on the photonic chip based on the one or more trimming patterns and trim the photonic chip by exposure to a plasma of a reactive gas, where the reactive gas is one of oxygen or nitrogen.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Application No. 63 / 320,734, entitled “SYSTEM AND METHOD FOR TRIMING PHOTONIC INTEGRATED CIRCUIT,” filed March 17, 2022, which is incorporated herein by reference for all purposes. For U.S. purposes, this application claims the benefit under 35 U.S.C. § 119 of U.S. Application No. 63 / 320,734, entitled “SYSTEM AND METHOD FOR TRIMING PHOTONIC INTEGRATED CIRCUIT,” filed March 17, 2022, which is incorporated herein by reference for all purposes.

[0002] TECHNICAL FIELD This disclosure relates generally to fabricating photonic integrated circuits, and more particularly to systems and methods for trimming photonic integrated circuits. [Background technology]

[0003] Silicon, a semiconductor, is the backbone material of modern integrated circuits (also called chips). A typical chip manufacturing process begins with preparing a silicon wafer and forming micro- and nano-devices in the wafer using lithography, implantation, and deposition techniques. Advances in this field have so far demanded greater control over the specifications of such fabrication schemes. As a result, silicon processing has become the most available process and silicon has become the most known material for realizing such micro- and nano-devices. A property of silicon is that it can be oxidized to silicon dioxide. Silicon dioxide is an insulator. Silicon-on-insulator (SOI) thin films are widely used as an alternative wafer substrate on which micro- and nano-devices can be built. Micro- and nano-devices realized on SOI wafers have advantages such as reduced parasitic capacitance, lower power consumption, and shorter gate delays compared to micro- and nano-devices realized on conventional silicon wafers.

[0004] Silicon and silicon dioxide are transparent materials at infrared wavelengths. Because the refractive index of silicon is higher than that of silicon dioxide, a slab of silicon can be patterned using conventional lithography techniques to obtain structures that can accept and guide infrared optical signals across a surface, similar to the way metal wires are used to transmit electrical signals. Such optical integrated circuits define the field of silicon photonics. Silicon photonic chips can benefit from manufacturing techniques that are compatible with electronic chip manufacturing. Silicon photonic chips can provide optical functions that are useful for a variety of applications, including, for example, communication transceiver modules, optical computers, and optical biosensing.

[0005] Silicon photonic chips can contain many active and passive elements. These include waveguides, grating couplers, edge couplers, directional couplers, ring resonators, photonic crystals, and photodetectors, all of which can be fabricated monolithically. The unique property of silicon is its high refractive index contrast compared to other readily available materials such as silicon dioxide. This property allows silicon structures to function as optical core materials when surrounded by materials with lower refractive index. The high refractive index contrast also facilitates the miniaturization of elements, allowing for the dense integration of complex optical circuits. Summary of the Invention

[0006] The present technique provides partially processed substrates for fabrication of photonic chips, along with methods and systems for fabricating photonic chips and / or trimming photonic devices.

[0007] According to a first aspect, there is provided a method of trimming an integrated photonic device, the method including fabricating a photonic device, optically measuring the photonic device to generate optical measurements, determining a trimming pattern using the optical measurements, creating a patterned resist on the photonic device using the determined trimming pattern, and trimming the photonic device by a plasma process to convert a thickness of core material of the photonic device exposed by openings in the patterned resist to a different material that may be retained in the photonic device after final fabrication.

[0008] According to another aspect, a method is provided for trimming an integrated photonic device, the method including optically measuring the photonic device, generating one or more trimming patterns based on at least the optical measurements, providing a patterned resist over the photonic device based on the one or more trimming patterns, and trimming the photonic device to adjust a performance metric of the photonic device. Trimming the photonic device includes exposing the photonic device to a plasma of a reactive gas through one or more openings in the patterned resist.

[0009] According to another aspect, a method is provided for trimming an integrated photonic device, the method including optically measuring the photonic device, generating one or more trimming patterns based on at least the optical measurements, providing a patterned resist over the photonic device based on the one or more trimming patterns, and trimming the photonic device to adjust a performance metric of the photonic device, wherein the trimming includes exposing the photonic device to a plasma of a reactive gas through one or more openings in the patterned resist.

[0010] According to another aspect, there are provided methods having novel and unique steps, acts, combinations of steps and / or acts, and subcombinations of steps and / or acts as described herein.

[0011] According to another aspect, a system for trimming a photonic chip is provided. The system includes a fabrication unit and a system controller communicatively coupled to the fabrication unit. The system controller is configured to cause the fabrication unit to fabricate the photonic chip in an offset state. The system controller is further configured to generate one or more trimming patterns based on an optical performance of the photonic chip and a first target optical performance of the photonic chip. The system controller is further configured to provide a patterned resist on the photonic chip based on the one or more trimming patterns and trim the photonic chip by exposure to a plasma of a reactive gas, where the reactive gas is one of oxygen or nitrogen.

[0012] According to another aspect, a system for trimming one or more photonic devices of a photonic chip is provided. The system includes a system controller, a measurement unit, and a plasma chamber. The system controller is configured to obtain optical measurements of optical properties of one or more photonic devices on the photonic chip from the measurement unit and generate one or more trimming patterns for one or more of the one or more photonic devices, respectively, based on the optical measurements. The system controller is further configured to control the fabrication unit to provide a patterned resist on the photonic chip based on the one or more trimming patterns. The one or more photonic devices of the photonic chip may be trimmed by exposing the photonic chip with the patterned resist to a plasma in the plasma chamber. The plasma comprises a reactive gas selected from oxygen and nitrogen.

[0013] According to another aspect, a system for trimming one or more photonic devices of a photonic chip is provided, the system including a fabrication unit and a system controller communicatively coupled to the fabrication unit, the system controller configured to: cause the fabrication unit to fabricate the photonic chip such that the one or more photonic devices are in an offset state; generate one or more trimming patterns based on optical performances of the one or more photonic devices of the photonic chip and a first target optical performance for the one or more photonic devices; provide a patterned resist on the photonic chip based on the one or more trimming patterns; and trim the one or more photonic devices of the photonic chip by exposure to a plasma comprising a reactive gas, the reactive gas being one of oxygen or nitrogen.

[0014] According to another aspect, there is provided an apparatus having any novel and inventive feature, combination of features, or subcombination of features described herein.

[0015] In some embodiments, the photonic device includes a core, and trimming includes converting a portion of the core from one material to another, different material.

[0016] In some embodiments, the photonic device comprises a silicon core.

[0017] In some embodiments, the core material comprises silicon.

[0018] In some embodiments, the plasma process includes an oxygen plasma process and the different material is silicon dioxide.

[0019] In some embodiments, the plasma process includes a nitrogen plasma process and the different material is silicon nitride.

[0020] In some embodiments, the portion of the core is a layer having a thickness greater than 2 nm, hi some embodiments, the portion of the core is a layer having a thickness in the range of 2 nm to 10 nm.

[0021] In some embodiments, the core is a silicon core.

[0022] In some embodiments, the trimming includes converting a portion of the core to silicon nitride.

[0023] In some embodiments, trimming includes converting the portion of the core to silicon dioxide.

[0024] In some embodiments, generating the one or more trimming patterns is further based on an intended optical performance for the photonic device, where the intended optical performance is different from a predetermined optimum optical performance of the photonic device.

[0025] In some embodiments, the method includes fabricating a photonic device in an offset state, where a value of the performance metric in the offset state differs from a predetermined optimal value, and where a sign of a difference between the value of the performance metric and the predetermined optimal value is reduced by trimming.

[0026] In some embodiments, the method includes fabricating a photonic device in an offset state, where a value of a performance metric in the offset state i is less than a predetermined optimal value.

[0027] In some embodiments, the method includes fabricating a photonic device in an offset state, where a value of a performance metric in the offset state i is greater than a predetermined optimal value.

[0028] In some embodiments, the method includes generating one or more process parameters based on the optical measurements and performing trimming using the one or more process parameters, in some embodiments, the process parameters include a plasma chamber pressure and / or an RF power applied to the plasma chamber, and the process parameters are selected to cause the plasma to penetrate into the photonic device to a depth in the range of 2 nm to 10 nm.

[0029] In some embodiments, optically measuring the photonic device includes coating the photonic device with a temporary material, optically measuring the coated photonic device, and removing the temporary material prior to providing the patterned resist, In some embodiments, the temporary material has substantially the same refractive index as a material that will be added to the photonic device during final fabrication of the photonic device.

[0030] In some embodiments, the method includes iteratively repeating the steps of optically measuring the photonic device, generating one or more trimming patterns based on at least the optical measurements, providing a patterned resist on the photonic device based on the one or more trimming patterns, and trimming the photonic device to adjust a performance metric of the photonic device, thereby progressively causing a value of the performance metric of the photonic device to approach an optimal or target value of the performance metric of the photonic device.

[0031] In some embodiments, the photonic device is one of a plurality of photonic devices fabricated on a common substrate, and the method includes performing the steps of the method for each of the plurality of photonic devices, and at least the step of trimming the photonic device to adjust a performance metric of the photonic device is performed simultaneously for the plurality of photonic devices.

[0032] In some embodiments, the photonic device comprises an optical resonator, an optical filter, or an optical waveguide.

[0033] In some embodiments, the photonic device is a photonic crystal device.

[0034] In some embodiments, the photonic device includes an optical resonator, and the performance metric of the photonic device includes a resonant wavelength or frequency or a Q-factor of the optical resonator.

[0035] In some embodiments, the plasma comprises a mixture of a reactive gas and an inert gas, hi some embodiments, the inert gas is argon.

[0036] In some embodiments, the plasma comprises a plasma of a plasma mixture comprising 15 to 50% oxygen and 50 to 85% argon.

[0037] In some embodiments, the first target optical performance is a predetermined optimum optical performance of the one or more photonic devices, where the performance metric has a predetermined optimum value.

[0038] In some embodiments, generating the one or more trimming patterns is based on an intended optical performance for the one or more photonic devices, where the intended optical performance differs from a predetermined optimum optical performance of the one or more photonic devices.

[0039] In some embodiments, an offset state refers to a state in which the value of the performance metric in the offset state differs from a predetermined optimum value, and the sign of the difference between the value of the performance metric and the predetermined optimum value is such that trimming reduces the magnitude of the difference.

[0040] In some embodiments, the optical performance of the one or more photonic devices and the first target optical performance of the one or more photonic devices are measured by a performance metric, and a value of the performance metric in the offset state is less than a predetermined optimum value for the performance metric.

[0041] In some embodiments, the optical performance of the one or more photonic devices and the first target optical performance of the one or more photonic devices are measured by a performance metric, and a value of the performance metric in the offset state is greater than a predetermined optimum value for the performance metric.

[0042] In some embodiments, the system includes a testing unit communicatively coupled to the fabrication unit and the system controller, the testing unit configured to perform optical characterization of one or more photonic devices of the one or more photonic devices on the photonic chip, thereby determining optical performance of the one or more photonic devices of the one or more photonic devices.

[0043] In some embodiments, the photonic chip includes a core, and the plasma including the reactive gas is effective to transform a portion of the core from one material to another material.

[0044] The system controller is configured to cause trimming of one or more photonic devices of the photonic chip for a time and under plasma conditions sufficient to cause a portion of the core to become a layer having a thickness greater than 2 nm, in some embodiments, the photonic chip includes a core, and the plasma comprising the reactive gas is effective to transform a portion of the core from one material to another, the portion of the core being a layer having a thickness in the range of 2 nm to 10 nm.

[0045] In some embodiments, the photonic chip includes a core, and the plasma including the reactive gas is effective to transform a portion of the core from one material to another material.

[0046] In some embodiments, the system controller is configured to generate one or more process parameters based on optical measurements made on the photonic chip and to control trimming using the one or more process parameters.

[0047] In some embodiments, the system includes a plasma chamber, and the process parameters include a plasma chamber pressure and / or RF power applied to the plasma chamber, and the process parameters are selected to cause the plasma to penetrate into the photonic tip to a depth in the range of 2 nm to 10 nm.

[0048] In some embodiments, the one or more photonic devices include a plurality of photonic devices fabricated on a common substrate, and the system controller is configured to perform, for each of the plurality of photonic devices, the steps of generating one or more trimming patterns for the photonic device based on an optical performance of the photonic device and a first target optical performance of the photonic device, providing a patterned resist on the photonic chip based on the one or more trimming patterns, and trimming the photonic device by exposing it to a plasma including a reactive gas, the reactive gas being one of oxygen or nitrogen. At least the step of trimming the photonic device is performed simultaneously for the plurality of photonic devices.

[0049] In some embodiments, the system controller is further configured to generate a photonic chip design, according to which the photonic chip is fabricated.

[0050] In some embodiments, the determination of the trimming pattern is made using a target optical performance of the photonic device.

[0051] In some embodiments, the target optical performance is a final target optical performance of the photonic device, or corresponds to a target optical performance that is closer to the final target optical performance than the optical performance indicated by the optical measurements.

[0052] In some embodiments, the plasma process is performed with a saturation level versus a duration to change the optical performance of the photonic device by trimming the photonic device to match a predetermined target optical performance.

[0053] In some embodiments, determining the trimming pattern further includes determining process parameters for an equipment used to perform the plasma process according to the saturation level.

[0054] In some embodiments, fabricating the photonic devices is performed according to a design determined to result in a statistical distribution of photonic devices in an initial state having various optical performance levels around an initial target optical performance that can be modified by trimming.

[0055] In some embodiments, optically measuring the photonic device includes coating the photonic device with a temporary material to simulate final performance of the photonic device after final fabrication, and optically measuring the coated photonic device to generate the optical measurements. The temporary material may be removed prior to providing the patterned resist.

[0056] In some embodiments, the temporary material has substantially the same refractive index as the material that is added to the photonic device after trimming and that is retained after final fabrication.

[0057] In some embodiments, the plasma process utilizes an oxygen plasma or a nitrogen plasma and excludes an additional etchant.

[0058] Some embodiments further provide for, after trimming of the photonic device, optically measuring the photonic device to generate further optical measurements, using the further optical measurements to determine that the photonic device is tolerant to the offset condition, determining a further trimming pattern using the further optical measurements, providing a further patterned resist on the photonic device using the determined further trimming pattern, further trimming the photonic device by a further plasma process, and converting a further thickness of core material of the photonic device exposed by the openings in the further patterned resist to a different material that is retained in the photonic device after final fabrication.

[0059] In some embodiments, determining the trimming pattern is performed using a first target optical performance for the photonic device, where determining the further trimming pattern is performed using a second target optical performance, the second target optical performance being closer to the final target optical performance than the first target optical performance.

[0060] In some embodiments, the plasma process is performed with first process settings such that when used with a patterned resist, trimming of the photonic device changes the optical performance of the photonic device by a first predetermined amount, and a further plasma process is performed for a first time at a first saturation level such that when used with a further patterned resist, further trimming of the photonic device changes the optical performance of the photonic device by a second predetermined amount.

[0061] In some embodiments, the first predetermined amount is greater than the second predetermined amount.

[0062] Some embodiments further provide for repeating a certain number of process steps after prior trimming of the photonic device, including optically measuring the photonic device to generate further optical measurements, using the further optical measurements to determine that the photonic device is not acceptable, determining a further trimming pattern using the further optical measurements, providing a further patterned resist on the photonic device using the determined further trimming pattern, further trimming the photonic device by a further plasma process, and converting a further thickness of core material of the photonic device exposed by the openings in the further patterned resist to a different material that may be retained in the photonic device after final fabrication.

[0063] Some embodiments further provide process steps of optically measuring the photonic device after a certain number of iterations to generate a final optical measurement, and using the final optical measurement to determine that the photonic device is acceptable.

[0064] In some embodiments, the plasma process uses a lower plasma chamber pressure than that used in the descum process.

[0065] In some embodiments, the plasma process uses a lower plasma chamber pressure than that used in the descum process and a lower RF power than that of the etch process.

[0066] The above and additional aspects and embodiments of the present disclosure will be apparent to those of ordinary skill in the art in view of the detailed description of various embodiments and / or aspects thereof, which may be viewed in conjunction with the drawings, a brief description of which is given below.

[0067] Further aspects and example embodiments are illustrated in the accompanying drawings and / or described in the following description.

[0068] It is emphasized that the invention relates to all combinations of the above-described features, even if these are recited in different claims. [Brief description of the drawings]

[0069] These and other advantages of the present disclosure will become apparent upon reading the following detailed description and upon reference to the drawings which illustrate non-limiting exemplary embodiments of the invention.

[0070] [Figure 1] FIG. 1 is a block diagram of a system for fabricating a photonic chip according to an exemplary embodiment of the present invention. [Diagram 2] 1 shows the statistical distribution of devices on a photonic chip according to performance metrics. [Diagram 3] 4 is a flow chart illustrating a method for trimming a photonic chip according to an exemplary embodiment of the present invention. [Figure 4] 4 is a plan view of a nanobeam cavity device illustrating an exemplary application of the trimming method of FIG. 3. [Diagram 5] 5 shows simulated trimming curves of resonant wavelength for the nanobeam cavity device of FIG. 4 versus a parameter X that defines the degree of trimming applied to the nanobeam cavity device. [Figure 6] 4 is a plan view of a microring device illustrating an exemplary application of the trimming method of FIG. 3.

[0071] While the present disclosure is susceptible to various modifications and alternative forms, specific embodiments or implementations have been shown by way of example in the drawings and are described in detail herein. It should be understood, however, that the present disclosure is not intended to be limited to the particular forms disclosed. Rather, the present disclosure covers all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0072] Throughout the following description, specific details are set forth in order to provide a thorough understanding of the invention. However, the invention may be practiced without these details. In other instances, well-known elements have not been shown or described in detail to avoid unnecessarily obscuring the invention. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

[0073] The foregoing summary, as well as the following detailed description of specific examples, will be better understood when read in conjunction with the appended drawings.

[0074] The high refractive index contrast between silicon and other materials such as silicon dioxide imposes several practical challenges: for example, sub-nanometer roughness around the waveguide surface made with silicon results in higher optical losses compared to the same roughness made with lower contrast materials such as silicon nitride or glass, and the small element size makes manufacturing tolerances significant compared to device size.

[0075] Inaccuracies in the dimensions of a device result in changes to its optical function. For example, small changes in the width or thickness of a waveguide change its effective refractive index. In particular, light propagating along a waveguide with inaccuracies acquires a different phase compared to that expected from an ideal waveguide. Such deviations can change the performance of the entire circuit depending on the design. Another class of devices where device inaccuracies result in significant changes in functionality are optical cavity devices, such as ring resonators or photonic crystal resonators. The resonant frequency of such devices made from silicon is typically a very strong function of the device dimensions. Thus, fabrication tolerances impose a large scatter in the predicted resonances for such devices. The scatter in performance can result, for example, in integrated optical filters that are mismatched to the target design wavelength.

[0076] Some of the deviations in device performance from design arise from systematic errors and are arguably controllable and repeatable. For example, a waveguide may turn out to be systematically a few nm wider than designed after going through a particular fabrication process. Such repeatable errors can be corrected by a calibration run of the chip fabrication, where the deviation in performance is measured and then a corrective bias is applied to the layout before further chip fabrication. The repeatable performance correction may be as simple as applying a constant bias to all devices, or as complex as applying a trained computational algorithm to calculate the required correction given parameters such as device type, neighboring devices, etc.

[0077] The second part of the deviation of device performance from the design is statistical in nature. For example, two identically designed cavities located next to each other on the same chip may have slightly different resonant frequencies. Similarly, two chips manufactured using the same process and parameters may turn out to exhibit different characteristics. Unlike reproducible deviations introduced due to systematic errors, statistical variations cannot be predicted on an individual basis and therefore cannot be corrected by layout preparation strategies such as calibration runs and / or computational corrections.

[0078] One way to reduce statistical deviations is to improve fabrication tolerances and / or create device designs that are essentially insensitive to device dimensions. However, in practice, fabrication processes cannot be pushed to their ideal limits, and device designs are not infinitely flexible. As a result, despite the precision of modern electronic fabrication methods, integrated photonic devices still suffer from statistical deviations.

[0079] Another approach to correcting statistical variations involves building active control elements on-chip to actively compensate for device performance deviations in fully fabricated devices. For example, a heater can be patterned next to a resonant cavity to dissipate power and thereby change the cavity temperature. This has the effect of changing the refractive index of the material, which can tune the cavity to a desired resonance. While this approach satisfies the need to tune a desired parameter, such active approaches typically require additional on-chip real estate that is not easy to implement. Furthermore, this approach can dissipate significant power and typically requires additional control electronics.

[0080] Yet another approach to correct for statistical variations is to apply interim trimming after the initial fabrication. In this approach, the optical performance of the fabricated device is measured and fed into further fabrication steps with the goal of applying minute changes to the device. This approach generally requires that the magnitude of the changes be individually tailored to the correction required by each device. There are several proposals on how to achieve this.

[0081] The first proposal involves a relatively standard process that involves adding one or more layers of material, such as silicon dioxide, silicon nitride, hafnium oxide, to a fabricated silicon chip. This is then followed by selective trimming, i.e., removing the added material, for example using a lithography process, followed by an etching process. These processes are non-trivial for some devices that include photonic crystal structures, especially considering that the added material layers may not fit into the high aspect ratio of small crystal holes that may be present in such devices. Similarly, this approach requires that the alignment used during the trimming lithography step be carefully aligned to the existing devices on the chip.

[0082] The second proposal involves non-standard processes that impose changes on the cladding or buried oxide material. This includes exposing chromophore-doped polymer cladding to a controlled electron beam, exposing buried oxide to strained silicon to trim the device, or annealing spin-on glass resist on the device with a focused laser that can reach temperatures as high as 1200°C. These processes are not easily controllable and could potentially result in unstable or damaging changes to some photonic devices. Furthermore, because these processes are non-standard, they are time consuming and impractical for large-scale fabrication, and usually require non-standard equipment.

[0083] The third proposal involves processes that impose changes on the silicon material structure itself. These changes include oxidation followed by oxide removal with wet etchants and / or surface oxidation of silicon due to heating caused by prolonged exposure to a focused laser. These processes are not smooth and controllable. Furthermore, the minimum step size in trimming per cycle is shown to be relatively large and cannot be easily applied differently to individual devices on a single chip. Finally, this proposal involves processes that are not as accurate as some of the more standard processes.

[0084] As can be appreciated, a method for trimming photonic chips and / or devices that can be performed without adding additional material is desirable. The method should be easy and fast to perform. The method should be implementable when trimming devices with high aspect ratios or devices with small structures.

[0085] In the following description, embodiments of a system and method for trimming a photonic chip by plasma oxidation and / or nitridation processes are described.

[0086] Referring now to Figure 1, a block diagram of a system for fabricating photonic chips is shown and generally identified by reference numeral 100. In this embodiment, the photonic chip fabrication system 100 is suitable for fabricating photonic chips having multiple components (devices) integrated thereon / therein. Examples of these devices are optical cavities, resonant channel drop filters, waveguides, coupled ring resonators, etc. As can be seen, the system 100 includes a fabrication unit 102, a testing unit 104, and a system controller 106.

[0087] The fabrication unit 102 fabricates the photonic chip using a combination of fabrication processes including material deposition, pattern definition, and pattern transfer. During material deposition, material is deposited on a handling wafer (Si wafer or SOI wafer or similar wafer) using one or more deposition techniques. For example, material may be deposited using chemical vapor deposition (CVD), molecular beam epitaxy (MBE), sputtering, or any other conventional deposition technique. The pattern definition process is performed using lithography techniques (e.g., optical lithography, e-beam lithography, etc.). The pattern transfer process includes applying one or more etching techniques to the photonic chip. After pattern transfer, the photonic chip may undergo additional material deposition using any one of the aforementioned deposition techniques. Depending on the type and function of the photonic chip, the fabrication process may include additional steps such as ion implantation, annealing, layer transfer, etc. One or more fabrication processes may be repeated in no particular order depending on the complexity of the photonic chip to be fabricated.

[0088] The test unit 104 is configured to measure the optical performance of the fabricated photonic chip using one or more test instruments. Examples of test instruments include an optical probe station and a spectrometer. Testing may be performed during one or more fabrication processes (in-situ) or after all fabrication processes are completed (ex-situ). Testing may include measuring the value of a performance metric of interest for one or more devices on the photonic chip against a predetermined value of the performance metric. The performance metric of interest may be, for example, any one of the energy, frequency, wavelength, phase, or Q-factor of one or more devices on the photonic chip.

[0089] The controller 106 is communicatively coupled to the fabrication unit 102 and the testing unit 104. The controller 106 includes one or more storage devices 108 and one or more processors 110 communicatively coupled to the one or more storage devices 108. The storage device 108 may be a hard disk or other tangible non-transitory computer readable medium. The storage device 108 stores one or more software modules 112 executed by the one or more processors 110. The storage device 108 further stores a database 114 containing one or more records of data utilized by the processor 110 in conjunction with the software modules 112. The data may include training data including fabrication process simulation data, fabrication process characteristic data, in-process inspection data, post-build inspection data, or any combination thereof, used by the processor to optimize one or more parameters used during fabrication.

[0090] By executing one or more software modules 112, the processor 110 causes the controller 106 to perform various functions within the photonic chip manufacturing system 100. For example, the processor 110 may execute a (CAD) software module 112 that causes the controller 106 to generate one or more photonic chip designs to be fabricated by the fabrication unit 102. Similarly, the processor 110 may execute an optimization routine that causes the controller 106 to optimize one or more process parameters during fabrication. The process parameters include plasma chamber control settings, which may include RF power and chamber pressure, depending on the type of plasma chamber used.

[0091] In other embodiments, hardware modules (not shown) may be implemented rather than the software modules 112 executed by the processor 110. The hardware modules may be internal or external to the controller 106. In other embodiments, a combination of software and hardware modules may also be used.

[0092] In some embodiments, instead of having a controller 106 that provides instructions and commands to the fabrication unit 102 and the testing unit 104, each of these units may include a local controller that controls the operation of the respective unit. For example, a first local controller associated with the fabrication unit 102 may control the fabrication process, while a second local controller associated with the testing unit 104 may control the tests to be performed on the photonic chip. In these embodiments, the first controller may be configured to communicate with the second controller. Other embodiments may include the controller 106 and one or more local controllers.

[0093] Further details of how the controller 106 operates in various exemplary embodiments are provided below.

[0094] 2, a statistical distribution of devices on a photonic chip according to performance metric is shown and is generally identified by the reference numeral 200. The performance metric of interest generally depends on the type of device. For example, the performance metric of interest for an optical cavity device may be the cavity resonance wavelength or resonance frequency.

[0095] As previously mentioned, due to systematic and statistical variations inadvertently introduced during fabrication, a photonic chip may end up in a state where its optical performance is upstream (exceeding) or downstream (falling short of) its intended optimal optical performance. Figure 2 illustrates a scenario where the photonic chip is initially in an offset state 202 that is upstream of an optimal state 204. As used herein, the term optimal state 204 refers to a state where the value of the performance metric of each device on the photonic chip is optimal, and the term offset state 202 refers to a state where the value of the performance metric of each device exceeds the value of the optimal state 204.

[0096] As can be seen, in the offset state 202, the performance metric distribution of the devices on the photonic chip is described by a bell curve. The devices are classified into bins A, B, C, D, E, F or G based on their performance metrics. Each bin A, B, C, D, E, F or G is associated with a performance deviation 206, 208, 210, 212, 214, 216 and 218, respectively, that defines the amount of trimming that needs to be applied to bring the device to the optimum state 204. In other words, the performance deviations 206, 208, 210, 212, 214, 216 and 218 are used when calculating one or more parameters to be applied when performing the trimming method described below.

[0097] As will be appreciated, one or more additional offset states may exist between the offset state 202 and the optimum state 204. In such an embodiment, the trimming method is applied in a stepwise manner with multiple trimming cycles, such that each trimming iteration brings the device closer to the optimum state 204. One or more of these offset states may be pre-provisioned or dynamically generated based on the details of the photonic chip. A table of offset states may be stored in the database 114 of the controller 106.

[0098] Although shown here as having a common optimum state 204, bins A, B, C, D, E, F, and G may each have an associated optimum state that is unique to each bin. This may or may not translate to each bin having a different performance deviation. As will be appreciated, the trimming method described below is independent of whether the devices on the photonic chip have a common optimum state (as shown in FIG. 2) or different optimum states. Similarly, although offset state 202 is defined as being upstream of optimum state 204, it may be downstream of optimum state 204 such that the value of the performance metric of each device at offset state 202 is less than the value at optimum state 204.

[0099] The method of trimming a photonic chip described below applies to photonic chips fabricated in an offset state. The photonic chip may be fabricated in an offset state, either intentionally or inadvertently, as described above. The method of trimming a photonic chip disclosed herein uses a resist pattern and a plasma of a reactive gas to selectively and controllably convert portions of the core of the device to a different material, which may or may not be removed after final fabrication. Converting portions of the core to a different material constitutes a change in the structure of the device, thus changing its optical functionality and / or performance. Using the resist pattern to selectively expose certain portions of the core of the device to a controlled plasma process allows the performance of the device to be fine-tuned toward an optimum state through one or more trimming iterations.

[0100] It should be noted that depending on the device, the optimum state may fall within the expected distribution, and depending on the details of the patterned resist and process parameters applied, the device may be treated using a plasma of reactive gases to shift the value of the device's performance metric in the desired direction. Although only one performance metric is shown in FIG. 2, the device may be biased across multiple performance metrics. Any of these numbers may be used as a basis for trimming the device toward a target functionality. It is also understood that multiple devices on a single photonic chip / wafer may each have a different optimum state, and may or may not be designed within initial goals that take into account eventual differences. In some embodiments, different devices with different optimum states undergo the same initial fabrication process, but are individually trimmed in different ways as needed.

[0101] 3, a flowchart describing a method for trimming a photonic chip is shown and generally identified by the reference numeral 300. The steps of the flowchart are not limited to the exact order shown, and in other embodiments, steps shown may be omitted or other intermediate steps may be added. In this embodiment, the processor 110 executes one or more software modules 112 to cause the controller 106 to perform the steps shown.

[0102] As can be seen, the process begins at step 302, where a photonic chip is fabricated in an offset state, such as offset state 202 depicted in FIG. 2. In the offset state, a performance metric of one or more devices on the photonic chip has a value that is greater than or less than a predetermined / desired optimum value. In some embodiments, the photonic chip is intentionally fabricated in an offset state. This may be achieved by tuning one or more parameters during design and / or fabrication to place the photonic chip in an offset state. For example, a bias may be applied to a particular geometric dimension.

[0103] In step 304, the controller initiates chip testing. Testing may include inspecting the physical structure of the photonic chip under a microscope and / or measuring the optical performance of the photonic chip. Testing may further include testing one or more devices on the photonic chip to determine performance deviations of the device. The performance deviations are determined by optical characterization of the device. The type of testing performed generally depends on the type of device and the performance metrics of interest. For example, the device may be measured for its optical functionality according to one or more performance metrics. In some embodiments, the device is substantially perfect, e.g., no additional material or cladding is required to finalize the fabrication. In such embodiments, testing 304 is performed by measuring the device. In other embodiments, the device is incomplete and requires additional material or cladding to reach its final form. In these embodiments, testing may include first temporarily coating the device to simulate the performance the device is expected to have in its final form, followed by measuring the device. This temporary coating may include adding a temporary material to the device that is later removed. The temporary material may possess similar optical properties as the permanent material that is expected to be added to the device. For example, if additional cladding is planned, the temporary material may have a refractive index that matches the refractive index of the material that will be added during the additional cladding. The structure and dimensions of the temporary material may be approximately the same as the material that will be added during the additional cladding. In some embodiments, this involves spin-coating an index-matching material (resist or similar material) onto the device and baking the photonic chip to remove the solvent in the spin-coated material prior to measurement. It should be noted that materials such as resist or index-matching liquid are well suited for use as temporary materials compared to harder options such as silicon dioxide that are not as easy to remove. After the test 304 is completed, the temporary material may be removed, for example, by a suitable solvent, before proceeding to other steps.

[0104] In step 306, results from the tests performed in step 304 are used to identify the type and / or magnitude of performance deviations and determine trimming patterns and process parameters. This is accomplished by providing the results as inputs to algorithms and / or via information contained in look-up tables. The performance deviations are used to determine the trimming direction and amount required to bring the devices to their optimum state. The trimming is controlled to either completely correct the devices or to bring the performance of the devices closer to the optimum state, as in the iterative embodiment described below. Determining the trimming pattern may further include determining the size, shape and location of one or more areas in each of the devices where the trimming pattern is used to mask the trimming in a controlled manner. The resulting trimming pattern is exported as a design layer similar to other design layers typically used in photonic chip design. Similarly, determining the process parameters may include determining a suitable reactive gas for trimming and / or determining one or more process parameters for treating the devices with a plasma of the reactive gas. The process parameters are stored or provided to ensure correct operation of equipment used in performing the plasma treatment process.

[0105] In some embodiments, the process parameters are not determined in step 306 but are instead predetermined. In such cases, the parameters constitute fixed conditions that the algorithm can use when determining the size and location of the openings in the trim pattern resist that will result in the desired modification. In other embodiments, in addition to the process parameters, certain constraints on the resist pattern are also predetermined. One example is preset openings that are constrained by a fixed length but have widths that can be changed depending on the performance. In such embodiments, only a finite number of control variables (e.g., the width of the openings) are changed and optimized by the algorithm.

[0106] As will be appreciated, some devices may require multiple trimming iterations to correct the performance deviation. In these embodiments, the controller determines the number of trimming iterations required to correct the performance deviation and the performance tolerance for each iteration based on the performance iterations. For example, the controller may determine that three trimming iterations are required to correct the performance deviation of a particular device and may generate a performance tolerance for each one of the three trimming iterations. The first trimming iteration may be a coarse iteration and therefore may have the largest performance tolerance, while the third trimming iteration, being the finest iteration, may have the smallest performance tolerance. In some embodiments, each subsequent trimming iteration has a smaller performance tolerance than the preceding trimming iteration.

[0107] In step 308, a resist pattern is applied using the trimming pattern determined from step 306. The resist pattern is applied by coating the photonic chip with a photoresist or electron resist and using a lithography tool to expose the trimming pattern. The resist is then developed to obtain openings in the resist in the trimming pattern.

[0108] The treatment process involves exposing the photonic chip to a plasma of a reactive gas, such as an oxygen plasma and / or a nitrogen plasma, to convert the core material exposed by the openings in the resist while the resist prevents conversion elsewhere. In some embodiments, the plasma is a plasma of a reactive gas (e.g., oxygen or nitrogen) mixed with a non-reactive gas (e.g., an inert gas such as argon).

[0109] For example, the plasma may be of a mixture including 15% to 50% oxygen and 50% to 85% argon by weight. The inclusion of a non-reactive gas in the plasma advantageously allows the plasma to erode the mask (patterned resist) less while converting the exposed core material to a given depth. For example, a plasma mixture including 15% to 50% oxygen and 50% to 85% argon by weight improves the selectivity of core material conversion vs. mask erosion by up to 40% over a pure oxygen plasma. The increased selectivity achievable with a plasma based on a gas mixture may enable the use of a thinner mask and / or application of a longer plasma duration and / or higher plasma energy for a given mask thickness. In proof-of-principle experiments, it has been found that a mass fraction of argon towards the higher end of the range of 50 to 85% provides better results while allowing a stable plasma to be maintained.

[0110] The mask erosion selectivity of a plasma based on a particular gas mixture for transforming a core material may be measured, for example, by exposing two samples, one covered with resist and the other bare silicon, to the plasma for a given time and measuring the resist thickness and silicon thickness of the samples before and after exposure to the plasma. The ratio of the silicon thickness reduction to the resist thickness reduction caused by the exposure may be used as a measure of selectivity.

[0111] While the inventors do not wish to be bound by any particular theory of operation, it is believed that the ions of the non-reactive gas physically break down oxides that tend to form on exposed core materials during the process, thereby expanding the depth to which the core material can be converted before any saturation occurs, and potentially reducing the time required to convert the core material to a given depth. Additionally, the inclusion of a non-reactive gas reduces the concentration of oxygen ions in the plasma, which may also reduce the rate at which the mask material is etched, especially if the material of the mask is oxygen sensitive (e.g., a soft polymer mask material). In some embodiments, the mask is made of a soft polymer mask material.

[0112] This process is performed using the process parameters determined in step 306 (or predefined parameters, if applicable) to apply the required amount of trimming to the device, i.e., converting the exposed core material to a different material to a desired thickness or depth, whereby the opening in the resist adjusts the shape and / or size of the plasma-exposed core material structure by converting the core material that defines the device to a different material that defines its immediate surroundings, which may or may not match any additional material or subsequent cladding material that is added in further fabrication steps.

[0113] The trim depth of the plasma treatment process is determined globally by the plasma parameters (e.g. RF power, chamber pressure, exposure time) used according to the designed process parameters. Thus, a lower depth level may be used for a fine trimming process and a higher depth level may be used for a coarse trimming step. The magnitude of the trimming effect is also determined locally by the design of the resist opening.

[0114] In general, the trimming accuracy depends on the accuracy (controllability) of the oxidation or nitridation depth, the accuracy of defining the opening in the resist, and the accuracy of aligning the resist opening with the original structure on the wafer. Setting a small oxidation or nitridation depth process can reduce the trimming range, even though it cannot change the magnitude of the resist lithography error. Therefore, the smaller the oxidation or nitridation depth, the smaller the trimming range, and therefore the higher the trimming accuracy. This can be used to design iterative trimming steps to improve the final accuracy of the device.

[0115] In step 312, one or more optical properties of the photonic chip are measured. This may include measuring the performance of individual devices on the photonic chip. The photonic chip may be temporarily coated and tested as necessary. The temporary coating may be removed after testing in a manner substantially similar to step 304.

[0116] In step 314, the controller determines whether the measured optical characteristics are within a predetermined range and / or meet the acceptance criteria / specifications. This includes determining whether the performance metrics of one or more devices on the chip are within a predetermined performance tolerance range. In some embodiments, the acceptance criteria are used to determine whether the photonic chip is acceptable in terms of absolute performance. In such cases, the acceptance criteria may further include the number of trimming iterations performed on the photonic chip, and / or how much the performance of each device on the photonic chip has improved from a previous iteration or compared to a predetermined expected or desired amount, etc. If the device is determined to be acceptable, control proceeds to step 320; otherwise, control proceeds to step 316 to store the data set.

[0117] In step 316, the controller stores a data set from the measurements of the photonic chip that determined one or more optical properties to be outside of a predetermined range. The stored data set may be used to optimize one or more fabrication processes and / or subsequent trimming operations.

[0118] In step 320, the controller determines whether trimming is complete. Trimming is complete when the number of trimming iterations generated by the controller is complete. If there are trimming iterations that are not yet completed, control returns to step 308 to generate patterned resist for the next trimming iteration. Each trimming iteration can be more accurate than the preceding trimming iteration. For example, the first trimming iteration can be coarse, while subsequent iterations can be more accurate. This is achieved by varying the process parameters (including the type of reactive gas), the shape and / or size of the openings in the resist, or both, during each trimming iteration.

[0119] In step 322, the controller finalizes the fabrication, which may include removing resist and / or applying cladding.

[0120] It should be noted that typical commercially available plasma chambers can perform the required plasma treatment process without any modification. These chambers are typically used for common applications such as descumming, ashing, etching, cleaning, and surface activation / treatment. It should also be understood that the reactive gases that may be advantageously used in the plasma treatment process depend on the core and surrounding materials and associated chemistries in the device. For example, in the common context of devices utilizing silicon as the core material, oxygen may be used for plasma treatment purposes. In such cases, the conversion includes the oxidation of silicon to produce silicon dioxide. It should be noted that both oxygen and nitrogen are typical reactive gases used in plasmas in typical plasma chambers, and both may be used to trim silicon core devices on SOI platforms.

[0121] It should be noted that the oxidation of silicon by oxygen plasma treatment process is a self-terminating process. This process means that as the oxide grows under oxygen plasma, the presence of the oxide on the surface inhibits further oxidation by acting as a barrier for the plasma to reach further silicon. As a result, the curve of the amount of oxidation versus oxidation time tends to saturate and changes similarly to a logarithmic curve. This means that for sufficiently long plasma exposure, the ultimate amount of silicon oxidation is not sensitively dependent on the initial plasma conditions. Self-termination also makes the oxidation rate particularly slow (e.g., less than 0.03 nm / sec) after a sufficiently long exposure (e.g., more than 30 seconds), so that the amount of silicon oxidation is not sensitively dependent on the length of time the plasma is applied. Another advantage that self-termination provides is the uniformity of the oxidation depth over a large wafer surface. Yet another advantage of self-termination is that the extra roughness that oxidation can induce in silicon is negligible. All these properties help make plasma oxidation clean and controllable with sub-nm precision. Such levels of repeatability and precession are not typically provided by plasma etching methods where the etching by-products are volatile gases and self-termination does not occur. Like plasma oxidation, plasma nitridation offers similar advantages.

[0122] It should be noted that oxygen plasma is widely used in nanofabrication to descum organic materials and residues. As mentioned above, the oxidation of silicon by plasma is a self-terminating process, so descum typically does not oxidize silicon deeper than 1-2 nm. This self-terminating oxidation of silicon is ideal for descum since the descum is only intended to remove unwanted material residues (such as residual photoresist) from the silicon wafer. Descum is not intended to actively transform silicon material to any appreciable extent, let alone an amount that would change the structure or function of silicon core devices. It should be noted that the typical depth of silicon dioxide that descum processes typically produce, 1-2 nm, is not high enough to be of practical use in trimming methods.

[0123] In contrast to typical descum processes, the present method utilizes a plasma treatment process in which the pressure in the plasma chamber is lower than that typically used in descum. This lower pressure, along with an increase in RF power applied to the chamber, can increase ion acceleration toward the silicon. This can advantageously increase the oxidation depth to levels beyond those typically expected or desired from a descum process. The 1 to 2 nm achievable by the descum process is typically not high enough to achieve a reasonably deep desired trim depth, which can be as deep as 10 nm, for example.

[0124] Oxygen and / or nitrogen plasmas are also used for dry etching applications, however, dry etching processes typically involve corrosive plasma etchants such as fluorine or chlorine. These processes are intended for material removal, rather than material conversion and preservation. As a result, such dry etching approaches are not self-terminating and generally cannot be controlled or repeated to the precision required by trimming processes.

[0125] Current plasma oxidation or nitridation processes offer two major advantages over the use of "dry etching" of silicon. The first advantage is that the oxidation or nitridation depth is highly repeatable to an accuracy of about 0.1 to 0.3 nm. In contrast, the depth resulting from dry etching is not considered repeatable. This repeatability is necessary for successful trimming; otherwise, the device will experience trimming that differs from the predicted / calculated value. The second advantage is that plasma oxidation or nitridation does not increase or decrease the surface roughness of silicon devices. In contrast, dry etching can increase surface roughness substantially. Increased roughness can significantly degrade optical performance by scattering guided light.

[0126] An additional advantage of the above described method for trimming a photonic chip will now be described.

[0127] Therefore, the method can be applied to silicon photonic chips with precision using existing machinery, unlike other trimming processes that require non-standard equipment.

[0128] Second, the lithography step resulting in the patterned resist can be performed using a high-speed direct writer, and the plasma treatment process can be applied to the entire wafer. In other words, the plasma treatment process can be applied to all devices on the wafer simultaneously. Thus, the method of trimming photonic chips described herein maintains a high throughput compared to known processes.

[0129] Third, plasma application at high ion acceleration (high RF power and / or low chamber pressure) results in a directional process. This means that the top surface is oxidized deeper than the vertically etched silicon walls typically produced by dry etching processes. This directionality is not present in some of the reviewed processes mentioned above. The directionality of the trimming method disclosed herein not only helps to simplify the algorithms that calculate the trimming parameters, but also helps to achieve the required accuracy.

[0130] Fourth, the method can be tuned for accuracy depending on the details of the device and process design. The trimming accuracy depends mainly on two factors: the accuracy of the opening (shape and placement) in the resist, and the accuracy with which the trimming saturation can be controlled. Standard lithography gives the accuracy of the opening definition, i.e. where the silicon will be processed, and the accuracy of the plasma oxidation or nitridation process gives the accuracy of the depth of the silicon conversion.

[0131] Fifth, the method can be performed at relatively low temperatures that reduce the potential for damage to devices on the photonic chip. The maximum temperature experienced by the devices during the trimming operation is significantly lower than typical resist lining steps, approximately 180° C. or less, which is not routinely considered high temperature in chip manufacturing.

[0132] Sixth, the method does not induce strain in the device silicon layers and does not add extra layers of material to the photonic chip, so there is nothing extra on the device to cause strain changes.

[0133] Seventh, this method can be used to provide different trims for different devices sharing a photonic chip and / or wafer: devices requiring different trims can each have their own opening in the resist.

[0134] Eighth, the method does not introduce additional photonic losses caused by absorption or scattering from the deposited materials as used in other known processes. Because the method does not add material to the device but instead transforms the device, there is no additional absorption or scattering due to the presence of many materials with which the optical field interacts. Furthermore, the plasma treatment process described herein maintains and / or reduces the original device surface roughness, so there is no increase in scattering losses. Although interfaces between oxidized and non-oxidized surfaces (or nitrided and non-nitrided surfaces) may cause additional scattering, this contribution is taken into account when generating the trimming pattern and / or when designing the photonic chip.

[0135] An exemplary application of the method of trimming a photonic device disclosed herein is described below with reference to FIG. 4. In this embodiment, the photonic device is a nanobeam cavity device 400. The nanobeam cavity device 400 includes a silicon structure 402 having a plurality of etched holes 406. The silicon structure 402 is surrounded by a silicon dioxide material 404. A resist opening 410 in the trimming pattern resist exposes an overlap area 412 between the trimming pattern and the edge of the silicon structure 402. The overlap area 412 is inversely proportional to a parameter X defined as the distance between the edge of the resist opening 410 and the horizontal bisector of the holes 406 etched in the silicon structure 402.

[0136] In this example, the nanobeam cavity device 400 is tuned to exhibit a desired resonance by converting a portion of the silicon structure 402 to silicon dioxide. This is accomplished by subjecting the overlap area 412 to the plasma treatment process described in Figure 3 using oxygen plasma as the reactive gas. The plasma treatment process results in depletion of the edges of the silicon structure 402 as the portion of the silicon structure 402 is converted to silicon oxide by oxidation, thus resulting in a change in the resonant wavelength of the nanobeam cavity device.

[0137] A simulated trimming curve of the resonant wavelength of the nanobeam cavity device 400 as a function of the parameter X is shown in Figure 5. As can be seen, the resonant wavelength increases with X as a portion of the silicon structure 402 is converted to silicon oxide. A significant change in the slope of the graph at X=8E-08m occurs when the plasma treatment process reaches the perimeter of the hole 406 etched in the silicon structure 402.

[0138] With reference to FIG. 6, another exemplary application of the method of trimming a photonic device disclosed herein is described below. In this embodiment, the photonic device is a microring device 600. The microring device 600 includes a ring silicon structure 602 surrounded by a silicon dioxide material 604. The trimming method of FIG. 4 is applied to tune the microring device 600 to exhibit a desired resonance. A resist opening 610 in the trimming pattern resist exposes an overlap area 612 between the trimming pattern and a portion of the silicon ring structure 602. When the silicon in the overlap area is subjected to a plasma treatment described herein, a portion of the silicon is converted to a different material. For example, when the plasma treatment is performed using oxygen as a reactive gas, a portion of the silicon structure 602 in the overlap is oxidized to silicon dioxide, thus effectively trimming a dimension of the silicon structure 602. In this example, the depth of two segments of the side of the silicon ring structure 602 is effectively reduced. The magnitude of the trim and resonant wavelength shift varies with the plasma exposure parameters and the amount of overlap 612 , which depends on the width 614 of the resist opening 610 .

[0139] Although the specific example of the plasma treatment process has been described in the context of oxygen plasma applied to silicon to produce silicon dioxide, it is believed that other types of reactive gases may be utilized as plasma during trimming and fall within the scope of the general method described above. For example, other plasma processes may include, but are not limited to, nitrogen plasma treatment. The methods and teachings disclosed above are equally valid for nitrogen plasma, but instead of oxidation, nitridation occurs. As mentioned above, nitrogen is a gas that is commonly available in plasma chambers. The advantage of nitrogen plasma over oxygen plasma is that it does not etch masking resist as quickly as oxygen plasma. Thus, a thinner resist can be used, and the thinner the resist, the smaller the minimum feature size of the trimming window.

[0140] It should be noted that the silicon-SiO2 interface is cleaner than the Si-silicon nitride interface, which is important for some devices, and in the case of nitride, the exact composition of the nitride layer is ambiguous. The device design and requirements should be factored into the selection of the plasma used for plasma processing according to the above, whether oxygen, nitrogen, or other plasma is used.

[0141] Although specific examples of the trimming systems and methods have been described in the context of SOI-based photonic chips, it should be understood that plasma treatment processing according to the above systems and methods is also contemplated for other photonic platforms, including silicon nitride and the like. The plasma treatment process generally converts the primary optical signal guide or core material of the photonic device into a different material that remains in the photonic device, i.e., is not removed during plasma processing. The different material is often similar, and in some embodiments the same, as the cladding material that surrounds the core material in the photonic device after fabrication. In general, this approach trims the photonic device by tuning the dimensions of the core material.

[0142] A controller for all or a portion of the systems described herein may be implemented in any of a variety of ways, which may include specially designed hardware, configurable hardware, a programmable data processor configured by providing software (which may optionally include "firmware") executable on a data processor, a special purpose computer or data processor executable on a data processor, a special purpose computer or data processor that is specially programmed, configured, or constructed to perform one or more steps in the methods detailed herein, and / or a combination of two or more of these. Examples of specially designed hardware are logic circuits, application specific integrated circuits ("ASICs"), large scale integrated circuits ("LSIs"), very large scale integrated circuits ("VLSIs"), etc. Examples of configurable hardware are one or more programmable logic devices, such as programmable array logic ("PALs"), programmable logic arrays ("PLAs"), and field programmable gate arrays ("FPGAs"). Examples of programmable data processors are microprocessors, digital signal processors ("DSPs"), embedded processors, graphics processors, math co-processors, general purpose computers, process controllers, server computers, cloud computers, mainframe computers, computer workstations, etc. For example, one or more data processors in control circuitry of the systems described herein, or of components of the systems, may implement the methods described herein by executing software instructions in program memory accessible to the processor.

[0143] The controller may include multiple components, either co-located or distributed.

[0144] Some aspects of the present technology are provided in the form of a program product. The program product may include any non-transitory medium carrying a set of computer-readable instructions that, when executed by a data processor, causes the data processor to perform the method of the present invention. The program product of the present invention may be in any of a wide variety of forms. The program product may include, for example, a non-transitory medium such as a magnetic data storage medium including a floppy disk, a hard disk drive, an optical data storage medium including a CD ROM, a DVD, an electronic data storage medium including a ROM, a flash RAM, an EPROM, a hard-wired or pre-programmed chip (e.g., an EEPROM semiconductor chip), a nanotechnology memory, etc. The computer-readable signals on the program product may be optionally compressed or encrypted.

[0145] In some embodiments, the invention may be implemented in software. For the sake of clarity, "software" includes any instructions executed on a processor, and may include, but is not limited to, firmware, resident software, microcode, code for configuring configurable logic circuits, applications, apps, etc. Both the processing hardware and software may be centralized or distributed (or a combination thereof) in whole or in part, as known to those skilled in the art. For example, the software and other modules may be accessible via local memory, a network, a browser or other application in a distributed computing context, or other means suitable for the purposes described above.

[0146] While particular implementations and applications of the present disclosure have been illustrated and described, it should be understood that the disclosure is not limited to the precise construction and compositions disclosed herein, and various modifications, changes and variations may become apparent from the foregoing description without departing from the spirit and scope of the invention as defined in the appended claims.

[0147] When a component (e.g., a software module, processor, assembly, device, circuit, etc.) is referred to herein, unless otherwise indicated, a reference to that component (including a reference to a "means") should be interpreted as including any component that performs the function of the described component (i.e., is functionally equivalent) as an equivalent of that component, including components that are not structurally equivalent to the disclosed structures that perform the functions in the illustrated exemplary embodiments of the present invention. Interpretation of Terms

[0148] Unless the context clearly indicates otherwise, throughout the specification and claims: "including", "comprises", and the like, are to be construed in their inclusive sense, i.e., "including but not limited to," as opposed to their exclusive or exhaustive sense; "Connected," "coupled," or variations thereof means a connection or coupling between two or more elements, whether direct or indirect, and the coupling or coupling between such elements may be physical, logical, or a combination thereof; The words "herein," "above," "below," and similar words, when used to describe this specification, shall refer to this specification as a whole and not to specific portions of this specification; "Or", when referring to a list of two or more items, covers all of the following interpretations of that word: any of the items in the list, all of the items in the list, any combination of the items in the list; The singular forms "a", "an", and "it" or "the" include any appropriate plural meanings, and these terms ("a", "an", "it" and "the") refer to one or more unless otherwise specified; "And / or" is used to indicate that one or both of the stated cases may occur, e.g., A and / or B includes both (A and B) and (A or B); "Approximately" when applied to a numerical value means ±10% of the numerical value; When a feature is described as being "optionally" or "optionally" present, or as being present "in some embodiments," the disclosure is intended to encompass embodiments in which the feature is present, other embodiments in which the feature is not necessarily present, and other embodiments in which the feature is excluded. Furthermore, when any combination of features is described in this application, this description is intended to serve as antecedent for the purposes of using exclusive language such as "solely," "only," and the like with respect to the combination of features, and the use of "negative" limitations to exclude the presence of other features. "First" and "second" are used for descriptive purposes and shall not be understood as indicating or implying a relative importance or as indicating the number of technical features indicated.

[0149] Directional terms such as "vertical," "transverse," "horizontal," "upper," "lower," "forward," "rearward," "inward," "outward," "left," "right," "front," "rear," "top," "bottom," "lower," "top," and the like are used in this specification and the appended claims (if any) in accordance with the particular orientation of the device described and illustrated. The subject matter described herein may assume a variety of alternative orientations. Thus, these directional terms are not precisely defined and should not be interpreted in a narrow sense.

[0150] When a range of values ​​is described, the described range includes all subranges of the range. The description of a range is intended to support the values ​​at the endpoints of the range, and any intermediate values ​​to the tenths of the unit of the lower limit of the range, as well as any subrange or collection of subranges of the range, unless the context clearly indicates otherwise or any part of the described range is specifically excluded. When a described range includes one or both of the endpoints of the range, ranges excluding either or both of those included endpoints are also included in the invention.

[0151] Specific numerical values ​​described herein are preceded by the word "about." In this context, "about" gives literal support for the exact numerical value it precedes, the exact numerical value plus or minus 5%, and all other numerical values ​​that are close to or approximately equal to that numerical value. Unless otherwise indicated, a specific numerical value is included within "about" the specifically recited numerical value if, in the context in which the specifically recited numerical value is presented, the specific numerical value is substantially equivalent to the specifically recited numerical value. For example, a statement that something has a numerical value of "about 10" should be interpreted as the set of the following statements: In some embodiments, the number is 10; In some embodiments, the value is in the range of 9.5 to 10.5; and If from the context one of ordinary skill in the art would understand a value within a particular range to be substantially equivalent to 10, since values ​​having that range would be understood to give substantially the same results as the value 10, then "about 10" also includes the following: In some embodiments, the numerical values ​​range from C to D, where C and D are the lower and upper endpoints, respectively, of a range that includes all values ​​substantially equivalent to the value 10.

[0152] Specific examples of systems, methods, and devices are described herein for illustrative purposes. These are examples only. The techniques provided herein may be applied to systems other than the exemplary systems described above. Many variations, modifications, additions, omissions, and permutations are possible within the scope of the practice of the invention. The invention includes variations of the described embodiments that will be apparent to those skilled in the art. This includes variations obtained by replacing features, elements, and / or operations with equivalent features, elements, and / or operations, by mixing and matching features, elements, and / or operations from different embodiments, by combining features, elements, and / or operations from the embodiments described herein with features, elements, and / or operations of other technologies, and / or by omitting combining features, elements, and / or operations from the described embodiments.

[0153] As will be apparent to those skilled in the art upon reading this disclosure, each of the individual embodiments described and illustrated herein has separate components and features that may be readily separated from or combined with the features of any other described embodiment without departing from the scope of the invention.

[0154] Any aspect described herein with respect to an apparatus can be applied to the method, and vice versa.

[0155] Any described method may be performed in the order of events described or in any other order that is logically possible. For example, while processes or blocks are presented in a given order, alternatives may perform routines or use systems having blocks in a different order, and some processes or blocks may be deleted, moved, added, subdivided, combined, and / or modified to provide alternatives or subcombinations. Each of these processes or blocks may be implemented in a variety of different ways. Further, while processes or blocks may be shown as being performed in serial, these processes or blocks may instead be performed in parallel, concurrently, or at different times.

[0156] Various features are described herein as being present in "some embodiments." Such features are not required and may not be present in all embodiments. An embodiment of the invention may include zero, any one, or any combination of two or more of such features. All possible combinations of such features are contemplated by the present disclosure, even if such features are shown in different drawings and / or described in different sections or paragraphs. This is limited only to the extent that certain of such features are incompatible with other of such features, in the sense that it would be impossible for a person of ordinary skill in the art to construct a practical embodiment combining such incompatible features. Thus, a statement that "some embodiments" have feature A and "some embodiments" have feature B should be interpreted as explicitly indicating that the inventors also contemplate embodiments combining feature A and feature B (unless the description states otherwise or feature A and feature B are essentially incompatible). This is true even if feature A and feature B are shown in different drawings and / or described in different paragraphs, sections, or sentences.

[0157] Accordingly, it is intended that the following appended claims and the claims introduced below be construed to include all such modifications, permutations, additions, omissions, and subcombinations that can reasonably be inferred. The claims should not be limited by the preferred embodiments set forth in the examples, but should be accorded the broadest interpretation consistent with the description as a whole.

Claims

1. 1. A method for trimming an integrated photonic device, comprising: generating one or more trimming patterns based on optical measurements of the photonic device; providing a patterned resist on the photonic device based on the one or more trimming patterns; trimming the photonic device to adjust a performance metric of the photonic device; A method comprising:

2. The method of claim 1 , wherein the photonic device includes a core, and the trimming includes converting a portion of the core from one material to another material.

3. The method of claim 2, wherein the trimming includes exposing the photonic device to a plasma of a reactive gas.

4. The method of claim 3 , wherein the core is a silicon core.

5. The method of claim 3 , wherein said trimming comprises converting said portion of said core to silicon nitride.

6. The method of claim 3 , wherein said trimming comprises converting said portion of said core to silicon dioxide.

7. The method of claim 1 , wherein generating the one or more trimming patterns is further based on a target optical performance for the photonic device.

8. 2. The method of claim 1, comprising fabricating the photonic device in an offset state, wherein a value of the performance metric in the offset state is different from a predetermined optimum value of the performance metric in an optimum state, and wherein said trimming causes the value of the performance metric to approach the predetermined optimum value of the performance metric.

9. generating one or more process parameters based on the optical measurements; performing said trimming using said one or more process parameters; The method of claim 1 , comprising:

10. the photonic device is one of a plurality of photonic devices fabricated on a common substrate; 10. The method of claim 1, wherein the method includes performing the steps of the method for each of the plurality of photonic devices, and wherein at least the step of trimming the photonic device to adjust the performance metric of the photonic device is performed simultaneously for multiple photonic devices.

11. 1. A system for trimming one or more photonic devices of a photonic chip, comprising: The production unit and a system controller communicatively coupled to the fabrication unit; Including, The system controller causing the fabrication unit to fabricate the photonic chip such that the one or more photonic devices are offset; generating one or more trimming patterns based on optical performance of the one or more photonic devices and a first target optical performance for the one or more photonic devices of the photonic chip; providing a patterned resist on the photonic chip based on the one or more trimming patterns; trimming the one or more photonic devices of the photonic chip; A system configured to:

12. 12. The system of claim 11, wherein the first target optical performance is a predetermined optimum optical performance of the one or more photonic devices, a performance metric of the one or more photonic devices having a predetermined optimum value.

13. 13. The system of claim 12, wherein the offset state is a state in which the value of the performance metric in the offset state differs from the predetermined optimum value, and wherein the trimming brings the value of the performance metric closer to the predetermined optimum value.

14. 12. The system of claim 11, further comprising a test unit communicatively coupled to the fabrication unit and the system controller, the test unit configured to perform optical characterization of the one or more photonic devices on the photonic chip, thereby determining optical performance of the one or more photonic devices.

15. 12. The system of claim 11, wherein the system controller is configured to generate one or more process parameters based on optical measurements performed on the photonic chip and to control the trimming using the one or more process parameters.

16. The system controller may further configure the optical performance of the one or more photonic devices by: coating the one or more photonic devices with a fugitive material to obtain one or more coated photonic devices; optically measuring the one or more coated photonic devices; removing the temporary material prior to providing the patterned resist; 12. The system of claim 11, configured to determine by optically measuring the one or more photonic devices using steps comprising:

17. 17. The system of claim 16, wherein the temporary material has substantially the same refractive index as a material that will be added to the one or more photonic devices in a later step.

18. The system controller optically measuring the one or more photonic devices; generating one or more trimming patterns based at least on said optically measuring; providing a patterned resist on the photonic chip based on the one or more trimming patterns; trimming the one or more photonic devices to adjust a performance metric of the one or more photonic devices; configured to iteratively repeat The system of claim 11 , whereby the value of the performance metric of the one or more photonic devices is progressively brought closer to an optimal value of the performance metric of the one or more photonic devices.

19. 1. A system for trimming one or more photonic devices of a photonic chip, comprising: a system controller; A measurement unit; Plasma chamber and Including, The system controller obtaining optical measurements of optical properties of one or more photonic devices from the measurement unit; generating respective trimming patterns for the one or more photonic devices based on the optical measurements; controlling a fabrication unit to provide a patterned resist on the photonic chip based on the trimming pattern; trimming the one or more photonic devices by exposing the photonic chip to a plasma comprising a reactive gas selected from oxygen and nitrogen; A system configured to:

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