Manufacturing method and power semiconductor device

Abstract

In at least one embodiment, a method is for manufacturing a power semiconductor device (1) and comprises the following: providing a SiC-based semiconductor body (2); irradiating at least a first portion (21) of a top surface (20) of the semiconductor body (2) with low-energy electron radiation (E); and producing an electrically insulating layer (3) on the at least one irradiated first portion (21).

Description

[Technical field]

[0001] A manufacturing method for a power semiconductor device is provided. Additionally, a power semiconductor device is provided. [Background technology]

[0002] The documents US 2019 / 0296146 and US 2002 / 0034852 refer to semiconductor devices having differently doped regions. Summary of the Invention [Problem to be solved by the invention]

[0003] The problem to be solved is to provide a power semiconductor device having improved electrical behavior. [Means for solving the problem]

[0004] This object is achieved, inter alia, by a manufacturing method and a power semiconductor device as specified in the independent claims. Further exemplary embodiments are specified in the dependent claims.

[0005] For example, in the method described herein, the flat band voltage V FB Improve the oxide-SiC interface, e.g., SiO 2 Low-energy electron radiation is used to reduce carbon (C) defects at the Si / SiC interface.

[0006] In at least one embodiment, a method is for manufacturing a power semiconductor device, comprising, for example, the following, in the order listed: providing a semiconductor body based on a carbon-containing semiconductor material such as SiC; - irradiating at least a first portion of a top surface of the semiconductor body with low energy electron radiation; - producing an electrical insulating layer on at least one irradiated first portion; For example, the low-energy electron radiation has a kinetic energy of at least 116 keV and at most 210 keV, and the low-energy electron radiation in the at least one first portion causes the semiconductor body to be a Si semiconductor body after irradiating the at least one first portion. 0.5+x C 0.5-x wherein x is at least 0.001 and at most 0.1, said layer having a thickness of at least 10 nm and at most 0.2 μm, and the electrically insulating layer is produced by thermal growth.

[0007] Despite the high bulk mobility of SiC, low inversion channel mobilities μ have been reported in SiC metal-oxide-semiconductor field-effect transistors (MOSFETs), resulting in on-state resistances that are much higher than expected from the bulk SiC properties. This discrepancy is due to the fact that SiO 2 The density of interface states at the Si / SiC interface, D it This is due to the large SiO 2 / Si interface. D it The nature of the lattice structure is generally attributed to the presence of C-related defects and intrinsic oxide acceptor defects. The presence of carbon in the SiC epilayer is due to implantation during oxidation. The implanted C atoms form clusters that create acceptor levels close to the conduction band. These levels shorten the charge carrier lifetime and act as scattering centers, thus reducing μ.

[0008] To improve the electronic properties of SiC MOSFETs, SiO 2 / n-type 4H-SiC interface C defect concentration D it should be reduced.

[0009] In the methods described herein, SiO 2 Pre-oxidation low-energy electron irradiation is used to reduce defects at the / n-type 4H-SiC interface.

[0010] For n-channel MOSFETs, there are several D techniques such as post-oxidation annealing (POA) and pre-oxidation implantation (POI). it Various methods are possible to reduce N 2 O or POCl 3 The POA around either the junction of the SiC band gap or the POI due to the donor impurities N, P, or Sb creates a D band gap at the top of the SiC band gap. it Decrease in POA (10 11 cm -2 eV -1 , low 10 for POI 12 cm -2 eV -1 ) and increase in μ (90 cm for POA) 2 V -1 s -1 , 20cm for POI 2 V -1 s -1 ~100cm 2 V -1 s -1 ) results. D it The reason for the decrease in μ and the subsequent increase in μ has been explained in terms of N or P atoms passivating the C clusters, or in terms of counterdoping. Nevertheless, both POA and POI have some drawbacks, the concentration of incorporated N or P is difficult to control by POA, and SiO 2 The flat band voltage V due to the introduction of N, P or Sb in FB In addition, P is more easily incorporated into SiC than N, so that normally-on devices can be obtained.

[0011] One idea of ​​the present method is, inter alia, to detect C-poor, i.e., V C The use of low-energy electron irradiation to generate a vacancy-rich layer of C, also called a C-rich layer, which acts as a sink for C and results in improved V FB and SiO 2D at the / 4H-SiC interface it This results in a reduction in

[0012] V C To produce , low-energy electron irradiation with energies of, for example, 116 keV to 210 keV is used. This is due to the substitution of C atoms, i.e. V C In this way, virtually no other defects, either complex or Si-related, are formed, such as those that arise after impurity implantation or high-energy electron irradiation.

[0013] After irradiation, [V C ] increases, and the displaced carbon interstitial (C I ) atoms diffuse deep into the bulk by thermal annealing at, for example, at most 500 °C. I Although C is mobile even at room temperature, the heat treatment can prevent the C atoms substituted by irradiation from clustering during oxidation.

[0014] For Al-implanted n-type 4H-SiC epilayers, [V C ] is 6 x 10 15 cm -3 After dry oxidation at 1150°C for 2 hours, [V C ] is 3 x 10 15 cm -3 This is about 3 × 10 15 cm -3 [C I ] was injected during oxidation. This means that, for example, in a 65 nm thick SiO 2 Before the formation of C ] is, for example, at least 3 × 10 15 cm -3 In this way, a C-poor layer is formed, and most of the C is removed during oxidation. I is clustered and D it does not form.

[0015] The methods described herein can achieve, for example, the following advantages: 1. [V C can be controlled by varying the electron irradiation dose to capture the C atoms implanted during oxidation.

[0016] 2. Unlike POA or POI, impurities are not incorporated into the oxide. 3. In the case of POA, high annealing temperatures, for example about 1300° C., are not required.

[0017] 4. Unlike implantation of N, P, or Sb, no undesirable impurity-related complexes or other defects are produced.

[0018] 5. The absence of implanted donor impurities such as P near the surface prevents a normally-on state.

[0019] 6. In the final product, [V C Reverse engineering is possible by monitoring the ion exchange rate (OES) of the nuclei, by deep level transient spectroscopy (DLTS), by photoluminescence, or by performing constant capacitance deep level transient spectroscopy (CC-DLTS).

[0020] 7. Improved on-state resistance R ON , low D it It is possible to achieve this. According to at least one embodiment, the kinetic energy of the electrons of the low-energy electron radiation is at least 116 keV. Alternatively or additionally, this energy is at most 210 keV. This means, for example, that at least 90% or at least 99% or at least 99.9% of the electrons of the low-energy electron radiation have said kinetic energy. By having such an energy, the C atoms of the SiC lattice can be specifically addressed by the radiation to move away from the top surface.

[0021] According to at least one embodiment, the dose of low energy electron radiation in the first portion is at least 10 10 cm -2 Or at least 10 12 cm -2 Or at least 10 14 cm -2 Alternatively or additionally, the dose is at most 10 17 cm -2 or at most 10 16 cm -2 or at most 10 15 cm -2 It is possible that:

[0022] According to at least one embodiment, the electrically insulating layer comprises oxygen. For example, the electrically insulating layer is an oxide layer, in particular a metal oxide or a semiconductor oxide layer. The electrically insulating layer may be a stoichiometric oxide.

[0023] According to at least one embodiment, the electrically insulating layer is SiO 2 Otherwise, the electrical insulation layer is made of Al 2 O 3 , NO x , Y 2 O 3 , ZrO 2 , HfO 2 , La 2 O 3 , Ta 2 O 5 , or TiO 2 It may be made of

[0024] According to at least one embodiment, the electrical insulation layer is produced by thermal growth, for example in the gas phase, the constituents of the electrical insulation layer are provided, they are for example SiO 2 In the case of , Si and O. For example, the temperature during the manufacture of the electrically insulating layer is at least 600°C or at least 800°C or at least 1000°C. Alternatively or additionally, the temperature is at most 1500°C or at most 1300°C or at most 1150°C.

[0025] According to at least one embodiment, producing the electrically insulating layer includes annealing previously applied material of the electrically insulating layer, all or most of the material of the electrically insulating layer may have been applied to the top surface of the semiconductor body prior to annealing.

[0026] For example, the temperature during annealing of the electrically insulating layer is at least 200° C. or at least 300° C. or at least 400° C. Alternatively or additionally, the temperature is at most 1000° C. or at most 800° C. or at most 600° C. For example, the annealing takes at least 0.5 hours or at least 1 hour, and / or the annealing takes at most 12 hours or at most 4 hours. The temperature during annealing can be lower than during application of the material of the electrically insulating layer.

[0027] Optionally, at least one temperature gradient may be applied during annealing and / or thermal growth.

[0028] According to at least one embodiment, the annealing is performed in a nitrogen-containing atmosphere. For example, the annealing may be oxygen-free or substantially oxygen-free in a N 2 In atmosphere, or in air or N 2 O, NO, O 2 , or O 3 The same can be true for the thermal growth of an electrically insulating layer.

[0029] According to at least one embodiment, irradiating the at least one first portion can be oxygen-free or substantially oxygen-free, or in air or N 2 O, NO, O 2 , or O 3 The reaction is carried out in a nitrogen-containing atmosphere, which may be one of:

[0030] According to at least one embodiment, the top surface of the semiconductor body is a flat surface of the semiconductor body. Thus, the power semiconductor device may be of planar design.

[0031] According to at least one embodiment, the method further includes forming one or more trenches in the semiconductor body. For example, the at least one trench is formed in the semiconductor body prior to irradiating the at least one first portion. The at least one trench may be manufactured by etching. Thus, the resulting power semiconductor device may be a trench design device.

[0032] According to at least one embodiment, the at least one first portion includes a sidewall and a bottom surface of the at least one groove. The at least one first region can be confined to the sidewall and / or the bottom surface of the at least one groove.

[0033] According to at least one embodiment, the method includes applying a mask material to the top surface prior to irradiating the at least one first portion, the mask material can define an area of ​​the top surface that is irradiated, or the penetration depth of the low energy electron radiation into the semiconductor body can be adjusted for a specified material by the mask material or by a thickness of the mask material.

[0034] According to at least one embodiment, during irradiation of the at least one first portion, the at least one first portion is free of mask material, while the remaining part of the top surface is partially or completely covered by the mask material. If the penetration depth of the low-energy electron radiation into the semiconductor body is to be adjusted by the mask material also in the first portion, the at least one first portion can be partially provided with the mask material and can have a reduced thickness compared to other areas of the top surface. Even the entire at least one first portion can be covered with a thin layer of mask material.

[0035] It is also possible to use not just one but several different mask materials. According to at least one embodiment, the low energy electron radiation in the at least one first portion causes carbon atoms to migrate from the top surface into the semiconductor body. That is, after irradiating the at least one first portion, the semiconductor body can be non-stoichiometric SiC. That is, in this region, the semiconductor body is Si 0.5+x C 0.5-x where x may be at least 0.001 or at least 0.01 and / or x is at most 0.1 or at most 0.02. The layer may have a thickness of at least 10 nm or at least 100 nm. Alternatively or additionally, the thickness is at most 1 μm or at most 0.2 μm.

[0036] Further provided is a power semiconductor device, for example manufactured by the method as illustrated in relation to at least one of the above-described embodiments. Accordingly, features of the power semiconductor device are also disclosed in relation to the method and vice versa.

[0037] In at least one embodiment, a power semiconductor device comprises a SiC-based semiconductor body and an electrically insulating layer applied to at least a first portion of a top surface of the semiconductor body, adjacent the electrically insulating layer, the semiconductor body being silicon rich and therefore carbon poor, e.g., compared to stoichiometric SiC.

[0038] According to at least one embodiment, the power semiconductor device is a metal-insulator-semiconductor field-effect transistor (MISFET) or an insulated gate-bipolar transistor (IGBT).

[0039] According to at least one embodiment, the power semiconductor device is configured for an operating voltage of at least 0.6 kV or at least 1.2 kV. Alternatively or additionally, the power semiconductor device is configured for an operating voltage of at most 10 kV or at most 6 kV.

[0040] According to at least one embodiment, the power semiconductor device is configured for an operating current of at least 10 A, or at least 0.1 kA, or at least 1 kA. Alternatively or additionally, the power semiconductor device is configured for an operating current of at most 20 kA, or at most 5 kA.

[0041] According to at least one embodiment, the power semiconductor device is a device selected from the following group: metal-oxide-semiconductor field-effect transistor (MOSFET), insulated-gate bipolar transistor (IGBT), gate turn-off thyristor (GTO), gate commutated thyristor (GCT), and junction gate field-effect transistor (JFET).

[0042] Power semiconductor devices are configured to be used, for example, in electric motors to convert direct current, for example from a battery, into alternating current. Power semiconductor devices may also be used, for example, in vehicles, such as hybrid or plug-in electric vehicles, or in rail, such as commuter trains.

[0043] The method described herein and the power semiconductor device described herein are described in more detail below by way of example embodiments with reference to the drawings. The same elements in the individual figures are indicated by the same reference numerals. However, the relationship between the elements is not shown to scale, rather the individual elements may be shown exaggerated in size to aid understanding. [Brief description of the drawings]

[0044] [Figure 1] 3A-3C are schematic cross-sectional views of method steps of an exemplary embodiment of a method for manufacturing a power semiconductor device described herein. [Diagram 2] 3A-3C are schematic cross-sectional views of method steps of an exemplary embodiment of a method for manufacturing a power semiconductor device described herein. [Diagram 3] 3A-3C are schematic cross-sectional views of method steps of an exemplary embodiment of a method for manufacturing a power semiconductor device described herein. [Figure 4] 3A-3C are schematic cross-sectional views of method steps of an exemplary embodiment of a method for manufacturing a power semiconductor device described herein. [Diagram 5] 3A-3C are schematic cross-sectional views of method steps of an exemplary embodiment of a method for manufacturing a power semiconductor device described herein. [Figure 6] 3A-3C are schematic cross-sectional views of method steps of an exemplary embodiment of a method for manufacturing a power semiconductor device described herein. [Figure 7] FIG. 1 illustrates a comparison of voltage versus capacitance characteristics between an exemplary embodiment of a power semiconductor device described herein and a modified device. [Figure 8] FIG. 1 illustrates a comparison of CC-DLTS characteristics versus temperature between an exemplary embodiment of a power semiconductor device described herein and a modified device. [Figure 9] FIG. 1 illustrates a comparison of VGS vs. IGS characteristics between an exemplary embodiment of a power semiconductor device described herein and a modified device. [Figure 10]FIG. 1 illustrates a comparison of VDS vs. IDS characteristics between an exemplary embodiment of a power semiconductor device described herein and a modified device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0045] 1 to 3 show an example of a method for manufacturing a power semiconductor device 1. As shown in FIG. According to Fig. 1, a semiconductor body 2 is provided. The semiconductor body 2 is based on SiC. For example, the semiconductor body 2 comprises a substrate and at least one epitaxially grown semiconductor layer thereon (not shown), both based on SiC. The semiconductor body 2 has a flat upper surface 20.

[0046] For example, the semiconductor body 2 includes a well region 24, which may be n-type 4H-SiC. Additionally, there may be two p-type regions within the semiconductor body 2. These regions may be the source region 23 and the drain region 5 when the semiconductor body 2 is configured as a MOSFET.

[0047] According to Fig. 2, a first portion 21 of the semiconductor body 2 is irradiated with low-energy electron radiation E. As the top surface 20, the first portion 21 is flat. It is possible that the low-energy electron radiation E is limited to the first portion 21 or that more of the top surface 20 is exposed to the low-energy electron radiation E. For example, the first portion 21 may extend completely between the doped regions 23, 25 and even partially include the doped regions 23, 25 that are visible in the top view of the top surface 20.

[0048] 2, only one first portion 21 is shown, but there may be multiple first portions 21. Similarly, there may be many more than two doped regions 24, 25.

[0049] For example, the kinetic energy of the electrons of the low-energy electron radiation E is at least 116 keV and at most 210 keV. Optionally, the dose of the low-energy electron radiation E in the first portion 21 is at least 1012 cm -2 And at most 10 17 cm -2 It is.

[0050] For example, irradiation with radiation E may be performed in air or in a nitrogen atmosphere, and therefore a vacuum may not be required for the process of FIG.

[0051] In the method step of Fig. 3, an electrically insulating layer 3 is applied to the upper surface 20 of the semiconductor body 2 in the first portion 21. The electrically insulating layer 3 is produced, for example, as a thermal oxide, at a high temperature, for example of at least 1000°C. Optionally, after applying the material of the electrically insulating layer 3, a thermal barrier layer, for example of N 2 O, NO, O 2 , or O 3 The annealing can be carried out in one of the following atmospheres:

[0052] For example, the electrical insulating layer 3 is SiO 2 It is made of. The low energy electron radiation E removes carbon atoms from the area adjacent to the top surface 20 in the first portion 21, resulting in the presence of Si-rich SiC in the first portion. Thus, the electrical behavior can be improved since the C clusters are prevented from interfering with the proper formation of the oxide layer of the electrically insulating layer 3.

[0053] 3 further shows that a gate electrode 4 is formed on the side of the electrically insulating layer 3 remote from the semiconductor body 3. The gate electrode 4 may be made of metal or of an ohmic conductive semiconductor material such as poly-Si. Depending on the material of the gate electrode 4, an annealing step may be performed after application of the material of the gate electrode 4, which may result in a composite annealing.

[0054] The completed power semiconductor device 1 may be, for example, a power MOSFET or an IGBT. In the case of an IGBT, of course, there is no drain region, but there may be a collector region as well as a drift region. Further electrodes other than the gate electrode 4, such as source, drain or collector electrodes, are not shown in the figure.

[0055] For example, the completed power semiconductor device 1 is configured for a current of at least 10 A and / or at most 10 kA. Alternatively or additionally, the power semiconductor device 1 is configured for a voltage of at least 0.6 kV and / or at most 6 kV.

[0056] Another example of a manufacturing method is shown in figures 4 and 5. According to figure 4, a semiconductor body 4 is provided and a trench 5 is formed in the semiconductor body 2.

[0057] In this case, the completed power semiconductor device 1 is configured as an IGBT. The semiconductor body 5 thus comprises a source region 23 at the top surface 20. Optionally, the source region 23 is divided into two sub-regions by a trench 5. The source region 23 is integrated into a well region 24. On the side of the well region 24 remote from the top surface 20 there is a drift region 26. On the side of the drift region 26 remote from the drift region 26 there is a collector region 25. Again, to simplify the drawing, electrodes for the various semiconductor regions 23, 24, 25 are not shown.

[0058] For example, grooves 5 extend from top surface 20 into drift region 26 and terminate within drift region 26. Other than as shown, grooves 5 need not have a flat bottom surface, but can have a rounded bottom surface or even a V-shaped bottom region, as viewed in a cross section perpendicular to top surface 20.

[0059] 4, at least the sidewalls and the bottom surface of the groove 5 are irradiated with low-energy electron radiation E. That is, the first portion 21 may consist of said sidewalls and the bottom surface. Other parts of the outer top surface 20 of the groove 5 may also be irradiated with low-energy electron radiation E.

[0060] Contrary to what is shown in FIG. 4, there may be several grooves 5 . According to Fig. 5, after irradiating the first portion 21 with radiation E, an electrical insulating layer 3 is applied to the sidewalls and bottom surface of the groove 5. In Fig. 5, the electrical insulating layer 5 has a constant thickness all along the sidewalls and bottom surface of the groove, but it is also possible for the electrical insulating layer 3 to have different thicknesses.

[0061] The remaining part of the trench 5 is then filled with the gate electrode 4 . If this is not the case, the same may be true for Figures 4 and 5 with respect to Figures 1-3, and vice versa.

[0062] In Fig. 6 another method of manufacturing the power semiconductor device 1 is shown. In this case, a mask material 6 is applied to the outer top surface 20 of the first portion 21. A second portion 22 outside the first portion 21 may therefore not be irradiated with low-energy electron radiation E. The first portion 21 can therefore be precisely defined by the mask material 6. The thickness of the mask material 6 can be, for example, at least 10 µm or at least 30 µm.

[0063] If this is not the case, the same may be true for FIG. 6 as for FIG. 1-FIG. 5, and vice versa.

[0064] 7 shows a comparison of the measured voltage U vs. capacitance C characteristics between an exemplary embodiment of the power semiconductor device 1 described herein and a modified device 9. The modified device 9 corresponds to the power semiconductor device 1 except for irradiation with low energy electron radiation E. Both devices 1, 9 are MOS capacitors.

[0065] Theoretical flat band voltage V FB is obtained by the difference between the gate metal work function and the semiconductor work function: V FB =□ M -□ S This results in a V of 0.14 eV. FB The measured UC characteristics yield values ​​of V of 0.38 eV for the pre-irradiated MOS device 1 and 1.80 eV for the reference device 9. FB can be extracted.

[0066] FIG. 8 shows a comparison of the measured temperature T vs. constant capacitance deep level transient spectroscopy (CC-DLTS) signal S characteristics between the MOS device 1 and the reference device 9. The CC-DLTS signal of the pre-irradiated device 1 is found to be lower than that of the reference device 9, indicating a lower D it This occurs on the low-temperature side of the CC-DLTS spectrum, i.e., near the conduction band edge.

[0067] To prove the effect of electron irradiation, TCAD simulations were performed on a SiC MOSFET before oxidation. First, about 10 12 eV -1 cm -2 A SiC MOSFET with a typical concentration of interface traps of 10 ... it is an order of magnitude lower.

[0068] [Table 1]

[0069] ON1, ON2, OF1, and OF2 may be considered simply as labels. Each electrically active level is located within the band gap. For example, OF1 is found 0.19 eV below the conduction band edge. An electrically active level creates a potential well into which electrons can fall. This well has a cross section. The larger it is, the easier it is to trap electrons.

[0070] Additionally, each electrically active level is associated with a defect having a specified concentration. FIG. 9 illustrates a V GS Versus I GS FIG. 10 shows a comparison of the V characteristics between the exemplary embodiment of the power semiconductor device 1 described herein and the modified device 9. DS Versus I DS 9 and 10 show a comparison of the characteristics of the reference device 9 described herein and the MOSFET 1 irradiated before oxidation.

[0071] In Figure 9, standard or lower D it Simulations performed on a MOSFET with a level of 1000 nm show an improvement in the transfer characteristics when the irradiation is performed before the application of the electrical insulating layer. Figure 10 shows the output characteristics of the same MOSFET. It can be seen that the curve for the irradiated MOSFET 1 shows an improvement over the reference MOSFET 9, with the on-resistance R ON This means that the number of

[0072] Components depicted in the figures exemplarily follow one another directly in the specified order, unless otherwise indicated. Components that are not in contact in the figures are exemplarily spaced apart from one another. Where lines are drawn parallel to one another, corresponding surfaces may be oriented parallel to one another. Similarly, unless otherwise indicated, the positions of the depicted components relative to one another are accurately reproduced in the figures.

[0073] The power semiconductor devices and methods described herein are not limited by the description based on the exemplary embodiments. Rather, even if any novel feature or any combination of features is not itself explicitly specified in the claims or the exemplary embodiments, the power semiconductor devices and methods also encompass this feature and this combination, and they specifically include any combination of features in the claims.

[0074] This patent application claims priority to European Patent Application No. 22162144.4, the disclosure of which is incorporated herein by reference. [Explanation of symbols]

[0075] Reference sign 1. Power Semiconductor Devices 2. Semiconductor body 20 Top side 21 First Part 22 Second Part 23 Source Region 24 well area 25 Drain Region 26 Drift Region 3 Electrical insulation layer 4. Gate electrode 5 grooves 6. Mask Materials 9 Correction Device C Capacitance in pF I DS A / cm 2 Unitary drain-to-source current density I GS A / cm 2 The current density between the gate and source of unity CC-DLTS signal in S mV Temperature in TK Voltage in UV V DS Voltage between drain and source in V V GS Gate to source voltage in volts

Claims

1. - providing a SiC-based semiconductor body (2), - irradiating at least one first portion (21) of the top surface (20) of said semiconductor body (2) with low-energy electron radiation (E) having a kinetic energy of at least 116 keV and at most 210 keV, said low-energy electron radiation (E) at said at least one first portion (21) causing said semiconductor body to undergo a transformation into a Si ０．５＋x C ０．５－x wherein x is at least 0.001 and at most 0.1, and said layer has a thickness of at least 10 nm and at most 0.2 μm; and - producing an electrically insulating layer (3) by thermal growth in said at least one irradiated first portion (21); A method for manufacturing a power semiconductor device (1), comprising:

2. x is at most 0.02, The method according to the preceding claims.

3. The dose of the low energy electron radiation (E) in the first portion (21) is at least 10 １２ cm －２ And at most 10 １７ cm －２ That is, 10. A method according to any one of the preceding claims.

4. The electrical insulating layer (3) contains oxygen.

10. A method according to any one of the preceding claims.

5. The electrical insulating layer (3) is SiO ２ Made of The method according to the preceding claims.

6. By producing the electrical insulating layer (3), SiO ２ / An n-type 4H-SiC interface is produced; The method according to the preceding claims.

7. said producing said electrically insulating layer (3) comprises annealing a previously applied material of said electrically insulating layer (3); 10. A method according to any one of the preceding claims.

8. The annealing is performed in an atmosphere comprising at least one of nitrogen and oxygen. The method according to the preceding claims.

9. The irradiating of the at least one first portion (21) is performed in a nitrogen-containing atmosphere.

10. A method according to any one of the preceding claims.

10. the upper surface (20) being a flat surface of the semiconductor body (2); 10. A method according to any one of the preceding claims.

11. forming at least one trench (5) in said semiconductor body (2) prior to irradiating said at least one first portion (21); The at least one first portion (21) comprises a sidewall and a bottom surface of the at least one groove (5), The method according to any one of claims 1 to 9.

12. Prior to irradiating the at least one first portion (21), a mask material (6) is applied to the top surface (20), and during irradiating the at least one first portion (21), the at least one first portion (21) does not contain the mask material (6), but a remaining part of the top surface (20) is covered by the mask material (6).

10. A method according to any one of the preceding claims.

13. A gate electrode (4) is formed directly on the electrically insulating layer (3) on the side remote from the semiconductor body (2), the gate electrode (4) being made of poly-Si; When viewed in a cross section perpendicular to the top surface (20), the electrically insulating layer (3) as well as the gate electrode (4) extend across the well region (24) from the source region (23) to the drain region (25) as a closed layer without holes.

10. A method according to any one of the preceding claims.

14. - a SiC-based semiconductor body (2), a thermally grown electrically insulating layer (3) applied to at least a first portion (21) of the top surface (20) of said semiconductor body (2); Equipped with adjacent to said electrically insulating layer (3), said semiconductor body (2) being silicon rich; Adjacent to the electrically insulating layer (3), the semiconductor body is made of Si ０．５＋x C ０．５－x wherein x is at least 0.001 and at most 0.1, and said layer has a thickness of at least 10 nm and at most 0.2 μm. Power semiconductor device (1).

15. a metal-insulator-semiconductor field effect transistor or an insulated gate bipolar transistor; The power semiconductor device (1) is configured for an operating voltage of at least 0.6 kV; A power semiconductor device (1) according to the preceding claims.

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