PACKAGE SUBSTRATE EMPLOYING PAD METALLIZATION LAYER FOR INCREASED SIGNAL ROUTING CAPACITY AND ASSOCIATED INTEGRATED CIRCUIT (IC) PACKAGE AND MANUFACTURING METHODS - Patent application

Abstract

A package substrate employing a pad metallization layer for increasing signal routing capacity, and associated integrated circuit (IC) packages and manufacturing methods. To support increased signal routing density within an IC package while mitigating an increase in overall IC package thickness, an outer metallization layer of a package substrate is provided as a thinner pad metallization layer. A metal layer within the pad metallization layer includes metal pads for forming external connections to the package substrate. This allows areas within adjacent metallization layers that would otherwise have larger width metal pads for forming external interconnects to be used for other signal routing within the package substrate. This allows the overall signal routing density of the package substrate to be increased while mitigating an increase in overall package substrate thickness if a full sized additional metallization layer were added to the package substrate.

Description

[Technical field]

[0001] Priority Application This application claims priority to U.S. patent application Ser. No. 17 / 656,477, filed Mar. 25, 2022, entitled “PACKAGE SUBSTRATES EMPLOYING PAD METALLIZATION LAYER FOR INCREASED SIGNAL ROUTING CAPACITY, AND RELATED INTEGRATED CIRCUIT (IC) PACKAGES AND FABRICATION METHODS,” which is incorporated by reference in its entirety. [Background technology]

[0002] I. Field of Disclosure The field of the disclosure relates to integrated circuit (IC) packages, and more particularly to the design and manufacture of package substrates that support signal routing to the semiconductor die(s) within the IC package.

[0003] II. Background technology Integrated circuits (ICs) are the basis of electronic devices. ICs are packaged in IC packages, also called "semiconductor packages" or "chip packages." An IC package includes one or more semiconductor dies ("dies" or "dice") as IC(s) mounted and electrically coupled to a package substrate for providing physical support and an electrical interface to the die(s). The package substrate includes one or more metallization layers that include metal interconnects (e.g., metal traces, metal lines), and vias couple the metal interconnects together between adjacent metallization layers to provide an electrical interface between the die(s). The die(s) are electrically interfaced to metal interconnects exposed on the top or outer metallization layer of the package substrate to electrically couple the die(s) to the metal interconnects of the package substrate. For example, the package substrate may include an embedded trace substrate (ETS) layer adjacent to the die to facilitate a higher density of bump / solder joints for bonding the die(s) to the package substrate. Metal interconnects in the outer metallization layer are bonded to other metal interconnects in other underlying metallization layers in the package substrate to provide signal routing paths to the bonded die. For example, the package substrate may be a three-layer (3L) ETS package substrate having three vertically stacked metallization layers.

[0004] Some IC packages are known as "hybrid" IC packages that include multiple die packages with respective dies for different purposes or applications. For example, a hybrid IC package may be an application die such as a communications modem or a processor (including systems). A hybrid IC package may also include one or more memory dies, for example, to provide memory to support data storage and data access by the application die. The multiple dies may be arranged in a single die layer and positioned horizontally adjacent to each other on a package substrate in an IC package. The multiple dies may also be provided in their own respective die packages stacked on top of each other in a three-dimensional (3D) configuration as an overall 3DIC package. Interposers may be positioned between the die packages to support providing electrical connections between the stacked dies in the package. 3DIC packages may be desirable to reduce the cross-sectional area of ​​the package. In a 3DIC package, a first bottom die supported directly on a package substrate is electrically coupled to a metallization layer of the package substrate via die interconnects to provide signal routing paths for the dies in the package substrate. Other stacked dies that are not directly adjacent to the package substrate in a 3DIC package can be electrically coupled to the package substrate by wire bonds and / or intermediate interposers to provide die-to-die (D2D) connections between the multiple stacked dies.

[0005] As die sizes in IC packages increase, the number of connections between the die(s) and the package substrate of the IC package also typically increases to provide the necessary signal routing paths between the die(s) and the package substrate. The increased number of signal routing paths creates a need to support a higher density of signal routing space within the package substrate of the IC package. This may require increasing the number of metallization layers within the package substrate to accommodate the higher density signal routing paths. However, adding additional metallization layers to the package substrate increases the overall height and thickness of the IC package, which may cause the IC package to exceed its overall package thickness requirement. Summary of the Invention

[0006] Aspects disclosed herein include a package substrate employing a pad metallization layer to increase signal routing capacity. The package substrate is configured to be employed in an integrated circuit (IC) package to provide a mounting structure and signal routing for a semiconductor die(s) ("die(s)"). Related manufacturing methods are also disclosed. The package substrate includes one or more metallization layers, each including a metal interconnect, to provide a signal routing path. The die(s) are coupled to the metal interconnects in a first outer metallization layer of the package substrate to provide electrical coupling between the die(s) and the package substrate for signal routing. External interconnects (e.g., ball grid array (BGA) interconnects) are formed in contact with metal pads in a second outer metallization layer to provide external connections to the IC package and the die(s) therein. As signal routing density requirements for IC packages increase, additional metallization layers may be required in the package substrate. The additional metallization layers contribute to an increase in the overall thickness of the IC package in an undesirable manner. In an exemplary embodiment, to support increased signal routing density in the IC package while mitigating the increase in overall IC package thickness, a second outer metallization layer of the package substrate is provided as an additional pad metallization layer to the package substrate. The pad metallization layer includes a metal layer including metal pads for forming external connections to the package substrate. The pad metallization layer also includes a pad via layer including vias coupled to metal pads and metal interconnects in adjacent inner metallization layers to provide signal routing paths between the external interconnects and the package substrate. In one embodiment, the pad metallization layer is a dedicated pad metallization layer in that the metal layer includes only metal pads for forming external connections and does not include metal interconnects used for internal signal routing within the package substrate. Metal pads for forming external interconnects that would otherwise be in adjacent inner metallization layers in the package substrate are essentially moved down to this additional pad metallization layer.This allows areas in adjacent metallization layers that would otherwise have larger width metal pads for forming external interconnects to be used to provide additional smaller width metal interconnects for providing other signal routing within the package substrate. Thus, the pad metallization layers allow adjacent internal metallization layers within the package substrate to increase the density of metal interconnects used for internal signal routing within the package substrate, increasing the overall signal routing density of the package substrate while reducing the increase in the overall IC package thickness.

[0007] In an exemplary embodiment, since the pad metallization layer is not formed of a glass material or cloth, such as a pre-impregnated glass (PPG) layer, the pad metallization layer can be provided as a thinner metallization layer in the package substrate. For example, the pad via layer in the pad metallization layer can be formed as a photo-imagable dielectric (PID) layer that does not include glass cloth material. Since other metallization layers in the package substrate may be sufficiently rigid to provide stability to reduce or avoid warpage, it may not be necessary to form the pad via layer of the pad metallization layer as a PPG layer to provide additional stability in the package substrate. Also, by providing the pad via layer in the pad metallization layer as a thinner layer, the height of the vias formed to couple the metal pads in the pad metallization layer to the metal interconnects in the adjacent inner metallization layers is reduced. The reduced height of the vias in the pad metallization layer also allows the width of the bonded metal interconnects in adjacent internal metallization layers to be reduced, thus providing additional area in the adjacent metallization layers to provide additional metal interconnects used for internal signal routing within the package substrate to support higher density signal routing. The reduced height of the vias in the pad metallization layer also reduces the risk of dimple formation during manufacturing. This may allow these vias in the pad metallization layer to be formed using, for example, an exposure and development process as opposed to the need for a laser drill and fill process.

[0008] Also, in another exemplary aspect, the reduced thickness of the pad via layer in the pad metallization layer reduces the risk of dimples forming in the vias, which may also allow the metal pads formed in the metal layer of the pad metallization layer to be of reduced thickness. This contributes to a reduction in the thickness of the metal layer in the pad metallization layer, and therefore the thickness of the pad metallization layer, compared to other metallization layers in the package substrate. The thinner metal layer with the thinner metal pad in the pad metallization layer also reduces the coefficient of thermal expansion (CTE) of the package substrate than would otherwise be present if the metal layer in the pad metallization layer were thicker. This helps to avoid or reduce warpage of the IC package by adding the pad metallization layer to the package substrate. For example, the metal layer in the pad metallization layer may be a 0.5 thick metallization layer, which means that it is half or about half the thickness of other metal layers in other metallization layers in the package substrate as a 1.0 thick metallization layer. Thus, in this example, if a package substrate includes three metallization layers, each having a 1.0 metal layer thickness, adding a pad metallization layer having a 0.5 metal layer to the package substrate provides the package substrate with a total of 3.5 metal layers contributing to the overall thickness of the package substrate, as opposed to adding an additional metallization layer to increase signal routing density, having a full sized 1.0 metal layer thickness, which in this example provides a thicker 4.0 metal layer package substrate for the IC package.

[0009] In this regard, in one exemplary embodiment, a package substrate is provided. The package substrate comprises a first metallization layer comprising a first metal layer having a first thickness. The first metal layer comprises one or more first metal interconnects. The package substrate also comprises a pad metallization layer comprising a first surface disposed adjacent to the first metallization layer and a second surface opposite the first surface. The pad metallization layer comprises a pad metal layer having a second thickness less than the first thickness. The pad metal layer comprises one or more metal pads adjacent to the second surface and each coupled to a first metal interconnect of the one or more metal interconnects. The package substrate also comprises one or more external interconnects each coupled to a metal pad of the one or more metal pads.

[0010] In another exemplary aspect, a method of manufacturing a package substrate for an IC package is provided. The method includes forming a first metallization layer, including forming a first metal layer having a first thickness and forming one or more first metal interconnects in the first metal layer. The method also includes forming a pad metallization layer having a first surface adjacent to the first metallization layer and a second surface opposite the first surface. Forming the pad metallization layer includes forming a pad metal layer having a second thickness less than the first thickness, forming one or more metal pads in the pad metal layer adjacent to the second surface, and coupling each metal pad of the one or more metal pads to a first metal interconnect of the one or more metal interconnects. The method also includes forming one or more external interconnects, each coupled to a metal pad of the one or more metal pads. [Brief description of the drawings]

[0011] [Figure 1]FIG. 1 is a side view of an integrated circuit (IC) package in the form of a three-dimensional IC (3DIC) package including stacked semiconductor dies ("die") and a package substrate including a pad metallization layer having a metal layer having metal pads for forming external metal interconnects to provide increased signal routing capacity within internal adjacent metallization layers within the package substrate. [Figure 2A] 2 is a side view of a package substrate including a pad metallization layer in the IC package of FIG. 1. [Figure 2B] 2 is a side view of a package substrate including a pad metallization layer in the IC package of FIG. 1. [Figure 3A] FIG. 2C is a side view of the package substrate of FIGS. 2A and 2B. [Figure 3B] FIG. 2C is a top view of a metal interconnect in an internal metallization layer adjacent to a dedicated pad metallization layer in the package substrate of FIGS. 2A and 2B, illustrating the increased density of signal routing paths in the adjacent metallization layer made possible by providing metal pads for external interconnects in the pad metallization layer. [Figure 4A] FIG. 1 is a side view of an alternative package substrate that may be provided in an IC package, the package substrate including an additional full-sized outer metallization layer that is not dedicated to metal pads for external interconnects. [Figure 4B] FIG. 4B is a top view of metal interconnects within the outer metallization layer of the IC package of FIG. 4A, illustrating an increased density of signal routing paths within the outer metallization layer. [Figure 5A] FIG. 4 is a top view of another signal routing design that can be provided by metal interconnects formed in an interior metallization layer adjacent to the pad metallization layer in the package substrate of FIGS. 2A and 2B. [Figure 5B] FIG. 4 is a top view of another signal routing design that can be provided by metal interconnects formed in an interior metallization layer adjacent to the pad metallization layer in the package substrate of FIGS. 2A and 2B. [Figure 6]FIG. 5 is a flowchart illustrating an exemplary manufacturing process for manufacturing a package substrate including a pad metallization layer having a metal layer having metal pads for forming external metal interconnects to provide increased signal routing capacity within internal adjacent metallization layers within the package substrate, including but not limited to the package substrate of FIGS. 1-3A and having the signal routing paths of FIGS. 3B and 5A-5B. [Figure 7A] FIG. 3B is a flowchart showing another exemplary manufacturing process for manufacturing a package substrate including a pad metallization layer having a metal layer having metal pads for forming external metal interconnects to provide increased signal routing capacity within internal adjacent metallization layers in the package substrate, including but not limited to the package substrate of FIGS. 1-3A, and having the signal routing paths of FIG. 3B and FIGS. 5A and 5B. [Figure 7B] FIG. 3B is a flowchart showing another exemplary manufacturing process for manufacturing a package substrate including a pad metallization layer having a metal layer having metal pads for forming external metal interconnects to provide increased signal routing capacity within internal adjacent metallization layers in the package substrate, including but not limited to the package substrate of FIGS. 1-3A, and having the signal routing paths of FIG. 3B and FIGS. 5A and 5B. [Figure 7C] FIG. 3B is a flowchart showing another exemplary manufacturing process for manufacturing a package substrate including a pad metallization layer having a metal layer having metal pads for forming external metal interconnects to provide increased signal routing capacity within internal adjacent metallization layers in the package substrate, including but not limited to the package substrate of FIGS. 1-3A, and having the signal routing paths of FIG. 3B and FIGS. 5A and 5B. [Figure 8A] 7A-7C are exemplary manufacturing stages during the manufacture of a package substrate including a pad metallization layer having a metal layer having metal pads for forming external metal interconnects to provide increased signal routing capacity within internal adjacent metallization layers within the package substrate. [Figure 8B]7A-7C , an exemplary manufacturing stage during the manufacture of a package substrate including a pad metallization layer having a metal layer having metal pads for forming external metal interconnects to provide increased signal routing capacity within internal adjacent metallization layers within the package substrate. [Figure 8C] 7A-7C , an exemplary manufacturing stage during the manufacture of a package substrate including a pad metallization layer having a metal layer having metal pads for forming external metal interconnects to provide increased signal routing capacity within internal adjacent metallization layers within the package substrate. [Figure 8D] 7A-7C , an exemplary manufacturing stage during the manufacture of a package substrate including a pad metallization layer having a metal layer having metal pads for forming external metal interconnects to provide increased signal routing capacity within internal adjacent metallization layers within the package substrate. [Figure 8E] 7A-7C , an exemplary manufacturing stage during the manufacture of a package substrate including a pad metallization layer having a metal layer having metal pads for forming external metal interconnects to provide increased signal routing capacity within internal adjacent metallization layers within the package substrate. [Figure 9] A block diagram of an exemplary processor-based system that may include components that may include an IC package including a package substrate including, but not limited to, the package substrate of Figures 1-3A and Figures 8A-8E, having the signal routing paths of Figures 3B and Figures 5A-5B, and including a pad metallization layer having a metal layer having metal pads for forming external metal interconnects to provide increased signal routing capacity within internal adjacent metallization layers within the package substrate according to the exemplary manufacturing process of Figures 6-7C. [Figure 10]FIG. 1 is a block diagram of an exemplary wireless communication device including radio-frequency (RF) components that may include an IC package including a package substrate including, but not limited to, the package substrate of FIGS. 1-3A and 8A-8E, having the signal routing paths of FIGS. 3B and 5A-5B, and including a pad metallization layer having a metal layer having metal pads for forming external metal interconnects to provide increased signal routing capacity within internal adjacent metallization layers within the package substrate according to the exemplary manufacturing process of FIGS. 6-7C. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Some exemplary aspects of the present disclosure will now be described with reference to the drawings. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0013] Aspects disclosed herein include a package substrate employing a reduced thickness pad metallization layer to increase signal routing capacity. The package substrate is configured to be employed in an integrated circuit (IC) package to provide a mounting structure and signal routing for a semiconductor die(s) ("die(s)"). Related manufacturing methods are also disclosed. The package substrate includes one or more metallization layers, each including a metal interconnect, to provide a signal routing path. The die interconnects of the die(s) are coupled to metal interconnects in a first outer metallization layer of the package substrate to provide electrical coupling between the die(s) and the package substrate for signal routing. External interconnects (e.g., ball grid array (BGA) interconnects) are formed in contact with metal pads in a second outer metallization layer to provide external connections to the IC package and the die(s) therein. As signal routing density requirements for IC packages increase, additional metallization layers may be required in the package substrate. The additional metallization layers undesirably contribute to an increase in the overall thickness of the IC package. In an exemplary embodiment, to support increased signal routing density in the IC package while mitigating the increase in overall IC package thickness, a second outer metallization layer of the package substrate is provided as an additional pad metallization layer to the package substrate. The pad metallization layer includes a metal layer including metal pads for forming external connections to the package substrate. The pad metallization layer also includes a pad via layer including vias coupled to metal pads and metal interconnects in adjacent inner metallization layers to provide signal routing paths between the external interconnects and the package substrate. In one embodiment, the pad metallization layer is a dedicated pad metallization layer in that the metal layer includes only metal pads for forming external connections and does not include metal interconnects used for internal signal routing within the package substrate. Metal pads for forming external interconnects that would otherwise be in adjacent inner metallization layers in the package substrate are essentially moved down to this additional pad metallization layer.This allows areas in adjacent metallization layers that would otherwise have larger width metal pads for forming external interconnects to be used to provide additional smaller width metal interconnects for providing other signal routing within the package substrate. Thus, the pad metallization layers allow adjacent internal metallization layers within the package substrate to increase the density of metal interconnects used for internal signal routing within the package substrate, increasing the overall signal routing density of the package substrate while reducing the increase in the overall IC package thickness.

[0014] 1 is a side view of an exemplary IC package 100 that includes a package substrate 102 that includes a pad metallization layer 104 having metal pads for supporting external connections to the package substrate 102. As described in more detail below, the pad metallization layer 104 enables other metallization layers to have a higher density of metal interconnects to increase the signal routing density of the package substrate 102. Before describing exemplary details of the pad metallization layer 104, other aspects of the IC package 100 will first be described.

[0015] In this regard, as shown in FIG. 1, IC package 100 is a 3D stacked die IC package 106 including multiple dies 108(1), 108(2) included in respective die packages 110(1), 110(2) stacked on top of one another in a vertical direction (Z-axis direction). A first die package 110(1) of IC package 100 includes a die 108(1) coupled to a package substrate 102. In this example, package substrate 102 includes a first outer metallization layer 115 disposed adjacent to a second inner metallization layer 114 that is adjacent to a third metallization layer 112. Metallization layers 112, 114, 115 provide an electrical interface for signal routing to die 108(1). Die 108(1) is coupled to die interconnects 116 (e.g., raised metal bumps) that are electrically coupled to metal interconnects 118 in top metallization layer 115. Metal interconnects 118 in the top metallization layer 115 are coupled to metal interconnects 120(1), 120(2) in the metallization layer 114, which are in turn coupled to metal pads 122 in the pad metallization layer 104, which will be described in more detail below. In this manner, the package substrate 102 provides interconnects between its metallization layers 112, 114, 115 and the pad metallization layer 104 to provide signal routing to the die 108(1). External interconnects 124 (e.g., ball grid array (BGA) interconnects) are coupled to metal pads 122 in the pad metallization layer 104 to provide interconnections through the package substrate 102 to the die 108(1) via the die interconnects 116.

[0016] As in this exemplary IC package 100 of FIG. 1, a second die package 110(2) is provided and coupled to the first die package 110(1) to support multiple dies to provide 3D stacking of dies. For example, the first die 108(1) in the first die package 110(1) can include an application processor, and the second die 108(2) can be a memory die, such as a dynamic random access memory (DRAM) die, that provides memory support for the application processor. In this regard, in this embodiment, the first die package 110(1) also includes an interposer substrate 128 disposed on a package mold 130 that encapsulates the first die 108(1). The interposer substrate 128 also includes one or more metallization layers 132, each including a metal interconnect 134, to provide interconnection to the second die 108(2) in the second die package 110(2). The second die package 110(2) is physically and electrically coupled to the first die package 110(1) by being coupled to the interposer substrate 128 via external interconnects 136 (e.g., solder bumps, BGA interconnects). The external interconnects 136 are coupled to metal interconnects 134 in the interposer substrate 128.

[0017] Vertical interconnects 138 (e.g., metal vertical interconnect accesses (vias), such as metal pillars, metal posts, through-mold vias (TMVs), etc.) are disposed in the package mold 130 of the first die package 106(1) to provide interconnects for routing signals from the second die 108(2) through the external interconnects 136 and the interposer substrate 128 to the first die 108(1). The vertical interconnects 138 extend in a vertical direction (Z-axis direction) from the interposer substrate 128 to the package substrate 102 in this example. The vertical interconnects 138 are coupled to the metal interconnects 134 in the interposer substrate 128. The vertical interconnects 138 are also coupled to the metal interconnects 118 in the top metallization layer 115 of the package substrate 102. In this manner, the vertical interconnects 138 provide a bridge for interconnections, such as input / output (I / O) connections, between the interposer substrate 128 and the package substrate 102. This provides a signal routing path between the second die 108(2) in the second die package 110(1) and the first die 108(1) and the external interconnects 124 through the package substrate 102.

[0018] As shown in a more detailed side view of the package substrate 102 in FIG. 2A, the pad metallization layer 104 is an outer metallization layer in the package substrate 102. The pad metallization layer 104 has a first surface 140 disposed adjacent to the metallization layer 112 and a second surface 142 opposite the first surface 140. The pad metallization layer 104 has a pad metal layer 144 which, in this example, includes only a metal interconnect in the form of a metal pad 122 for providing an external connection signal path to the package substrate 102. In this regard, as shown in FIG. 1, the external interconnect 124 is formed in contact with a metal pad 122 in the pad metal layer 144 exposed from the pad metallization layer 104 to provide an external interface to the package substrate 102. The metal pad 122 in the pad metal layer 144 is adjacent to the second surface 142 of the pad metallization layer 104. For example, the package substrate 102, and more particularly its external interconnects 124, may be coupled to a circuit board or other substrate to provide physical and electrical connections to the IC package 100. The pad metallization layer 104 also includes a pad-via layer 146 including a via 148 coupled to the metal pad 122 and also coupled to a metal interconnect 120(1) in the adjacent internal metallization layer 112 to provide a signal routing path between the external interconnects 124 and the package substrate 102. The metallization layer 112 includes a via layer 150 including a via 152 coupled to the metal interconnect 120(1) and to a metal interconnect 154 in the metallization layer 114 to provide a signal routing path between the metallization layers 112, 114. The metallization layer 114 also includes a via layer 156 including a via 158 coupled to the metal interconnect 154 and to a metal interconnect 118 in the metallization layer 115 to provide a signal routing path between the metallization layers 114, 115.

[0019] By providing an additional pad metallization layer 104 in the package substrate 102 shown in Figures 1-2B, the signal routing capacity of the package substrate 102 can be increased while minimizing the need to add an additional larger sized metallization layer to the package substrate 102. This is because, as shown in the package substrate 102 of Figures 1-2B, the metal pads 122 for forming external interconnects that would otherwise be in the metallization layer 114 if the pad metallization layer 104 was not present are essentially moved down to the pad metallization layer 104. In this embodiment, each metal pad 122 in the pad metallization layer 104 is coupled to an external interconnect 124 such that the metal pads 122 in the pad metallization layer 104 are provided exclusively for signal routing to the external interconnects 124, and not for internal signal routing within the package substrate 102. The provision of metal pads 122 for forming external interconnects 124 in the added pad metallization layer 104 provides additional area in the adjacent metallization layer 112 that would otherwise have larger width metal pads for forming external interconnects that are used to provide additional smaller width metal interconnects 120(2) for providing other signal routing within the package substrate 102. The pad metallization layer 104 thus allows adjacent internal metallization layers 114 within the package substrate 102 to increase the density of metal interconnects 120(2) used for internal signal routing within the package substrate 102, increasing the overall signal routing density of the package substrate 102 while reducing the increase in the overall IC package thickness H1 in the Z-axis direction.

[0020] In this example, the addition of a pad metallization layer 104 to the package substrate 102, which includes metal pads 122 for supporting external interconnects 124, increases the thickness of the package substrate 102 and contributes to the height H1 of the package substrate 102. However, the pad metallization layer 104 in this example has a reduced Z-axis thickness H2 than simply providing another metallization layer, e.g., thickness H3 of the other metallization layers 112, 114 in the package substrate 102 in the Z-axis direction. Thus, by providing the pad metallization layer 104 in the package substrate 102, signal routing density in adjacent metallization layers 112 in the package substrate 102 is increased by only increasing the thickness H1 of the package substrate by thickness H2, as opposed to, e.g., another metallization layer of thickness H3.

[0021] 2A, it is also desirable to reduce the Z-axis height or thickness H4 of the pad via layer 146 and the Z-axis height or thickness H5 of the pad metallization layer 144, if possible, to minimize the thickness H2 of the pad metallization layer 104 in the package substrate 102. In this regard, in this embodiment, in order to reduce the height or thickness H4 of the pad via layer 146, the pad via layer 146 in the pad metallization layer 104 is not formed of a glass material or cloth, such as a pre-impregnated glass (PPG) layer, in this embodiment. Since the other metallization layers 112, 114, 115 in the package substrate 102 may be sufficiently rigid to provide stability to reduce or avoid warpage, it may not be necessary to form the pad via layer 146 of the pad metallization layer 104 as a PPG layer to provide additional stability in the package substrate 102. As an example, one, some, or all of the metallization layers 112, 114, 115 may be formed from or include a glass material, such as a PPG material, to increase its rigidity. This allows for a pad via layer 146 to be provided in the pad metallization layer 104 with a reduced height or thickness H4 and / or width, and the overall height or thickness H2 of the pad metallization layer 104 may be reduced compared to the height or thickness H7 and / or width of the via layer 150 in the adjacent metallization layer 112. This in turn reduces the impact of the pad metallization layer 104 on the overall thickness or height H1 of the package substrate 102.

[0022] For example, the pad via layer 146 and / or its vias 148 may have a height or thickness H4 between 10 micrometers (μm) and 15 μm, such as 10 micrometers (μm). The via layer 150 and / or its vias 152 in the adjacent metallization layer 112 may have a respective height or thickness H7 between 25 μm and 45 μm, such as 25 μm. As another example, the ratio of the height or thickness H7 of the via layer 150 and / or its vias 152 to the height or thickness H4 of the pad via layer 146 and / or its vias 148 may be at least 1.6.

[0023] Also, as shown in another side view of the package substrate 102 in FIG. 2B, by providing the pad via layer 146 as a thinner layer in the pad metallization layer 104, this reduces the height or thickness H6 of the via 148 formed to couple the metal pad 122 in the pad metallization layer 104 to the metal interconnect 120(1) in the adjacent interior metallization layer 112. For example, to reduce the height or thickness H6 of the via 148, the pad via layer 146 of the pad metallization layer 104 can be formed as a photoimageable dielectric (PID) layer such that the via 148 in the pad via layer 146 can be formed from an imaging and developing process, as opposed to, for example, by laser drilling. The via 148 has a height or thickness H6 that is less than the height or thickness H7 of the via 152 in the adjacent metallization layer 112. The reduced height of the vias 148 in the pad metallization layer 104 also allows for a reduced width W1 of the bonded metal interconnects 120(1) in the adjacent internal metallization layer 112, thus providing additional area in the adjacent metallization layer 112 for providing additional metal interconnects 120(2) used for internal signal routing within the package substrate 102 to support higher density signal routing. The reduced height of the vias 148 in the pad metallization layer 104 also reduces the risk of dimple formation during manufacturing. As described in more detail below, this can allow these vias 148 in the pad metallization layer 104 to be formed using, for example, an exposure and development process, as opposed to the need for a laser drill and fill process.

[0024] As shown in FIG. 2B, it should be noted that the metallization layer 112 adjacent to the pad metallization layer 104 includes a metal interconnect 120(1) of width W1 that is coupled to a via 148 in the via pad layer 146 of the pad metallization layer 104 to provide connectivity between the metallization layer 112 and the external interconnect 124 (FIG. 1). The metallization layer 112 also includes other metal interconnects 120(2) of width W2, which is smaller than width W1, that are not coupled to the via 148 in the pad metallization layer 104. These other metal interconnects 120(2) are used for internal signal routing within the metallization layer 112 of the package substrate 102. This is to increase the signal routing density within the metallization layer 112, and therefore within the package substrate 102, by providing an additional pad metallization layer 104 having metal pads 122 to provide external connections where additional area is available within the metallization layer 112 adjacent to the pad metallization layer 104 for providing additional metal interconnects 120(2) that are not bonded to the metal pads 122.

[0025] Also, in this embodiment, since the pad via layer 146 in the pad metallization layer 104 has a reduced height or thickness H4, which reduces the risk of dimples forming in the vias 148, this may also allow the metal pads 122 formed in the pad metallization layer 144 of the pad metallization layer 104 to also have a reduced height or thickness H8. This contributes to a reduced height or thickness H8 of the pad metallization layer 144 in the pad metallization layer 104, and therefore a reduced thickness H2 of the pad metallization layer, for example, compared to other metallization layers 112, 114 in the package substrate 102. The thinner metal layer 144 with the thinner metal pads 122 in the pad metallization layer 104 may also reduce the coefficient of thermal expansion (CTE) of the package substrate 102 than would otherwise be present if the pad metallization layer 144 in the pad metallization layer 104 were thicker. This helps to avoid or reduce warpage of the IC package 100 by adding the pad metallization layer 104 to the package substrate 102.

[0026] The height or thickness H9, H10 of any of the metal layers 160, 162, and / or 164 within the metallization layers 112, 114, 115 10 , H 11 For example, the height or thickness H9, H10 of each of the metal layers 160, 162, and 164 may be 12 μm to 16 μm. 10 , H 11 The height or thickness H9, H10, H12, and H14 of the pad metal layer 144 in the pad metallization layer 104 may be between 10 μm and 12 μm. In one embodiment, the height or thickness H9, H10, H12, and H14 of the metal layers 160, 162, and / or 164 in the metallization layers 112, 114, 115, respectively, may be between 10 μm and 12 μm. 10 , H 11 It should be noted that the ratio of either of these to the height or thickness H5 of the pad metal layer 144 may be at least 1.2.

[0027] As another example, the pad metal layer 144 in the pad metallization layer 104 can be a 0.5 thickness metallization layer, meaning that it is half or approximately half the thickness of the other metal layers 160, 162, 164 in the other metallization layers 112, 114, 115 in the package substrate 102 as a 1.0 thickness metallization layer. Thus, in this example, if the package substrate 102 includes three metallization layers 112, 114, 115 each having a 1.0 thickness metal layer 160, 162, 164, adding the pad metallization layer 104 having a 0.5 pad metal layer 144 to the package substrate 102 provides the package substrate 102 with a total of 3.5 metal layers contributing to the overall thickness H1 of the package substrate 102. This is in contrast to adding additional metallization layers to increase signal routing density, having full-sized 1.0 thick metal layers, such as metal layers 160, 162, 164, which in this embodiment provides a thicker 4.0 metal layer package substrate for IC package 100.

[0028] Also shown in Figures 3A and 3B are additional areas provided in the metallization layer 112 adjacent to the pad metallization layer 104 in the package substrate 102 to provide additional metal interconnects 120(2) for increased signal routing density. Figure 3A is a side view of the package substrate 102 of Figures 2A and 2B. Figure 3B is a top view of the metal interconnects 120(1), 120(2) routed in the metallization layer 112 adjacent to the pad metallization layer 104 in the package substrate 102 shown in Figure 3A. As shown in Figure 3B, there are eight metal lines of metal interconnects 120(2) running horizontally in the Y-axis direction between the metal interconnects 120(1) coupled to metal pads 122 in the pad metallization layer 104. As discussed above and shown in FIG. 3B, by moving the metal pad 122 with the external interconnect 124 formed thereon from the metallization layer 112 to the additional pad metallization layer 104, the metal interconnect 120(1) can be formed with a smaller width W1. This formation of the smaller sized via 148 facilitates the smaller sized metal interconnect 120(1) as described above. This provides additional space for the formation of other metal interconnects 120(2) for internal signal routing within the metallization layer 112, as opposed to the package substrate 402 as shown in FIG. 4A.

[0029] 4A is a side view of a package substrate 402 that does not include a pad metallization layer, but rather includes four metallization layers 404, 412, 414, 415. The metallization layers 412, 414, 415 are similar to the metallization layers 112, 114, 115 in the package substrate 102 of FIGS. 2A-3B. However, as shown in the top view of the metallization layers 404 in FIGS. 4A and 4B, the package substrate 402 includes a fourth outer metallization layer 404 having a larger metal interconnect 422 formed thereon with a width W3 for coupling to an external interconnect. In this embodiment, the outer metallization layer 404 has a greater Z-axis height than the pad metallization layer 104 of the package substrate of FIGS. 1-3B. For example, the height or thickness H of the outer metallization layer 404 of the package substrate 402 is 1 / 1000 . 12is greater than the height or thickness H1 of the outer pad metallization layer 104 of the package substrate 102 of FIGS. 1-3A. For example, the height or thickness H 12 may be 167 μm as an example, while the height or thickness H1 of the pad metallization layer 104 of the package substrate 102 of FIGS. 1-3A may be 148 μm as an example.

[0030] The reduction in height H1 of the outer pad metallization 104 of the package substrate 102 is achieved by reducing the height or thickness H5 of the pad metal layer 144 in the pad metallization 104 of FIGS. 1-3A to the height or thickness H of the metal layer 444 in the outer metallization 404 on which the metal interconnects 420, 422 are formed. 13 For example, the height or thickness H5 of the pad metal layer 144 in the pad metallization 104 is less than the height or thickness H 13 1-3A , the height or thickness H4 of the pad via layer 146 in the pad metallization layer 104 of the package substrate 102 can be 8 μm, compared to 12 μm. 14 For example, the height or thickness H4 of the pad via layer 146 in the pad metallization layer 104 of the package substrate 102 of FIGS. 1-3A is smaller than the height or thickness H 14 can be 10 μm compared to 25 μm.

[0031] The metallization layer 404 in the package substrate 402 of Figure 4A also includes a metal interconnect 422 having a width W3 that is greater than the width W1 of the metal interconnect 120(1) in the pad metallization layer 104 in the package substrate 102 of Figures 1A-3. Because the width W3 of the metal interconnect 422 is greater, less area is available in the outer metallization layer 404 for formation of the metal interconnect 420 for internal signal routing within the metallization layer 404 of the package substrate 402 compared to the area available for the metal interconnect 120(1) in the metallization layer 112 of the package substrate 102 of Figures 3A and 3B.

[0032] Other routing schemes than those shown in FIG. 3B can be provided in the metallization layer 112 adjacent to the pad metallization layer 104 in the package substrate 102 of FIGS. 1-3B. For example, FIG. 5A is a top view of another signal routing design that can be provided in an alternative metallization layer 112(1) that can be disposed adjacent to the pad metallization layer 104 in the package substrate 102 of FIGS. 1-3B. As shown therein, the metal interconnects 120(1) can be located closer to each other in the X-axis direction in a row in the Y-axis than those shown in FIG. 3B. This is possible because the width W1 of the metal interconnects 120(1) can be made smaller by moving the metal pads 122 into the adjacent pad metallization layer 104, as described above. The metal interconnects 120(2) used for internal signal routing are located between adjacent rows of the metal interconnects 120(1). The metal interconnects 120(2) can also extend in a curved manner in the X-axis direction in addition to the Y-axis direction. FIG. 5B is a top view of yet another signal routing design that may be provided in an alternative metallization layer 112(2) that may be disposed adjacent to the pad metallization layer 104 in the package substrate 102 of FIGS. 1-3B. As shown therein, the metal interconnects 120(1) may be located closer together in the X-axis direction in a row in the Y-axis than those shown in FIG. 3B. This is possible because the width W1 of the metal interconnects 120(1) may be smaller by moving the metal pads 122 into the adjacent pad metallization layer 104, as described above. The metal interconnects 120(2) used for internal signal routing are located between adjacent rows of the metal interconnects 120(1). The metal interconnects 120(2) may extend in a curved manner in the X-axis direction in addition to the Y-axis direction.

[0033] A package substrate for an IC package including a pad metallization layer having a metal layer with metal pads for forming external metal interconnects for providing increased signal routing capacity within an internal adjacent metallization layer within the package substrate, including but not limited to the package substrate of Figures 1-3A and 8A-8E, having signal routing paths of Figures 3B and 5A-5B, according to the exemplary manufacturing process of Figures 6-7C and according to any embodiment disclosed herein, can be provided in an IC package provided or integrated within any processor-based device. The manufacturing process 600 of Figure 6 can be used to manufacture the package substrate 102 of Figures 1-3B with the signal routing paths of Figures 3B and 5A-5B, as one example. The manufacturing process 800 of Figure 8 will be described in conjunction with the package substrate 102 of Figures 1-3B, as one example.

[0034] In this regard, a first step of the manufacturing process 600 of Figure 6 may include forming a first metallization layer 112 (block 602 of Figure 6). Forming the first metallization layer 112 may include forming a first metal layer 160 having a first thickness H9 (block 604 of Figure 6) and forming one or more first metal interconnects 120(1), 120(2) in the first metal layer 160 (block 606 of Figure 6). A next step of the manufacturing process 600 may be forming a pad metallization layer 104 comprising a first surface 140 adjacent to the first metallization layer 112 and a second surface 142 opposite the first surface 140 (block 608 of Figure 6). Forming the pad metallization layer 104 may include forming a pad metal layer 144 having a second thickness H5 less than the first thickness H9 (block 610 of FIG. 6), forming one for more metal pads 122 in the pad metal layer 144 adjacent the second surface 142 (block 612 of FIG. 6), and bonding each metal pad 122 of the one or more metal pads 122 to a first metal interconnect 120(1) of the one or more metal interconnects 120(1) (block 614 of FIG. 6). A next step in the manufacturing process 600 may include forming one or more external interconnects 124 each bonded to one metal pad 122 of the one or more metal pads 122 (block 616 of FIG. 6).

[0035] Other manufacturing processes may be employed to manufacture a package substrate for an IC package including a pad metallization layer having a metal layer with metal pads for forming external metal interconnects for providing increased signal routing capacity within internal adjacent metallization layers within the package substrate, including but not limited to the package substrate 102 of Figures 1-3B, having signal routing paths of Figures 3B and 5A-5B, and may be manufactured by different manufacturing processes. In this regard, Figures 7A-7C are a flow chart illustrating another exemplary manufacturing process 700 for manufacturing a package substrate including a pad metallization layer having a metal layer with metal pads for forming external metal interconnects for providing increased signal routing capacity within internal adjacent metallization layers within the package substrate, including but not limited to the package substrate 102 of Figures 1-3B, having signal routing paths of Figures 3B and 5A-5B. Figures 8A-8E are exemplary manufacturing stages 800A-800E during the manufacture of a package substrate according to the manufacturing process 700 of Figures 7A-7C. The manufacturing process 700 illustrated in the manufacturing stages 800A-800E of FIGS. 8A-8E refers to the package substrate 102 of FIGS. 1-3B and will therefore be described with reference to the package substrate 102 of FIGS. 1-3B.

[0036] In this regard, as shown in the manufacturing stage 800A of FIG. 8A, the first exemplary step of the manufacturing process 700 is to form a pad-via layer 146 on the stack-up of metallization layers 112, 114, 115 (block 702 of FIG. 7A). The metallization layers 112, 114, 115 have already been fabricated and bonded together as part of a three-layer (3L) embedded trace board (ETS) package substrate 802 in this process step. The pad-via layer 416 is formed as a stack of dielectric material 804 on the bottom surface 806 of the metallization layer 112 and is also disposed on the metal interconnects 120(1), 120(2) of the metallization layer 112. In this embodiment, the dielectric material 804 does not include a glass material, such as a PPG material, as previously described to reduce the thickness of the pad-via layer 146. As shown in manufacturing stage 800B of FIG. 8B, the next exemplary step of manufacturing process 700 is then to process pad via layer 146 to form via opening 808 in which via 148 is formed that is coupled to metal interconnect 120(1) in the metallization layer (block 704 of FIG. 7A). In this example, pad via layer 146 is exposed and developed using a lithography process. Pad via layer 146 is not drilled to form via opening 808 in this example because pad via layer 146 is of a sufficiently small thickness in the Z-axis direction to be able to sufficiently form via opening 808 using a lithography process.

[0037] Then, as shown in manufacturing stage 800C of FIG. 8C, the next exemplary step in the manufacturing process 700 is to fill the via opening 808 with a metal material (e.g., copper) to form the via 148 connected to the metal interconnect 120(1) and to form the metal pad 122 as part of the pad metallization layer 104 (block 706 of FIG. 7B). After the metal material is disposed in the via opening 808 and plates the pad via layer 146, the pad metal layer 144 is exposed and developed to remove the metal material in the pad metal layer 144, leaving the metal pad 122 still coupled to the via 148. The pad via layer 146 and the pad metal layer 144 form the pad metallization layer 104. Then, as shown in manufacturing stage 800D of FIG. 8D, the next exemplary step in the manufacturing process 700 is to remove the carrier 810 (shown in FIG. 8C) attached to the ETS package substrate 802 to leave the completed package substrate 102 (block 708 of FIG. 7B). 8E, the next exemplary step in the manufacturing process 700 is to form a solder resist layer 812 on the metallization layer 115 on the die side of the IC package (block 710 in FIG. 7C). The solder resist layer 812 is laminated onto the metallization layer 115 and then exposed and developed using a lithography process to form openings 814 adjacent to the metal interconnects 118 in the metallization layer 115. The die interconnects of the bonded die can bond to the metal interconnects 118 in the metallization layer 115 to be electrically bonded to the package substrate 102.

[0038] Package substrates including, but not limited to, those of Figures 1-3A and 8A-8E, having signal routing paths of Figures 3B and 5A-5B, and having pad metallization layers having metal layers having metal pads for forming external metal interconnects to provide increased signal routing capacity within internal adjacent metallization layers within the package substrate, according to the exemplary manufacturing process of Figures 6-7C, and according to any embodiment disclosed herein, can be provided within an IC package provided or integrated within any processor-based device. Examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, mobile phones, smartphones, session initiation protocol (SIP) phones, tablets, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smart watches, health or fitness trackers, eyewear, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multicopters.

[0039] In this regard, FIG. 9 illustrates an example of a processor-based system 900 including circuitry that may be provided within IC packages 902(1)-902(5). Any of the IC packages 902(1)-902(5) may include a package substrate including, but not limited to, the package substrate of FIGS. 1-3A and 8A-8E, including a pad metallization layer having a metal layer having metal pads for forming external metal interconnects to provide increased signal routing capacity within internal adjacent metallization layers within the package substrate, according to the exemplary manufacturing process of FIGS. 6-7C, and according to any aspect disclosed herein. In this example, the processor-based system 900 may be formed as an IC 904 within the IC package 902 and as a system-on-a-chip (SoC) 906. The processor-based system 900 includes a central processing unit (CPU) 908 including one or more processors 910, which may also be referred to as CPU cores or processor cores. The CPU 908 may have a cache memory 912 coupled to the CPU 908 for rapid access to temporarily stored data. The CPU 908 may be coupled to a system bus 914 to interconnect master and slave devices included in the processor-based system 900. As is well known, the CPU 908 communicates with these other devices by exchanging address, control, and data information via the system bus 914. For example, the CPU 908 may communicate bus transaction requests to a memory controller 916, which is an example of a slave device. Although not shown in FIG. 9, multiple system buses 914 may be provided, with each system bus 914 constituting a different fabric.

[0040] Other master and slave devices may be connected to the system bus 914. As shown in FIG. 9, these devices may include, by way of example, a memory system 920 including a memory controller 916 and a memory array(s) 918, one or more input devices 922, one or more output devices 924, one or more network interface devices 926, and one or more display controllers 928. Each of the memory system(s) 920, the one or more input devices 922, the one or more output devices 924, the one or more network interface devices 926, and the one or more display controllers 928 may be provided in the same or different IC packages 902(5). The input device(s) 922 may include any type of input device, including, but not limited to, input keys, switches, voice processors, and the like. The output device(s) 924 may include any type of output device, including, but not limited to, audio, video, other visual indicators, and the like. The network interface device(s) 926 may be any device configured to enable the exchange of data to and from the network 930. The network 930 may be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH network, and the Internet. The network interface device(s) 926 may be configured to support any type of communication protocol desired.

[0041] The CPU 908 may also be configured to access a display controller(s) 928 via the system bus 914 to control information sent to one or more displays 932. The display controller(s) 928 send information to be displayed to the display(s) 932 via one or more video processors 934 that process the information to be displayed in a format suitable for the display(s) 932. The display controller(s) 928 and the video processor(s) 934 may be included as ICs in the same or different IC package 902(5) and in the same or different IC package 902(1) that includes the CPU 908, as one example. The display(s) 932 may include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc.

[0042] FIG. 10 illustrates an exemplary wireless communication device 1000 including a radio frequency (RF) component formed from one or more IC packages 1002, any of which may include, but are not limited to, the package substrate of FIGS. 1-3A and 8A-8E, including a package substrate including a pad metallization layer having a metal layer having metal pads for forming external metal interconnects for providing increased signal routing capacity within an internal adjacent metallization layer within the package substrate, according to the exemplary manufacturing process of FIGS. 6-7C, and according to any aspect disclosed herein. The wireless communication device 1000 may include, or be provided within, any of the devices referenced above, as examples. As shown in FIG. 10, the wireless communication device 1000 includes a transceiver 1004 and a data processor 1006. The data processor 1006 may include a memory for storing data and program codes. The transceiver 1004 includes a transmitter 1008 and a receiver 1010 supporting bidirectional communication. In general, the wireless communication device 1000 may include any number of transmitters 1008 and / or receivers 1010 for any number of communication systems and frequency bands. All or a portion of the transceiver 1004 may be implemented in one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc.

[0043] The transmitter 1008 or receiver 1010 may be implemented with a super-heterodyne architecture or a direct-conversion architecture. In a super-heterodyne architecture, the signal is frequency converted between RF and baseband in multiple stages, e.g., from RF to intermediate frequency (IF) in one stage and then from IF to baseband in another stage for the receiver 1010. In a direct-conversion architecture, the signal is frequency converted between RF and baseband in one stage. The super-heterodyne and direct-conversion architectures may use different circuit blocks and / or have different requirements. In the wireless communication device 1000 of FIG. 10, the transmitter 1008 and receiver 1010 are implemented with a direct-conversion architecture.

[0044] On the transmit path, a data processor 1006 processes data to be transmitted and provides I and Q analog output signals to a transmitter 1008. In the example wireless communication device 1000, the data processor 1006 includes digital-to-analog converters (DACs) 1012(1), 1012(2) that convert digital signals generated by the data processor 1006 into I and Q analog output signals, e.g., I and Q output currents, for further processing.

[0045] Within the transmitter 1008, low pass filters 1014(1), 1014(2) filter the I and Q analog output signals, respectively, to remove undesired signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 1016(1), 1016(2) amplify the signals from the low pass filters 1014(1), 1014(2), respectively, and provide I and Q baseband signals. An upconverter 1018 upconverts the I and Q baseband signals along with I and Q TX local oscillator (LO) signals through mixers 1020(1), 1020(2) from a transmit (TX) local oscillator (LO) signal generator 1022 to provide an upconverted signal 1024. A filter 1026 filters the upconverted signal 1024 to remove undesired signals caused by frequency upconversion as well as noise in the receive frequency band. A power amplifier (PA) 1028 amplifies the upconverted signal 1024 from filter 1026 to obtain a desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 1030 and transmitted via an antenna 1032.

[0046] In the receive path, an antenna 1032 receives a signal transmitted by a base station and provides a receive RF signal, which is routed through a duplexer or switch 1030 and provided to a low noise amplifier (LNA) 1034. The duplexer or switch 1030 is designed to operate with a specific RX to TX duplexer frequency separation such that the receive (RX) signal is isolated from the TX signal. The received RF signal is amplified by the LNA 1034 and filtered by a filter 1036 to obtain a desired RF input signal. Downconversion mixers 1038(1), 1038(2) mix the output of the filter 1036 with I and Q RX LO signals (i.e., LO_I and LO_Q) from a RX LO signal generator 1040 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 1042(1), 1042(2) and further filtered by low pass filters 1044(1), 1044(2) to obtain I and Q analog input signals, which are provided to data processor 1006. In this embodiment, data processor 1006 includes analog-to-digital converters (ADCs) 1046(1), 1046(2) that convert the analog input signals to digital signals for further processing by data processor 1006.

[0047] In the wireless communication device 1000 of FIG. 10, the TX LO signal generator 1022 generates I and Q TX LO signals used for frequency up-conversion, while the RX LO signal generator 1040 generates I and Q RX LO signals used for frequency down-conversion. Each LO signal is a periodic signal having a particular fundamental frequency. The TX phase-locked loop (PLL) circuit 1048 receives timing information from the data processor 1006 and generates control signals used to adjust the frequency and / or phase of the TX LO signal from the TX LO signal generator 1022. Similarly, the RX PLL circuit 1050 receives timing information from the data processor 1006 and generates control signals used to adjust the frequency and / or phase of the RX LO signal from the RX LO signal generator 1040.

[0048] Those skilled in the art will further appreciate that the various exemplary logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, as instructions stored in a memory or in another computer-readable medium and executed by a processor or other processing device, or as a combination of both. The memories disclosed herein may be of any type and size and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various exemplary components, blocks, modules, circuits, and steps have been generally described above in terms of their functionality. How such functionality is implemented will depend on the particular application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may realize the described functionality in various ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0049] The various example logic blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0050] Aspects disclosed herein may be embodied in hardware or instructions stored in the hardware and may reside in, for example, a Random Access Memory (RAM), a flash memory, a Read Only Memory (ROM), an Electrically Programmable ROM (EPROM), an Electrically Erasable Programmable ROM (EEPROM), a register, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. Alternatively, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and the storage medium may reside as discrete components in a remote station, a base station, or a server.

[0051] It should also be noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The described operations may be performed in many different sequences other than the sequence shown. Furthermore, an operation described in a single operational step may actually be performed in several different steps. In addition, one or more operational steps discussed in the exemplary aspects may be combined. It should be understood that many different modifications may be made to the operational steps shown in the flowchart diagrams, as would be readily apparent to one of ordinary skill in the art. Those skilled in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0052] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0053] The following numbered clauses describe example implementations. 1. a first metallization layer, a first metal layer having a first thickness, a first metal layer comprising one or more first metal interconnects; a first metallization layer; a pad metallization layer having a first surface disposed adjacent the first metallization layer and a second surface opposite the first surface, a pad metal layer having a second thickness less than the first thickness, a pad metal layer adjacent to the second surface and comprising one or more metal pads each coupled to a first metal interconnect of the one or more first metal interconnects; a pad metallization layer; one or more external interconnects, each coupled to a metal pad of the one or more metal pads; A package substrate comprising: 2. 13. The package substrate of claim 1, wherein each metal pad of the one or more metal pads is coupled to one external interconnect of the one or more external interconnects. 3. the first metallization layer further comprises one or more second metal interconnects; each of the one or more second metal interconnects is not coupled to a metal pad of the one or more metal pads; 3. A packaging substrate as claimed in claim 1 or 2. 4. the one or more first metal interconnects each have a first width; the one or more second metal interconnects each have a second width that is less than the first width; 4. A packaging substrate as defined in clause 3. 5. 5. The package substrate of any one of clauses 1 to 4, wherein a ratio of the first thickness of the first metal layer to the second thickness of the pad metal layer is at least 1.2. 6. the first metal layer has a first thickness between 12 micrometers (μm) and 16 μm; The second thickness of the pad metal layer is 10 μm to 12 μm. 5. A packaging substrate according to any one of clauses 1 to 4. 7. the pad metallization layer further comprises a pad via layer disposed adjacent to the pad metal layer; the pad-via layer comprises one or more pad vias each coupled to a first metal interconnect of the one or more first metal interconnects and to a metal pad of the one or more metal pads; 7. A packaging substrate according to any one of clauses 1 to 6. 8. the first metallization layer further comprises a first via layer disposed adjacent to the first metal layer; the first via layer comprises one or more first vias each coupled to a first metal interconnect of the one or more first metal interconnects; 8. A packaging substrate as defined in clause 7. 9. a second metallization layer adjacent to the first metallization layer such that the first metallization layer is disposed between the second metallization layer and the pad metallization layer; 9. The package substrate of clause 8, further comprising a second metallization layer comprising a second metal layer comprising one or more second metal interconnects. 10. the one or more pad vias have a first height; the one or more first vias have a second height that is greater than the first height; 10. A packaging substrate as claimed in clause 8 or 9. 11. 11. The packaging substrate of any one of clauses 7 to 10, wherein the pad-via layer does not comprise a glass material. 12. the pad-via layer does not include a glass material; the first via layer comprises a glass material; 11. A packaging substrate according to any one of clauses 8 to 10. 13. the pad-via layer includes a photoimageable dielectric (PID) layer; the first via layer comprises a pre-impregnated glass (PPG) layer; 13. A packaging substrate according to any one of clauses 8 to 10 and 12. 14. the first via layer has a third thickness; the pad via layer has a fourth thickness less than the third thickness; 14. A packaging substrate according to any one of clauses 7 to 13. 15. 15. The packaging substrate of clause 14, wherein a ratio of the third thickness of the first via layer to the fourth thickness of the pad via layer is at least 1.6. 16. the third thickness of the first via layer is 25 μm to 45 μm; The fourth thickness of the pad via layer is 10 μm to 15 μm. 15. The packaging substrate of clause 14. 17. 17. The package substrate of any one of clauses 1 to 16, wherein the package substrate is integrated into a device selected from the group consisting of a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a Global Positioning System (GPS) device, a mobile phone, a mobile phone, a smartphone, a Session Initiation Protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multicopter. 18. 1. A method for manufacturing a package substrate for an integrated circuit (IC) package, comprising: forming a first metallization layer, forming a first metal layer having a first thickness; forming one or more first metal interconnects in a first metal layer; forming a first metallization layer, the first metallization layer comprising: forming a pad metallization layer having a first surface adjacent the first metallization layer and a second surface opposite the first surface; forming a pad metal layer having a second thickness less than the first thickness; forming one or more metal pads in a pad metal layer adjacent the second surface; coupling each metal pad of the one or more metal pads to a first metal interconnect of the one or more first metal interconnects; forming a pad metallization layer, comprising: forming one or more external interconnects each coupled to a metal pad of the one or more metal pads; A method comprising: 19. 20. The method of claim 18, wherein forming the one or more external interconnects includes bonding an external interconnect of the one or more external interconnects to a respective metal pad of the one or more metal pads. 20. forming one or more second metal interconnects in the first metallization layer; not coupling each of the one or more second metal interconnects to a metal pad of the one or more metal pads; 20. The method of claim 18 or 19, further comprising: twenty one. forming the one or more first metal interconnects includes forming one or more first metal interconnects in the first metal layer, each of a first width; forming the one or more second metal interconnects includes forming one or more second metal interconnects in the first metal layer, each of a second width less than the first width; The method described in clause 20. twenty two. forming a pad metallization layer; forming a pad via layer adjacent to the pad metal layer; forming one or more pad vias in the pad via layer, each pad via coupled to a first metal interconnect of the one or more first metal interconnects and to a metal pad of the one or more metal pads; Further comprising: 22. The method according to any one of clauses 18 to 21. twenty three. forming a first metallization layer; forming a first via layer adjacent to the first metal layer; forming one or more first vias each coupled to a first metal interconnect of the one or more first metal interconnects; Further comprising: 23. The method according to claim 22. twenty four. forming a second metallization layer adjacent to the first metallization layer such that the first metallization layer is disposed between the second metallization layer and the pad metallization layer; forming a second metal layer comprising one or more second metal interconnects; 24. The method of claim 23, further comprising forming a second metallization layer. twenty five. forming a first via layer in the first metallization layer includes forming a first via layer having a third thickness; forming a pad via layer in the pad metallization layer includes forming a pad via layer having a fourth thickness less than the third thickness; 25. The method according to any one of clauses 22 to 24. [Explanation of symbols]

[0054] 100 IC packages 102 Package Substrate 104 Outer Pad Metallization 106 3D stacked die IC package 108 Die 110 Die Package 112 Metallized layer 114 Metallized layer 115 Metallized layer 116 Die Interconnect 118 Metallic Interconnects 120 Metallic Interconnects 122 Metal Pad 124 External Interconnect 128 Interposer Board 130 Package mold 132 Metallized layer 134 Metallic Interconnects 136 External Interconnects 138 Vertical Interconnect 140 First Surface 142 Second Surface 144 Pad metal layer 146 Pad-Via Layer 148 Beer 150 via layer 152 Beer 154 Metallic Interconnects 156 Via Layer 158 Beer 160 metal layer 162 Metal layer 164 Metal layer 402 Package Substrate 404 Metallized layer 412 Metallized layer 414 Metallized layer 415 Metallized layer 416 Pad Via Layer 420 Metallic Interconnects 422 Metallic Interconnects 444 Metal layer 446 Via Layer 802 ETS package substrate 804 Dielectric Materials 806 Bottom 808 via opening 810 Career 812 Resist layer 814 Opening 900 System 902 IC package 910 Processor 912 Cache Memory 914 System Bus 916 Memory Controller 918 Memory Array 920 Memory System 922 Input Devices 924 Output Device 926 Network Interface Device 928 Display Controller 930 Network 932 Display 934 Video Processor 1000 Wireless Communication Devices 1002 IC package 1004 Transceiver 1006 Data Processor 1008 Transmitter 1010 Receiver 1014 Low-pass filter 1016 Amplifier 1018 Upconverter 1020 Mixer 1022 LO signal generator 1024 signal 1026 Filter 1028 Power Amplifier 1030 Switch 1032 Antenna 1036 Filter 1038 Downconversion mixer 1040 LO signal generator 1044 Low Pass Filter 1050 PLL circuit

Claims

1. a first metallization layer, a first metal layer having a first thickness, a first metal layer comprising one or more first metal interconnects; a first metallization layer; a pad metallization layer having a first surface disposed adjacent to the first metallization layer and a second surface opposite the first surface, a pad metal layer having a second thickness less than the first thickness, a pad metal layer adjacent the second surface and comprising one or more metal pads each coupled to a first metal interconnect of the one or more first metal interconnects; a pad via layer disposed adjacent to the pad metal layer, a pad-via layer comprising one or more pad vias each coupled to a first metal interconnect of the one or more first metal interconnects and to a metal pad of the one or more metal pads; Equipped with a pad metallization layer; one or more external interconnects each coupled to one of the one or more metal pads; A package substrate comprising:

2. The package substrate of claim 1 , wherein each metal pad of the one or more metal pads is coupled to one external interconnect of the one or more external interconnects.

3. the first metallization layer further comprises one or more second metal interconnects; each of the one or more second metal interconnects is not coupled to one of the one or more metal pads; the one or more first metal interconnects each have a first width; the one or more second metal interconnects each have a second width that is less than the first width; The package substrate of claim 1 .

4. a ratio of the first thickness of the first metal layer to the second thickness of the pad metal layer is at least 1.2; Preferably, the first thickness of the first metal layer is between 12 micrometers (μm) and 16 μm; the second thickness of the pad metal layer is 10 μm to 12 μm; The package substrate of claim 1 .

5. the first metallization layer further comprises a first via layer disposed adjacent to the first metal layer; the first via layer comprising one or more first vias each coupled to a first metal interconnect of the one or more first metal interconnects; The package substrate of claim 1 .

6. a second metallization layer adjacent to the first metallization layer such that the first metallization layer is disposed between the second metallization layer and the pad metallization layer; The package substrate of claim 5 further comprising a second metallization layer comprising a second metal layer comprising one or more second metal interconnects.

7. the one or more pad vias have a first height; the one or more first vias have a second height greater than the first height; The package substrate according to claim 5 .

8. 10. The package substrate of claim 1, wherein the pad-via layer does not include a glass material. or the pad-via layer does not include a glass material; the first via layer comprises a glass material; Preferably, the pad-via layer comprises a photoimageable dielectric (PID) layer; the first via layer comprises a pre-impregnated glass (PPG) layer; The package substrate according to claim 5 .

9. the first via layer has a third thickness; the pad-via layer has a fourth thickness less than the third thickness; a ratio of the third thickness of the first via layer to the fourth thickness of the pad via layer is at least 1.6; Preferably, the third thickness of the first via layer is 25 μm to 45 μm; the fourth thickness of the pad-via layer is 10 μm to 15 μm; The package substrate according to claim 5 .

10. 10. The package substrate of claim 1 integrated into a device selected from the group consisting of a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smartphone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multicopter.

11. 1. A method of manufacturing a package substrate for an integrated circuit (IC) package, comprising: forming a first metallization layer; forming a first metal layer having a first thickness; forming one or more first metal interconnects in the first metal layer; forming a first metallization layer, the first metallization layer comprising: forming a pad metallization layer having a first surface adjacent to the first metallization layer and a second surface opposite the first surface; forming a pad metal layer having a second thickness less than the first thickness; forming one or more metal pads in the pad metal layer adjacent the second surface; coupling each metal pad of the one or more metal pads to a first metal interconnect of the one or more first metal interconnects; forming a pad via layer adjacent to the pad metal layer; forming one or more pad vias in the pad via layer, each pad via coupled to a first metal interconnect of the one or more first metal interconnects and to a metal pad of the one or more metal pads; forming a pad metallization layer, forming one or more external interconnects each coupled to one of the one or more metal pads; A method comprising:

12. 12. The method of claim 11 , wherein forming the one or more external interconnects comprises coupling one external interconnect of the one or more external interconnects to a respective metal pad of the one or more metal pads.

13. forming one or more second metal interconnects within the first metallization layer; not coupling each of the one or more second metal interconnects to one of the one or more metal pads; Further comprising: forming the one or more first metal interconnects includes forming the one or more first metal interconnects in the first metal layer, each of the one or more first metal interconnects having a first width; 12. The method of claim 11 , wherein forming the one or more second metal interconnects comprises forming the one or more second metal interconnects in the first metal layer, each of the one or more second metal interconnects having a second width that is smaller than the first width.

14. forming the first metallization layer; forming a first via layer adjacent to the first metal layer; forming one or more first vias each coupled to a first metal interconnect of the one or more first metal interconnects; Further comprising: forming a second metallization layer adjacent to the first metallization layer such that the first metallization layer is disposed between the second metallization layer and the pad metallization layer; forming a second metal layer comprising one or more second metal interconnects; further comprising forming a second metallization layer. The method of claim 11.

15. forming the first via layer in the first metallization layer includes forming the first via layer having a third thickness; forming the pad via layer in the pad metallization layer includes forming the pad via layer having a fourth thickness less than the third thickness; The method of claim 11.

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