Integrated devices and integrated passive devices including magnetic materials

Abstract

The integrated device includes a die substrate including a plurality of transistors, an interconnect portion coupled to the die substrate, and a packaging portion coupled to the interconnect portion. The interconnect portion includes at least one die dielectric layer and a plurality of die interconnects coupled to the plurality of transistors. The packaging portion includes at least one magnetic layer and a plurality of metallization interconnects coupled to the plurality of die interconnects.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority to and the benefit of nonprovisional application Ser. No. 17 / 705,041, filed in the United States Patent Office on March 25, 2022, the entire contents of which are incorporated by reference herein as if fully set forth below in their entirety, and for all applicable purposes.

[0002] Various features relate to packages, integrated devices, and / or integrated passive devices. [Background technology]

[0003] The package may include a substrate, an integrated device, and an integrated passive device. The substrate may include a plurality of interconnects. The integrated device and / or the integrated passive device may be coupled to the interconnects of the substrate. There is currently a need to provide smaller packages with improved performance. Summary of the Invention

[0004] Various features relate to packages, integrated devices, and / or integrated passive devices.

[0005] One example provides an integrated device including a die substrate including a plurality of transistors, an interconnect portion coupled to the die substrate, and a packaging portion coupled to the interconnect portion. The interconnect portion includes at least one die dielectric layer and a plurality of die interconnects coupled to the plurality of transistors. The packaging portion includes at least one magnetic layer and a plurality of metallization interconnects coupled to the plurality of die interconnects.

[0006] Another example provides a device including a die substrate, an interconnect portion coupled to the die substrate, and a packaging portion coupled to the interconnect portion, the interconnect portion including at least one die dielectric layer and a plurality of die interconnects, the packaging portion including at least one magnetic layer and a plurality of metallization interconnects coupled to the plurality of die interconnects.

[0007] Another example provides a method of providing a die substrate, the method forming an interconnect portion on the die substrate, where forming the interconnect portion includes forming at least one die dielectric layer and forming a plurality of die interconnects, the method forming a packaging portion on the interconnect portion, where forming the packaging portion includes forming a plurality of metallization interconnects coupled to the plurality of die interconnects and forming at least one magnetic layer.

[0008] Various features, nature and advantages may become apparent from the following detailed description when read in conjunction with the drawings in which like reference characters identify correspondingly throughout. [Brief description of the drawings]

[0009] [Figure 1] 1 illustrates an exemplary side view of a package including a substrate, an integrated device, and an integrated passive device. [Diagram 2] 1 is an exemplary side view of an integrated device including magnetic material. [Diagram 3] 2 is another exemplary side view of an integrated device including magnetic material. [Figure 4] FIG. 1 illustrates an exemplary side view of an integrated passive device (IPD) including magnetic material. [Diagram 5] FIG. 2 is another exemplary side view of an integrated passive device (IPD) including magnetic material. [Figure 6] 1 is an example diagram of a device including an inductor disposed within a magnetic material. [Figure 7]1 is an example graph of quality factors of several example inductors at various frequencies. [Figure 8] 1 is an example graph of inductance of several example inductors at various frequencies. [Figure 9] 1 is an exemplary table showing the inductance and quality factor of several exemplary inductors. [Figure 10A] 1A-1C illustrate an exemplary sequence for manufacturing an integrated device including magnetic material. [Figure 10B] 1A-1C illustrate an exemplary sequence for manufacturing an integrated device including magnetic material. [Figure 10C] 1A-1C illustrate an exemplary sequence for manufacturing an integrated device including magnetic material. [Figure 10D] 1A-1C illustrate an exemplary sequence for manufacturing an integrated device including magnetic material. [Figure 10E] 1A-1C illustrate an exemplary sequence for manufacturing an integrated device including magnetic material. [Figure 10F] 1A-1C illustrate an exemplary sequence for manufacturing an integrated device including magnetic material. [Figure 10G] 1A-1C illustrate an exemplary sequence for manufacturing an integrated device including magnetic material. [Figure 10H] 1A-1C illustrate an exemplary sequence for manufacturing an integrated device including magnetic material. [Figure 10I] 1A-1C illustrate an exemplary sequence for manufacturing an integrated device including magnetic material. [Figure 11] FIG. 1 is an exemplary flow diagram of a method for manufacturing an integrated device including magnetic material. [Figure 12] FIG. 13 is another exemplary flow diagram of a method for manufacturing an integrated device including magnetic material. [Figure 13] FIG. 1 illustrates an example flow diagram of a method for manufacturing a package including a substrate, an integrated device, and an integrated passive device. [Figure 14]FIG. 1 illustrates an example flow diagram of a method for manufacturing a package including a substrate, an integrated device, and an integrated passive device. [Figure 15] FIG. 1 illustrates various electronic devices that may integrate the die, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In the following description, specific details are described to provide a thorough understanding of various aspects of the present disclosure. However, it will be understood by those skilled in the art that aspects can be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring aspects in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure aspects of the present disclosure.

[0011] The present disclosure describes a package including a substrate and an integrated device coupled to the substrate. The integrated device includes a die substrate including a plurality of transistors, an interconnect portion coupled to the die substrate, and a packaging portion coupled to the interconnect portion. The interconnect portion includes at least one die dielectric layer and a plurality of die interconnects coupled to the plurality of transistors. The packaging portion includes at least one magnetic layer and a plurality of metallization interconnects coupled to the plurality of die interconnects. The packaging portion includes an inductor defined by at least one metallization interconnect from the plurality of metallization interconnects. The at least one magnetic layer includes an insulating layer, a dielectric layer, and / or a non-conductive material. The at least one magnetic layer has a permeability value (e.g., a relative permeability value) greater than 1. The magnetic layer is configured to help improve (e.g., increase) a quality factor (Q) and / or inductance of an inductor within the packaging portion. As described further below, by helping to improve the quality factor and / or inductance of the inductor, inductors having a smaller form factor (e.g., size) may be formed within the packaging while still having a quality factor and / or inductance that is equal to or better than the quality factor and / or inductance of a larger inductor.

[0012] Exemplary Integrated Devices Including Magnetic Materials 1 shows a side view of a package 100 including a substrate 102, an integrated device 103, and an integrated passive device 105 (IPD). The package 100 is coupled to a board 106 via a number of solder interconnects 110. The board 106 includes at least one board dielectric layer 160 and a number of board interconnects 162. The board 106 may include a printed circuit board (PCB).

[0013] The substrate 102 includes at least one dielectric layer 120 (e.g., a substrate dielectric layer), a plurality of interconnects 122 (e.g., substrate interconnects), a solder resist layer 140, and a solder resist layer 142. The integrated device 103 is coupled to the substrate 102 via a plurality of solder interconnects 130. The integrated passive device 105 is coupled to the substrate 102 via a plurality of solder interconnects 150. The substrate may have a different number of metal layers. Different implementations may use different substrates. The substrate may include an embedded trace substrate (ETS). The at least one dielectric layer 120 may include a prepreg.

[0014] The package (e.g., 100) may be implemented in a radio frequency (RF) package. The RF package may be a radio frequency front end (RFFE) package. The package (e.g., 100) may be configured to provide Wireless Fidelity (WiFi) communications and / or cellular communications (e.g., 2G, 3G, 4G, 5G). The package (e.g., 100) may be configured to support Global System for Mobile (GSM) communications, Universal Mobile Telecommunications System (UMTS), and / or Long-Term Evolution (LTE). The package (e.g., 100) may be configured to transmit and receive signals having different frequencies and / or different communication protocols.

[0015] As described further below, the integrated device 103 and / or the integrated passive device 105 may include at least one magnetic layer. The at least one magnetic layer may include an insulating layer, a dielectric layer, and / or a non-conductive material (e.g., a material that does not conduct electricity). The at least one magnetic layer may have a permeability value greater than 1 (e.g., greater than about 10, in the range of 6-12). The magnetic layers may have different permeability values ​​at different frequencies. The permeability values ​​of the magnetic materials and / or layers described in this disclosure are relative permeability values, defined as the ratio of the permeability of the material to the permeability of free space. Thus, the permeability values ​​described for the magnetic materials and / or layers illustrated and / or described in this disclosure may represent relative permeability values ​​relative to a defined permeability value of free space (e.g., a reference permeability value). In some implementations, free space has a permeability value of μ0=4π×10 -7 It can be defined to have a defined permeability value of H / m (Henry / meter). Materials that have a relative permeability value greater than 1 can be considered to be magnetic materials.

[0016] At least one magnetic layer is configured to improve the inductance and / or quality factor of an inductor disposed within and / or surrounded by the magnetic layer, with the improved inductor performance allowing smaller, more compact inductors to be formed within the integrated device 103 and / or the integrated passive device 105.

[0017] 2 illustrates an exemplary cross-sectional side view of an integrated device 103. The integrated device 103 may include a die (e.g., a semiconductor die). The integrated device 103 includes a die substrate 200, a plurality of transistors 210, at least one oxide layer 220, at least one die dielectric layer 224, a plurality of die interconnects 221, a high-K dielectric layer 222, a passivation layer 226, at least one magnetic layer 240, a plurality of metallization interconnects 241, a passivation layer 250, a plurality of pillar interconnects 251, and a plurality of solder interconnects 130.

[0018] The integrated device 103 may include an active portion 201, an interconnect portion 202, and a packaging portion 204. The active portion 201 may include a back end of line (BEOL) portion. The interconnect portion 202 may be a die interconnect portion. The interconnect portion 202 may include a front end of line (FEOL) portion. The packaging portion 204 may include a redistribution portion (e.g., an RDL portion). The interconnect portion 202 is coupled to the active portion 201. The interconnect portion 202 is disposed on the active portion 201. The packaging portion 204 is coupled to the interconnect portion 202. The packaging portion 204 is disposed on the interconnect portion 202. The interconnect portion 202 is disposed between the active portion 201 and the packaging portion 204.

[0019] The active portion 201 may include a die substrate 200, a plurality of transistors 210, and / or at least one oxide layer 220. The plurality of transistors 210 may be formed and / or disposed in and / or on the die substrate 200. The die substrate 200 may include silicon (Si). The plurality of transistors 210 may form and / or define one or more logic blocks. The at least one oxide layer 220 is disposed on the die substrate 200 and / or the plurality of transistors 210. The plurality of transistors 210 may be any type of transistor (e.g., CMOS transistors, planar transistors, field effect transistors). The at least one oxide layer 220 may include silicon dioxide. A back-end-of-line (BEOL) process may be used to fabricate and / or form the plurality of transistors 210 and / or the at least one oxide layer 220. The interconnect portion 202 is coupled to the die substrate 200 , the plurality of transistors 210 , and / or the at least one oxide layer 220 .

[0020] The interconnect portion 202 may include a plurality of die interconnects 221, at least one die dielectric layer 224, a high-K dielectric layer 222, and / or a passivation layer 226. The plurality of die interconnects 221 may include at least one die interconnect 225, at least one die interconnect 227, and at least one die interconnect 229 (e.g., 229a, 229b). The plurality of die interconnects 221 may be coupled to a plurality of transistors 210. For example, the at least one die interconnect 225 may be coupled (e.g., directly or indirectly) to the plurality of transistors 210. The passivation layer 226 may be disposed on the at least one die dielectric layer 224 and / or the at least one die interconnect 229 (e.g., 229a, 229b).

[0021] The interconnect portion 202 includes a capacitor 203 defined by at least a portion of the at least one die interconnect 225, a high K dielectric layer 222, and at least a portion of the at least one die interconnect 227. The capacitor 203 may be disposed within the at least one die dielectric layer 224. The high K dielectric layer 222 is disposed between the at least one die interconnect 225 and the at least one die interconnect 227. The high K dielectric layer 222 may have a higher dielectric constant than the dielectric constant of the at least one die dielectric layer 224.

[0022] At least one die interconnect 225 may be disposed on a first metal layer (M1) of the integrated device, at least one die interconnect 227 may be disposed on a second metal layer (M2) of the integrated device, and at least one die interconnect 229 may be disposed on a third metal layer (M3) of the integrated device. It is noted that there may be at least one via die interconnect between the first metal layer (M1) and the third metal layer (M3). It is also noted that there may be at least one via die interconnect between the second metal layer (M2) and the third metal layer (M3). The via die interconnect(s) between the first metal layer (M1) and the third metal layer (M3) and the via die interconnect(s) between the second metal layer (M2) and the third metal layer (M3) are considered to be part of the multiple die interconnects 221.

[0023] The packaging portion 204 includes a plurality of metallization interconnects 241, at least one magnetic layer 240, a passivation layer 250, and / or a plurality of pillar interconnects 251. The plurality of solder interconnects 130 may be coupled to the plurality of pillar interconnects 251. The plurality of metallization interconnects 241 may include at least one metallization interconnect 242, at least one metallization interconnect 243, at least one metallization interconnect 244, at least one metallization interconnect 245, and / or at least one metallization interconnect 246. The at least one metallization interconnect 243 may be disposed on a fourth metal layer (M4) of the integrated device, and the at least one metallization interconnect 245 may be disposed on a fifth metal layer (M5) of the integrated device. At least one metallization interconnect 242 may include via metallization interconnect(s). At least one metallization interconnect 244 may include via metallization interconnect(s). At least one metallization interconnect 246 may include via metallization interconnect(s). The plurality of metallization interconnects 241 may include a plurality of redistribution interconnects (e.g., redistribution layer (RDL) interconnects). A passivation layer 250 may be formed and / or disposed on the at least one magnetic layer 240. The passivation layer 250 may include polyimide (PI). The plurality of metallization interconnects 241 are coupled to the plurality of die interconnects 221. For example, at least one metallization interconnect 242 is coupled to at least one die interconnect 229 through one or more openings in the passivation layer 226.

[0024] The packaging portion 204 includes at least one inductor defined and / or formed from at least one metallization interconnect from the plurality of metallization interconnects 241. For example, the at least one inductor may be defined by at least one metallization interconnect 243 and / or at least one metallization interconnect 245. The inductor and / or the at least one metallization interconnect from the plurality of metallization interconnects 241 may be disposed within the at least one magnetic layer 240. The combination of the capacitor 203 in the interconnect portion 202 and the inductor in the packaging portion 204 may be used as a filter for one or more signals.

[0025] The at least one magnetic layer 240 includes magnetic layer 240a, magnetic layer 240b, and magnetic layer 240c. The at least one magnetic layer 240 includes an insulating layer, a dielectric layer, and / or a non-conductive material. The at least one magnetic layer 240 can be both a dielectric material and a magnetic material. Thus, the at least one magnetic layer 240 can have both dielectric and magnetic properties. The at least one magnetic layer 240 can include one or more materials. The at least one magnetic layer 240 has a permeability value greater than 1 (e.g., greater than about 10, in the range of 6-12). The magnetic layers can have different permeability values ​​at different frequencies. The permeability values ​​of the magnetic materials and / or layers described in this disclosure are relative permeability values, defined as the ratio of the permeability of a material to the permeability of free space. Thus, the magnetic permeability values ​​described for the magnetic materials and / or layers shown and / or described in this disclosure may represent relative magnetic permeability values ​​relative to a defined magnetic permeability value (e.g., a reference magnetic permeability value) of free space. In some implementations, free space has a permeability value μ0=4π×10 -7The at least one magnetic layer 240 may be defined to have a defined permeability value of H / m (henry / meter). A material having a relative permeability value greater than 1 may be considered to be a magnetic material. The at least one magnetic layer 240 includes a magnetic loss tangent value in the range of about 0.01 to 0.04. The at least one magnetic layer 240 may include Ajinomoto Magnetic Film (AMF). The at least one magnetic layer 240 surrounds (e.g., partially surrounds, completely surrounds) the inductor and / or the plurality of metallization interconnects 241. For example, the at least one magnetic layer 240 includes (e.g., has magnetic properties) a magnetic material that (i) is in contact with the inductor and / or the plurality of metallization interconnects 241 and (ii) at least partially surrounds the inductor (or a portion of the inductor) and / or the plurality of metallization interconnects 241 (or a portion of the plurality of metallization interconnects 241). The at least one magnetic layer 240 is configured to improve the inductance and / or quality factor of an inductor disposed within and / or surrounded by the at least one magnetic layer 240. The improved inductor performance may result in smaller, more compact inductors being formed within the integrated device 103.

[0026] Magnetic layer 240a, magnetic layer 240b, and magnetic layer 240c may be considered as one magnetic layer or as separate magnetic layers. In some implementations, there may be more or less than three magnetic layers. In some implementations, magnetic layer 240a, magnetic layer 240b, and magnetic layer 240c may have the same properties (e.g., same permeability, same magnetic loss tangent value). In some implementations, magnetic layer 240a, magnetic layer 240b, and / or magnetic layer 240c may have different properties (e.g., different permeability, different magnetic loss tangent values). For example, a first magnetic layer may have a first permeability (e.g., a first permeability value, a first relative permeability value) and a first magnetic loss tangent value, and a second magnetic layer may have a second permeability (e.g., a second permeability value, a second relative permeability value) and a second magnetic loss tangent value. In some implementations, magnetic layer 240a, magnetic layer 240b, and / or magnetic layer 240c may have similar and / or the same values ​​for some properties and different values ​​for other properties. A more detailed description of how at least one magnetic layer 240 helps improve the performance of the inductor is further described below in at least Figures 7-9.

[0027] Figure 3 shows another exemplary diagram of an integrated device 103. The integrated device 103 of Figure 3 is similar to the integrated device 103 of Figure 2 and therefore includes similar components as the integrated device 103 of Figure 2. The integrated device 103 of Figure 3 does not include a passivation layer 250 over the magnetic layer 240c. Additionally, in Figure 3, the integrated device 103 includes a thicker layer of the magnetic layer 240c.

[0028] The integrated device (e.g., 103) may include a die (e.g., a semiconductor bare die). The integrated device may include a power management integrated circuit (PMIC). The integrated device may include an application processor. The integrated device may include a modem. The integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a gallium arsenide (GaAs)-based integrated device, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si)-based integrated device, a silicon carbide (SiC)-based integrated device, a memory, a power management processor, and / or combinations thereof. The integrated device (e.g., 103) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). The integrated device may include a transistor. The integrated device may be an example of an electrical component and / or an electrical device. In some implementations, an integrated device may include chiplets. Chiplets may be manufactured using processes that provide better yields compared to other processes used to manufacture other types of integrated devices, which may lower the overall cost of manufacturing the chiplets. Different chiplets may have different sizes and / or shapes. Different chiplets may be configured to provide different functions. Different chiplets may have different interconnect densities (e.g., interconnects with different widths and / or spacings). In some implementations, several chiplets may be used to perform the functions of one or more chips (e.g., one or more integrated devices). Using several chiplets that perform several functions may reduce the overall cost of the package compared to using a single chip to perform all of the functions of the package.

[0029] Exemplary Integrated Passive Devices (IPDs) Including Magnetic Materials 4 illustrates an exemplary cross-sectional side view of an integrated passive device 105. The integrated passive device 105 may include a passive die. The integrated passive device 105 includes a die substrate 200, at least one oxide layer 220, at least one die dielectric layer 224, a plurality of die interconnects 221, a high-K dielectric layer 222, a passivation layer 226, at least one magnetic layer 240, a plurality of metallization interconnects 241, a passivation layer 250, a plurality of pillar interconnects 251, and a plurality of solder interconnects 150.

[0030] Integrated passive device 105 may be similar to integrated device 103 and therefore includes the same or similar components as integrated device 103. However, integrated passive device 105 may not have multiple transistors in die substrate 200. Integrated passive device 105 may not have any active devices in die substrate 200.

[0031] The integrated passive device 105 may include an interconnect portion 202 and a packaging portion 204. The interconnect portion 202 may be a die interconnect portion. The interconnect portion 202 may include a front-end-of-line (FEOL) portion. The packaging portion 204 may include a redistribution portion (e.g., an RDL portion). The interconnect portion 202 is coupled to a die substrate 200 and / or at least one oxide layer 220. The interconnect portion 202 is disposed on the die substrate 200 and / or at least one oxide layer 220. The packaging portion 204 is coupled to the interconnect portion 202. The packaging portion 204 is disposed on the interconnect portion 202. The interconnect portion 202 is disposed between the die substrate 200 and the packaging portion 204.

[0032] The interconnect portion 202 may include a plurality of die interconnects 221, at least one die dielectric layer 224, a high-K dielectric layer 222, and / or a passivation layer 226. The plurality of die interconnects 221 may include at least one die interconnect 225, at least one die interconnect 227, and at least one die interconnect 229 (e.g., 229a, 229b). The passivation layer 226 may be disposed on the at least one die dielectric layer 224 and / or the at least one die interconnect 229 (e.g., 229a, 229b).

[0033] The interconnect portion 202 includes a capacitor 203 defined by at least a portion of the at least one die interconnect 225, a high K dielectric layer 222, and at least a portion of the at least one die interconnect 227. The capacitor 203 may be disposed within the at least one die dielectric layer 224. The high K dielectric layer 222 is disposed between the at least one die interconnect 225 and the at least one die interconnect 227.

[0034] At least one die interconnect 225 may be disposed on a first metal layer (M1) of the integrated passive device, at least one die interconnect 227 may be disposed on a second metal layer (M2) of the integrated passive device, and at least one die interconnect 229 may be disposed on a third metal layer (M3) of the integrated passive device. It is noted that there may be at least one via die interconnect between the first metal layer (M1) and the third metal layer (M3). It is also noted that there may be at least one via die interconnect between the second metal layer (M2) and the third metal layer (M3). The via die interconnect(s) between the first metal layer (M1) and the third metal layer (M3) and the via die interconnect(s) between the second metal layer (M2) and the third metal layer (M3) are considered to be part of the multiple die interconnects 221.

[0035] The packaging portion 204 includes a plurality of metallization interconnects 241, at least one magnetic layer 240, a passivation layer 250, and / or a plurality of pillar interconnects 251. The plurality of solder interconnects 150 may be coupled to the plurality of pillar interconnects 251. The plurality of metallization interconnects 241 may include at least one metallization interconnect 242, at least one metallization interconnect 243, at least one metallization interconnect 244, at least one metallization interconnect 245, and / or at least one metallization interconnect 246. The at least one metallization interconnect 243 may be disposed on a fourth metal layer (M4) of the integrated passive device, and the at least one metallization interconnect 245 may be disposed on a fifth metal layer (M5) of the integrated passive device. At least one metallization interconnect 242 may include via metallization interconnect(s). At least one metallization interconnect 244 may include via metallization interconnect(s). At least one metallization interconnect 246 may include via metallization interconnect(s). The plurality of metallization interconnects 241 may include a plurality of redistribution interconnects (e.g., redistribution layer (RDL) interconnects). A passivation layer 250 may be formed and / or disposed on the at least one magnetic layer 240. The passivation layer 250 may include polyimide (PI). The plurality of metallization interconnects 241 are coupled to the plurality of die interconnects 221. For example, at least one metallization interconnect 242 is coupled to at least one die interconnect 229 through one or more openings in the passivation layer 226.

[0036] Packaging portion 204 includes at least one inductor defined and / or formed from at least one metallization interconnect from multiple metallization interconnects 241. For example, the at least one inductor may be defined by at least one metallization interconnect 243 and / or at least one metallization interconnect 245. The combination of capacitor 203 in interconnect portion 202 and inductor in packaging portion 204 may be used as a filter for one or more signals.

[0037] The at least one magnetic layer 240 includes magnetic layer 240a, magnetic layer 240b, and magnetic layer 240c. The at least one magnetic layer 240 includes an insulating layer, a dielectric layer, and / or a non-conductive material. The at least one magnetic layer 240 has a permeability value (e.g., a relative permeability value) greater than 1 (e.g., about 10). The at least one magnetic layer 240 includes a magnetic loss tangent value in the range of about 0.01 to 0.04. The at least one magnetic layer 240 surrounds the inductor and / or the plurality of metallization interconnects 241. The at least one magnetic layer 240 is configured to improve the inductance and / or quality factor of the inductor disposed within and / or surrounded by the at least one magnetic layer 240. Inductance is related to the magnetic energy (via a magnetic field) stored by the conductor and / or inductor. Conductors and / or inductors that are surrounded by magnetic material (e.g., at least one magnetic layer 240) store more energy and therefore have a higher inductance. Furthermore, the quality factor of the inductor (defined by dividing the magnetic energy by the loss energy) increases if the loss energy (related to the loss tangent) does not increase proportionately at the same time. The improved inductor performance allows smaller and more compact inductors to be formed within the integrated passive device 105. Thus, if an application requires an inductor with minimum inductance and / or minimum quality factor, instead of providing a larger form factor inductor without a magnetic layer, a smaller form factor inductor surrounded by a magnetic layer can be provided.

[0038] In some implementations, magnetic layers 240a, 240b, and 240c may have the same properties (e.g., same permeability, same magnetic loss tangent value). In some implementations, magnetic layers 240a, 240b, and / or 240c may have different properties (e.g., different permeability, different magnetic loss tangent values). For example, a first magnetic layer may have a first permeability (e.g., a first permeability value, a first relative permeability value) and a first magnetic loss tangent value, and a second magnetic layer may have a second permeability (e.g., a second permeability value, a second relative permeability value) and a second magnetic loss tangent value. In some implementations, magnetic layers 240a, 240b, and / or 240c may have similar and / or the same values ​​for some properties and different values ​​for other properties.

[0039] Figure 5 shows another example diagram of an integrated passive device 105. The integrated passive device 105 of Figure 5 is similar to the integrated passive device 105 of Figure 4 and therefore includes similar components as the integrated passive device 105 of Figure 4. The integrated passive device 105 of Figure 5 does not include a passivation layer 250 over the magnetic layer 240c. Additionally, in Figure 5, the integrated passive device 105 includes a thicker layer of magnetic layer 240c.

[0040] FIG. 6 illustrates a device 600 including an inductor 602 and at least one magnetic layer 604. The device 600 may represent an integrated device 103 and / or an integrated passive device 105. The inductor 602 may be formed within a packaging portion of the device 600. The inductor 602 may be formed and / or defined by at least one metallization interconnect within the packaging portion of the device 600. The inductor 602 may be surrounded by at least one magnetic layer 604. The at least one magnetic layer 604 may be similar and / or the same as the at least one magnetic layer 240. It is noted that the device 600 may include more than one inductor. The inductors may have different shapes, sizes, windings, configurations, and / or arrangements. The inductors may be disposed on one or more metal layers (e.g., metallization layers) of the device 600.

[0041] 7 illustrates an example graph 700 illustrating the quality factor (Q) of several inductors over example frequencies. The graph 700 includes a first plot line 710 for a first inductor, a second plot line 720 for a second inductor, a third plot line 730 for a third inductor, and a fourth plot line 740 for a fourth inductor.

[0042] 8 illustrates an example graph 800 showing the inductance of several inductors over example frequencies. The graph 800 includes a first plot line 810 for a first inductor, a second plot line 820 for a second inductor, a third plot line 830 for a third inductor, and a fourth plot line 840 for a fourth inductor.

[0043] The first inductor, the second inductor, the third inductor, and the fourth inductor have the same design, however, the first inductor, the second inductor, the third inductor, and the fourth inductor are each surrounded by a different dielectric layer having different properties.

[0044] FIG. 9 shows an example table 900 illustrating various inductances and quality factors of a first inductor, a second inductor, a third inductor, and a fourth inductor at a particular frequency.

[0045] The first inductor (associated with first plot line 710 and first plot line 810) is not surrounded by a magnetic material, but instead is surrounded by a non-magnetic dielectric material having a loss tangent (e.g., electrical loss tangent) of 0.01, resulting in an inductance of 1 nanohenry (nH) at 1.5 GHz and a quality factor (Q) of 20 at 1.5 GHz. The second inductor (associated with second plot line 720 and second plot line 820) is surrounded by a magnetic material having a permeability of 10 and a loss tangent (e.g., magnetic loss tangent) of 0.04, resulting in an inductance of 7 nH at 1.5 GHz and a quality factor (Q) of 23 at 1.5 GHz. The third inductor (associated with third plot line 730 and third plot line 830) is surrounded by a magnetic material having a permeability of 10 and a loss tangent (e.g., magnetic loss tangent) of 0.02, resulting in an inductance of 7 nH at 1.5 GHz and a quality factor (Q) of 40 at 1.5 GHz. The fourth inductor (associated with fourth plot line 740 and fourth plot line 840) is surrounded by a magnetic material having a permeability of 10 and a loss tangent (e.g., magnetic loss tangent) of 0.01, resulting in an inductance of 7 nH at 1.5 GHz and a quality factor (Q) of 60 at 1.5 GHz.

[0046] Thus, the above example demonstrates that the magnetic layer can improve the inductance of the inductor by a factor of seven. One advantage of a more effective and / or powerful inductor design is that a smaller and more compact inductor can be provided within the integrated device and / or integrated passive device while still meeting the design and / or performance requirements of the integrated device and / or integrated passive device. This can help reduce the overall size and / or form factor of the integrated device and / or integrated passive device.

[0047] It should be noted that the graphs and values ​​shown in Figures 7-9 are exemplary. Different implementations may have the same, similar, or different values ​​over the same or different frequencies. For example, a magnetic layer (e.g., magnetic dielectric layer) permeability value of 10 is exemplary. Other magnetic layers having other permeability values ​​(e.g., relative permeability values) greater than 1 may be used (e.g., 1, 6.5, 7, 8, 11). It should be noted that magnetic layers may have different permeability values ​​for different frequencies.

[0048] Having described various integrated devices and / or integrated passive devices having at least one magnetic layer, a process for fabricating an integrated device having at least one magnetic layer is described below.

[0049] Exemplary sequence for fabricating an integrated device including a magnetic layer 10A-10I illustrate an example sequence for providing or manufacturing an integrated device including at least one magnetic layer, which in some implementations may be used to provide or manufacture an integrated device 103 as described in this disclosure.

[0050] It should be noted that the sequence of Figures 10A-10I may combine one or more steps to simplify and / or clarify the sequence for providing or manufacturing an integrated device. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be exchanged or substituted without departing from the spirit of the disclosure. In different implementations, the integrated device may be manufactured differently. It should be noted that the sequence of Figures 10A-10I may be used to manufacture an integrated passive device (e.g., 105) that includes at least one magnetic layer. The sequence shown in Figures 10A-10I may be performed on a wafer (e.g., a silicon wafer) and then singulated into several integrated devices. A similar approach may be performed for the integrated passive device.

[0051] Stage 1, as shown in Figure 10A, illustrates a state after a die substrate 200 is provided. The die substrate 200 may include silicon (Si). A plurality of transistors 210 may be formed in and / or on the die substrate 200. BEOL processes may be used to fabricate the plurality of transistors 210. Providing the die substrate 200 may include providing a wafer (e.g., a silicon wafer).

[0052] Stage 2 shows the state after at least one oxide layer 220 is formed on the die substrate 200 and / or the plurality of transistors 210. The at least one oxide layer 220 may include silicon dioxide. A deposition process and / or lamination process may be used to form the at least one oxide layer 220. The at least one oxide layer 220 may be formed from plasma enhanced tetraethyl orthosilicate (PE TEOS). In some implementations, the at least one oxide layer 220 may already be formed when the die substrate 200 is provided in Stage 1.

[0053] Stage 3 illustrates the state after at least one die interconnect 225 is formed on the at least one oxide layer 220. The at least one die interconnect 225 may be formed on the die substrate 200 and / or the plurality of transistors 210. The at least one die interconnect 225 may be coupled (e.g., directly or indirectly) to the plurality of transistors 210 through one or more openings in the at least one oxide layer 220. Plating and patterning processes may be used to form the at least one die interconnect 225.

[0054] Stage 4 shows the state after high K dielectric layer 222 is formed over at least a portion of at least one die interconnect 225. High K dielectric layer 222 may include silicon nitride. Deposition, stacking, and / or patterning processes may be used to form high K dielectric layer 222.

[0055] Stage 5 shows the state after at least one solder interconnect 227 is formed on the at least one high-K dielectric layer 222. Plating and patterning processes may be used to form the at least one die interconnect 227. At least a portion of the at least one die interconnect 225, the high-K dielectric layer 222, and the at least one die interconnect 227 may form and / or define a capacitor.

[0056] Stage 6, as shown in FIG. 10B, illustrates the state after the at least one die dielectric layer 224 has been formed and patterned. Deposition, lamination, exposure, development, and / or etching processes may be used to form and pattern the at least one die dielectric layer 224. The at least one die dielectric layer 224 may be formed over and around the at least one die interconnect 225 and the at least one die interconnect 227. The at least one die dielectric layer 224 may include a plurality of cavities 1024. The at least one die dielectric layer 224 may be formed such that the at least one die interconnect 225, the high K dielectric layer 222, and the at least one die interconnect 227 are disposed within the at least one die dielectric layer 224.

[0057] Stage 7 illustrates the state after at least one solder interconnect 229 is formed on the at least one die dielectric layer 224. Plating and patterning processes may be used to form the at least one die interconnect 229. Forming the at least one die interconnect 229 may include forming a via die interconnect in the at least one die dielectric layer 224 (e.g., in the cavity 1024 of the at least one die dielectric layer 224). The via die interconnect(s) may be considered part of the at least one die interconnect 229. The at least one die interconnect 229 may be coupled to the at least one die interconnect 225 and the at least one die interconnect 227.

[0058] Stage 8 shows the state after a passivation layer 226 is formed over the at least one die interconnect 229 and / or the at least one die dielectric layer 224. The passivation layer 226 may include silicon dioxide and / or silicon nitride. A deposition and / or lamination process may be used to form the passivation layer 226.

[0059] 10C, after at least one metallization interconnect 242 has been formed through at least one opening in the passivation layer 226. A plating process and a patterning process may be used to form the at least one metallization interconnect 242. The at least one metallization interconnect 242 may be bonded to at least one die interconnect 229.

[0060] Stage 10 shows the state after the magnetic layer 240a is formed over the passivation layer 226 and the at least one metallization interconnect 242. A lamination process may be used to form the magnetic layer 240a. A grinding process may be used to remove a portion of the magnetic layer 240a and expose the at least one metallization interconnect 242. A portion of the at least one metallization interconnect 242 may also be ground away.

[0061] Stage 11 shows the state after at least one metallization interconnect 243 is formed on the at least one metallization interconnect 242 and the magnetic layer 240a. A plating process and a patterning process may be used to form the at least one metallization interconnect 243. The at least one metallization interconnect 243 is bonded to the at least one metallization interconnect 242.

[0062] Stage 12, as shown in Figure 10D, illustrates the state after at least one metallization interconnect 244 is formed on the at least one metallization interconnect 243. A plating process and a patterning process may be used to form the at least one metallization interconnect 245. The at least one metallization interconnect 244 is bonded to the at least one metallization interconnect 243.

[0063] Stage 13 shows the state after magnetic layer 240b is formed over at least one metallization interconnect 243, at least one metallization interconnect 244, and magnetic layer 240a. A lamination process may be used to form magnetic layer 240b. A grinding process may be used to remove a portion of magnetic layer 240b and expose at least one metallization interconnect 244. A portion of at least one metallization interconnect 244 may also be ground away.

[0064] Stage 14 illustrates the state after at least one metallization interconnect 245 is formed on the at least one metallization interconnect 244 and the magnetic layer 240b, as shown in Figure 10E. A plating process and a patterning process may be used to form the at least one metallization interconnect 245. The at least one metallization interconnect 245 is formed on the at least one metallization interconnect 244.

[0065] Stage 15 illustrates the state after at least one metallization interconnect 246 is formed on the at least one metallization interconnect 245. Plating and patterning processes may be used to form the at least one metallization interconnect 246. The at least one metallization interconnect 246 is bonded to the at least one metallization interconnect 245.

[0066] Stage 16 shows the state after magnetic layer 240c is formed on at least one metallization interconnect 245, at least one metallization interconnect 246, and magnetic layer 240b, as shown in FIG. 10F. A lamination process may be used to form magnetic layer 240c. A grinding process may be used to remove a portion of magnetic layer 240c and expose at least one metallization interconnect 246. A portion of at least one metallization interconnect 246 may also be ground away. Magnetic layers 240a, 240b, and / or 240c may be the same magnetic layer (e.g., including the same magnetic material) or may be magnetic layers having different properties (e.g., different magnetic permeability values).

[0067] Stage 17 shows the state after a passivation layer 250 is formed over at least one metallization interconnect 246 and / or magnetic layer 240c. Passivation layer 250 may include polyimide (PI). A deposition and / or lamination process may be used to form passivation layer 250.

[0068] Stage 18, as shown in Figure 10G, illustrates the state after an opening 1050 has been formed in the passivation layer 250. To form the opening 1050, an exposure, development, and / or etching process may be used.

[0069] Stage 19 illustrates the state after a plurality of pillar interconnects 251 are formed over the at least one metallization interconnect 246 through the openings 1050 in the passivation layer 250, as shown in FIG. 10H. A plating process and a patterning process may be used to form the plurality of pillar interconnects 251. Some portions of the plurality of pillar interconnects 251 may be considered part of the at least one metallization interconnect.

[0070] Stage 20 illustrates the state after a plurality of solder interconnects 130 have been formed on the plurality of pillar interconnects 251, as shown in FIG. 10I. A solder reflow process may be used to form the plurality of solder interconnects 130.

[0071] As mentioned above, the above sequence can be manufactured on a wafer (e.g., a silicon wafer) such that several integrated devices are formed simultaneously, and then the wafer is singulated to form individual integrated devices including the magnetic layer. The above sequence can be manufactured in one facility or several facilities. For example, a wafer including an active part 201 and an interconnect part 202 can be provided, and a packaging part 204 can be manufactured on the interconnect part 202. The wafer including the active part 201, the interconnect part 202, and the packaging part 204 can be singulated to form several integrated devices.

[0072] Illustrative flow diagram of a method for manufacturing an integrated device including a magnetic layer In some implementations, manufacturing the integrated device includes several processes. Figure 11 shows an example flow diagram of a method 1100 for providing or manufacturing an integrated device including at least one magnetic layer. In some implementations, the method 1100 of Figure 11 can be used to provide or manufacture the integrated device 103. The method 1100 can be performed on a wafer (e.g., a silicon wafer) and then singulated into several integrated devices.

[0073] It should be noted that the method 1100 of Figure 11 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing an integrated device. In some implementations, the order of the processes may be changed or modified. Furthermore, the method 1100 of Figure 11 may be performed to provide or manufacture an integrated passive device (e.g., 105) having at least one magnetic layer.

[0074] The method provides (at 1105) a die substrate (e.g., 200). The die substrate 200 may include silicon (Si). The die substrate 200 may include a wafer (e.g., a silicon wafer). A plurality of transistors 210 may be formed in and / or on the die substrate 200. A plurality of logic blocks may be formed and / or defined by the plurality of transistors 210. BEOL processes may be used to fabricate the plurality of transistors 210. When fabricating integrated passive devices, the die substrate 200 may be free of transistors (e.g., free of active devices). Stage 1 of FIG. 10A illustrates and describes an example of providing a die substrate.

[0075] The method forms (at 1110) at least one oxide layer (e.g., 220) on the die substrate 200 and / or the plurality of transistors 210. The at least one oxide layer 220 may include silicon dioxide. A deposition process and / or lamination process may be used to form the at least one oxide layer 220. The at least one oxide layer 220 may be formed from plasma enhanced tetraethyl orthosilicate (PE TEOS). In some implementations, the at least one oxide layer 220 may already be formed when the die substrate 200 is provided (at 1105). Stage 2 of FIG. 10A illustrates and describes one example of at least one oxide layer formed on the die substrate 200 and / or the plurality of transistors.

[0076] The method forms and patterns (at 1115) at least one die interconnect (e.g., 225) on the oxide layer. The at least one die interconnect 225 may be formed on the die substrate 200 and / or the plurality of transistors 210. The at least one die interconnect 225 may be coupled to the plurality of transistors 210 through one or more openings in the at least one oxide layer 220. Plating and patterning processes may be used to form the at least one die interconnect 225. Stage 3 of FIG. 10A illustrates and describes one example of at least one die interconnect formed on an oxide layer.

[0077] The method forms and patterns (at 1120) at least one high K dielectric layer over a portion of the at least one die interconnect 225. The high K dielectric layer 222 may include silicon nitride. A deposition, stacking, and / or patterning process may be used to form the high K dielectric layer 222. Stage 4 of Figure 10A illustrates and describes one example of a high K dielectric layer formed over at least a portion of the die interconnect.

[0078] The method forms and patterns (at 1125) at least one die interconnect (e.g., 227) on the high-K dielectric layer. Plating and patterning processes may be used to form the at least one die interconnect 227. The at least one die interconnect 225, the high-K dielectric layer 222, and at least a portion of the at least one die interconnect 227 may form and / or define a capacitor. Step 5 of Figure 10A illustrates and describes one example of a die interconnect formed on a high-K dielectric layer.

[0079] The method forms and patterns (at 1130) at least one die dielectric layer (e.g., 224). The at least one die dielectric layer 224 may be formed over and around the at least one die interconnect 225 and the at least one die interconnect 227. The at least one die dielectric layer 224 may include a plurality of cavities 1024. Deposition, lamination, exposure, development, and / or etching processes may be used to form and pattern the at least one die dielectric layer 224. Stage 6 of FIG. 10B illustrates and describes one example of forming and patterning a die dielectric layer.

[0080] The method also forms and patterns (at 1130) at least one die interconnect (e.g., 229) on the at least one die dielectric layer 224. Plating and patterning processes may be used to form the at least one die interconnect 229. The at least one die interconnect 229 may be bonded to other die interconnects. Step 7 of Figure 10B illustrates and describes one example of a die interconnect formed on a die dielectric layer.

[0081] The method forms (at 1135) a passivation layer (e.g., 226) over the at least one die interconnect 229 and the at least one die dielectric layer 224. The passivation layer 226 may include silicon dioxide and / or silicon nitride. A deposition and / or lamination process may be used to form the passivation layer 226. Stage 8 of Figure 10B illustrates and describes one example of a passivation layer formed over the die interconnect and the die dielectric layer.

[0082] The method forms and patterns (at 1140) at least one metallization interconnect (e.g., 242). A plating process and a patterning process may be used to form the at least one metallization interconnect 242. Stage 9 of FIG. 10C illustrates and describes one example of a metallization interconnect formed through at least one opening in the passivation layer. The method also forms (at 1140) a magnetic layer (e.g., 240a) on the passivation layer 226 and the at least one metallization interconnect 242. A lamination process may be used to form the magnetic layer 240a. A grinding process may be used to remove a portion of the magnetic layer 240a and expose the at least one metallization interconnect 242. A portion of the at least one metallization interconnect 242 may also be ground away. Stage 10 of FIG. 10C illustrates and describes one example of a magnetic layer formed on the passivation layer and the metallization interconnect. The method can iteratively repeat (at 1140) the process of (i) forming and patterning metallization interconnects, and (ii) forming and grinding a magnetic layer for as many layers as necessary. Steps 11-16 of Figures 10C-10F illustrate and describe an example of iteratively forming metallization interconnects and magnetic layers.

[0083] The method forms (at 1145) a passivation layer (e.g., 250) over at least one metallization interconnect (e.g., 246) and / or magnetic layer (e.g., 240c). The passivation layer 250 may include polyimide (PI). A deposition and / or lamination process may be used to form the passivation layer 250. Stage 17 of FIG. 10F illustrates and describes the passivation layer formed over the metallization interconnect and magnetic layer. The method also forms (at 1145) an opening (e.g., 1050) in the passivation layer (e.g., 250). Exposure, development, and / or etching processes may be used to form the opening 1050. Stage 18 of FIG. 10G illustrates and describes one example of an opening in the passivation layer.

[0084] The method forms (at 1150) a plurality of pillar interconnects (e.g., 251) on the metallization interconnect(s). Plating and patterning processes may be used to form the plurality of pillar interconnects 251. Some portions of the plurality of pillar interconnects 251 may be considered part of at least one metallization interconnect. Step 19 of FIG. 10H illustrates and describes one example of a plurality of pillar interconnects formed on a metallization interconnect through an opening in a passivation layer.

[0085] The method also forms (at 1150) a plurality of solder interconnects (e.g., 130). The plurality of solder interconnects 130 may be bonded to the plurality of pillar interconnects 251. A solder reflow process may be used to form the plurality of solder interconnects 130. Stage 20 of FIG. 10I illustrates and describes the plurality of solder interconnects formed on the plurality of pillar interconnects.

[0086] As described above, method 1100 can be fabricated on a wafer (e.g., a silicon wafer) such that several integrated devices are formed simultaneously, and the wafer is then singulated to form individual integrated devices including the magnetic layer.

[0087] Illustrative flow diagram of a method for manufacturing an integrated device including a magnetic layer In some implementations, manufacturing the integrated device includes several processes. Figure 12 shows an example flow diagram of a method 1200 for providing or manufacturing an integrated device including at least one magnetic layer. In some implementations, the method 1200 of Figure 12 can be used to provide or manufacture the integrated device 103. The method 1200 can be performed on a wafer (e.g., a silicon wafer) and then singulated into several integrated devices.

[0088] It should be noted that the method 1200 of Figure 12 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing an integrated device. For example, one or more of the processes of the method 1200 may include one or more of the processes of the method 1100. In some implementations, the order of the processes may be changed or modified. Furthermore, the method 1200 of Figure 12 may be performed to provide or manufacture an integrated passive device (e.g., 105) having at least one magnetic layer.

[0089] The method provides (at 1205) a die substrate (e.g., 200). The die substrate 200 may include silicon (Si). The die substrate 200 may include a wafer (e.g., a silicon wafer). A plurality of transistors 210 may be formed in and / or on the die substrate 200. A plurality of logic blocks may be formed and / or defined by the plurality of transistors 210. BEOL processes may be used to fabricate the plurality of transistors 210. The die substrate 200 may be part of and / or define an active portion (e.g., 201) of an integrated device. When fabricating an integrated passive device, the die substrate 200 may be free of transistors (e.g., free of active devices). Stage 1 of FIG. 10A illustrates and describes an example of providing a die substrate.

[0090] The method includes forming (at 1210) an interconnect portion (e.g., 202) on a die substrate (e.g., 200), where forming the interconnect portion 202 includes forming at least one die dielectric layer and forming a plurality of die interconnects. The interconnect portion 202 may be bonded to the die substrate 200.

[0091] Forming the interconnect portion 202 may include forming at least one oxide layer (e.g., 220) on the die substrate 200 and / or the plurality of transistors 210, forming and patterning at least one die interconnect (e.g., 225) on the oxide layer, forming and patterning at least one high-K dielectric layer on a portion of the at least one die interconnect 225, forming and patterning at least one die interconnect (e.g., 227) on the high-K dielectric layer, forming and patterning at least one die dielectric layer (e.g., 224), forming and patterning at least one die interconnect (e.g., 229) on the at least one die dielectric layer 224, and / or forming a passivation layer (e.g., 226) on the at least one die interconnect 229 and the at least one die dielectric layer 224.

[0092] The interconnect portion 202 may include a capacitor defined by at least some of the die interconnects from the plurality of die interconnects. Forming the interconnect portion 202 may include processes 1110-1135 of the method 1100 of Figure 11. Steps 2-8 of Figures 10A-10B illustrate one example of forming the interconnect portion.

[0093] The method includes forming (at 1215) a packaging portion (e.g., 204) over the interconnect portion (e.g., 202), where forming the packaging portion 204 includes forming a plurality of metallization interconnects coupled to the plurality of die interconnects and forming at least one magnetic layer. The packaging portion 204 may be coupled to the interconnect portion 202.

[0094] Forming the packaging portion may include forming and patterning at least one metallization interconnect (e.g., 242), forming a magnetic layer (e.g., 240a) over the passivation layer 226 and the at least one metallization interconnect 242, grinding away a portion of the magnetic layer 240a to expose the at least one metallization interconnect 242 (a portion of the at least one metallization interconnect 242 may also be ground away), forming a passivation layer (e.g., 250) over the at least one metallization interconnect (e.g., 246) and / or the magnetic layer, forming a plurality of pillar interconnects (e.g., 251) over the metallization interconnect(s), and / or forming a plurality of solder interconnects. It should be noted that the plurality of solder interconnects may or may not be considered part of the packaging portion of the integrated device and / or the integrated passive device.

[0095] The packaging portion 204 may include an inductor defined by at least one metallization interconnect from the plurality of metallization interconnects. The at least one magnetic layer includes an insulating layer, a dielectric layer, and / or a non-conductive material. The at least one magnetic layer has a permeability value (e.g., a relative permeability value) greater than 1.

[0096] The method can repeat the processes of (i) forming and patterning metallization interconnects and (ii) forming and grinding a magnetic layer iteratively for as many layers as needed. Forming the packaging portion 204 can include processes 1140-1150 of the method 1100 of Figure 11. Steps 9-20 of Figures 10C-10I show an example of forming the packaging portion.

[0097] As described above, method 1200 can be fabricated on a wafer (e.g., a silicon wafer) such that several integrated devices are formed simultaneously, and the wafer is then singulated to form individual integrated devices including the magnetic layer.

[0098] Exemplary sequence for manufacturing a package containing an integrated device and an integrated passive device 13 illustrates an example sequence for providing or manufacturing a package including an integrated device including a magnetic layer and / or an integrated passive device including a magnetic layer. In some implementations, the sequence of FIG. 13 can be used to provide or manufacture a package 100 including an integrated device and / or an integrated passive device.

[0099] It should be noted that the sequence of FIG. 13 may combine one or more stages to simplify and / or clarify the sequence for providing or manufacturing a package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the disclosure. The sequence of FIG. 13 may be used to manufacture one package or several packages at a time (as part of a wafer).

[0100] 13, stage 1 shows the state after a substrate 102 is provided. The substrate 102 may be provided by a supplier or may be manufactured. The substrate 102 includes at least one dielectric layer 120 and a number of interconnects 122, a solder resist layer 140 and a solder resist layer 142. The substrate 102 may include an embedded trace substrate (ETS). In some implementations, the at least one dielectric layer 120 may include a prepreg layer or layers.

[0101] Stage 2 shows the state after the integrated device 103 has been bonded to a first surface (e.g., top surface) of the substrate 102. The integrated device 103 may be bonded to the substrate 102 via a plurality of solder interconnects 130. The plurality of solder interconnects 130 are bonded to the plurality of interconnects 122. A solder reflow process may be used to bond the integrated device 103 to the plurality of interconnects 122 via the plurality of solder interconnects 130.

[0102] Stage 2 also illustrates the state after the integrated passive device 105 has been bonded to a first surface (e.g., top surface) of the substrate 102. The integrated passive device 105 may be bonded to the substrate 102 via a plurality of solder interconnects 150. The plurality of solder interconnects 150 are bonded to the plurality of interconnects 122. A solder reflow process may be used to bond the integrated passive device 105 to the plurality of interconnects 122 via the plurality of solder interconnects 150.

[0103] Stage 3 shows the state after the plurality of solder interconnects 110 are bonded to the substrate 102. The plurality of solder interconnects 110 may be bonded to interconnects disposed on the second surface of the at least one dielectric layer 120. A solder reflow process may be used to bond the plurality of solder interconnects 110 to the substrate 102. Stage 3 may show the package 100. The packages (e.g., 100) described in this disclosure may be manufactured one at a time or may be manufactured integrally as part of one or more wafers and then singulated into individual packages.

[0104] 1 is an exemplary flow diagram of a method for manufacturing a package including an integrated device and an integrated passive device; In some implementations, manufacturing a package including an integrated device including a magnetic layer and / or an integrated passive device including a magnetic layer includes several processes. Figure 14 shows an example flow diagram of a method 1400 for providing or manufacturing a package including an integrated device including a magnetic layer and / or an integrated passive device including a magnetic layer. In some implementations, the method 1400 of Figure 14 can be used to provide or manufacture the package 100 of Figure 1 described in this disclosure. However, the method 1400 can be used to provide or manufacture any of the packages described in this disclosure.

[0105] It should be noted that the method of Figure 14 may combine one or more processes to simplify and / or clarify a method for providing or manufacturing an integrated device including a magnetic layer and / or a package including an integrated passive device including a magnetic layer. In some implementations, the order of the processes may be changed or modified.

[0106] The method includes (at 1405) providing a substrate (e.g., 102). The substrate 102 may be provided by a supplier or may be manufactured. The substrate 102 includes at least one dielectric layer 120 and a number of interconnects 122. The substrate 102 may include an embedded trace substrate (ETS). In some implementations, the at least one dielectric layer 120 may include a prepreg layer. Stage 1 of FIG. 13 illustrates and describes an example of providing a substrate with escape interconnects.

[0107] The method includes (at 1410) bonding at least one integrated device (e.g., 103) to a first surface of a substrate (e.g., 102). For example, the integrated device 103 may be bonded to the substrate 102 via a plurality of solder interconnects 130. The plurality of solder interconnects 130 are bonded to the plurality of interconnects 122. A solder reflow process may be used to bond the integrated device 103 to the substrate via the plurality of solder interconnects 130.

[0108] The method also includes (at 1410) bonding at least one integrated passive device (e.g., 105) to the first surface of the substrate (e.g., 102). For example, the integrated passive device 105 may be bonded to the substrate 102 via a plurality of solder interconnects 150. The plurality of solder interconnects 150 are bonded to the plurality of interconnects 122. A solder reflow process may be used to bond the integrated passive device 105 to the plurality of interconnects via the plurality of solder interconnects 150. Stage 2 of Figure 13 illustrates and describes one example of an integrated device and an integrated passive device bonded to a substrate.

[0109] The method continues (at 1415) bonding the plurality of solder interconnects (e.g., 110) to a second surface of the substrate (e.g., 102). A solder reflow process may be used to bond the plurality of solder interconnects 110 to the substrate. Stage 3 of Figure 13 illustrates and describes one example of bonding the solder interconnects to the substrate.

[0110] Exemplary Electronic Devices FIG. 15 illustrates various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system in package (SiP), or system on chip (SoC). For example, a mobile phone device 1502, a laptop computer device 1504, a fixed location terminal device 1506, a wearable device 1508, or an autonomous vehicle 1510 may include a device 1500 as described herein. The device 1500 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. The devices 1502, 1504, 1506, and 1508 and the vehicle 1510 illustrated in FIG. 15 are merely examples. Other electronic devices may also be equipped with device 1500, including, but not limited to, a group of devices (e.g., electronic devices) including mobile devices, portable data units such as handheld personal communication system (PCS) units, personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of things (IoT) devices, servers, routers, electronic devices implemented in automated vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0111] One or more of the components, processes, features, and / or functions shown in Figures 1-9, 10A-10I, and / or 11-15 may be rearranged and / or combined into a single component, process, feature, or function, or embodied as several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from the present disclosure. It should also be noted that Figures 1-9, 10A-10I, and / or 11-15 and corresponding descriptions thereof in this disclosure are not limited to dies and / or ICs. In some implementations, Figures 1-9, 10A-10I, and / or 11-15 and corresponding descriptions thereof in this disclosure may be used to manufacture, create, provide, and / or produce devices and / or integrated devices. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat dissipation device, and / or an interposer.

[0112] It should be noted that the figures in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the figures may not be to scale. In some cases, for purposes of clarity, not all components and / or parts may be shown. In some cases, the position, location, size, and / or shape of various parts and / or components in the figures may be exemplary. In some implementations, various components and / or parts in the figures may be optional.

[0113] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the described feature, advantage, or mode of operation. The term "coupled" is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, object A and object C can still be considered to be coupled to each other even though they are not in direct physical contact with each other. The term "electrically coupled" can mean that two objects are directly or indirectly coupled together such that an electric current (e.g., signal, power, ground) can propagate between the two objects. Two objects that are electrically coupled may or may not propagate an electric current between the two objects. The use of the terms "first," "second," "third," and "fourth" (and / or anything more than fourth) is arbitrary. Any of the components described may be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component may also be a first component, a second component, a third component, or a fourth component. The term "encapsulating" means that an object may partially encapsulate or completely encapsulate another object. The terms "top" and "bottom" are arbitrary. A component located at the top may be located above a component located at the bottom. A top component may also be considered a bottom component, and vice versa.As described in this disclosure, a first component disposed "over" a second component can mean that the first component is disposed above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, a first component may be disposed above (e.g., above) a first surface of the second component, and a third component may be disposed above (e.g., below) a second surface of the second component, where the second surface is opposite the first surface. It is further noted that in the context of one component being disposed above another component, the term "over" as used herein can be used to mean a component that is on and / or within (e.g., on the surface of or embedded within) the other component. Thus, for example, a first component present on a second component can mean (1) that the first component is present on the second component but is not in direct contact with the second component, (2) that the first component is present on (e.g., on a surface of) the second component, and / or (3) that the first component is present within (e.g., embedded within) the second component. A first component that is disposed "in" a second component can be partially disposed within the second component or can be completely disposed within the second component. The term "about 'value X'" or "approximately value X" as used in this disclosure means within 10 percent of "value X". For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1.

[0114] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include a trace, a via, a pad, a pillar, a metallization layer, a redistribution layer, and / or an under bump metallization (UBM) layer / interconnect. In some implementations, an interconnect may include a conductive material that may be configured to provide an electrical path for a signal (e.g., a data signal), ground, and / or power. An interconnect may include two or more elements or components. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or sequences to form an interconnect. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating, and / or a plating process may be used to form the interconnects.

[0115] It should also be noted that various disclosures contained herein may be described as a process, which is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operations as a sequential process, many of the operations may be performed in parallel or simultaneously. Additionally, the order of operations may be rearranged. A process terminates when its operations are completed.

[0116] Further examples are described below to facilitate understanding of the present disclosure.

[0117] Aspect 1: An integrated device comprising: a die substrate including a plurality of transistors; an interconnect portion coupled to the die substrate; and a packaging portion coupled to the interconnect portion. The interconnect portion includes at least one die dielectric layer and a plurality of die interconnects coupled to the plurality of transistors. The packaging portion includes at least one magnetic layer and a plurality of metallization interconnects coupled to the plurality of die interconnects.

[0118] Example 2: The integrated device of example 1, wherein at least one magnetic layer comprises an insulating layer and / or a dielectric layer.

[0119] Example 3: The integrated device of example 1 or 2, wherein at least one magnetic layer comprises a non-conductive material.

[0120] Embodiment 4: The integrated device of embodiments 1-3, wherein at least one magnetic layer has a relative permeability value greater than 1.

[0121] Embodiment 5: The integrated device according to embodiments 1 to 4, wherein at least one magnetic layer has a magnetic loss tangent value in the range of 0.01 to 0.04.

[0122] Aspect 6: The integrated device of aspects 1-5, wherein the at least one magnetic layer comprises a first magnetic layer including a first magnetic permeability value and a second magnetic layer including a second magnetic permeability value. The first magnetic permeability value can be a first relative magnetic permeability value. The second magnetic permeability value can be a second relative magnetic permeability value.

[0123] Embodiment 7: An integrated device as described in embodiments 1 to 6, wherein the interconnect portion includes a capacitor defined by at least some of the die interconnects from the plurality of die interconnects.

[0124] Example 8: The integrated device of Example 7, wherein the packaging portion includes an inductor defined by at least one metallization interconnect from the plurality of metallization interconnects.

[0125] Example 9: The integrated device of Examples 1-8, wherein the packaging portion is a redistribution portion, and the plurality of metallization interconnects includes a plurality of redistribution interconnects.

[0126] Aspect 10: The integrated device according to aspects 1 to 9, wherein the integrated device is a die configured to operate as a power management integrated circuit (PMIC).

[0127] Aspect 11: A device comprising: a die substrate, an interconnect portion coupled to the die substrate, and a packaging portion coupled to the interconnect portion. The interconnect portion includes at least one die dielectric layer and a plurality of die interconnects. The packaging portion includes at least one magnetic layer and a plurality of metallization interconnects coupled to the plurality of die interconnects.

[0128] Example 12: The device of example 11, wherein at least one magnetic layer comprises an insulating layer, a dielectric layer, and / or a non-conductive material, and wherein at least one magnetic layer has a relative permeability value greater than 1.

[0129] Example 13: The device of example 11 or 12, wherein the at least one magnetic layer comprises a first magnetic layer including a first magnetic permeability value and a second magnetic layer including a second magnetic permeability value. The first magnetic permeability value can be a first relative magnetic permeability value. The second magnetic permeability value can be a second relative magnetic permeability value.

[0130] Example 14: A device described in Examples 11 to 13, wherein the interconnect portion includes a capacitor defined by at least some of the die interconnects from the plurality of die interconnects.

[0131] Example 15: The device of example 14, wherein the packaging portion includes an inductor defined by at least one metallization interconnect from the plurality of metallization interconnects.

[0132] Example 16: The device of Examples 11-15, wherein the die substrate, the interconnect portion, and the packaging portion are part of an integrated passive device (IPD).

[0133] Aspect 17: The device described in aspects 11 to 16, wherein the device is selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in an autonomous vehicle.

[0134] Aspect 18: A method provides a die substrate. The method forms an interconnect portion on the die substrate, where forming the interconnect portion includes forming at least one die dielectric layer and forming a plurality of die interconnects. The method forms a packaging portion on the interconnect portion, where forming the packaging portion includes forming a plurality of metallization interconnects coupled to the plurality of die interconnects and forming at least one magnetic layer.

[0135] Example 19: The method of example 18, wherein the die substrate includes a plurality of transistors and a plurality of die interconnects are formed such that the plurality of die interconnects are coupled to the plurality of transistors.

[0136] Aspect 20: The method of aspect 18 or 19, wherein at least one magnetic layer comprises an insulating layer, a dielectric layer, and / or a non-conductive material, and at least one magnetic layer has a relative permeability value greater than 1.

[0137] Aspect 21: The method described in aspects 18 to 20, wherein the interconnection portion includes a capacitor defined by at least some die interconnections from the plurality of die interconnections, and the packaging portion includes an inductor defined by at least one metallization interconnection from the plurality of metallization interconnections.

[0138] Various features of the present disclosure described herein can be implemented in various systems without departing from the present disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the aspects of the present disclosure is intended to be illustrative and not intended to limit the scope of the claims. Thus, the present teachings can be readily applied to other types of devices, and many alternatives, modifications, and variations will be apparent to those skilled in the art. [Explanation of symbols]

[0139] 100 packages 102 Substrate 103 Integrated Devices 105 Integrated Passive Devices 106 Board 110 Interconnection 120 Dielectric layer 122 Interconnection 130 Interconnection 140 Resist layer 142 Resist layer 150 Interconnect 160 Board Dielectric Layer 162 Board Interconnect 200 Die Substrate 201 Active part 202 Interconnection Part 203 Capacitor 204 Packaging section 210 Transistor 220 Oxide layer 221 Die Interconnect 222 High K Dielectric Layer 224 die dielectric layer 225 Die Interconnect 226 Passivation Layer 227 Die Interconnect 229 Die Interconnect 240 Magnetic Layer 240a Magnetic layer 240b Magnetic layer 240c magnetic layer 241 Metallization Interconnects 242 Metallization Interconnects 243 Metallization Interconnects 244 Metallization Interconnects 245 Metallization Interconnects 246 Metallization Interconnects 250 Passivation Layer 251 Pillar Interconnect 600 devices 602 Inductor 604 Magnetic Layer 1024 Cavity 1050 Opening 1500 devices 1502 Mobile Phone Device 1504 Laptop Computer Device 1506 Fixed Location Terminal Device 1508 Wearable Devices 1510 Autonomous Vehicles

Claims

1. 1. An integrated device comprising: a die substrate including a plurality of transistors; an interconnect portion coupled to the die substrate, at least one die dielectric layer; a plurality of die interconnects coupled to the plurality of transistors; a passivation layer coupled to the at least one die dielectric layer; an interconnection portion including: a packaging portion coupled to the interconnect portion, at least one magnetic layer; a plurality of metallization interconnects coupled to the plurality of die interconnects; a packaging portion including: Equipped with an integrated device, wherein the passivation layer is disposed between i) the die substrate and the plurality of metallization interconnects, and ii) the die substrate and the at least one magnetic layer;

2. The integrated device of claim 1 , wherein the at least one magnetic layer comprises an insulating layer and / or a dielectric layer.

3. The integrated device of claim 1 , wherein the at least one magnetic layer comprises a non-conductive material.

4. The integrated device of claim 1 , wherein the at least one magnetic layer has a relative permeability value greater than one.

5. 10. The integrated device of claim 1, wherein the at least one magnetic layer has a magnetic loss tangent value in the range of 0.01 to 0.

04.

6. the at least one magnetic layer a first magnetic layer including a first magnetic permeability value; a second magnetic layer including a second magnetic permeability value; The integrated device of claim 1 , comprising:

7. The integrated device of claim 1 , wherein the interconnect portion comprises a capacitor defined by at least some die interconnects from the plurality of die interconnects.

8. The integrated device of claim 7 , wherein the packaging portion includes an inductor defined by at least one metallization interconnect from the plurality of metallization interconnects.

9. the packaging portion is a redistribution portion; the plurality of metallization interconnects includes a plurality of redistribution interconnects; The integrated device of claim 1 .

10. The integrated device of claim 1 , wherein the integrated device is a die configured to operate as a power management integrated circuit (PMIC).

11. The packaging portion further includes a second passivation layer; the at least one magnetic layer is disposed between the passivation layer and the second passivation layer; the passivation layer and the second passivation layer are separate passivation layers; The integrated device of claim 1 .

12. 1. A method comprising: providing a die substrate; forming an interconnect portion on the die substrate, forming at least one die dielectric layer; forming a plurality of die interconnects; forming a passivation layer coupled to the at least one die dielectric layer; forming an interconnect portion on the die substrate, forming a packaging portion over the interconnect portion; forming a plurality of metallization interconnects coupled to the plurality of die interconnects; forming at least one magnetic layer; forming a packaging portion over the interconnect portion, Including, the plurality of metallization interconnects and the at least one magnetic layer are formed such that the passivation layer is disposed between i) the die substrate and the plurality of metallization interconnects, and ii) the die substrate and the at least one magnetic layer.

13. the die substrate includes a plurality of transistors; the plurality of die interconnects are formed such that the plurality of die interconnects are coupled to the plurality of transistors; The method of claim 12.

14. the at least one magnetic layer comprises an insulating layer, a dielectric layer, and / or a non-conductive material; the at least one magnetic layer having a relative permeability value greater than 1; The method of claim 12.

15. the interconnect portion includes a capacitor defined by at least some die interconnects from the plurality of die interconnects; the packaging portion includes an inductor defined by at least one metallization interconnect from the plurality of metallization interconnects. The method of claim 12.

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