Semiconductor device and method for manufacturing the same

Abstract

The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. According to an embodiment, a method for manufacturing a semiconductor device includes forming a thin film structure on a substrate, forming a trench in the thin film structure, forming a blocking layer covering at least a portion of the trench, forming a charge storage layer on the blocking layer, doping the charge storage layer with carbon, forming a tunneling layer on the charge storage layer, and forming a channel layer covering the tunneling layer and the substrate. According to an embodiment, the conformality of the charge storage layer can be improved during the manufacturing process of the semiconductor device.

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] Semiconductor devices are components that are primarily used in electronic circuits and similar devices that utilize the electrical conductivity properties of semiconductors. Semiconductors can be classified into memory semiconductors and non-memory semiconductors. Memory semiconductors can be classified into volatile memories such as DRAM and SRAM, and non-volatile memories such as Mask ROM, EP ROM, EEP ROM, and flash memory.

[0003] FIG. 1 shows the structure of a semiconductor device.

[0004] Referring to FIG. 1, in order to manufacture a semiconductor device 1, first, insulating layers 110a-110e and gate layers 112a-112e may be alternately and repeatedly deposited on a substrate 100 to form a thin film structure (TS).

[0005] A trench (TR) may then be formed through the thin film structure (TS) exposing the substrate 100 .

[0006] Once the trenches (TR) are formed, semiconductor patterns 120, 130, 140, and 150 may be formed inside the trenches (TR). More specifically, a blocking layer 120 covering at least a portion of the trenches (TR) and a charge storage layer 130 disposed on the blocking layer 120 may be formed inside the trenches (TR). In addition, a tunneling layer 140 may be formed on the charge storage layer 130. After the tunneling layer 140 is formed, a channel layer 150 may be formed to cover the exposed portion of the substrate 100.

[0007] One of the factors that determine the electrical characteristics of the semiconductor device 1 shown in FIG. 1 is the conformality of the charge storage layer 130. The conformality of the charge storage layer 130 means the uniformity of the thickness of the charge storage layer 130 measured in the Z-axis direction in FIG. 1. For example, the conformality of the charge storage layer 130 can be defined as the ratio (D2 / D1) of the thickness (D2) of the charge storage layer 130 measured in a lower region (e.g., the peripheral region of the gate layer 112a) to the thickness (D1) of the charge storage layer 130 measured in an upper region (e.g., the peripheral region of the gate layer 112e) of the semiconductor device 1. The closer D2 / D1 is to 1, the higher the conformality. The higher the conformality, the more uniform the thickness of the charge storage layer 130.

[0008] 1, that is, the number of insulating layers 110a-110e and gate layers 112a-112e included in the thin film structure (TS) increases, the aspect ratio of the semiconductor device 1 increases. As the aspect ratio of the semiconductor device 1 increases, the length of the charge storage layer 130 in the Z-axis direction also increases, which causes a problem that the conformality of the charge storage layer 130 decreases during the manufacturing process of the semiconductor device 1.

[0009] A decrease in the conformality of the charge storage layer 130 may degrade the electrical characteristics of the semiconductor device 1. For example, a decrease in the conformality of the charge storage layer 130 may degrade the threshold voltage (V T In addition, if the conformality of the charge storage layer 130 decreases, there is a problem that the variation in threshold voltage between the cells included in the semiconductor device 1 or the variation between the threshold voltage of the cells in the upper region and the threshold voltage of the cells in the lower region of the semiconductor device 1 increases. Summary of the Invention [Problem to be solved by the invention]

[0010] It is an object of the present disclosure to improve the electrical properties of semiconductor devices by increasing the conformality of a charge reservoir layer during the manufacture of the semiconductor devices.

[0011] The object of the present specification is not limited to the object mentioned above, and other objects and advantages of the present specification not mentioned can be more clearly understood from the examples of the present specification described below. In addition, the object and advantages of the present specification can be realized by the elements and combinations thereof described in the claims. [Means for solving the problem]

[0012] According to one embodiment, a method for manufacturing a semiconductor device includes forming a thin film structure on a substrate, forming a trench in the thin film structure, forming a blocking layer covering at least a portion of the trench, forming a charge storage layer on the blocking layer, doping the charge storage layer with carbon, forming a tunneling layer on the charge storage layer, and forming a channel layer covering the tunneling layer and the substrate.

[0013] According to an embodiment, a semiconductor device includes a substrate, a thin film structure formed on the substrate, a blocking layer covering at least a portion of a trench formed in the thin film structure, a charge storage layer formed on the blocking layer, a tunneling layer formed on the charge storage layer, and a channel layer covering the tunneling layer and the substrate, and the charge storage layer may be doped with carbon. Effect of the Invention

[0014] According to the embodiment, the conformality of the charge storage layer can be improved during the manufacturing process of the semiconductor device, and thus electrical characteristics of the semiconductor device according to the embodiment, such as the dispersion of threshold voltages of cells included in the semiconductor device, the threshold voltage variation between cells, and the threshold voltage variation between cells in an upper region and cells in a lower region, can be improved. [Brief description of the drawings]

[0015] [Figure 1] 1A and 1B are diagrams illustrating a structure of a semiconductor element. [Diagram 2] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to an embodiment. [Diagram 3] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to an embodiment. [Figure 4] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] The above-mentioned objects, features and advantages will be described in detail below with reference to the accompanying drawings, so that those skilled in the art to which the present specification pertains can easily implement the embodiments of the present specification. In describing the present specification, if a detailed description of a known technology related to the present specification is deemed to obscure the gist of the present specification, the detailed description will be omitted. Hereinafter, preferred embodiments according to the present specification will be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings indicate the same or similar components.

[0017] 2 to 4 show a manufacturing process of a semiconductor device according to one embodiment.

[0018] First, as shown in FIG. 2, insulating layers 210a-210e and gate layers 212a-212e may be alternately and repeatedly deposited on a substrate 200 to form a thin film structure (TS).

[0019] In an embodiment, the substrate 200 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate, but the type of the substrate 200 is not limited thereto.

[0020] In one embodiment, the insulating layers 210a-210e may be silicon oxide films formed by a thermal oxidation process or by using a deposition technique. In one embodiment, the insulating layers 210a-210e may have the same thickness. In another embodiment, some of the insulating layers 210a-210e may have different thicknesses.

[0021] In one embodiment, the gate layers 212a-212e may include a silicon nitride film formed by a nitridation process. The gate layers 212a-212e may be sacrificial films. That is, after the formation of the channel layer 250 (described later) is completed and the silicon nitride film is removed, a metal material such as Al, Cu, or W may be deposited on the gate layers 212a-212e.

[0022] In one embodiment, the insulating layers 210a-210e and the gate layers 212a-212e may be formed using a thermal chemical vapor deposition (thermal CVD), plasma enhanced chemical vapor deposition (plasma enhanced CVD), physical chemical vapor deposition (physical CVD), or atomic layer deposition (ALD) process.

[0023] Next, a trench (TR) may be formed penetrating the thin film structure (TS) to expose the substrate 200. The trench (TR) may be formed two-dimensionally on the upper surface of the thin film structure (TS) from a planar perspective. In one embodiment, the trench (TR) may be formed by forming a first mask pattern (not shown) having an opening defining an area in which the trench (TR) is to be formed on the thin film structure (TS) and anisotropically etching the thin film structure (TS) using the first mask pattern (not shown) as an etching mask. The first mask pattern may be formed of a material having selectivity with respect to the insulating layers 210a-210e and the gate layers 212a-212e. The upper surface of the substrate 200 may be over-etched by the etching process, resulting in a recess in the upper portion of the substrate 200.

[0024] A blocking layer 220 may then be formed to cover at least a portion of the trench (TR) while exposing the substrate 100. The blocking layer 220 may include a high dielectric film (e.g., a metal oxide such as aluminum oxide or hafnium oxide) having a higher dielectric constant than the tunnel dielectric film.

[0025] A charge storage layer 230 may then be formed on the blocking layer 220. The charge storage layer 230 may include a dielectric material having traps capable of storing charge, such as a nitride such as SiN and / or a metal oxide.

[0026] 3, the charge storage layer 230 may be doped with carbon. In one embodiment, a carbon compound 300 may be supplied into a chamber in which the semiconductor device 2 in which the charge storage layer 230 is formed is provided. In one embodiment, the carbon compound 300 supplied into the chamber may be CH4, C2H4, C2H6, C3H7, C3H8, iC4H 10 , nC4H 10 , nC5H 12 , C6H6, C6H 12 , C7H8, C8H 18 , C 10 H 22 , C 12 H 26 It may include at least one of the following:

[0027] In one embodiment, an atmospheric gas can be provided in the chamber in which the semiconductor device 2 is provided. The atmospheric gas provided in the chamber can be any of H2, D2, and N2.

[0028] When the carbon compound 300 is supplied into the chamber, the semiconductor device 2 can be subjected to a heat treatment in a state where the pressure in the chamber is set to a predetermined process pressure. In one embodiment, the process pressure can be determined within a range of 1 atm to 100 atm. Furthermore, the temperature in the chamber when the heat treatment is performed, i.e., the process temperature, can be determined within a range of 400°C to 600°C.

[0029] When the carbon doping of the charge storage layer 230 is completed by the above-mentioned process, the semiconductor device 2 can be taken out of the chamber, and the carbon compound 300 shown in FIG. 3 can be removed.

[0030] With the carbon compound 300 removed, the tunneling layer 240 may be formed on the charge storage layer 230 as shown in Fig. 4. The tunneling layer 240 may include an oxide and / or an oxynitride.

[0031] A channel layer 250 may then be formed between the tunneling layers 240. The channel layer 250 may be formed to cover the substrate 200 exposed at the bottom of the trench (TR). In one embodiment, the channel layer 250 may include an oxide, such as polysilicon.

[0032] Fig. 4 shows a semiconductor device 2 according to an embodiment produced by the process described above. The semiconductor device 2 in the embodiment shown in Fig. 4 includes cells (CL1 to CL5) stacked in five layers. However, the number of layers of cells in the semiconductor device 2 may vary depending on the embodiment.

[0033] Each of the cells (CL1 to CL5) included in the semiconductor device 2 has a stacked structure including gate layers 212a to 212e and semiconductor patterns 220, 230, 240, and 250. For example, as shown in FIG. 4, the first cell (CL1) includes a gate layer 212a, a blocking layer 220, a charge storage layer 230, a tunneling layer 240, and a channel layer 250, which are stacked in sequence. The second cell (CL2) to the fifth cell (CL5) may also have the same stacked structure as the first cell (CL1). Here, the charge storage layer 230 may contain carbon by the carbon doping process as described above.

[0034] According to the above embodiment, after the charge storage layer 230 is formed, a carbon doping process is performed on the charge storage layer 230. When the charge storage layer 230 is doped with carbon, the conformality of the charge storage layer 230 can be improved, and the electrical characteristics of the semiconductor device 2 can be improved.

[0035] First, it is possible to improve the dispersion of the threshold voltage of each cell included in the semiconductor device 2. Table 1 shows the results of measuring the threshold voltage of the cells included in each semiconductor device 2 manufactured at different process pressures when the carbon doping process is performed on the charge storage layer 230 according to the above-mentioned embodiment. "Non-doped" in Table 1 is the threshold voltage data of the cells included in the semiconductor device in which the carbon doping process on the charge storage layer 230 is not performed.

[0036] [Table 1]

[0037] As shown in Table 1, the threshold voltage of each cell included in the semiconductor device in which the charge storage layer 230 does not contain carbon was measured, and the minimum value was 1, the maximum value was 2.3, and the dispersion was expressed as 1.3. On the other hand, the dispersion of the threshold voltage of each cell included in the semiconductor device in which the charge storage layer 230 was subjected to the carbon doping process according to the above-mentioned embodiment is smaller than 1.3. Therefore, the uniformity of the cells of the semiconductor device in which the charge storage layer 230 contains carbon is higher than that of the semiconductor device in which the charge storage layer 230 does not contain carbon.

[0038] Also, as shown in Table 1, when a carbon doping process is performed on the charge storage layer 230, as the pressure in the chamber, i.e., the process pressure, increases, the dispersion of the threshold voltages of each cell included in the semiconductor device becomes smaller, and the uniformity of the cells becomes higher.

[0039] Furthermore, as in the above-described embodiment, when the carbon doping process is performed on the charge storage layer 230, the conformality of the charge storage layer 230 is increased compared to when the carbon doping process is not performed on the charge storage layer 230. In other words, when the carbon doping process is performed on the charge storage layer 230, the thickness of the charge storage layer 230 measured in the Z-axis direction becomes uniform. As a result, the threshold voltage variation of each cell included in the semiconductor device 2 containing carbon in the charge storage layer 230 is reduced, and the uniformity of the cells can be improved.

[0040] In addition, when the conformality of the charge storage layer 230 is increased by the carbon doping process on the charge storage layer 230, the deviation between the threshold voltage of a cell (e.g., the fifth cell (CL5) or the fourth cell (CL4)) arranged in the upper region of the semiconductor device 2 and the threshold voltage of a cell (e.g., the first cell (CL1) or the second cell (CL2)) arranged in the lower region of the semiconductor device 2 is reduced, thereby improving the uniformity of the cells.

[0041] As described above, the present specification has been described with reference to the exemplary drawings, but the present specification is not limited to the embodiments and drawings disclosed in the present specification, and various modifications may be made by those skilled in the art. Furthermore, even if the effects of the configurations of the present specification are not explicitly described and explained in the above-mentioned embodiments of the present specification, the effects that can be predicted by the configurations should also be recognized.

Claims

1. forming a thin film structure on a substrate; forming a trench in the thin film structure; forming a blocking layer covering at least a portion of the trench; forming a charge storage layer on the blocking layer; doping the charge storage layer with carbon; forming a tunneling layer on the charge storage layer; forming a channel layer covering the tunneling layer and the substrate; Including, A method for manufacturing a semiconductor device.

2. The step of doping the charge storage layer with carbon includes: After the charge storage layer is formed, supplying a carbon compound into a chamber in which the semiconductor device is disposed; performing a heat treatment on the semiconductor device while the pressure in the chamber is set to a predetermined process pressure; Including, The method for manufacturing a semiconductor device according to claim 1 .

3. The predetermined process pressure is Determined within 1 atm to 100 atm, The method for manufacturing a semiconductor device according to claim 2 .

4. An ambient gas is provided in the chamber, The atmospheric gas is H ２ , D ２ , N ２ Either The method for manufacturing a semiconductor device according to claim 2 .

5. The process temperature of the heat treatment in the chamber is Determined within 400°C to 600°C; The method for manufacturing a semiconductor device according to claim 2 .

6. The carbon compound is CH ４ , C ２ H ４ , C ２ H ６ , C ３ H ７ , C ３ H ８ , iC ４ H １０ , nC ４ H １０ , nC ５ H １２ , C ６ H ６ , C ６ H １２ , C ７ H ８ , C ８ H １８ , C １０ H ２２ , C １２ H ２６ At least one of The method for manufacturing a semiconductor device according to claim 2 .

7. A substrate; a thin film structure formed on the substrate; a blocking layer covering at least a portion of a trench formed in the thin film structure; a charge storage layer formed on the blocking layer; a tunneling layer formed on the charge storage layer; a channel layer covering the tunneling layer and the substrate; Including, The charge storage layer is doped with carbon; Semiconductor element.

8. After the charge storage layer is formed, a carbon compound is supplied into a chamber in which the semiconductor device is disposed, and a heat treatment is performed on the semiconductor device while the pressure in the chamber is set to a predetermined process pressure. The semiconductor device according to claim 7.

9. The predetermined process pressure is Determined within 1 atm to 100 atm, The semiconductor device according to claim 8.

10. An ambient gas is provided in the chamber, The atmospheric gas is H ２ , D ２ , N ２ Either The semiconductor device according to claim 8.

11. The process temperature of the heat treatment in the chamber is Determined within 400°C to 600°C; The semiconductor device according to claim 8.

12. The carbon compound is CH ４ , C ２ H ４ , C ２ H ６ , C ３ H ７ , C ３ H ８ , iC ４ H １０ , nC ４ H １０ , nC ５ H １２ , C ６ H ６ , C ６ H １２ , C ７ H ８ , C ８ H １８ , C １０ H ２２ , C １２ H ２６ At least one of The semiconductor device according to claim 8.

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