Power module and method for assembling a power module - Patents.com

Abstract

The power module (100) comprises: a first substrate (101) having a first connection point (111); a second substrate (102) having a second connection point (112), the first connection point (111) and the second connection terminal (112) being electrically connected in parallel to a common terminal (104); and a plurality of power semiconductor chips (103), a first portion of the power semiconductor chip (103) being connected to the first substrate (101). a plurality of power semiconductor chips (103) mounted on a first substrate (101) and electrically connected to a first connection point (111), a second portion of the power semiconductor chip (103) mounted on a second substrate (102) and electrically connected to a second connection point (112); and a vibration damping device (200) electrically connected between the first substrate (101) and the second substrate (102).

Description

[Technical field]

[0001] The present disclosure relates to a power module and a method for assembling a power module.

[0002] A power electronic device, such as a converter, may comprise a number of power semiconductors, which may be housed by so-called power modules.

[0003] For example, there is a need for improved power modules that enable high speed switching. Additionally, there is a need for methods for assembling such power modules.

[0004] SUMMARY OF THE DISCLOSURE

[0002] Embodiments of the present disclosure relate to an improved power module. Other embodiments of the present disclosure relate to a method for assembling a power module.

[0005] According to one embodiment, the power module comprises: a first substrate having a first connection point; a second substrate having a second connection point, the first connection point and the second connection point being electrically connected in parallel to a common terminal; a plurality of power semiconductor chips, a first portion of the power semiconductor chips being attached to a first substrate and electrically connected to a first connection point, and a second portion of the power semiconductor chips being attached to a second substrate and electrically connected to a second connection point; a vibration damping device, the vibration damping device being electrically connected between a first substrate and a second substrate; Equipped with.

[0006] The power module is for example part of a so-called half-bridge power module. The power semiconductor chip is for example a wide bandgap silicon carbide power semiconductor.

[0007] A half-bridge is an electric circuit comprising two switch elements or two pairs each of one switch element and one diode, connected in series between two DC nodes and providing an AC node or output point therebetween. The DC nodes and the AC node / output point may be electrically connected to the power terminals of a power module. Each switch element may consist of one or more semiconductor switches electrically connected in parallel. The switch elements are for example realized by the power semiconductor chips mentioned above.

[0008] The power module may be used, for example, in an electrical converter or inverter capable of rectifying an AC voltage supplied to a DC link or a battery. The inverter may also be capable of generating an AC voltage from a DC voltage supplied to an electric motor, such as the motor of an electric vehicle. The electrical converter may also be a DC-DC converter. The power module may be used in automotive applications, such as electric cars, motorcycles, buses, off-road vehicles, etc.

[0009] The power module may be, for example, an inverter or converter for renewable energy such as wind turbines, photovoltaic panels, tidal power plants, and electric vehicles (EVs), or traction applications. The power module may be realized in a so-called six-pack configuration using three half-bridge power semiconductor modules for three phases.

[0010] The power module may be adapted to handle currents of more than 5 A, in particular more than 10 A. The power module may be adapted to handle voltages of less than 1 kV, or may be adapted to handle voltages between 1 kV and 30 kV.

[0011] The power module comprises two separate substrates. The substrates are configured to carry and support the power semiconductor chips. Furthermore, the substrates are configured to electrically connect the chips. A first part of the chip is mechanically and electrically connected to the first substrate. A second part of the chip is electrically and mechanically connected to the second substrate. It is also possible that more than two substrates are electrically connected in parallel. Thus, the chips of the power module are distributed over several, at least two substrates. For example, each substrate comprises 10, 20 or more chips.

[0012] In particular, the first substrate and the second substrate are part of a first switch side. The device may comprise a further substrate for a second switch side. The chips of the first side are connected in parallel. The gates of the chips are connected to a common terminal via a first connection point and a second connection point. The first connection point is configured to electrically contact the first substrate. The second connection point is configured to electrically contact the second substrate.

[0013] To prevent destructive vibrations between the two substrates, a vibration damping device is connected between the two substrates. Thus, potential destructive vibrations are sufficiently damped even when fast switching is performed. Destructive vibrations occur, for example, during turn-off and they are partly self-excited via the Miller capacitance. Such resonances are caused when the parasitic gate loop inductances of the two substrates differ significantly. The vibration damping device allows the elimination of destructive resonances without compromising the switching performance of the power module. The vibration damping device includes at least one of a dissipative element or a high impedance element to damp the resonance.

[0014] According to an embodiment, the vibration damping device comprises a damper. The damper comprises a resistor. The damper is electrically connected to the first substrate and the second substrate in the area outside the first and second connection points. The damper, in particular, is not in direct contact with the first or second connection points. The damper is connected to the substrate. In particular, the damper is electrically connected between the first substrate and the second substrate. Thus, for example, it is not necessary to place resistors directly at the connection points. This increases the switching speed. Resonance is reliably eliminated.

[0015] According to an embodiment, the damper comprises a capacitor. The capacitor and the resistor are electrically connected to each other. Therefore, it is only necessary to have a resistor as the damper. In addition, it is possible to have a resistor and a series capacitor as the damper. The capacitor prevents low-frequency current flow between the substrates and thus prevents the resistor from breaking. For example, the capacitor and the resistor are connected to each other by wire bonds.

[0016] According to an embodiment, the resistor is connected to the first and / or second substrate by a wire bond. Alternatively or additionally, the resistor and / or the capacitor is connected to the first and / or second substrate by a sintered connection. Alternatively or additionally, the resistor and / or the capacitor is connected to the first and / or second substrate by a solder connection. The connection is, for example, an electrical connection and / or a mechanical connection.

[0017] According to an embodiment, the damper comprises a plurality of resistors. The resistors are connected in parallel. Each of the resistors is connected to the first and second substrates, for example by wire bond connections. According to an embodiment, the damper comprises a plurality of capacitors.

[0018] According to one embodiment, the vibration damping device includes a first ferrite bead. The vibration damping device includes a second ferrite bead. The first ferrite bead is electrically connected between a first connection point and a common terminal. The second ferrite bead is electrically connected between a second connection point and the common terminal.

[0019] The ferrite beads each have an impedance that is highly frequency dependent. The resistance of the ferrite beads is negligible at frequencies below about 1 MHz. At higher frequencies substantial resistance occurs. The switching of the semiconductor chips of the power module is therefore not affected when ferrite beads are implemented, since the switching typically occurs at frequencies below 1 MHz, for example. Parasitic or destructive vibrations typically occur at frequencies between 10 MHz and 100 MHz. These vibrations are therefore efficiently damped by the ferrite beads of the damping device.

[0020] According to a further embodiment, the vibration damping device comprises a differential mode choke. The differential mode choke is electrically connected between the first connection point and the second connection point and between the second connection point and the common terminal. Thus, the differential mode choke is implemented in the gate signal path. The differential mode choke provides a low impedance between the first connection point and the common terminal. Furthermore, the differential mode choke provides a low impedance between the second connection point and the common terminal. Furthermore, the differential mode choke provides a high impedance between the first connection point and the second connection point. This high impedance between the first connection point and the second connection point damps resonant and destructive vibrations.

[0021] According to an embodiment, the damping device comprises at least one of a damper, a differential mode choke, and a ferrite bead. Any combination of the different embodiments is therefore possible.

[0022] According to an embodiment, the power semiconductor chips are one of IGBT, diode, MOSFET, thyristor, JFET, HEMT, respectively. The substrates, for example, each include an upper metallization and a lower metallization and an insulating layer therebetween. The substrates may be insulated metal substrates. The substrates may be direct bonded copper substrates or direct bonded aluminum substrates, or active metal bracing substrates with insulating ceramic or insulating resin layers.

[0023] According to one embodiment, the power module has an asymmetric layout. For example, the connection of the first connection point and the connection of the second connection point to the common terminal include straight sections of different lengths. This asymmetric design with straight sections of different lengths is possible because the vibration damping device damps critical vibrations that would be generated by this design.

[0024] According to an embodiment, in use, the first substrate and the second substrate are at a common potential. Since the two substrates are part of the same side of the switch and are connected in parallel, they contain the same or essentially the same potential. Thus, the vibration damping device is electrically connected to the two substrates that contain a common potential. In particular, elements of the vibration damping device, such as resistors, capacitors, or other elements, are connected between the two substrates and connected to the same potential on the two different substrates.

[0025] A further embodiment relates to a method for assembling a power module, which may be used to assemble a power module according to an embodiment described herein, and therefore all features disclosed in relation to the power module are also disclosed in relation to the method and vice versa.

[0026] According to one embodiment, a method for assembling a power module comprises the steps of: - providing a first substrate having a first connection point and a second substrate having a second connection point; -connecting the first connection point and the second connection point in parallel to a common terminal; - mounting a first portion of a plurality of power semiconductor chips on a first substrate and electrically connecting the first portion to a first connection point; - mounting a second portion of the plurality of power semiconductor chips on a second substrate and electrically connecting the second portion to a second connection point; electrically connecting a vibration damping device between the first substrate and the second substrate; Includes.

[0027] Hereinafter, the power module and the method for assembling the power module will be described in more detail with reference to the drawings based on exemplary embodiments. The attached figures are included to provide further understanding. In the figures, elements of the same structure and / or function may be referred to by the same reference signs. It should be understood that the embodiments shown in the figures are exemplary representations and are not necessarily drawn to scale. Insofar as elements or components correspond to each other in terms of their functions in different figures, the description thereof will not be repeated for each of the following figures. For clarity, elements may not appear with corresponding reference signs in all figures. [Brief description of the drawings]

[0028] [Figure 1] FIG. 1 illustrates an exemplary embodiment of a power module. [Diagram 2] FIG. 1 illustrates an exemplary embodiment of a power module. [Diagram 3] FIG. 1 illustrates an exemplary embodiment of a power module. [Figure 4] FIG. 1 illustrates an exemplary embodiment of a power module. [Diagram 5] FIG. 1 illustrates an exemplary embodiment of a power module. [Figure 6] FIG. 1 illustrates an exemplary embodiment of a power module. [Figure 7] FIG. 1 illustrates an exemplary embodiment of a power module. [Figure 8] FIG. 1 illustrates an exemplary embodiment of a differential mode choke. [Figure 9] FIG. 1 illustrates an exemplary embodiment of a differential mode choke. [Figure 10] FIG. 2 illustrates an exemplary embodiment of a voltage curve. [Figure 11] FIG. 2 illustrates an exemplary embodiment of a voltage curve. [Figure 12] 1 is a flow chart of an exemplary embodiment of a method for assembling a power module. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] FIG. 1 illustrates an exemplary embodiment of a power module 100. The power module may be used in an electrical converter or inverter. For example, the power module is part of a module used to rectify an AC voltage that is supplied to a DC link or a battery. An inverter may also generate an AC voltage from a DC voltage.

[0030] The power module 100 comprises a first substrate 101. The power module 100 comprises a second substrate 102. The first substrate 101 and the second substrate 102 are separate substrates. The power module 100 comprises a so-called multi-substrate layout. The two substrates 101, 102 are two stand-alone substrates that can be processed independently of each other. The two substrates 101, 102 are mechanically and electrically connected to each other during the manufacturing of the power module 100 and can be stored and processed independently before that.

[0031] Each of the substrates 101, 102 includes a plurality of power semiconductor chips 103. In particular, the chips 103 are each SiC chips. Other chip types can be used. For example, each of the substrates 101, 102 includes more than 10 chips, for example 20 chips 103.

[0032] The chips 103 of the first substrate 101 are each connected to a first connection point 111, which may also be called a gate trace or a gate runner. In particular, all gates of the chips 103 of the first substrate 101 are electrically connected to the first connection point 111. The first connection point 111 may also be called a gate connection point.

[0033] The chips 103 of the second substrate 102 are each connected to a second connection point 112, which may also be referred to as a gate trace or a gate runner. In particular, the gates of the chips 103 of the second substrate 102 are connected to the second connection point 112. The second connection point 112 may also be referred to as a gate connection point.

[0034] The first substrate 101 includes a first connection point 111 electrically connected to a gate of a chip 103 corresponding to the first substrate 101. The second substrate 102 includes a second connection point 112 electrically connected to a gate of a chip 103 of the second substrate 102.

[0035] The first substrate 101 and the second substrate 102 are both electrically connected to a common terminal 104, which may also be referred to as a common trace. The common terminal is specifically connected to a gate terminal of the power module 100. Thus, the first connection point 111 and the second connection point 112 are both connected to the gate terminal via the common terminal 104. Thus, the chips 103 of the first substrate 101 and the second substrate 102 are connected in parallel.

[0036] FIG. 1 shows a schematic asymmetric design of a power module 100 with respect to the electrical connection of the substrates 101, 102 to the common terminal 104, in particular to the gate terminal line 107 connecting the common terminal 104 to the gate terminal. The first substrate 101 is connected to the common terminal 104 at a different position than the second substrate 102. The connection of the first connection point 111 to the common terminal 104 includes a distance 106 to the connection of the second connection point 112 to the common terminal 104. The first connection point 111 is further away from the gate terminal line 107 than the second connection point 112. The connection point 111 is located further away from the gate terminal line 107 by the distance 106. The electrical path of the connection of the two substrates 101, 102 to the common terminal 104 is asymmetric. The distance from the first connection point 111 is longer than the distance from the second connection point 112. This difference in distance leads to a difference in the gate loop inductance caused by the distance 106. The difference in gate loop inductance is, for example, about 15 nH.

[0037] During use of the power module 100, fast switching of the power semiconductor chip 103 may lead to destructive oscillations between the first substrate 101 and the second substrate 102, especially due to the distance 106. Oscillation loops may extend between the substrates 101, 102 via the gate paths, the Miller capacitance and the drain side of the switches. For example, destructive oscillations occur during turn-off, and they are partly self-excited via the Miller capacitance. Such resonances may be caused when the parasitic gate loop inductances of the two substrates 101, 102 differ significantly from that of the schematic power module 100.

[0038] According to the present disclosure, a dissipative or high impedance element is introduced on or between the substrates 101, 102 to eliminate, avoid or damp the resonance. Thus, a robust solution is realized to eliminate destructive resonance without compromising the switching performance of the power module 100 and the power semiconductor chip 103. The dissipative or high impedance element is realized as a damping device 200. The damping device 200 is shown diagrammatically in FIG. 1 and described in more detail with respect to FIGS. 2-12.

[0039] FIG. 2 shows a first embodiment of a damping device 200. The damping device 200 comprises a damper 201. The damper 201 is electrically and mechanically connected to the first substrate 101. A wire bond connection 204 electrically connects the damper 201 to the second substrate 102. The damper 201 is disposed in an area 105 of the first substrate 101 outside the first connection point 111. The damper 201, in particular the resistor 202 of the damper 201, is not mechanically connected to the surface of the first connection point 111. There is no direct mechanical or electrical contact between the damper 201 and the first connection point 111. The area 105 is an area of ​​the first substrate 101 that is completely disposed beside the first connection point 111 without overlapping it. The wire bond connection 204 is not directly mechanically connected to the second connection point 112, but is connected to the second substrate 10 beside the second connection point 112.

[0040] The damper 201 is mounted between the substrates 101, 102. The resistor 202 is inserted into the resonant circuit as a resistive element. The connection of the first connection point 111 and the second connection point 112 to the common terminal 104 can be a direct connection without an additional resistor. Therefore, due to the direct connection of the connection points 111, 112 to the common terminal 104, the switching speed is increased. The damper 201 eliminates the resonance.

[0041] Both substrates 101, 102 are at the same potential, or at least essentially the same potential, for example the drain potential of a switch.The damper 201 can therefore be realised only by a resistor 202 as shown in FIG.

[0042] FIG. 3 shows a further embodiment of the power module 100, which comprises a capacitor 203 in addition to the embodiment shown in FIG. 2. The capacitor 203 is part of the damper 201. The capacitor 203 and the resistor 202 of the damper 201 are electrically connected in series. Thus, low frequencies that may destroy the resistor 202 can be avoided by the capacitor 203. For example, the capacitor 203 is connected on the second substrate 101 in the area 105 outside the connection point 112. It is also possible to arrange the resistor 202 and the capacitor 203 in the reversed arrangement. In the reversed arrangement, the capacitor 203 is arranged on the first substrate 101 and the resistor 202 is arranged on the second substrate 102. The resistor 202 and the capacitor 203 are connected by a wire bond connection 204.

[0043] As shown in Fig. 4, according to an embodiment, the damper 201 comprises a number of resistors 202. All resistors 202 of the damper 201 are arranged in the area 105 outside the connection points 111, 112. Similarly, the damper 201 according to a further embodiment comprises a number of capacitors 203, such that the number of arrangements shown in Fig. 3 are arranged between the substrates 111, 112.

[0044] The damper 201 comprises a resistor 202 and an optional capacitor 203. The damper 201 can be realized in many variants, such as the examples shown in figures 2 to 5. For example, instead of a wirebond connection 204, the damper 201, in particular the resistor 202, is connected to the substrates 101, 102 by a sintered connection 205 and / or a solder connection 206 (figure 5). According to the embodiment of figure 5, the damper 201 connects both substrates 101, 102.

[0045] The damper 201 comprises, for example, a so-called snubber. For example, the RC snubber is a monolithic RC snubber. The damper includes some parasitic equivalent series inductance. The damper may comprise a separate monolithic RC snubber. The RC snubber may also be built on the basis of MLCCs. The characteristics of the RC snubber are, for example, a resistance of 1 Ω to 1 kΩ and a capacitance of 100 pF to 1 μF.

[0046] FIG. 6 shows a power module 100 according to a further embodiment. The power module 100 comprises a first ferrite bead 211 and a second ferrite bead 212. The ferrite beads 211, 212 are each configured to suppress high frequency electronic noise. The ferrite beads 211, 212 each include a ferrite ceramic. The first ferrite bead 211 is connected in series between the first connection point 111 and the common terminal 104. The second ferrite bead 212 is connected in series between the second connection point 112 and the common terminal 104. Thus, the ferrite beads 111, 112 eliminate vibrations between the two substrates 101, 102 in use. For example, the first ferrite bead 211 is disposed on the first connection point 111. For example, the second ferrite bead 212 is disposed on the second connection point 112.

[0047] The impedance of the ferrite beads 211, 212 strongly depends on the frequency. For example, at frequencies below 1 MHz, the resistance is negligible. At higher frequencies, for example, substantial resistance occurs. For example, the impedance value at the resonant frequency of the ferrite beads is 1 Ω to 1 kΩ. The resonant frequency is, for example, 100 KHz to 100 MHz.

[0048] In particular, according to the embodiment, the ferrite bead is arranged in the gate signal path. In particular, the ferrite bead is not arranged outside the gate signal path. In particular, the power module 100 comprises the same number of ferrite beads 211, 212 as there are substrates 101, 102. In particular, the power module 100 comprises more ferrite beads 211, 212 than there are substrates 101, 102. In particular, the power module 100 does not comprise more substrates 101, 102 than there are ferrite beads 211, 212. Thus, in particular, there is at least one ferrite bead 211, 212 for each substrate 101, 102. The ferrite bead 211 is connected to the first connection point 111. Thus, there is no need for a separate ferrite bead for each separate chip 103. The same is true for the second substrate 102.

[0049] Thus, each substrate 101, 102 is connected to the common terminal 104 through one ferrite bead 211, 212. At normal switching frequencies, the resistance of the ferrite beads 211, 212 is low, so reliable switching is possible. At higher vibration frequencies, the resistance of the ferrite beads 211, 212 at the vibration frequency is high, so vibration is attenuated reliably.

[0050] 7 shows a power module 100 according to a further embodiment. The damper 200 comprises a differential mode choke 207. The differential mode choke 207 is implemented in the gate signal path between the common terminal 104 and the gate terminal line 107. In particular, the differential mode choke is disposed in the common terminal 104 between the connection to the first substrate 101 and the connection to the second substrate 102. The differential mode choke 207 provides low impedance between the first connection point 111 and the gate terminal line 107 and between the second connection point 112 and the gate line 107.

[0051] The differential mode choke 207 provides a high impedance between the first connection point 111 and the second connection point 112. This is also shown diagrammatically in Fig. 8 and Fig. 9. Fig. 8 shows the differential mode choke in the so-called common mode for driving the gate of the chip 103. In this mode, the differential mode choke 207 has a low impedance. Fig. 9 shows the so-called differential mode in which spurious vibrations occur. In this mode, the differential mode choke 207 has a high impedance. For example, the common mode impedance at the resonant frequency is 1 Ω to 100 kΩ or more. Typical resonant frequencies are 1 MHz to 1 KHz.

[0052] According to an embodiment, the differential mode choke is implemented, for example, by using a common mode choke with appropriate connections. The differential mode choke 207 is connected to the common terminal 104 and the connection points 111, 112 and the gate terminal line 107 in the manner of a T-junction. The differential mode choke 207 is implemented between the first substrate 101 and the second substrate 102.

[0053] Figure 10 shows diagrammatically an example of a gate voltage 301 of the first substrate 101 and a further gate voltage 302 of the second substrate 102 during turn-off. Figure 10 shows the curves of the gate voltages 301, 302 without the damping device 200.

[0054] 11 shows curves of gate voltages 301, 302 according to an exemplary embodiment having a damping device 200 disposed between the substrates 101, 102. Without the damping device 200, destructive vibrations would occur. Vibrations between the two substrates 101, 102 are shown in FIG. 10. These vibrations may lead to damage or even destruction of the power module 100.

[0055] As shown in Fig. 11, no vibrations occur in the damping device 200 according to the different embodiments. Only a small and insignificant residual portion of vibrations between the substrates may occur, which will not damage or destroy the power module 100.

[0056] In Figures 10 and 11, time is plotted on the X-axis and gate voltage is plotted on the Y-axis.

[0057] Thus, in the damping device 200, destructive vibrations are effectively eliminated. In particular, since there are no additional resistive elements on the connection points 111, 112 that slow down the switching, the switching performance is significantly improved. The power semiconductor chips 103 can be distributed on several substrates 101, 102, which allows for an asymmetric design. Balanced current sharing between parallel substrates 101, 102 and between parallel chips 103 is possible. Only a single connection point 111, 112 is required per substrate 101, 102. This allows for cost-effective manufacturing and low complexity of the power module 100. The asymmetric design of the connection points 111, 112 and the common terminal 104 as well as the gate terminal line 107 allows for a reduced complexity of the overall terminal design and connection point design. The power module 100 is realized in a cost-effective manner.

[0058] Fig. 12 shows a flow chart of an exemplary embodiment of a method for assembling the power module 100. For example, a power module according to one of Figs. 2 to 7 can be manufactured in this manner.

[0059] In step 401, a first substrate 101 and a second substrate 102 are provided. In a second step 402 , the first connection point 111 of the first substrate 101 and the second connection point 112 of the second substrate 102 are connected in parallel to the common terminal 104 .

[0060] In step 403, a first portion of the plurality of power semiconductor chips 103 is attached to the first substrate 102. Step 403 also includes electrically connecting the first portion of chips 103 to the first connection points 111.

[0061] In step 404, a second portion of the plurality of semiconductor chips 103 is attached to the second substrate 102. Step 404 also includes electrically connecting the second portion of the chips 103 to the second connection points 112.

[0062] In step 405, the vibration damping device 200 is provided. Step 405 also includes electrically connecting the vibration damping device 200 between the first substrate 101 and the second substrate 102.

[0063] The order of steps 401-405 may also be different than that described, for example step 403 before step 402.

[0064] The embodiments shown in Figures 1-12 described above represent exemplary embodiments of the improved power modules and methods for assembling the power modules, and therefore, they do not constitute an exhaustive list of all embodiments of the improved apparatus and methods. Actual apparatus and methods may differ from the illustrated embodiments, for example, in terms of arrangement, apparatus, and elements.

[0065] Reference sign 100 Power Module 101 First substrate 102 Second substrate 103 Power Semiconductor Chip 104 Common terminal 105 areas 106 distance 107 Gate terminal wire 111 First Connection Point 112 Second Connection Point 200 Damping Device 201 Damper 202 Resistor 203 Capacitor 204 Wirebond connection 205 Sintered Connection 206 Solder Connection 207 Differential Mode Choke 211 First Ferrite Bead 212 Second Ferrite Bead 301,302 Gate voltage 401~405 Method steps

Claims

1. - a first substrate (101) having a first gate connection point (111); - a second substrate (102) having a second gate connection point (112), wherein the first gate connection point (111) and the second gate connection point (112) are electrically connected in parallel to a common terminal (104), and the common terminal (104) is a common gate terminal; and further, - a plurality of power semiconductor chips (103), wherein a first portion of the power semiconductor chips (103) is attached to the first substrate (101) and electrically connected to the first gate connection point (111), and a second portion of the power semiconductor chips (103) is attached to the second substrate (102) and electrically connected to the second gate connection point (112); - a vibration damping device (200) electrically connected between the first substrate (101) and the second substrate (102), wherein the connection of the first gate connection point (111) and the second gate connection point (112) to the common terminal (104) has an asymmetric layout; - the connection of the first gate connection point (111) to the common terminal (104) is located at a distance (106) from the connection of the second gate connection point (112) to the common terminal (104), and the electrical paths of the connections of the first and second substrates (101, 102) to the common terminal (104) are asymmetric; - the first gate connection point (111) is located further away from the gate terminal line (107) by the distance (106) than the second gate connection point (112), a power module (100).

2. The power module (100) according to claim 1, wherein the vibration damping device (200) comprises a damper (201), the damper (201) comprises a resistor (202), and the damper (201) is electrically connected to the first substrate (101) and the second substrate (102) within a region (105) outside the first and second gate connection points (111, 112).

3. The power module (100) according to claim 2, wherein the damper (201) comprises a capacitor (203) electrically connected to the resistor (202).

4. The power module (100) according to claim 2 or 3, comprising at least one of wire bond connection (204), sintered connection (205), and solder connection (206) for electrically connecting the damper (201) to the first substrate (101) or the second substrate (102).

5. The power module (100) according to any one of claims 2 to 3, wherein the damper (201) includes a plurality of resistors (202), and the resistors (202) are connected in parallel.

6. - The power semiconductor chip (103) is one of an IGBT, MOSFET, diode, thyristor, JFET, and HEMT, and the power module (100) according to any one of claims 1 to 5.

7. The power module (100) according to any one of claims 1 to 6, wherein the first substrate (101) and the second substrate (102) are at a common potential.

8. The power module (100) according to any one of claims 1 to 7, wherein the second connection point (112) is located between the first connection point (111) and the gate terminal line (107).

9. - Providing a first substrate (101) having a first gate connection point (111) and a second substrate (102) having a second gate connection point (112); - Connecting the first gate connection point (111) and the second gate connection point (112) in parallel to a common terminal (104), wherein the common terminal (104) is a common gate terminal, and the connection of the first gate connection point (111) and the second gate connection point (112) to the common terminal (104) has an asymmetric layout, the connection of the first gate connection point (111) to the common terminal (104) is located at a distance (106) to the connection of the second gate connection point (112) to the common terminal (104), the electrical paths of the connection of the first and second substrates (101, 102) to the common terminal (104) are asymmetric, and the first gate connection point (111) is located further away from the gate terminal line (107) by the distance (106) than the second gate connection point (112). Further, - Attaching a first portion of a plurality of power semiconductor chips (103) to the first substrate (101) and electrically connecting the first portion to the first gate connection point (111); - attaching a second portion of the plurality of power semiconductor chips (103) to the second substrate (102) and electrically connecting the second portion to the second gate connection point (112); - electrically connecting a vibration damping device (200) between the first substrate (101) and the second substrate (102); A method for assembling a power module (100) comprising the steps above.

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