Low-intensity photomasks and systems, methods, and program products for making low-intensity photomasks for use in flat panel display lithography - Patents.com

Abstract

A method of manufacturing a photomask, the method including receiving initial photomask design data associated with one or more patterns to be formed on the photomask, and optimizing the initial photomask design data to minimize printing exposure energy while maintaining acceptable pattern quality and size. In some embodiments, the optimizing includes setting minimization of printing exposure energy as a priority design rule, setting optimization of pattern quality and size as a secondary design rule, iterating sizing of mask design features to determine a range of size bias that satisfies both the priority design rule and the secondary design rule to provide an initial optimized mask design, and adjusting mask variations across the range of size bias to determine mask variations that further optimize the initial optimized mask design to obtain a final optimized mask design.

Description

[Technical field]

[0001] Related Applications This application claims priority to and the benefit of U.S. Provisional Patent Application No. 63 / 323,527, filed March 25, 2022, and entitled "LOW INTENSITY PHOTOMASK AND SYSTEM, METHOD AND PROGRAM PRODUCT FOR MAKING LOW INTENSITY PHOTOMASK FOR USE IN FLAT PANEL DISPLAY LITHOGRAPHY," the entire contents of which are incorporated herein by reference.

[0002] The present invention relates generally to the manufacture of photomasks, and more particularly to the manufacture of photomasks used in flat panel display (FPD) lithography. [Background technology]

[0003] The lithography process in flat panel display (FPD) manufacturing determines the performance and output capacity of flat panel products. Reducing the process time in lithography steps is a key factor for reducing the product turnaround time (TAT) and thus improving the total production capacity output of the product, which means improving the productivity in panel manufacturing.

[0004] When optimizing a mask layout to improve general lithography performance, it is often necessary to adjust the mask feature size, shape, and optical properties (e.g., phase shift, transmission level) to improve printing of the mask on the substrate. The optical properties are often adjusted using mask structures, for example, adding or adjusting thin films on the mask. In optical proximity correction, the edges of the mask features are adjusted so that when the mask is printed on the substrate by the lithography scanner, the printed mask features best match the desired design features. Typical figures of merit to guide adjustment of mask features relate to pattern fidelity, image focus range, and exposure latitude.

[0005] Photomask technology has contributed to the capabilities and productivity of integrated circuit (IC) and flat panel display (FPD) manufacturing, including implementation of masks that improve process capability, margins, and yields. Such masks include advanced binary or multi-tone masks and phase-shifting masks, to name a few. These masks are primarily composed of a transparent substrate and patterned absorbing films (e.g., CrOx, CrON) and phase-shifting films (e.g., MoSi, SiN) to provide and maintain the optical, physical, and mechanical requirements of the mask. Therefore, in mask fabrication, the optimal mask process conditions for processing these films and their controllability affect the mask patterning quality and performance in the lithography process.

[0006] However, for FPD panel processes, the designs and processes are very different from traditional IC products and require special dedicated solutions. For example, cutting edge panel product designs have features with significantly larger dimensions that are patterned over significantly larger areas, and the geometry family of such features is often different compared to advanced IC designs. In this regard, FPD panel designs do not require the more sophisticated mask making processes used in complex IC designs. Therefore, a mask making process that is more suitable for FPD lithography processes is needed. Summary of the Invention [Problem to be solved by the invention]

[0007] The objective of the present invention is to provide a mask making process in which the mask shape and mask structure are optimized to achieve the minimum printing exposure energy while maintaining acceptable pattern quality and size. This is in contrast to conventional techniques used, for example, in IC lithography, where the mask shape and structure are optimized to achieve optimal pattern quality and size. By effectively changing the priority of the optimization merit function from improving pattern quality to minimum exposure dose level, a significant increase in throughput for lithography scanners can be achieved while maintaining acceptable image quality for flat panel display applications. [Means for solving the problem]

[0008] In some exemplary embodiments, a method for manufacturing a photomask includes: (A) receiving initial photomask design data related to one or more patterns to be formed on the photomask; (B) optimizing the initial photomask design data to minimize printing exposure energy while maintaining acceptable pattern quality and size, the optimizing steps including: 1. setting minimization of printing exposure energy as a priority design rule; 2. setting optimization of pattern quality and size as a secondary design rule; 3. iterating sizing of mask design features to determine a range of size bias that satisfies both the priority design rule and the secondary design rule to provide an initial optimized mask design; and 4. adjusting mask variations across the range of size bias to further optimize the initial optimized mask design to obtain a final optimized mask design; and (C) generating optimized photomask design data based on the final optimized mask design.

[0009] In some exemplary embodiments, the range of size bias includes a negative size bias.

[0010] In some exemplary embodiments, the range of size bias includes a positive size bias.

[0011] In some exemplary embodiments, the mask deformation includes a pattern edge compensation deformation.

[0012] In some exemplary embodiments, the mask variations include mask structure variations.

[0013] In some exemplary embodiments, the mask variations include scanner illumination shape variations.

[0014] In some exemplary embodiments, the mask variations include pattern edge compensation variations, mask structure variations, scanner illumination shape variations, and combinations thereof.

[0015] In some exemplary embodiments, the method further includes performing optical proximity correction on the optimized photomask design data.

[0016] In some exemplary embodiments, the method further comprises providing a mask blank.

[0017] In some exemplary embodiments, the method further includes processing a mask blank using the optimized photomask design data to form a photomask for use in a lithography process.

[0018] In some exemplary embodiments, the photomask is a large photomask for use in lithography processes to manufacture flat panel displays (FPDs).

[0019] In some exemplary embodiments, a method for forming a flat panel display includes irradiating light from a light energy source onto a glass plate substrate through a large photomask formed according to the method of claim 11 in a photolithography process, wherein at least one circuit pattern is transferred from the large photomask to the glass plate substrate.

[0020] In some exemplary embodiments, the flat panel display is a liquid crystal display, an active matrix liquid crystal display, an organic light emitting diode, a light emitting diode, a plasma display panel, or an active matrix organic light emitting diode.

[0021] These and other features and advantages of the present invention will be presented in more detail in the following detailed description and the accompanying drawings, which illustrate, by way of example, the principles of the invention.

[0022] Various exemplary embodiments of the present invention will be described in detail with reference to the following figures. [Brief description of the drawings]

[0023] [Figure 1] 1A-1C show an original mask pattern layout compared to a modified mask pattern layout according to an exemplary embodiment of the present invention. [Diagram 2] 11 is a graph showing dose versus CD trends for differently biased line and space features in accordance with an exemplary embodiment of the present invention. [Diagram 3] 1 is a graph illustrating dose versus CD trends for an insulating contact feature according to an exemplary embodiment of the present invention. [Figure 4A] FIG. 13 illustrates one variation in the mask that may be considered in the optimization process for dose minimization, according to an exemplary embodiment of the present invention. [Figure 4B] FIG. 13 illustrates another variation in the mask that may be considered in the optimization process for dose minimization, according to an exemplary embodiment of the present invention. [Figure 4C] FIG. 13 illustrates another variation in the mask that may be considered in the optimization process for dose minimization, according to an exemplary embodiment of the present invention. [Diagram 5] FIG. 1 is a simplified block diagram of one embodiment of a flat panel display (FPD) manufacturing system and associated FPD manufacturing flow, in accordance with an exemplary embodiment of the present invention. [Figure 6] FIG. 1 is a schematic diagram of an exemplary mask enhancer system. [Figure 7] FIG. 2 illustrates an exemplary computer system associated with a mask enhancer system in accordance with various embodiments of the present invention. [Figure 8] FIG. 2 illustrates a process for mask design optimization according to an exemplary embodiment of the present invention. [Figure 9] 1 is a graph showing aerial image intensity (mJ / cm2) versus position on the x-axis (nm) illustrating an intensity profile in accordance with an exemplary embodiment of the present invention. [Figure 10] 1 is a graph illustrating optimal energy level versus pattern size according to an exemplary embodiment of the present invention. [Figure 11] FIG. 9 illustrates a process flow in which the low-strength mask design optimization process described above with reference to FIG. 8 is augmented with an additional step. [Figure 12A] FIG. 1 illustrates an example of preparing a low-intensity mask for an FPD design pattern according to an exemplary embodiment of the present invention. [Figure 12B] FIG. 13 illustrates another example of preparing a low-intensity mask for an FPD design pattern according to an exemplary embodiment of the present invention. [Figure 12C] FIG. 13 illustrates another example of preparing a low-intensity mask for an FPD design pattern according to an exemplary embodiment of the present invention. [Figure 13] 1A-1C illustrate the structure and strength of a PSM mask according to an exemplary embodiment of the present invention. [Figure 14] FIG. 1 illustrates a comparison between intensity profiles of various PSM masks according to an exemplary embodiment of the present invention. [Figure 15] 1 is a table showing the productivity gain in percentage for 1.5 μm line space patterns with low intensity mask bias and dose variation according to an exemplary embodiment of the present invention. [Figure 16] 1 is a table showing the productivity gain in percentage for 1.8 μm contact hole patterns by varying low intensity mask bias and dose according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] A flat panel display (FPD) is an electronic viewing technology used to display content (e.g., still images, video, text, or other visual material) in a variety of entertainment, consumer electronics, personal computers, and mobile devices, as well as many types of medical, transportation, and industrial equipment. Current types of FPD include, for example, LCD (liquid crystal display), AMLCD (active matrix liquid crystal display), OLED (organic light emitting diode), LED (light emitting diode), PDP (plasma display panel), and AMOLED (active matrix OLED).

[0025] During FPD manufacturing, the FPD lithography system shines light onto a photomask that contains the original thin-film transistor (TFT) circuit pattern, and the light passes through a lens to expose the pattern onto a glass plate substrate. For large glass plates, the exposure process is repeated several times to form the pattern across the entire plate.

[0026] FIG. 1 shows an original mask pattern layout compared to a modified mask pattern layout according to an exemplary embodiment of the present invention. The original pattern layout, shown in solid lines, is designed to obtain a target critical dimension (CD) or layout using optimal dose conditions to obtain a ±10% CD tolerance in panel lithography. This traditional method originates from the history of integrated circuits and is limited by the narrower process latitude in this type of lithography. However, in flat panel lithography processes, larger pattern sizes often already have sufficient process windows for exposure latitude and depth of focus, and there is more flexibility to adjust the pattern size to lower the intensity threshold, and therefore obtain improved scanner throughput. In this regard, the dotted lines in FIG. 1 show the preferred pattern bias to achieve a lower threshold exposure for the specific pattern in this example.

[0027] In this case, a lower intensity mask is produced with smaller design geometries, indicated by the dotted lines in Figure 1, giving lower exposure times for these fully transmissive feature patterns. Although not shown in Figure 1, certain other features on the mask, such as dark field contact hole designs, require larger design feature bias (rather than smaller bias) to achieve shorter exposure times. In some embodiments, these size bias techniques are applied to flat panel processes to create higher productivity masks.

[0028] Figure 2 is a graph showing the dose vs. CD trend for differently biased line and space features. Line 6 is the data trend for exposure energy targeting 1.5 μm CD for line and space patterns. According to the graph, 115 mJ / cm2 is required to achieve a 1.5 μm CD target. 2 exposure energy must be used. However, in some embodiments, the lithography process can be optimized to minimize the exposure energy, in which case smaller lines with the same pitch size can be used. This is represented by lines 7, 8, and 9, where lower exposure energy is required to obtain the same pattern size on the panel, resulting in higher throughput.

[0029] 3 is a graph illustrating the reverse effect when the design pattern is an insulating contact feature, according to an exemplary embodiment of the present invention. Specifically, in this exemplary embodiment, a positive bias is applied to the design contact to create larger features on the mask and achieve a lower dose mask effect to define the target CD pattern on the panel. Line 10 is 180 mJ / cm 2 3 shows the conditions for obtaining a 2.0 μm contact CD at a dose of 10 μm, while the other lines show the effect of dose minimization when the contact features on the mask are made larger.

[0030] In some embodiments, this bias optimization method can be applied to an entire mask pattern consisting of various feature shapes and sizes by simultaneously optimizing the bias of the shapes according to the exposure minimization rules. More specifically, in some embodiments, by using a pattern correction tool with exposure minimization bias rules, the printing dose for the entire mask can be effectively reduced while the pattern can be correctly printed on the panel for proper display device function.

[0031] 4A, 4B, and 4C show various variations in the mask that may be considered in the optimization process for dose minimization, according to an exemplary embodiment of the present invention.

[0032] 4A illustrates pattern edge compensation variations that may be adjusted to minimize dose according to an exemplary embodiment of the present invention, such as bias, hammerhead, serif, jog, scattering bar, and combinations thereof, to name a few.

[0033] 4B illustrates mask structure variations that can be tailored to minimize dose according to an exemplary embodiment of the present invention, including, for example, phase shifter layers, absorber layers, transmissive layers, anti-reflective layers, and combinations thereof, to name a few.

[0034] 4C illustrates scanner illumination geometry variations that can be adjusted to minimize dose, according to an exemplary embodiment of the present invention, including variations in arc-shaped illumination, such as adjusting arc width, arc degree, arc spacing, arc shape, and combinations thereof, to name a few.

[0035] In some exemplary embodiments, mask variations may be adjusted individually or in combination to minimize dose. For example, pattern edge compensation, mask structure, and / or scanner illumination shape may be adjusted individually or in any combination of two or more variations.

[0036] 5 is a simplified block diagram of one embodiment of a flat panel display (FPD) manufacturing system 100 and associated FPD manufacturing flow, according to an exemplary embodiment of the invention. FPD manufacturing system 100 includes multiple entities, such as design house 120, mask house 130, and FPD manufacturer 150 (i.e., factory), that interact with each other in the design, development, and manufacturing cycle and / or services related to the production of FPD devices 160. The multiple entities may be connected by a communications network, which may be a single network or a variety of different networks, such as an intranet or the Internet, and may include wired and / or wireless communication channels. Each entity may interact with the other entities and may provide services to and / or receive services from the other entities. In some embodiments, one or more of design house 120, mask house 130, and FPD manufacturer 150 may have a common owner, may coexist in a common facility, and may even use common resources.

[0037] In various embodiments, design house 120, which may include one or more design teams, generates FPD design layout 122. FPD design layout 122 may include various geometric patterns designed for the manufacture of FPD device 160. By way of example, the geometric patterns may correspond to patterns of metal, oxide, or semiconductor layers that make up various components of FPD device 160 to be manufactured. The various layers combine to form various features of FPD device 160, such as thin film transistors (TFTs). For example, various portions of FPD design layout 122 may include features such as active areas, gate electrodes, source and drain regions, metal lines or vias for metal interconnects, openings for bond pads, and other features known in the art to be formed in an FPD glass substrate and various material layers disposed on the glass substrate. In an exemplary embodiment, design house 120 implements a design procedure to form FPD design layout 122. The design procedure may include logical design, physical design, and / or place and route. FPD design layout 122 may be represented in one or more data files that contain information related to the geometric patterns to be used to fabricate FPD device 160. In some embodiments, FPD design layout 122 may be represented in a variety of formats, such as the Open Artwork System Interchange Standard (OASIS) file format, the GDSII file format, or the DFII file format, to name a few.

[0038] In some embodiments, the design house 120 can transmit the FPD design layout 122 to the mask house 130, for example via a network connection as described above. The mask house 130 can then use the FPD design layout 122 to manufacture one or more masks to be used in fabricating various layers of the FPD device 160 according to the FPD design layout 122. In various examples, the mask house 130 performs mask data preparation 132, in which the FPD design layout 122 is converted into a form that can be physically written by a mask writer, and further performs mask fabrication 144, in which the design layout prepared by the mask data preparation 132 is modified to suit a particular mask writer and / or mask manufacturer and then fabricated. In the example of FIG. 2, the mask data preparation 132 and the mask fabrication 144 are shown as separate elements. However, in some embodiments, the mask data preparation 132 and the mask fabrication 144 may be collectively referred to as mask data preparation.

[0039] In some embodiments, mask data preparation 132 includes application of one or more resolution enhancement techniques (RET) to compensate for potential lithography errors, such as those that may result from diffraction, interference, or other process effects. In some embodiments, optical proximity correction (OPC) may be used to adjust line widths depending on the density of surrounding geometric features, add "dogbone" end caps to the ends of lines to prevent shortening of the line ends, correct for electron beam (e-beam) proximity effects, or achieve other purposes. For example, OPC techniques may add sub-resolution assist features (SRAFs), which may include, for example, adding scattering bars, serifs, and / or hammerheads to the FPD design layout 122 according to an optical model or rule, thereby refining the final pattern on the glass substrate after the lithography process to improve resolution and accuracy. Mask data preparation 132 may also include additional RET, such as off-axis illumination (OAI), phase shift masks (PSM), other suitable techniques, or combinations thereof.

[0040] In some embodiments, mask data preparation 132 may include mask process correction (MPC) that is used to correct errors introduced during the mask making process. For example, MPC can be used to correct for effects of the mask making process, such as fogging, development and etch loads, and e-beam proximity effects. In some embodiments, the MPC process modifies the post-OPC design layout to compensate for limitations that may occur during mask fabrication 144.

[0041] In some embodiments, mask data preparation 132 may include a lithography process check (LPC) that simulates the processing performed by FPD manufacturer 150 to create FPD device 160. The LPC may simulate this processing based on FPD design layout 122 to produce a simulated manufactured device, such as FPD device 160. The processing parameters in the LPC simulation may include parameters associated with various processes in the FPD manufacturing cycle, parameters associated with tools used to manufacture the FPD, and / or other aspects of the manufacturing process. By way of example, the LPC may take into account various factors, such as aerial image contrast, depth of focus (DOF), mask error emphasis factor (MEEF), other suitable factors, or a combination thereof.

[0042] In some embodiments, after the simulated manufactured device is created by LPC, if the simulated device layout is not close enough to the geometry to meet the design rules, certain steps of mask data preparation 132, such as OPC and MPC, may be repeated to further refine the IC design layout 122.

[0043] It should be understood that the above description of mask data preparation 132 has been simplified for purposes of clarity and that data preparation may also include additional functions such as logic operations (LOPs) to modify the FPD design layout in accordance with manufacturing rules. Additionally, the processes applied to the FPD design layout 122 during data preparation 132 may be performed in a variety of different orders.

[0044] After mask data preparation 132, during mask fabrication 144, a mask or group of masks can be fabricated based on the modified FPD design layout. In some embodiments, an electron beam (e-beam) or multiple e-beams mechanism is used to form a pattern on a mask (photomask or reticle) based on the modified FPD design layout. In some embodiments, the mask pattern includes opaque and transparent regions. A radiation beam, such as an ultraviolet (UV) beam used to expose a radiation sensitive material layer (e.g., photoresist) coated on the wafer, is blocked by the opaque regions and transmitted through the transparent regions. In some embodiments, a binary mask includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chrome) coated on the opaque regions of the mask. In some embodiments, the mask is formed using phase shifting techniques. In a phase shift mask (PSM), various features of a pattern formed on the mask are configured to have a pre-set phase difference to enhance image resolution and imaging quality. In some embodiments, the phase shift mask can be an attenuated PSM or an alternating PSM.

[0045] In some embodiments, FPD manufacturer 150 can use a mask (or masks) produced by mask house 130 to transfer one or more mask patterns to product glass substrate 152, thus producing FPD devices 160 on product glass substrate 152. FPD manufacturer 150 can include an FPD manufacturing facility, which can include multiple manufacturing facilities for producing a variety of different FPD products. For example, FPD manufacturer 150 can include a first manufacturing facility for front-end fabrication (i.e., front-end-of-line (FEOL) fabrication) of multiple FPD products, a second manufacturing facility can provide back-end fabrication (i.e., back-end-of-line (BEOL) fabrication) for interconnection and packaging of FPD products, and a third manufacturing facility can provide other services. In various embodiments, product FPD 152 in and / or on which FPD devices 160 are produced can include a glass substrate, where the type of glass can be, for example, aluminosilicate glass, borosilicate glass, or fused silica, to name a few. In some embodiments, the large photomask may be appropriately sized to accommodate the photolithographic processing of the glass plate substrate used to form the FPD.

[0046] In some exemplary embodiments, mask data preparation may include the use of a mask enhancer system. In this regard, FIG. 6 illustrates a schematic diagram of an exemplary mask enhancer system 204 for enhancing a photomask layout in accordance with some embodiments. Some embodiments of the mask enhancer system 204 include an OPC enhancer 222 that receives the mask layout M generated by the design house 120 and generates an OPC-processed (e.g., corrected) mask layout M. As described above, OPC is a lithography technique used to correct or enhance the mask layout M and create improved imaging effects to reproduce the original layout drawn by the FPD design house 120 on a glass substrate. For example, OPC can be used to compensate for imaging distortions due to optical diffraction. In some embodiments, the mask layout M is a data file that includes information of a geometric pattern to be generated on a substrate, and the OPC enhancer 222 modifies the data file and generates a corrected data file representing the corrected mask layout M′.

[0047] In some exemplary embodiments, the mask projection apparatus 230 may be applied to the corrected mask layout M to generate a projected mask layout 238 onto the wafer. In some embodiments, the corrected mask layout M is a data file, and the mask projection apparatus 230 simulates the projection of the corrected mask layout M′ onto the wafer to generate a simulated projected mask layout 238. The defect detector 232 of the mask enhancer 204 inspects the projected mask layout 238 and finds defect regions 236 in the projected mask layout 238. Although the corrected mask layout M′ is OPC processed, defect regions may be generated when the corrected mask layout M′ is projected onto the substrate 208.

[0048] In some embodiments, the defect corrector 234 of the mask enhancer 204 may receive the defect regions 236 and the corrected mask layout M' and perform further corrections, e.g., enhancements, on the corrected mask layout M', thereby generating an enhanced mask layout M". In some embodiments, the defect detector 232 may be coupled to the defect corrector 234 to produce a layout detection and correction system 233 that receives the projected mask layout 238 and the corrected mask layout M' and provides an enhanced mask layout M".

[0049] In some exemplary embodiments, the mask enhancer system 204 includes specialized hardware components, software components, and / or a combination of both hardware and software components to perform various procedures related to photomask enhancement and correction as part of the FPD manufacturing process. In this regard, FIG. 7 illustrates an exemplary computer system associated with a mask enhancer system according to various embodiments of the present invention. In some embodiments, the computer system includes a server 401, a display 402, one or more input interfaces 403, and one or more output interfaces 404, all of which are conventionally coupled by one or more buses 405. Examples of suitable buses include, for example, PCI-Express, AGP, PCI, ISA, etc., to name a few.

[0050] A computer system may include any number of graphics processors. The graphics processor may reside on a motherboard, such as integrated with a motherboard chipset. One or more graphics processors may reside on external boards connected to the system via a bus, such as an ISA bus, a PCI bus, an AGP port, a PCI Express, or other system bus, to name a few. The graphics processors may be on separate boards, each connected to a bus, such as a PCI Express bus, connected to each other, and connected to the rest of the system. Additionally, there may be separate buses or connections (e.g., Nvidia SLI or ATI CrossFire connections, to name two) over which the graphics processors can communicate with each other. This separate bus or connection may be used in addition to or instead of the system bus.

[0051] The server 401 may include one or more CPUs 406, one or more GPUs 407, and one or more memory modules 412. Each CPU and GPU may be a single-core or multi-core unit. Examples of suitable CPUs include Intel Pentium®, Intel Core™ 2 Duo, AMD Athlon 64, AMD Opteron®, to name a few. Examples of suitable GPUs include Nvidia GeForce®, ATI Radeon®, to name a few. The input interface 403 may include a keyboard 408 and a mouse 409. The output interface 404 may include a printer 410.

[0052] In some embodiments, communication interface 411 is a network interface that allows the computer system to communicate over a wireless or wired network. Communication interface 411 may be coupled to a network transmission line, a transmission medium (not shown), such as twisted pair, coaxial cable, fiber optic cable, to name a few. In another embodiment, communication interface 411 provides a wireless interface, i.e., communication interface 411 uses a wireless transmission medium. Examples of other devices that can be used to access the computer system via communication interface 411 include mobile phones, PDAs, personal computers, to name a few (not shown).

[0053] The memory module 412 may generally include different modalities, such as semiconductor memory, such as random access memory (RAM), disk drives, etc. In various embodiments, the memory module 412 stores an operating system 413, data structures 414, instructions 415, applications 416, and procedures 417.

[0054] Storage devices include mass storage disk drives, floppy disks, magnetic disks, optical disks, magneto-optical disks, fixed disks, hard disks, CD-ROMs, recordable CDs, DVDs, recordable DVDs (e.g., DVD-R, DVD+R, DVD-RW, DVD+RW, HD-DVD, or Blu-ray Discs), flash and other non-volatile solid state storage (e.g., USB flash drives), battery-backed volatile memory, tape storage, readers, and other similar media, and combinations thereof.

[0055] In various embodiments, the specific software instructions, data structures, and data implementing various embodiments of the invention are typically embodied in server 401. In general, an embodiment of the invention is tangibly embodied using a computer readable medium, e.g., a memory, and includes instructions, applications, and procedures that, when executed by a processor, cause a computer system to utilize the invention, e.g., collect and analyze data, pixelate structures, determine edge placement error, move edge fragments, optimize edge fragment placement, etc. The memory can store software instructions, data structures, and data for any of the operating systems, data collection applications, data aggregation applications, data analysis procedures, etc., in semiconductor memory, disk memory, or a combination thereof.

[0056] A computer-implemented or computer-executable version of the invention may be embodied using, stored on, or associated with a computer-readable medium. A computer-readable medium may include any medium that participates in providing instructions to one or more processors for execution. Such media may take many forms, including but not limited to non-volatile media, volatile media, and transmission media. Non-volatile media include, for example, flash memory, or optical or magnetic disks. Volatile media include static or dynamic memory, such as cache memory or RAM. Transmission media include coaxial cables, copper wire, fiber optic lines, and wires arranged in a bus. Transmission media may also take the form of electromagnetic, radio frequency, acoustic, or light waves, such as those generated during radio wave or infrared data communications.

[0057] For example, a binary, machine-executable version of the software of the present invention may be stored or reside in RAM or cache memory or a mass storage device. The source code of the software of the present invention may also be stored or reside in a mass storage device (e.g., a hard disk, magnetic disk, tape, or CD-ROM). As a further example, the code of the present invention may be transmitted over wires, radio waves, or a network such as the Internet.

[0058] The operating system may be implemented by any conventional operating system, including Windows® (a registered trademark of Microsoft Corporation), Unix® (a registered trademark of the Open Group in the United States and other countries), Mac OS® (a registered trademark of Apple Computer, Inc.), Linux® (a registered trademark of Linus Torvalds), and other operating systems not expressly enumerated herein.

[0059] In various embodiments, the invention may be implemented as a method, system, or article of manufacture using standard programming or engineering techniques, or both, to generate software, firmware, hardware, or any combination thereof. The term "article of manufacture" (or alternatively "computer program product") as used in this application is intended to encompass a computer program accessible from any computer-readable device, carrier, or media. Furthermore, the software in which the various embodiments are implemented may be accessible via a transmission medium, for example, over a network from a server. The article of manufacture in which the code is implemented also includes transmission media, such as network transmission lines and wireless transmission media. Thus, the article of manufacture also includes the medium in which the code is embedded. Those skilled in the art will recognize that many modifications can be made to this configuration without departing from the scope of the invention.

[0060] The computer system illustrated in Figure 7 is not intended to be limiting of the present invention, as other alternative hardware and / or software environments may be used without departing from the scope of the present invention.

[0061] FIG. 8 illustrates a process for mask design optimization according to an exemplary embodiment of the present invention. In step S01 of the process, a mask correction tool may receive or otherwise acquire data related to the original mask design layers and lithography tool scanner illumination conditions. In step S03, a dose minimization rule is set as a priority rule, and a minimum acceptable design for matching the target layer is set as a secondary rule. In some embodiments, the minimum acceptable design may be a minimum acceptable CD tolerance range. In step S05, the mask model is calibrated for pattern dose for printing over a wide bias range. In this step, mask data is generated that represents the change in mask features according to the bias range. For example, a line and space pattern may be reduced in size compared to the original mask pattern data over a negative bias range, and a contact hole pattern may be increased in size compared to the original mask pattern data over a positive bias range.

[0062] In step S07, the pattern edges, mask features, and / or scanner illumination shapes are varied over a negative and / or positive bias range to satisfy the minimum dose rule while still achieving a minimum acceptable target layer match. In this step, only one of the variations can be adjusted over the bias range, or two or more variations can be combined and varied over the bias range to determine the iteration that achieves the minimum dose while maintaining a minimum acceptable quality and size of the features.

[0063] In some embodiments, the process flow shown in FIG. 8 advances the optimization of the mask pattern for low exposure cases, which enhances the throughput when the mask is applied in lithography printing. Without being bound by theory, in panel manufacturing processes, the lithography process has a large process margin compared to that of IC manufacturing. Large pattern design and exposure tool capabilities enable the use of low intensity masks in panel lithography processes for better throughput and productivity.

[0064] Figure 9 shows the relationship between the position on the x-axis (nm) and the aerial image intensity (mJ / cm 2 ) showing intensity profile 1 for a 1.5 μm line and 1.5 μm space pattern (3.0 μm pitch) and intensity profile 2 for a 1.7 μm line and 1.3 μm space pattern (3.0 μm pitch) according to an exemplary embodiment of the present invention. In some embodiments, such intensity profiles generated using the results of aerial image simulations can be used to select optimal designs and intensity levels. In this example, for intensity profile 1, to obtain a pattern size of 1.5 μm, the intensity or energy level is close to 0.3 to achieve the target CD (shown as line 3). If an oversizing of 0.2 μm is used to generate a low intensity mask (intensity profile 2), a 0.2 energy level can be used to achieve the target CD (shown as line 4). That is, a lower dose or energy can be used to define the same size pattern. Therefore, a shorter exposure time can be used in the panel lithography process to improve the throughput and manufacturability of the panel process.

[0065] 10 is a graph showing optimal energy levels versus pattern size according to an exemplary embodiment of the present invention. The use of a low intensity mask with optimal resizing allows the use of lower energies as a trend towards optimal dose conditions.

[0066] Since the present invention prioritizes low exposure cases rather than pattern fidelity cases as in conventional pattern correction methods, in some embodiments, functionality can be added to the optimization flow to identify and compensate for issues that may result from prioritizing dose minimization rules. In this regard, FIG. 11 illustrates a process flow in which the low-intensity mask design optimization process described above with reference to FIG. 8 is augmented with additional steps. The first additional step (step S09) is Mask Rules Checking (MRC), which ensures that the low-intensity mask design does not introduce mask shapes and features that are too complex for manufacturing. The second additional step is Pattern Matching (PM) (step S11), which selectively positions and adjusts special mask patterns to address printing issues that may have been introduced by the low-intensity mask optimization process. The third additional step is Optical Proximity Correction (OPC) (step S13), which continues to adjust the patterns for pattern quality without negating the dose minimization benefits of the low-intensity mask design process flow. The final low-intensity mask design as an augmentation of these steps is completed in step S15. In some embodiments, the overall low-intensity mask design process may include any number of iterations of low-intensity optimization with additional steps to compensate for problems until a final mask design that meets the desired parameters is achieved, as indicated by the dashed arrows in Figure 11. In some embodiments, the additional steps described above may or may not be required in the overall low-intensity mask data correction flow, and any number of these additional steps may be included in the overall process, either individually or in combination.

[0067] 12A-12C show an example of preparing a low-intensity mask for an FPD design pattern. The mask in this example is intended to form part of a contact array layer in an FPD panel process. The original mask redesigned as low-intensity mask design 400 is shown in FIG. 12A and includes contact openings 410. MRC tools can then be used to detect overlaps or rule violations of design and process features, and corrections can be made using the applied rules in the MRC process and pattern matching. FIG. 12B shows the mask after MRC and OPC processes, which can be applied to improve process windows or for other specific purposes. FIG. 12C shows a verification and validation step, where a simulation method for an optimized low-intensity mask can be used to identify potential issues (such as bridging issues shown in simulated features 412 projected by the mask), and the issues can then be corrected in the data for final low-intensity mask manufacturing.

[0068] 4A-4C, in some embodiments, special illumination and mask structure conditions can be employed in mask fabrication and printing to improve low-intensity mask effectiveness and dose reduction opportunities. In some embodiments, low-intensity optimization can benefit from setting mask phase shift and optical transmission parameters (including multiple transmission levels) along with other film properties that can create high-contrast masks, thereby providing more freedom to optimize the low-intensity mask design flow for greater productivity and faster FPD production.

[0069] Traditionally, masks used in FPD panel manufacturing processes are exposed using exposure tools with circular apertures. In some embodiments, larger opening aperture types can be used to deliver larger amounts of energy to the mask. Also, OAI (off-axis illumination) is currently used in the FPD area (see FIG. 4C). In some embodiments, the design and sizing of the OAI can be optimized to improve the effectiveness of low intensity masks.

[0070] 4B, mask technology in panel lithography can contribute to obtain process window and productivity improvements in FPD manufacturing. In this regard, in some embodiments, various types of masks can be used in the FPD manufacturing process, such as binary intensity masks (BIM), phase shift masks (PSM), RIM-type PSM, high transmission masks (HTM), a combination of PSM and HTM, and double-sided anti-reflective masks (DAR), to name a few.

[0071] FIG. 13 shows the structure and strength of a PSM mask, and FIG. 14 shows a comparison between the intensity profiles of various PSM masks. In some embodiments, PSM masks can be used in FPD manufacturing processes to improve process windows and resolution. Without being bound by theory, a higher quality intensity profile can be obtained by a 180 degree phase shift through a phase material, as shown in FIG. 13. In some embodiments, the PSM mask is processed to the low intensity mask optimization discussed herein, and the improved intensity profile and higher contrast of such a mask can further enhance the overall process. As an example, FIG. 14 shows simulation results for various mask types, showing that the intensity profile of PSM has better contrast and profile characteristics compared to BIM. Intensity profile 510 corresponds to a BIM mask, intensity profiles 520-560 correspond to PSM masks in the 5%-50% transmission range, and intensity profile 570 corresponds to a contact mask.

[0072] In some embodiments, dose minimization can be used to apply feature bias to binary type masks at 1.5 μm design rules to achieve 10-30% improvements in FPD manufacturing. In some embodiments, high contrast masks such as PSM masks achieve 30% or more gains in productivity.

[0073] Figure 15 is a table showing the productivity gain in percentage for a 1.5 μm line space pattern with low intensity mask bias and dose variation according to an exemplary embodiment of the present invention, and Figure 16 is a table showing the productivity gain in percentage for a 1.8 μm contact hole pattern with low intensity mask bias and dose variation according to an exemplary embodiment of the present invention. The tables in Figures 15 and 16 show that various redesign optimizations according to the exemplary embodiments result in significant improvements in the process flow.

[0074] In some embodiments, to address the issue of obtaining consistent results using the dose minimization process described herein, especially when applied across an FPD design layout consisting of patterns with various designs and design rules, a mask rule checker tool can be used to verify rule checks and a pattern matching tool can be used to find critical patterns. In some embodiments, an FPD OPC model can be applied to remove possible data errors across the field FPD area.

[0075] Although the foregoing specification provides a detailed description of particular embodiments of the invention, it should be understood that many of the details described herein may be significantly modified by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. 1. A method for manufacturing a photomask, comprising: (A) receiving initial photomask design data relating to one or more patterns to be formed on a photomask; (B) optimizing the initial photomask design data to minimize printing exposure energy while maintaining acceptable pattern quality and size, 1. Setting the minimization of printing exposure energy as a priority design rule; 2. Setting pattern quality and size optimization as secondary design rules; 3. Iteratively sizing mask design features to determine a range of size biases that satisfy both the priority design rules and the secondary design rules to provide an initial optimized mask design; and 4. Adjusting mask variations across the range of size bias to determine mask variations that further optimize the initial optimized mask design to obtain a final optimized mask design. an optimizing step, comprising: (C) generating optimized photomask design data based on the final optimized mask design. The method includes:

2. The method of claim 1 , wherein the range of size bias includes a negative size bias.

3. The method of claim 1 , wherein the range of size bias includes a positive size bias.

4. The method of claim 1 , wherein the mask deformation comprises a pattern edge compensation deformation.

5. The method of claim 1 , wherein the mask deformation comprises a mask structure deformation.

6. The method of claim 1 , wherein the mask variations include scanner illumination shape variations.

7. The method of claim 1 , wherein the mask modifications include pattern edge compensation modifications, mask structure modifications, scanner illumination shape modifications, and combinations thereof.

8. The method of claim 1 , further comprising performing optical proximity correction on the optimized photomask design data.

9. The method of claim 1 , further comprising providing a mask blank.

10. 10. The method of claim 9, further comprising processing the mask blank using the optimized photomask design data to form a photomask for use in a lithography process.

11. 11. The method of claim 10, wherein the photomask is a large photomask for use in a lithography process to manufacture flat panel displays (FPDs).

12. 13. A method for forming a flat panel display, comprising the steps of irradiating a glass plate substrate with light from an optical energy source through a large photomask formed according to the method of claim 11 in a photolithography process, wherein at least one circuit pattern is transferred from the large photomask to the glass plate substrate.

13. 13. The method of claim 12, wherein the flat panel display is a liquid crystal display, an active matrix liquid crystal display, an organic light emitting diode, a light emitting diode, a plasma display panel, or an active matrix organic light emitting diode.

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