Technique for high aspect ratio carbon etching using an inserted charge dissipation layer
By introducing a conductive layer between the nitride graphite layer and the insulating layer, the distortion problem caused by the high-profile charge accumulation in the nitride graphite layer is solved, and a higher linearity and accuracy of the structure is achieved.
Patent Information
- Application Number
- JP2024554676
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2022-03-28
- Filing Date
- 2023-03-24
- Publication Date
- 2025-04-15
AI Technical Summary
The problem of conical distortion of the high-level semiconductor structure in the graphite nitride is mainly due to the distortion caused by the accumulation of charge in the high-level semiconductor structure.
A conductive layer is introduced between the graphite nitride layer and the insulating layer, and the conductive layer material has a lower resistance than the graphite nitride layer so that in a high aspect, the charge accumulated in the structure can be circulated through the conductive layer, thereby reducing distortion.
By introducing a conductive layer, the distortion caused by charge accumulation in the high-sided structure in the graphite nitride layer is effectively reduced, and the linearity and accuracy of the structure are improved.
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Abstract
Description
[Technical field]
[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of priority and the filing date of U.S. Non-provisional Patent Application No. 17 / 706,408, filed March 28, 2022, the entirety of which is incorporated herein by reference.
[0002] The present disclosure relates to high aspect ratio semiconductor structures and methodologies for fabricating high aspect ratio semiconductor structures, and more particularly, to high aspect ratio amorphous carbon layers and related fabrication techniques. [Background technology]
[0003] High aspect ratio semiconductor structures include relatively deep and narrow features with a large ratio of depth to width. For example, certain high aspect ratio structures, such as high aspect vias, may have aspect ratios of 50:1 or more. These high aspect ratio features may be included in semiconductor devices such as three-dimensional (3D) NAND flash memory. A typical 3D NAND memory includes multiple layers (e.g., 32, 64, or 128 layers) of memory cells stacked on top of each other, which dramatically increases the storage capacity of the memory device for the same 2D footprint.
[0004] Amorphous carbon layers (ACLs) can be used as hardmask materials for certain materials due to their good etch selectivity to dielectrics such as oxides or nitrides used in 3D NAND memories. However, under some conditions, high aspect ratio features etched into the ACL may exhibit distortion, such as twisting, due to charge accumulation in the ACL. Summary of the Invention
[0005] According to one aspect of the present disclosure, a semiconductor device structure includes a dielectric layer formed on a silicon substrate, an amorphous carbon layer formed on the dielectric layer, and a charge dissipation layer formed between the amorphous carbon layer and the dielectric layer, the charge dissipation layer comprising a material having a resistivity lower than that of the amorphous carbon layer. In one embodiment, the charge dissipation layer is formed directly on the dielectric layer.
[0006] In one embodiment, the amorphous carbon layer comprises a second amorphous carbon layer, and the semiconductor device structure further comprises a first amorphous carbon layer formed between the charge dissipation layer and the dielectric layer, In one embodiment, the second thickness of the second amorphous carbon layer is greater than the first thickness of the first amorphous carbon layer.
[0007] In one embodiment, the charge dissipation layer comprises a silicon-containing material, hi one embodiment, the silicon-containing material comprises amorphous silicon, polysilicon, single crystal silicon, or doped silicon.
[0008] In one embodiment, the charge dissipation layer comprises a metallic material, hi one embodiment, the metallic material comprises tungsten, titanium, tantalum, ruthenium, or aluminum.
[0009] In one embodiment, a portion of the charge dissipation layer is bonded to the silicon substrate at an edge of the semiconductor device structure, hi one embodiment, the amorphous carbon layer has a thickness between about 2500 nanometers and about 3500 nanometers, and the charge dissipation layer has a thickness of about 50 nanometers.
[0010] In one embodiment, the dielectric layers comprise a 3D NAND memory stack, hi one embodiment, the 3D NAND memory stack includes alternating oxide and nitride layers.
[0011] According to another aspect, a method for manufacturing a semiconductor device includes forming a dielectric layer on a silicon substrate, forming a charge dissipation layer on the dielectric layer, and forming an amorphous carbon layer on the charge dissipation layer, the charge dissipation layer comprising a material having a resistivity lower than a resistivity of the amorphous carbon layer.
[0012] In one embodiment, the method further includes forming a mask layer on the amorphous carbon layer and etching a high aspect ratio feature through the amorphous carbon layer, the charge dissipation layer, and the dielectric layer using the mask layer. In one embodiment, the amorphous carbon layer has a thickness of about 2500 nanometers to about 3500 nanometers and the charge dissipation layer has a thickness of about 50 nanometers prior to etching the high aspect ratio feature through the amorphous carbon layer. In one embodiment, the high aspect ratio feature comprises a hole having a diameter of about 70 nanometers. In one embodiment, the high aspect ratio feature comprises a slot having a width of about 150 nanometers.
[0013] In one embodiment, forming the charge dissipation layer includes forming an electrical interface between the charge dissipation layer and a portion of the silicon substrate. In one embodiment, forming the electrical interface includes forming a sidewall of the charge dissipation layer along a sidewall of the dielectric layer. Forming the amorphous carbon layer includes forming a sidewall of the amorphous carbon layer overlying a sidewall of the charge dissipation layer that does not contact the silicon substrate.
[0014] In one embodiment, the amorphous carbon layer includes a second amorphous carbon layer, and the method further includes forming a first amorphous carbon layer on the dielectric layer prior to forming the charge dissipation layer. Forming the charge dissipation layer on the dielectric further includes forming the charge dissipation layer on the first amorphous carbon layer, and the first thickness of the first amorphous carbon layer is less than the second thickness of the second amorphous carbon layer.
[0015] In one embodiment, the charge dissipation layer comprises a silicon-containing material, hi one embodiment, the silicon-containing material comprises amorphous silicon, polysilicon, single crystal silicon, or doped silicon.
[0016] In one embodiment, the charge dissipation layer comprises a metallic material, hi one embodiment, the metallic material comprises tungsten, titanium, tantalum, ruthenium, or aluminum.
[0017] In one embodiment, forming the charge dissipation layer includes bonding the charge dissipation layer to the silicon substrate at an edge of the silicon substrate. In one embodiment, the first amorphous carbon layer includes walls surrounding the dielectric layer and grounded to the silicon substrate at an electrical interface, and the charge dissipation layer includes walls surrounding the walls of the first amorphous carbon layer and grounded to the silicon substrate at an electrical interface. In one embodiment, the second amorphous carbon layer does not contact the silicon substrate.
[0018] In one embodiment, the dielectric layers comprise a 3D NAND memory stack, hi one embodiment, the 3D NAND memory stack includes alternating oxide and nitride layers.
[0019] According to another aspect, a semiconductor device structure includes a silicon substrate including a first surface extending to a wafer edge, a dielectric layer formed on the first surface of the silicon substrate, and a charge dissipation layer formed on the dielectric layer. The charge dissipation layer includes a wall surrounding the dielectric layer, the wall being coupled to the silicon substrate between the wafer edge and the dielectric layer, the charge dissipation layer having a thickness of about 50 nanometers. The semiconductor device structure further includes an amorphous carbon layer formed on the charge dissipation layer. The amorphous carbon layer has a thickness of about 2500 nanometers to 3500 nanometers, and the charge dissipation layer includes a material having a resistivity lower than that of the amorphous carbon layer.
[0020] In one embodiment, the amorphous carbon layer includes a second amorphous carbon layer, and the semiconductor device further includes a first amorphous carbon layer formed between the charge dissipation layer and the dielectric layer, the first amorphous carbon layer having a thickness less than a thickness of the second amorphous carbon layer. [Brief description of the drawings]
[0021] The concepts described herein are illustrated by way of example, and not by way of limitation, in the accompanying figures. For simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. Where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.
[0022] [Figure 1] FIG. 1 illustrates a cross-sectional elevation view of at least one embodiment of a semiconductor device that includes a charge dissipation layer disposed below an amorphous carbon layer (ACL). [Diagram 2] 1 is a cross-sectional elevation view of another embodiment of a semiconductor device including a charge dissipation layer disposed within an amorphous carbon layer (ACL) toward a bottom of the ACL. [Diagram 3] 3 is a simplified flowchart of at least one embodiment of a method for manufacturing the semiconductor device of FIGS. 1 and 2. [Figure 4] 4 is a cross-sectional elevation view of at least one embodiment of a semiconductor device formed during the method of FIG. 3 and having a dielectric formed on a substrate. [Diagram 5] 5 is a cross-sectional elevation view of at least one embodiment of the semiconductor device of FIG. 4 after forming a charge dissipation layer on the dielectric during the method of FIG. 3. [Figure 6] 6 is a cross-sectional elevation view of at least one embodiment of the semiconductor device of FIG. 5 after forming an ACL hard mask over the charge dissipation layer during the method of FIG. 3. [Figure 7] 7 is a cross-sectional elevation detail view of at least one embodiment of the semiconductor device of FIG. 6. [Figure 8]7 is a cross-sectional elevation view of at least one embodiment of the semiconductor device of FIG. 6 after forming a mask layer during the method of FIG. 3. [Figure 9] 9 is a cross-sectional elevation view of at least one embodiment of the semiconductor device of FIG. 8 after etching a mask layer during the method of FIG. 3. [Figure 10] 10 is a cross-sectional elevation view of at least one embodiment of the semiconductor device of FIG. 9 after etching the ACL during the method of FIG. 3. [Figure 11] 11 is a cross-sectional elevation view of at least one embodiment of the semiconductor device of FIG. 10 after etching a dielectric during the method of FIG. 3. [Figure 12] 5 is a cross-sectional elevation view of another embodiment of the semiconductor device of FIG. 4 after forming an ACL hard mask on the dielectric during the method of FIG. 3. [Figure 13] 13 is a cross-sectional elevation view of at least one embodiment of the semiconductor device of FIG. 12 after forming a charge dissipation layer on the ACL during the method of FIG. 3. [Figure 14] 14 is a cross-sectional elevation view of at least one embodiment of the semiconductor device of FIG. 13 after forming an ACL hard mask over the charge dissipation layer during the method of FIG. 3. [Figure 15] FIG. 15 is a cross-sectional elevation detail view of at least one embodiment of the semiconductor device of FIG. 14. [Figure 16] 15 is a cross-sectional elevation view of at least one embodiment of the semiconductor device of FIG. 14 after forming a mask layer during the method of FIG. 3. [Figure 17] 17 is a cross-sectional elevation view of at least one embodiment of the semiconductor device of FIG. 16 after etching a mask layer during the method of FIG. 3. [Figure 18] 18 is a cross-sectional elevation view of at least one embodiment of the semiconductor device of FIG. 17 after etching the ACL during the method of FIG. 3. [Figure 19] 19 is a cross-sectional elevation view of at least one embodiment of the semiconductor device of FIG. 18 after etching a dielectric during the method of FIG. 3. [Figure 20]1 is a cross-sectional elevation view of a typical semiconductor device after etching an ACL hardmask. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0023] While the concepts of the present disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail, It should be understood, however, that there is no intention to limit the concepts of the present disclosure to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives consistent with the scope of the disclosure and the appended claims.
[0024] References herein to "one embodiment," "one embodiment," "exemplary embodiment," and the like indicate that the described embodiment may include a particular feature, structure, or characteristic, but not all embodiments necessarily include that particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in relation to an embodiment, it is submitted that it is within the knowledge of one of ordinary skill in the art to affect such feature, structure, or characteristic in relation to other embodiments, whether or not explicitly described. In addition, it should be understood that an item in a list in the format "at least one of A, B, and C" may mean (A);(B);(C):(A and B);(B and C); or (A, B, and C). Similarly, an item in the format "at least one of A, B, and C" may mean (A);(B);(C):(A and B);(B and C); or (A, B, and C).
[0025] The disclosed embodiments may, in some cases, be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried by or stored on a transitory or non-transitory machine-readable (e.g., computer-readable) storage medium, which may be read and executed by one or more processors. A machine-readable storage medium may be embodied as any storage device, mechanism, or other physical structure (e.g., a volatile or non-volatile memory, media disk, or other media device) for storing or transmitting information in a machine-readable form.
[0026] In the figures, some structural or method features may be shown in a particular arrangement and / or order. However, it should be understood that such a particular arrangement and / or order may not be required. Rather, in some embodiments, such features may be arranged in a different manner and / or order than as shown in the example figures. Additionally, the inclusion of structural or method features in a particular figure is not meant to imply that such features are required in all embodiments, and in some embodiments, they may not be included or may be combined with other features.
[0027] As first described above with reference to FIG. 20, an amorphous carbon layer (ACL) may be used as a hard mask material for etching certain semiconductor devices. For example, as shown in FIG. 20, a typical semiconductor device includes a dielectric 2004 formed on a substrate 2002, an ACL hard mask 2006 formed on the dielectric 2004, and a mask layer 2008 formed on the ACL 2006. The dielectric 2004 may be a monolithic layer, such as an oxide, or multiple layers of dielectrics, such as oxides and nitrides, included in a NAND memory array stack. The mask layer 2008 may include photoresist and other typical mask materials. As shown, a feature 2010 is formed in the mask layer 2008, and the feature is etched into the ACL 2006. However, as shown in FIG. 20, the etched feature 2010 is distorted in the ACL 2006. In particular, the feature 2010 is twisted, meaning that the interior walls 2012 of the feature 2010 are curved away from vertical. In a typical hard ACL 2006, twisting may begin at a depth of about 1.5 μm. In certain circumstances, twisting may be reduced by increasing the ionization energy of the plasma used for etching by applying a pulsed bias. However, increasing the ionization energy to reduce twisting may increase other types of distortion, such as bowing. Thus, in a typical semiconductor manufacturing process, a tradeoff may need to be made between the various types of distortion.
[0028] 1, a semiconductor device 100 fabricated in accordance with the techniques disclosed herein is shown. The semiconductor device 100 includes a dielectric 104 formed on a silicon substrate 102. A charge dissipation layer 106 is formed on the dielectric 104, and an amorphous carbon layer (ACL) 108 is formed on the charge dissipation layer 106. A plurality of high aspect ratio features 110 are defined through the ACL 108, the charge dissipation layer 106, and the dielectric 104. The high aspect ratio features 110 may be embodied as holes, trenches, slits, or other features having a relatively large depth to width ratio. As described further below, the high aspect ratio features 110 of the semiconductor device 100 may include reduced distortion (e.g., straight sides) compared to high aspect ratio features formed in a typical semiconductor device, such as device 2000. Additionally, because device structure 100 includes an ACL 108 on top of dielectric 104 similar to device structure 2000, device structure 100 may be compatible with similar processes as exemplary device structure 2000 and may be used to manufacture similar devices.
[0029] The silicon substrate 102 may be embodied as any type of silicon substrate on which the dielectric layer 104 and other semiconductor device components may be formed. The dielectric 104 may be embodied as a monolithic dielectric component, such as an oxide, or as a stack of components, such as alternating oxide and nitride layers. For example, in some embodiments, the dielectric layer 104 may be embodied as an oxide-nitride-oxide-nitride (ONON) stack used to fabricate 3D NAND flash memory devices. The dielectric layer 104 may have a thickness of, for example, about 6 micrometers to 12 micrometers. As another example, in some embodiments, the dielectric layer 104 may have a thickness of about 45 micrometers. It should be understood that the illustrated architecture of the semiconductor device 100 of FIG. 1 is a simplified and abstracted illustration of the associated device, and that other embodiments, depending on the type and complexity of the device 100, may include additional or different architectures, layers, devices, portions, and / or structures not shown in the associated figures for clarity of the drawings.
[0030] The ACL 108 may be embodied as a layer of relatively hard amorphous carbon that may function as a hard mask for the device 100, as described further below. For example, the ACL 108 may have a density of, for example, about 1.6-2.2 g / cm 3 The ACL 108 may be an amorphous carbon-hydrogen alloy having a relatively high density from about 10 to 20 GPa and a relatively high hardness from about 10 to 20 GPa. Exemplarily, the ACL 108 may be embodied as an Advanced Patterning Film (APF) commercially available from Applied Materials, Inc. of Santa Clara, California.
[0031] The charge dissipation layer 106 may be embodied as a material layer having a resistivity lower than that of the ACL 108. In some embodiments, the charge dissipation layer 106 may be embodied as a silicon-containing material, such as amorphous silicon (a-Si), polysilicon (p-Si), or single crystal silicon. Additionally, in some embodiments, the silicon-containing material may be doped with one or more other elements to reduce resistivity. Furthermore, in some embodiments, the charge dissipation layer 106 may be embodied as a metallic material, such as aluminum, titanium, tungsten, tantalum, and / or ruthenium. In some embodiments, the charge dissipation layer 106 may be embodied as tungsten silicide (WSi) or other relatively conductive ceramic materials.
[0032] As shown in FIG. 1, device 100 includes a plurality of high aspect ratio (HAR) features 110. Each of the features has a relatively high ratio of depth to width or other opening size. For example, in some embodiments, each of features 110 may be a contact hole having a diameter of about 50-80 nanometers, or a slot having a width of about 150 nanometers. As mentioned above, in exemplary embodiments, dielectric layer 104 has a thickness of 6-12 micrometers (i.e., 6000-12000 nm). Thus, in those embodiments, features 110 may have an aspect ratio of about 75:1-150:1. HAR features 110 may be used to form individual memory cell transistors, gates, vias, or other semiconductor device features for, for example, 3D NAND memory devices.
[0033] Additionally, although various layers of device structure 100 have been described as being formed "on" another layer of device structure 100, it should be understood that such layers of device structure 100 (and other device structures described herein) may be formed directly on top of the other layer or may have one or more other intervening layers (e.g., an insulator layer) between the two described layers. For example, although charge dissipation layer 106 has been described as being formed on dielectric layer 104, semiconductor device structure 100 may include one or more layers (e.g., a mask layer or an insulator layer) between the corresponding charge dissipation layer and the dielectric layer.
[0034] 2, another embodiment of a semiconductor device 200 is shown. The exemplary semiconductor device 200 includes a silicon substrate 102, a dielectric 104, and another ACL 112 formed on the dielectric layer 104. A charge dissipation layer 106 is formed on the ACL 112, and an ACL 108 is formed on the charge dissipation layer 106. The combined thickness of the ACL 108, charge dissipation layer 106, and ACL 112 is similar to the combined thickness of the ACL 108 and charge dissipation layer 106 shown in FIG. 1. As will be described further below, similar to the device 100 shown in FIG. 1, the device 200 may include high aspect ratio features 110 with reduced distortion compared to typical devices.
[0035] 3, in some embodiments, a method 300 may be performed to fabricate silicon device structures 100, 200. It should be understood that not all fabrication steps may be described below, but one of ordinary skill in the art would understand that additional, related and unrelated steps (e.g., various cleaning steps) may be performed throughout the method 300. The method 300 begins at block 202, where a dielectric layer 104 is formed on a silicon substrate 102, as shown in FIG. 4. It should be understood that at this stage of the method 300, the silicon substrate 102 may have a substantially greater thickness than at later stages of the method 300 in order to provide physical support for the devices 100, 200.
[0036] Referring back to block 302 of FIG. 3, any suitable fabrication process may be used to form the dielectric layer 104. For example, in some embodiments at block 304, the dielectric layer 104 may be formed as an ONON patterned stack. In those embodiments, the dielectric layer 104 may be formed by alternately depositing conductive and insulating layers, such as silicon oxide and silicon nitride, on the silicon substrate 102 (e.g., to form an “ONON” patterned stack). The silicon oxide and silicon nitride layers may be formed on the silicon substrate 102 using any suitable deposition, growth, or formation technique, such as chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD). Additionally or alternatively, in other embodiments, the dielectric layer 104 may be formed by alternately depositing layers of silicon oxide and polysilicon on the silicon substrate 102 (e.g., to form an “OPOP” patterned stack). In some embodiments, at block 306, the dielectric layer 104 may be formed as a monolithic oxide component, such as a monolithic layer of silicon oxide.
[0037] After the initial dielectric layer 104 is formed in block 302, in some embodiments, the method 300 may proceed to block 308, where a relatively thin amorphous carbon layer (ACL) 112 is formed on the dielectric layer 104, as shown in Figure 12. The ACL 112 has a thickness 1202, which is relatively thin compared to the corresponding thickness of the ACL 108 formed on the charge dissipation layer 106, as described further below.
[0038] 3, after forming the dielectric layer 104, and in some embodiments, after forming the ACL 112, the method 300 proceeds to block 310, where the charge dissipation layer 106 is formed. For example, as shown in FIG. 5, in some embodiments, the charge dissipation layer 106 may be formed directly on the dielectric layer 104 of the device 100. As another example, as shown in FIG. 13, in some embodiments, the charge dissipation layer 106 may be formed directly on the ACL 112 of the device 200. The charge dissipation layer 106 is relatively thin compared to the dielectric layer 104. For example, in some embodiments, the charge dissipation layer 106 may have a thickness of about 50 nanometers. In other embodiments, the charge dissipation layer 106 may have a thickness of up to a few micrometers (e.g., less than 3 micrometers). The charge dissipation layer 106 is configured to be capable of conducting charge away from the ACL 108.
[0039] As discussed above, the charge dissipation layer 106 may be formed from a material having a lower resistivity than the ACL 108. The charge dissipation layer 106 may be formed using any suitable deposition, growth, sputtering, or formation technique, such as a chemical vapor deposition (CVD) technique or a plasma enhanced chemical vapor deposition (PECVD) technique. In some embodiments, at block 312, the charge dissipation layer 106 may be formed from a metal-containing material, such as a material including aluminum, titanium, tungsten, tantalum, and / or ruthenium. In some embodiments, at block 314, the charge dissipation layer 106 may be formed from a silicon-containing material, such as amorphous silicon, polysilicon, single crystal silicon, or doped silicon.
[0040] Referring again to FIG. 3, after forming the charge dissipation layer 106, in block 316, the ACL 108 hard mask layer is formed. As described above, the ACL 108 is formed from a hard amorphous carbon material. The material of the ACL 108 has good etch selectivity with respect to the dielectric layer 104. After formation, the ACL 108 may have a thickness of several micrometers. In one embodiment, the ACL 108 may have a thickness of about 2.5 micrometers to 3.5 micrometers (i.e., about 2500 nm to 3500 nm). Thus, after formation, the charge dissipation layer 106 is disposed toward the bottom surface of the ACL 108, i.e., closer to the dielectric layer 104 than the top surface of the ACL 108. For example, as shown in FIG. 6, in some embodiments, the ACL 108 is formed directly on the charge dissipation layer 106 of the device 100. As another example, as shown in FIG. 14, in some embodiments, the ACL 108 is formed on the charge dissipation layer 106 that is formed on the ACL 112 of the device 200. In those embodiments, the first ACL 112 may be formed on the dielectric layer 104, the charge dissipation layer 106 may be formed on the first ACL 112, and the second ACL 108 may be formed on the charge dissipation layer 106. As shown in FIG. 14, the ACL 108 has a thickness 1402 that is greater than the thickness 1202 of the ACL 112. For example, the thickness 1402 may be about 2500 nm to 3500 nm, and the thickness 1202 may be much smaller (e.g., a few hundred nm). Thus, the charge dissipation layer 106 of the device 200 is also disposed toward the bottom of the ACLs 108, 112. As mentioned above, in some embodiments, the combined thickness of the ACL 108 and charge dissipation layer 106 of device 100 may be the same or approximately the same as the combined thickness of the ACL 108, charge dissipation layer 106, and ACL 112 of device 200. Additionally or alternatively, although shown in Figures 6 and 14 as including a single charge dissipation layer 106, it should be understood that in some embodiments, a similar device may include multiple charge dissipation layers 106 separated by additional ACLs 112.
[0041] As mentioned above, the charge dissipation layer 106 may be coupled to the silicon substrate 102 at the wafer edge or may be otherwise grounded to provide a destination for the charge. For example, a detailed view of the wafer edge of the device 100 is shown in FIG. 7. As shown in FIG. 7, the charge dissipation layer 106 includes a sidewall 114 that surrounds the dielectric layer 104. The sidewall 114 contacts the silicon substrate 102 at an electrical interface 116. As shown, the interface 116 is disposed between the dielectric layer 104 and the wafer edge 118 of the silicon substrate 102. Similarly, the ACL 108 includes a sidewall 120 that surrounds the sidewall 114 of the charge dissipation layer 106. Illustratively, the ACL 108 overlies the charge dissipation layer 106 but does not contact the silicon substrate 102.
[0042] As another example, a detailed view of the wafer edge of device 200 is shown in Figure 15. The exemplary ACL 112 includes a sidewall 122 that surrounds the dielectric layer 104. The charge dissipation layer 106 includes a sidewall 114 that surrounds the sidewall 122 of the ACL 112, as does the dielectric layer 104. The sidewall 114 of the charge dissipation layer 106 also contacts the silicon substrate 102 at an electrical interface 116 between the wafer edge 118 and the dielectric layer 104. As shown in Figure 15, the exemplary ACL 108 overlies the charge dissipation layer 106 but does not contact the silicon substrate 102.
[0043] Referring back to FIG. 3, after forming the ACL 108, the remainder of the device stack is formed in block 318. The remainder of the stack may include, for example, one or more mask layers or other patterning features for photolithography. For example, the full stack of device 100 is shown in FIG. 8 and the full stack of device 200 is shown in FIG. 16. In block 320, a silicon oxynitride (SiON) layer 802 is formed. The SiON layer 802 may have a thickness of about 135 nanometers to about 400 nanometers. In an exemplary embodiment, the SiON layer 802 has a thickness of 300 nanometers. In block 322, an optical dispersion layer (ODL) 804 may be formed. The ODL 804 may be formed from a soft carbon material and may have a thickness of about 200 nanometers to about 400 nanometers. In an exemplary embodiment, the ODL 804 has a thickness of 400 nanometers. In block 324, a silicon anti-reflective coating (SiARC) layer 806 may be formed. The SiARC layer 806 may have a thickness of about 30 nanometers to 35 nanometers. At block 326, a photoresist (PR) layer 808 may be formed. The PR layer 808 may have a thickness of about 15 nanometers to 80 nanometers. In an exemplary embodiment, the PR layer 808 has a thickness of 50 nanometers.
[0044] At block 328, the mask layer is patterned with one or more features 110. As discussed above, the features 110 may be embodied as high aspect ratio features, such as holes or slots. After patterning, a portion of the ACL 108 disposed within the features 110 is exposed for etching. For example, as shown in FIG. 9 and FIG. 17, after patterning, the features 110 are defined through the PR layer 808, the SiARC layer 806, the ODL 804, and the SiON layer 802.
[0045] Referring back to FIG. 3, after patterning the mask, a high aspect ratio etch of the patterned feature 110 is performed in block 330. The feature 110 may be etched, for example, by plasma etching the device 100, 200 in an inductively coupled plasma (ICP) chamber. In block 332, a carbon etch of the ACL hard mask is performed. For example, the carbon etch may be performed using a carbon etch chemistry that includes oxygen and sulfur (e.g., O2, SO2, or COS). Etching the hard mask may remove the ACL 108, the charge dissipation layer 106, and portions of the ACL 112 (if present) that are revealed in the feature 110. Depending on the material bond energy, ion energy, and chemistry, in some embodiments, the charge dissipation layer 106 may not be opened during the carbon etch. In such embodiments, an additional etch step with an etch chemistry that includes CF species or halogen species may be required to remove the charge dissipation layer 106. Additionally or alternatively, in some embodiments, additives such as CF or halogens may be added at certain stages of the carbon etch to open up the charge dissipation layer. During the etch, excess charge transferred to the ACL 108 by ions associated with the plasma etch process may be conducted away from the feature 110 by the charge dissipation layer 106. Furthermore, unlike the ACL 108, the charge dissipation layer 106 may not accumulate charge on its sidewalls, so that ions descending into the feature 110 will not bend laterally, reducing twisting. Thus, by reducing the charging of the ACL 108, twisting and other distortions of the feature 110 may also be reduced. This reduction in twisting distortion may be achieved without increasing the ionization energy and therefore without increasing bowing or other distortions. After the carbon etch, a portion of the dielectric layer 104 within the feature 110 is exposed for etching. For example, as shown in FIG. 10, after carbon etching of device 100, feature 110 is defined through PR layer 808, SiARC layer 806, ODL 804, SiON layer 802, ACL 108, and charge dissipation layer 106.As another example, as shown in FIG. 18, after carbon etching of device 200, feature 110 is defined through PR layer 808, SiARC layer 806, ODL 804, SiON layer 802, ACL 108, charge dissipation layer 106, and ACL 112.
[0046] Referring back to FIG. 3, after performing the carbon etch, in block 334, a dielectric etch of the dielectric layer 104 is performed. Etching the dielectric layer 104 removes the portion of the dielectric layer 104 that is exposed in the feature 110. Etching the dielectric layer 104 also includes removing the mask layers (e.g., the PR layer 808, the SiARC layer 806, the ODL 804, and the SiON layer 802) and portions of the ACL hard mask layer 108. For example, FIG. 11 shows the device 100 after the dielectric etch, and FIG. 19 shows the device 200 after the dielectric etch. As shown, after the dielectric etch, the feature 110 is defined through the ACL 108, the charge dissipation layer 106, the ACL 112 (if present), and the dielectric layer 104. In some embodiments, the remaining ACL 108, 122 may be removed by O2 ashing, and the remaining charge dissipation layer 106 may be removed by wet cleaning with an appropriate chemistry.
[0047] After performing the dielectric etch, method 300 is complete. After completing the high aspect ratio etch, device 100, 200 may be subjected to further processing steps to fabricate a completed semiconductor device, such as a 3D NAND memory device. Again, it should be understood that blocks 302-334 described above are exemplary process steps for forming device 100, 200, and that in other embodiments, additional or different process steps may be used and / or blocks 302-334 described above may be performed in a different sequential order.
[0048] While the present disclosure has been illustrated and described in detail in the drawings and foregoing description, it is to be understood that such illustration and description are to be considered as illustrative and not restrictive in character, that only exemplary embodiments have been shown and described, and that all changes and modifications which come within the spirit of the disclosure are desired to be protected.
[0049] There are several advantages of the present disclosure that arise from the various features of the methods, devices, and systems described herein. It should be noted that alternative embodiments of the methods, devices, and / or systems of the present disclosure may not include all of the features described, but may still benefit from at least some of the advantages of such features. Those skilled in the art may readily devise their own implementations of the methods, devices, and systems that incorporate one or more of the features of the present invention and fall within the spirit and scope of the present disclosure as defined by the appended claims.
Claims
1. 1. A semiconductor device structure comprising: a dielectric layer formed on a silicon substrate; an amorphous carbon layer formed on the dielectric layer; a charge dissipation layer formed between the amorphous carbon layer and the dielectric layer, the charge dissipation layer comprising a material having a resistivity lower than a resistivity of the amorphous carbon layer.
2. The semiconductor device structure of claim 1 , wherein the charge dissipation layer is formed directly on the dielectric layer.
3. the amorphous carbon layer comprises a second amorphous carbon layer; 2. The semiconductor device structure of claim 1, further comprising a first amorphous carbon layer formed between the charge dissipation layer and the dielectric layer, a second thickness of the second amorphous carbon layer being greater than a first thickness of the first amorphous carbon layer.
4. The semiconductor device structure of claim 1 , wherein the charge dissipation layer comprises a silicon-containing material.
5. 5. The semiconductor device structure of claim 4, wherein the silicon-containing material comprises amorphous silicon, polysilicon, single crystal silicon, or doped silicon.
6. The semiconductor device structure of claim 1 , wherein the charge dissipation layer comprises a metallic material.
7. The semiconductor device structure of claim 6 , wherein the metallic material comprises tungsten, titanium, tantalum, ruthenium, or aluminum.
8. The semiconductor device structure of claim 1 , wherein a portion of the charge dissipation layer is coupled to the silicon substrate at an edge of the semiconductor device structure.
9. the amorphous carbon layer has a thickness of about 2500 nanometers to about 3500 nanometers; 10. The semiconductor device structure of claim 1, wherein the charge dissipation layer has a thickness of about 50 nanometers.
10. The semiconductor device structure of claim 1 , wherein the dielectric layers form a 3D NAND memory stack.
11. 1. A method for manufacturing a semiconductor device, comprising: forming a dielectric layer on a silicon substrate; forming a charge dissipation layer over the dielectric layer; forming an amorphous carbon layer on the charge dissipation layer, the charge dissipation layer comprising a material having a resistivity lower than a resistivity of the amorphous carbon layer.
12. forming a mask layer on the amorphous carbon layer; and etching high aspect ratio features through the amorphous carbon layer, the charge dissipation layer, and the dielectric layer using the mask layer; the amorphous carbon layer has a thickness of about 2500 nanometers to about 3500 nanometers, the charge dissipation layer has a thickness of about 50 nanometers; The method of claim 11 , wherein the high aspect ratio feature comprises a hole having a diameter of about 70 nanometers or a slot having a width of about 150 nanometers.
13. The method of claim 11 , wherein forming the charge dissipation layer comprises forming an electrical interface between the charge dissipation layer and a portion of the silicon substrate.
14. forming the electrical interface includes forming a sidewall of a charge dissipation layer along a sidewall of the dielectric layer; The method of claim 13 , wherein forming the amorphous carbon layer comprises forming sidewalls of the amorphous carbon layer overlapping sidewalls of the charge dissipation layer that do not contact the silicon substrate.
15. the amorphous carbon layer comprises a second amorphous carbon layer; the method further comprising forming a first amorphous carbon layer on the dielectric layer prior to forming the charge dissipation layer; forming the charge dissipation layer on the dielectric layer further comprises forming the charge dissipation layer on the first amorphous carbon layer; The method of claim 11 , wherein a first thickness of the first amorphous carbon layer is less than a second thickness of the second amorphous carbon layer.
16. The method of claim 15 , wherein forming the charge dissipation layer comprises bonding the charge dissipation layer to the silicon substrate at an edge of the silicon substrate.
17. the first amorphous carbon layer includes a wall surrounding the dielectric layer and grounded to the silicon substrate at an electrical interface; 17. The method of claim 16, wherein the charge dissipation layer includes a wall surrounding the wall of the first amorphous carbon layer and grounded to the silicon substrate at the electrical interface.
18. The method of claim 17 , wherein the second amorphous carbon layer does not contact the silicon substrate.
19. 1. A semiconductor device structure comprising: a silicon substrate including a first surface extending to an edge of the wafer; a dielectric layer formed on the first surface of the silicon substrate; a charge dissipation layer formed on the dielectric layer, the charge dissipation layer including a wall surrounding the dielectric layer, the wall being bonded to the silicon substrate between the wafer edge and the dielectric layer, the charge dissipation layer having a thickness of about 50 nanometers; an amorphous carbon layer formed on the charge dissipation layer, the amorphous carbon layer having a thickness of about 2500 nanometers to 3500 nanometers, the charge dissipation layer comprising a material having a resistivity lower than a resistivity of the amorphous carbon layer.
20. the amorphous carbon layer comprises a second amorphous carbon layer; 20. The semiconductor device structure of claim 19, further comprising a first amorphous carbon layer formed between the charge dissipation layer and the dielectric layer, the first amorphous carbon layer having a thickness less than a thickness of the second amorphous carbon layer.