MEMORY SYSTEM AND METHOD OF OPERATION THEREOF - Patent application

Abstract

The present disclosure provides a memory system and its operating method, which is related to the field of storage technology, for solving the problem of parity data buffering efficiency. The memory system includes a controller and a three-dimensional nonvolatile memory coupled together. The three-dimensional nonvolatile memory includes a three-dimensional memory array. The three-dimensional memory array includes a plurality of word lines and a plurality of pages coupled together. The controller is configured to: calculate received page data corresponding to a first word line in units of page data corresponding to one word line to obtain first RAID parity data, store the first RAID parity data in a parity buffer space, calculate received page data and i-th RAID parity data corresponding to an (i+1)th word line to obtain (i+1)th RAID parity data, store the (i+1)th RAID parity data in a parity buffer space, and overwrite the i-th RAID parity data with the (i+1)th RAID parity data, where i is a positive integer equal to or greater than 1.

Description

[Technical field]

[0001] The present disclosure relates to the field of storage technologies, and more particularly to memory systems and methods of operation thereof. [Background technology]

[0002] Redundant array of independent disks (RAID) technology is widely used in memory systems. RAID technology can be understood as a technology that combines multiple disk drives into one logical unit for the purpose of data redundancy processing and performance improvement to ensure the reliability of stored data. Summary of the Invention [Problem to be solved by the invention]

[0003] RAID technologies are classified into different levels based on different performance. In a RAID5 solution, a controller may generate RAID parity data based on valid data and store the RAID parity data on a disk. If a disk is damaged, the controller can restore the data in the damaged disk based on the current valid data and the corresponding RAID parity data. Currently, the RAID parity data calculated by a controller of a memory system is first stored in a buffer space of the controller. During storage, if the amount of RAID parity data exceeds the capacity of the buffer space, a swap operation may be used to share the limited capacity of the buffer space in a time-division manner. In other words, in the process of calculating RAID parity data and buffering the RAID parity data, it may be necessary to perform multiple swap operations or even wait for the swap operation to finish before the calculation can continue, which affects the write performance of the controller. [Means for solving the problem]

[0004] SUMMARY OF THE DISCLOSURE The embodiments of the present disclosure provide a memory system and a method of operating the same to solve the problem of low controller write performance.

[0005] In order to achieve the above objectives, the following technical measures are used in the embodiments of the present disclosure.

[0006] According to an embodiment, a memory system is provided, the memory system includes a controller and a three-dimensional non-volatile memory, the three-dimensional non-volatile memory includes a three-dimensional memory array, the three-dimensional memory array includes a plurality of word lines and a plurality of pages coupled together, the controller is coupled to the three-dimensional non-volatile memory, the controller is configured to calculate received page data corresponding to a first word line in units of page data corresponding to one word line to obtain redundant array RAID parity data of a first independent disk, store the first RAID parity data in a parity buffer space, calculate received page data corresponding to an (i+1)th word line and an i-th RAID parity data to obtain an (i+1)th RAID parity data, store the (i+1)th RAID parity data in a parity buffer space, and overwrite the i-th RAID parity data, where i is a positive integer equal to or greater than 1.

[0007] Generally, in the process of storing RAID parity data by the controller, if the amount of RAID parity data is greater than the capacity of the parity buffer space, it is necessary to use a swap operation to share the limited parity buffer space in a time-division manner. Since the RAID parity data in the embodiment of the present application is obtained by calculating the page data corresponding to one word line, the parity buffer space can be filled with the RAID parity data obtained by calculating the page data corresponding to one word line. Therefore, in the embodiment of the present application, the storage process of RAID parity data can reduce the storage load and reduce the number of swap operations performed by the controller, thereby improving the write performance of the controller.

[0008] In some embodiments, the controller is further configured to write the wth RAID parity data to the three dimensional non-volatile memory when the value of i is w-1, where w is the number of word lines corresponding to one fund.

[0009] The wth RAID parity data obtained after multiple calculations is written to the three-dimensional non-volatile memory, so that the number of writes in the controller and the three-dimensional non-volatile memory can be reduced, and the memory space required for storing the RAID parity data in the three-dimensional non-volatile memory can be reduced.

[0010] In some embodiments, the controller is further configured to configure a first memory space of the write buffer space for buffering the RAID parity data if the parity buffer space is insufficient.

[0011] Since the first memory space of the write buffer space is also used for buffering RAID parity data, the memory space required for the RAID parity data can be satisfied and there is no need to perform a swap operation, thereby realizing continuity of buffering the RAID parity data and improving the write performance of the controller.

[0012] In some embodiments, the controller is further configured to store pages of data corresponding to the first word line through the (i+1)th word line in a second memory space of the write buffer space.

[0013] The page data corresponding to the first word line and the (i+1)th word line may be stored in the three-dimensional nonvolatile memory by the host computer. The page data corresponding to each word line is first stored in the second memory space of the write buffer space, so that the host computer can read data from and write data to the three-dimensional nonvolatile memory at a high speed.

[0014] In some embodiments, the configuration priority of the second memory space of the write buffer space is higher than the configuration priority of the first memory space.

[0015] When the capacity of the second memory space required to store page data corresponding to multiple word lines is filled, the first memory space is then allocated to parity buffer space for buffering RAID parity data, so that storage of page data corresponding to multiple word lines can be ensured.

[0016] In some embodiments, the parity buffer space includes a parity data buffer space and a garbage collection buffer space, the parity data buffer space is used to buffer RAID parity data, the garbage collection buffer space is used to buffer garbage collection data, and the garbage collection data including the RAID parity data corresponds to data that needs to be collected in the page data.

[0017] Garbage collection buffer space is further allocated in the parity buffer space for buffering RAID parity data corresponding to the data that needs to be collected in the page data corresponding to multiple word lines. In this way, the memory occupied for garbage collection data in the three-dimensional non-volatile memory can be released.

[0018] In some embodiments, the controller is further configured to perform a swap operation after power-on.

[0019] Since the buffer space is initialized after the controller is powered on, the parity buffer space can be cleared to begin buffering the RAID parity data.

[0020] In some embodiments, the controller is further configured to continue performing calculation operations on the page data corresponding to the (i+1)th word line after calculation of the received page data corresponding to the i-th word line is completed.

[0021] The controller continuously performs operations such as waiting for and performing calculations, and stores the RAID parity data in the parity buffer space after the calculations are completed, without the need to perform swap operations, thereby realizing the continuity of buffering the RAID parity data and improving the write performance of the controller.

[0022] In some embodiments, the RAID parity data is obtained by performing an XOR operation on page data corresponding to one word line.

[0023] In some embodiments, the (i+1)th RAID parity data is used to verify page data corresponding to the first word line through the (i+1)th word line.

[0024] When there is corrupted page data in the page data corresponding to the first word line to the (i+1)th word line, the corrupted page data can be restored by using the (i+1)th RAID parity data.

[0025] According to another aspect, a method for operating a memory system is provided. The memory system includes a controller and a three-dimensional non-volatile memory, the three-dimensional non-volatile memory includes a three-dimensional memory array, the three-dimensional memory array includes a plurality of word lines and a plurality of pages coupled together, the controller is coupled to the three-dimensional non-volatile memory, the method includes: calculating received page data corresponding to a first word line in units of page data corresponding to one word line to obtain redundant array RAID parity data of a first independent disk, and storing the first RAID parity data in a parity buffer space; calculating received page data corresponding to an (i+1)th word line and an i-th RAID parity data to obtain an (i+1)th RAID parity data, and storing the (i+1)th RAID parity data in a parity buffer space, where the (i+1)th RAID parity data overwrites the i-th RAID parity data, and i is a positive integer equal to or greater than 1.

[0026] In some embodiments, the method further includes writing, by the controller, the wth RAID parity data to the three-dimensional non-volatile memory when the value of i is w-1, where w is the number of word lines corresponding to one fund.

[0027] In some embodiments, before storing the first RAID parity data in the parity buffer space, the method further includes setting, by the controller, a first memory space of the write buffer space for buffering the RAID parity data if the parity buffer space is insufficient.

[0028] In some embodiments, the method further includes storing, by the controller, pages of data corresponding to the first word line through pages of data corresponding to the (i+1)th word line in a second memory space of the write buffer space.

[0029] In some embodiments, the configuration priority of the second memory space of the write buffer space is higher than the configuration priority of the first memory space.

[0030] In some embodiments, the parity buffer space includes a parity data buffer space and a garbage collection buffer space, the parity data buffer space is used to buffer RAID parity data, the garbage collection buffer space is used to buffer garbage collection data, and the garbage collection data including the RAID parity data corresponds to data that needs to be collected in the page data.

[0031] In some embodiments, the method further includes performing, by the controller, a swap operation after power-on.

[0032] In some embodiments, the method further includes, after the calculation of the received page data corresponding to the i-th word line is completed, continuing, by the controller, to perform a calculation operation on the page data corresponding to the (i+1)th word line.

[0033] In some embodiments, the RAID parity data is obtained by performing an XOR operation on page data corresponding to one word line.

[0034] In some embodiments, the (i+1)th RAID parity data is used to verify page data corresponding to the first word line through the (i+1)th word line.

[0035] According to yet another aspect, a controller is provided, coupled to a three-dimensional non-volatile memory, the three-dimensional non-volatile memory comprising a three-dimensional memory array, the three-dimensional memory array comprising a plurality of word lines and a plurality of pages coupled thereto, the controller being configured to: calculate received page data corresponding to a first word line in units of page data corresponding to one word line to obtain redundant array RAID parity data of a first independent disk, and store the first RAID parity data in a parity buffer space; and calculate received page data corresponding to the (i+1)th word line and i-th RAID parity data to obtain i-th RAID parity data, and store the (i+1)th RAID parity data in the parity buffer space, wherein the (i+1)th RAID parity data overwrites the i-th RAID parity data, where i is a positive integer greater than or equal to 1.

[0036] In some embodiments, the controller is further configured to write the wth RAID parity data to the three dimensional non-volatile memory when the value of i is w-1, where w is the number of word lines corresponding to one fund.

[0037] In some embodiments, the controller is further configured to set a first memory space of the write buffer space for buffering the RAID parity data if the parity buffer space is insufficient.

[0038] In some embodiments, the controller is further configured to store pages of data corresponding to the first word line through the (i+1)th word line in a second memory space of the write buffer space.

[0039] In some embodiments, the configuration priority of the second memory space of the write buffer space is higher than the configuration priority of the first memory space.

[0040] In some embodiments, the parity buffer space includes a parity data buffer space and a garbage collection buffer space, the parity data buffer space is used to buffer RAID parity data, the garbage collection buffer space is used to buffer garbage collection data, and the garbage collection data including the RAID parity data corresponds to data that needs to be collected in the page data.

[0041] In some embodiments, the controller is further configured to perform a swap operation after power-on.

[0042] In some embodiments, the controller is further configured to continue performing calculation operations on the page data corresponding to the (i+1)th word line after calculation of the received page data corresponding to the i-th word line is completed.

[0043] In some embodiments, the RAID parity data is obtained by performing an XOR operation on page data corresponding to one word line.

[0044] In some embodiments, the (i+1)th RAID parity data is used to verify page data corresponding to the first word line through the (i+1)th word line.

[0045] According to yet another aspect, an electronic system is provided, the electronic system including a host computer and the memory system described above.

[0046] It can be understood that the beneficial effects that can be achieved by the memory system and its operating method provided in the above-mentioned embodiments of the present disclosure can be referred to the beneficial effects of the above-mentioned memory controller, and the details will not be described again here.

[0047] In order to more clearly describe the technical solutions of the present disclosure, the following briefly describes the accompanying drawings required for some embodiments of the present disclosure. Obviously, the accompanying drawings in the following description only show the drawings of some embodiments of the present disclosure, and those skilled in the art can still derive other drawings from these accompanying drawings. In addition, the accompanying drawings in the following description may be regarded as schematic diagrams, and are not constraints on the actual size of the product related to the embodiments of the present disclosure, the actual steps of the method, the actual timing of the signals, etc. [Brief description of the drawings]

[0048] [Figure 1] 1 is a schematic diagram of a memory system according to an embodiment of the present application. [Diagram 2] 1 is a schematic structural diagram of a NAND flash memory according to an embodiment of the present application; [Diagram 3] FIG. 2 is a schematic structural diagram of a data for which data protection is performed using two word lines according to an embodiment of the present application; [Figure 4] FIG. 2 is a schematic diagram of types of memory space according to an embodiment of the present application. [Diagram 5] FIG. 13 is a schematic diagram of RAID parity data obtained through calculation in another round according to an embodiment of the present application. [Figure 6] 1 is a schematic flowchart of a swap operation according to an embodiment of the present application. [Figure 7] FIG. 2 is a schematic structural diagram of a controller according to an embodiment of the present application; [Figure 8] 4 is a flowchart of a method of operating a memory system according to an embodiment of the present application. [Figure 9] FIG. 2 is a schematic structural diagram of a data for which data protection is performed using one word line according to an embodiment of the present application; [Figure 10] 4 is a flowchart of a method of operating a memory system according to an embodiment of the present application. [Figure 11] FIG. 2 is a schematic diagram of a memory space according to an embodiment of the present application. [Figure 12] 1 is a flowchart of buffering data by a controller according to an embodiment of the present application. [Figure 13] 1 is a schematic structural diagram of an electronic device according to an embodiment of the present application; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0049] The following clearly and completely describes the technical solutions in some embodiments of the present disclosure with reference to the accompanying drawings. Obviously, the described embodiments are only a part, not all, of the embodiments of the present disclosure. All other embodiments obtained by those skilled in the art based on the embodiments provided in the present disclosure shall be within the protection scope of the present disclosure.

[0050] In describing the present disclosure, it should be understood that directional or positional relationships indicated by the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inside," and "outer" are based on directional or positional relationships shown in the accompanying drawings and are only used to facilitate the description of the present disclosure, and are not used to indicate or suggest that a device or element must have a particular orientation or be constructed and operated using a particular orientation, and therefore are not to be understood as limitations of the present disclosure.

[0051] Unless otherwise required by context, throughout this specification and claims, the term "comprises" is interpreted as open and inclusive, i.e., "including but not limited to." In the description herein, the terms "an embodiment," "some embodiments," "exemplary embodiments," "exemplary," or "some examples" are intended to indicate that a specific feature, structure, material, or characteristic associated with an embodiment or example is included in at least one embodiment or example of the present disclosure. Graphical representations of the above terms do not necessarily refer to the same embodiment or example. In addition, a specific feature, structure, material, or characteristic described may be included in any one or more embodiments or examples in any suitable manner.

[0052] The terms "first" and "second" below are used for descriptive purposes only and are not intended to indicate or suggest relative importance or to implicitly designate the number of technical features shown. Thus, features defined by "first" and "second" may explicitly or implicitly include one or more features. In the embodiments of the present disclosure, "multiple" herein means "two or more" unless otherwise stated.

[0053] The use of "applicable to" or "configured to" herein implies open and inclusive language that does not exclude devices that are applicable to or configured to perform additional tasks or steps.

[0054] Additionally, the use of "based on" suggests openness and inclusiveness because a process, step, calculation, or other activity "based on" one or more stated conditions or values ​​may in fact be based on additional conditions or values ​​other than those stated.

[0055] As used herein, "about," "approximately," or "approximately" includes stated values ​​as well as averages that are within an acceptable range of deviation from the specified value. The acceptable range of deviation is as determined by one of ordinary skill in the art and takes into account the measurement under discussion and the error associated with the particular numerical measurement (i.e., the limitations of the measurement system).

[0056] In describing some embodiments, the terms "coupled" and "connected" and their derivatives may be used. For example, some embodiments may be described using the term "connected" to indicate that two or more components are in direct physical or electrical contact with each other. For example, some embodiments may be described using the term "coupled" to indicate that two or more components are in direct physical or electrical contact with each other. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of the present specification.

[0057] As used herein, the term "substrate" refers to a material onto which subsequent layers of material may be added. The substrate itself may be patterned. Materials added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include various semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or a sapphire wafer.

[0058] The term "three-dimensional non-volatile memory" refers to a semiconductor device formed by a column of memory cell transistors (herein referred to as a "memory cell column", e.g., a NAND memory cell column) aligned in an array on a major surface or source layer of a substrate and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertically / orthogonally" means nominally perpendicular to the major surface (i.e., lateral plane) or source layer of the substrate.

[0059] As used in this disclosure, the term "RAID" refers to "Redundant Array of Independent Disks" technology. Although "RAID" refers to any array of independent disks, it should be understood that implementations of the present application may be implemented at the hardware level using any type of non-volatile memory device, such as a NAND flash memory device.

[0060] 1 is a schematic diagram of a memory system according to an embodiment of the present application. The memory system 10 includes a controller 101 and a three-dimensional non-volatile memory 102. The controller 101 may communicate with a host computer 11 external to the memory system 10. The controller 101 may further be connected to the three-dimensional non-volatile memory 102 through a memory channel. In some embodiments, as shown in FIG. 1, the memory system 10 may include at least one three-dimensional non-volatile memory 102. Each three-dimensional non-volatile memory 102 may be managed by the controller 101.

[0061] The host computer 11 may send data to be stored in the three-dimensional non-volatile memory 102 to the controller 101. The host computer 11 may further read data from the three-dimensional non-volatile memory 102 through the controller 101. The controller 101 may process input / output (I / O) requests received from the host computer 11 and ensure the integrity and effective storage of the data to be stored according to the I / O requests. For example, the controller 101 may buffer the data received from the host computer 11 and perform RAID calculation according to the received data to obtain RAID parity data and buffer the RAID parity data. The RAID parity data is used to restore data corrupted in the encoding or storage process. The controller 101 may further send the data received from the host computer 11 and the RAID parity data obtained through calculation to the three-dimensional non-volatile memory 102 for storage.

[0062] The host computer 11 is a dedicated processor configured to perform data processing of the three-dimensional non-volatile memory 102. For example, the host computer 11 may include a central processing unit (CPU) or a system on a chip (SoC), such as an application processor. Data is transmitted between the host computer 11 and the controller 101 by using at least one of a variety of interface protocols.

[0063] For example, the interface protocol includes at least one of a Universal Serial Bus (USB) protocol, a Microsoft Management Console (MMC) protocol, a Peripheral Component Interconnect (PCI) protocol, a Peripheral Component Interconnect Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Integrated Drive Electronics (IDE) protocol, or a Firewire protocol.

[0064] In some embodiments, the controller 101 may be configured to control operations in the three-dimensional non-volatile memory 102, such as read operations, write operations, erase operations, encoding operations, and the like. The controller 101 may also be configured to manage various functions related to data stored or to be stored in the three-dimensional non-volatile memory 102, including, but not limited to, bad block management, garbage collection, logical to physical address conversion, wear leveling, and the like. In some implementations, the controller 101 is further configured to process error correction code (ECC) on data read from or written to the three-dimensional non-volatile memory 102. Of course, the controller 101 may also perform any other suitable functions on the three-dimensional non-volatile memory 102, such as formatting the three-dimensional non-volatile memory 102. This is not particularly limited in the embodiments of the present application.

[0065] In some implementations, the controller 101 may control operations in the three dimensional non-volatile memory 102 by using the generated control signals to control striping, calculations, or storage of data in the three dimensional non-volatile memory 102. Alternatively, the controller 101 may receive signals used for operations in the three dimensional non-volatile memory 102 from the host computer 11 to control striping, calculations, or storage of data in the three dimensional non-volatile memory 102.

[0066] In some implementations, the controller 101 may have various modules in a single device. The single device may be, for example, an integrated circuit chip, such as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA), or a single device with a dedicated function. In some implementations, the components of the controller 101 may be provided in an integrated device or may be distributed in different locations but communicate with each other through a network.

[0067] In some embodiments, the three-dimensional non-volatile memory 102 in the present disclosure may be a flash memory, for example, a NAND flash memory. The NAND flash memory may also be referred to as a flash memory or NAND for short. Of course, the three-dimensional non-volatile memory 102 in the present disclosure may be other memories. This is not limited in the present application. Only the example in which the three-dimensional non-volatile memory 102 is a NAND flash memory is used for the purpose of explanation.

[0068] As shown in Figure 2, Figure 2 is a schematic structural diagram of a NAND flash memory according to an embodiment of the present application. In order to increase the storage capacity, the NAND flash memory 20 generally includes multiple dies 201, for example D0 and D1. Each die 201 has multiple planes (PL), for example PL0, PL1, PL2, and PL3.

[0069] Each PL may include one or more memory blocks. Each memory block may be further divided into a number of strings (STRs). Each STR includes memory cells configured to store an upper page (UP) data portion, a middle page (MP) data portion, and a lower page (LP) data portion. The memory cells are coupled to a number of vertically arranged word lines (WLs) and a number of horizontally arranged bit lines (BLs). Structurally, each STR may include a number of gate conductive layers extending laterally. A memory block includes a number of gate conductive layers stacked vertically in a number of levels, and each gate conductive layer is coupled to memory cells distributed laterally in a number of pages in the STRs in the memory block. As the number of gate conductive layers continues to increase vertically, the storage capacity of the NAND flash memory increases accordingly, and the space between adjacent gate conductive layers becomes smaller, resulting in a large interference between adjacent gate conductive layers.

[0070] RAID5 is widely used in NAND flash memory to improve the integrity and readability of memory cells. In general, RAID5 divides memory data in a memory block into multiple data parts by using striping in the memory block, performs an XOR operation between the data parts in the stripe to generate corresponding parity check data, and stores the parity check data in the memory cell. It can be understood that one stripe includes data parts located in two dimensions. For example, one stripe includes data located horizontally across different memory blocks and different PLs of different DIEs and vertically located at different levels in the same memory block. In other words, in the horizontal direction, one stripe may include data parts at the same position in different PLs. In the vertical direction, one stripe may include data parts at the same position in different levels. The data parts include the parity check data of the stripe. If programming fails in one data part of the stripe, an XOR operation can be performed by using the parity check data of the stripe and the remaining data parts in the stripe to restore the corrupted data. For example, in a stripe having 128 data portions, 127 data portions are configured to store memory data and one data portion is configured to store parity check data for the stripe. Thus, the error correction capability using RAID5 with such a striping configuration can be described as (127+1), i.e., one parity check data portion protects 127 memory data portions.

[0071] As an example, a triple level cell (TLC) NAND is used. As shown in Table 1, Table 1 shows some or all of the memory data to be stored in the three-dimensional non-volatile memory 102. The memory data requires a RAID computation operation by the controller 101 before being stored in the three-dimensional non-volatile memory 102. In one example, it is assumed that the memory data is to be stored in two dies (DIE0 and DIE1). Each die includes four PLs: PL0, PL1, PL2, and PL3. Each PL includes six STRs: STR0, STR1, STR2, STR3, STR4, and STR5. Each STR includes memory cells configured to store a UP data portion, a MP data portion, and a LP data portion. The memory cells are coupled to a number of vertically aligned word lines.

[0072] For ease of explanation, in Table 1, the word lines are labeled with word line numbers, e.g., WL0, WL1, etc. Moreover, for ease of illustration, the data portions (e.g., UP data portion, MP data portion, and LP data portion) are also numbered. For example, the LP data portion stored in memory cells in the 0th string (STR0) and coupled to the 0th word line (WL0) has a data number "0". The MP data portion stored in memory cells in the 0th string (STR0) and coupled to the 0th word line (WL0) has a data number "1". The UP data portion stored in memory cells in the 0th string (STR0) and coupled to the 0th word line (WL0) has a data number "2". Data portions stored in memory cells of the same word line coupled to the same page in different planes have the same data number. For example, the data portions stored in memory cells coupled to WL0 in PL0 and PL1 have the same data number "0".

[0073] In Table 1, the number of word lines can vary from 32, 64, 96, and 128 to 256. It should be noted that the RAID operations are applicable to any suitable three-dimensional non-volatile memory 102, but are not limited by a particular amount of dies, planes, strings, and word lines in the three-dimensional non-volatile memory 102. In some implementations, in each PL (e.g., PL0 and PL1), a word line in each level (e.g., WL0) can be coupled to 18 data portions (e.g., data portions 0 to 17).

[0074] [Table 1]

[0075] Since there is interference between WL0 and WL1, in order to implement data protection, when receiving data from the host computer 11, the controller 101 may perform calculations by using RAID5 and based on the page data of the data pages respectively corresponding to the two word lines to obtain RAID parity data, i.e., to implement data protection by using page data corresponding to the two word lines.

[0076] In one embodiment, for example, in a TLC NAND including two dies, one word line and 18 pages are combined. Each page includes one parity page and 127 data pages. The RAID parity data in the parity page is obtained through calculations of the 127 data pages in the page. That is, one parity page can be used to protect 127 data pages. Thus, two word lines correspond to 36 parity pages. The 36 parity pages form one round. As shown in FIG. 3, FIG. 3 shows 576 page lines in DIE0 and DIE1, denoted as P0 to P575. Each page line includes pages of multiple PLs. Round 0 (301) includes P0 to P35, round 2 (302) includes P36 to P71, ... round 16 (303) includes P540 to P575. That is, 16 rounds are required to store 576 pages. 16 rounds form one fund.

[0077] When receiving data and performing calculations to obtain RAID parity data, the controller 101 must first buffer the received data and RAID parity data, and then send the received data and RAID parity data to the NAND flash memory for storage. Therefore, the memory space in the controller 101 is described here first.

[0078] 4 is a schematic diagram of types of memory spaces in controller 101. The memory spaces may include read buffer space, copy buffer space, parity buffer (PB) space, etc. FIG. 4 is merely a schematic example and is not limiting, and controller 101 further includes other buffer spaces. Parity buffer space may be used to store RAID parity data and garbage collection (GC) data.

[0079] Based on the description of FIG. 4, in one embodiment, when a mode of RAID parity protection with two word lines is used, typically 1152 KB of memory space is required to buffer the RAID parity data and garbage collection data corresponding to the two word lines. Because the parity buffer space is a limited memory space, typically only 320 KB of memory space is provided for use by the RAID parity data and garbage collection data. Therefore, the controller 101 needs to use a swap operation to share the limited parity buffer space in a time-division manner.

[0080] As shown in FIG. 5, FIG. 5 is a schematic diagram of RAID parity data obtained through calculation in one round according to an embodiment of the present application. P0 to P35 on the vertical axis represent the indexes of 36 page lines in one round. When the controller 101 buffers the RAID parity data, it is assumed that 12 PBs are allocated. Each PB has a capacity of 16KB and is configured to store the RAID parity data of one parity page. The horizontal axis represents the usage status of each of the 12 PBs (PB0 to PB11) at different stages, for example, from moment t1 to moment t17. For example, the controller 101 may obtain 3 PBs of RAID parity data, for example, P0 to P2, through calculation at moment t1, and obtain 3 PBs of RAID parity data, for example, P3 to P5, through calculation at moment t2. In this case, 6 PBs of RAID parity data, for example, P0 to P5, are stored. When the RAID parity data of two PBs, for example P6 and P7, is obtained through calculation at the instant t3, in this case, the RAID parity data of eight PBs, for example P0 to P7, has been stored. At the instant t4, a swap operation is performed once. That is, when each of the eight PBs is filled with the stored RAID parity data, the controller 101 needs to perform a swap operation once. That is, the calculated RAID parity data of the eight parity pages is backed up to the three-dimensional non-volatile memory 102. Then, the three-dimensional non-volatile memory 102 can restore the RAID parity data of the eight parity pages to be used.

[0081] For the above procedure of swap operation, reference may be made to Fig. 6. Fig. 6 is a schematic flow chart of swap operation. When each of the 8 PBs is filled with stored RAID parity data, memory controller 101 must first send a program command to load swap operation, then wait for calculation (wait encoding), do calculation (encoding), finish calculation (encoding done), and do program swap (prog swap).

[0082] Therefore, in one round, the controller 101 needs to execute a total of five swap operations at the instant t4, the instant t7, the instant t10, the instant t13, and the instant t16, respectively. Each swap operation includes eight parity page calculation operations and eight parity page read operations. During a swap operation, it even needs to wait for the previous swap operation to be completed before it can continue to send program commands to execute the next swap operation. The write performance of the controller 101 is relatively low.

[0083] The embodiment of the present application provides an operation method of a memory system. In this method, RAID parity data is obtained through calculation in units of page data corresponding to one word line, and the RAID parity data is buffered in a parity buffer space of a buffer module. After the first RAID parity data is buffered in the parity buffer space, the second RAID parity data is buffered, and the second RAID parity data overwrites the first RAID parity data. In the operation method of the memory system provided in the present disclosure, the RAID parity data is obtained through calculation of page data corresponding to one word line, and the parity buffer space can be sufficient for buffering the RAID parity data. Therefore, the storage process of the RAID parity data of the present application can reduce the storage load and reduce the number of swap operations performed by the controller 101, thereby improving the write performance of the controller.

[0084] As shown in FIG. 7, FIG. 7 is a schematic structural diagram of a controller according to an embodiment of the present application.

[0085] The controller 101 may perform a calculation operation. For example, the controller 101 calculates each of the received page data corresponding to the first word line in units of page data corresponding to one word line to obtain the first RAID parity data, and stores the first RAID parity data in the parity buffer space. In an embodiment, the first RAID parity data may be obtained through calculation of 18 page data corresponding to the first word line. Therefore, the first RAID parity data may correspond to the data of 18 parity data.

[0086] In addition, the controller 101 is coupled to the three-dimensional non-volatile memory 102 and may perform a data write operation or a data read operation in response to a control signal. The controller 101 may be configured to temporarily store data transmitted between the host computer 11 and the three-dimensional non-volatile memory 102. For example, as the host computer 11 writes data to the three-dimensional non-volatile memory 102 or as the host computer 11 reads data from the three-dimensional non-volatile memory 102, the controller 101 may be configured to temporarily store page data corresponding to one word line or RAID parity data calculated in units of page data corresponding to one word line. In some implementations, the controller 101 may include a static random access memory (SRAM) or a dynamic random access memory (DRAM). This is not particularly limited in the embodiments of the present application.

[0087] In addition, the controller 101 may provide data to and control communication with the three-dimensional non-volatile memory 102 via a data bus.

[0088] The controller 101 may include any suitable type of general purpose or special purpose microprocessor, digital signal processor, or microcontroller. The controller 101 may be configured as a standalone processor module dedicated to performing signal analysis or scanning scheme control. Optionally, the controller 101 may be configured as a shared processor module for performing other functions unrelated to signal analysis / scanning scheme. The controller 101 may include multiple functional units or modules that may be implemented using software, hardware, middleware, firmware, or any combination thereof. The multiple functional units may perform operations such as read operations, write operations, erase operations, striping operations, calculation operations, decision-making operations, or control operations on the storage of RAID parity data based on signals from the host computer 11 and pre-stored control data.

[0089] In some implementations, the controller 101 may perform configuration tasks, such as setting a first memory space of a write buffer space for buffering RAID parity data. In some implementations, the controller 101 may perform a swap operation.

[0090] An embodiment of the present application provides an operating method of a memory system, which is applicable to the structure of the memory system shown in Figure 1. As shown in Figure 8, Figure 8 is a flowchart of an operating method of a memory system according to an embodiment of the present application. The method includes the following steps:

[0091] Step 801: The controller 101 calculates the received page data corresponding to the first word line in units of page data corresponding to one word line to obtain the first RAID parity data, and stores the first RAID parity data in a parity buffer space.

[0092] In some embodiments, as shown in FIG. 9, FIG. 9 is a schematic structural diagram of data for which data protection is performed by using one word line according to an embodiment of the present application. The page data corresponding to one word line can be 18 pages of data. FIG. 9 shows 288 pages of data in DIE0 and DIE1. Round 0 (901) includes P0 to P17, round 1 (902) includes P18 to P31, ..., and round 16 (903) includes P270 to P287. That is, 16 rounds are needed to store 288 pages. The 16 rounds form one fund.

[0093] The RAID parity data is obtained by performing an XOR operation on the page data corresponding to one word line.

[0094] In some embodiments, the controller 101 may perform an XOR operation on the page data corresponding to one word line to obtain the first RAID parity data. In one embodiment, when the data of one page among the data of 18 pages corresponding to one word line are d1, d2, d3, d4, and d5, the RAID parity data corresponding to the page is:

[0095]

number

[0096] It is.

[0097] In addition, the controller 101 may use a parity check algorithm to add a parity check bit to the first RAID parity data obtained through calculation. The parity check may be understood as a check that is performed according to whether the number of "1" in one group of bits of the transmitted binary code is odd or even. Checking using an odd number is called odd check, and checking otherwise is called even check.

[0098] When the odd check mode is used, an XOR operation is performed on the first RAID parity data, and then an XOR is performed on the result and "1", so that the value of the odd check bit in the first RAID parity data can be obtained. When the even check mode is used, an XOR operation is performed on the first RAID parity data, and then an XOR is performed on the result and "0", so that the value of the even check bit in the first RAID parity data can be obtained. Therefore, the accuracy of the first RAID parity data can be ensured.

[0099] In addition, for RAID parity data, other operations besides XOR operations may be performed on page data corresponding to one word line, which is not limited in this application.

[0100] It should be noted that the page data corresponding to one word line may be data pre-written into the three-dimensional non-volatile memory 102 by the host computer 11. For example, the page data may be binary digital data of symbols, text, numbers, conversations, images, videos, or combinations thereof.

[0101] Step 802: The controller 101 calculates the received page data and the i-th RAID parity data corresponding to the (i+1)th word line to obtain the (i+1)th RAID parity data, stores the (i+1)th RAID parity data in the parity buffer space, and overwrites the i-th RAID parity data with the (i+1)th RAID parity data, where i is a positive integer greater than or equal to 1.

[0102] After storing the first RAID parity data in the parity buffer space, the controller 101 may perform a calculation operation on the received page data corresponding to the second word line and the first RAID parity data to obtain the second RAID parity data. It is assumed that the first word line corresponds to page data of 18 pages, which are D1, D2, ..., and D18, respectively. An XOR operation is performed on the page data of D1 to D18, respectively. Correspondingly, a group of RAID parity data is obtained for the page data of each page. The first RAID parity data may include 18 groups of RAID parity data, which are P1, P2, ..., and P18, respectively. The second word line also corresponds to page data of 18 pages, which are D19, D20, ..., and D36, respectively. In this case, an XOR operation is performed on the data D19 of the first page in the page data corresponding to the second word line and the first group of RAID parity data P1 in the 18 groups of RAID parity data to obtain the first group of RAID parity data P19 in the second RAID parity data.

[0103]

number

[0104] The remaining groups of RAID parity data in the second RAID parity data can be obtained by using a method similar to the method of obtaining the first group of RAID parity data in the second RAID parity data. Then, the controller 101 stores the second RAID parity data obtained through calculation in the parity buffer space and overwrites the first RAID parity data.

[0105] Therefore, it can be inferred that after storing the i-th RAID parity data in the parity buffer space, the controller 101 can calculate the received page data and the i-th RAID parity data corresponding to the (i+1)-th word line to obtain the (i+1)-th RAID parity data. Optionally, as shown in FIG. 10, FIG. 10 shows another operation method of the memory system provided in the embodiment of the present application. The method can further include the following step 803. When the value of i is w-1, the controller 101 writes the w-th RAID parity data to the three-dimensional non-volatile memory 102, and w is the number of word lines corresponding to one fund.

[0106] In the embodiment of the present application, when one fund includes w word lines, if the wth word line is the last word line in the current data storage process, after buffering the wth RAID parity data in the parity buffer space, the controller 101 sends the wth RAID parity data to the three-dimensional non-volatile memory 102. For example, when one fund includes 16 word lines, i.e. w=16, in this case, an XOR operation is performed on the received page data corresponding to the 15th word line and the 14th RAID parity data, so that the 15th RAID parity data can be obtained. The 15th RAID parity data is stored in the parity buffer space, which overwrites the 14th RAID parity data. An XOR operation is performed on the received page data corresponding to the 16th word line and the 15th RAID parity data, so that the 16th RAID parity data can be obtained, and the 16th RAID parity data is stored in the parity buffer space, which overwrites the 15th RAID parity data. In this case, since the controller 101 has completed the calculation of the RAID parity data for the page data corresponding to the word lines in one fund, the 16th RAID parity data can be sent to the three-dimensional non-volatile memory 102. If any page data corresponding to the word lines in one fund is corrupted, the page data can be restored according to the 16th RAID parity data and other page data corresponding to the word lines in the funds.

[0107] For valid data in the three-dimensional nonvolatile memory 102, those skilled in the art can understand that due to the physical state of memory cells, programming interference in the storage process, etc., the valid data stored in the three-dimensional nonvolatile memory 102 may be bit-flipped and turned into incorrect data. Therefore, the incorrect data needs to be restored to valid data. Therefore, RAID parity data may also be stored in the three-dimensional nonvolatile memory 102, and the valid data may be restored according to the RAID parity data corresponding to the valid data, thereby improving the accuracy of storing the valid data in the three-dimensional nonvolatile memory 102.

[0108] Optionally, before step 801, the method may further include the following steps:

[0109] Step 804: If the parity buffer space is insufficient, the controller 101 sets a first memory space of the write buffer space for buffering the RAID parity data.

[0110] As shown in FIG. 11, FIG. 11 is a schematic diagram of memory space according to an embodiment of the present application. In an embodiment, when the word line protection mode is used, a total of 448KB of memory space is required for RAID parity data and garbage collection data. The capacity of the parity buffer space is assumed to be 384KB. The capacity of the first memory space in the write buffer space that can be allocated by the controller 101 is 128KB, and the first memory space is used to buffer the RAID parity data. In this case, the total memory space used to store the RAID parity data and garbage collection data in the parity buffer space is 512KB. The controller 101 can allocate 448KB of memory space from the parity buffer space for buffering the RAID parity data and garbage collection data. The remaining memory space can be used to store other system data.

[0111] Naturally, since the total memory space used for storing RAID parity data and garbage collection data in the parity buffer space is 512KB, when the word line protection mode is used, the total memory space required for RAID parity data and garbage collection data is larger than 512KB, and the controller 101 may allocate a portion of the memory space from the parity buffer space to buffer the RAID parity data and garbage collection data, and the remaining memory space can be used to store other system data. For example, a total of 576KB of memory space is required for the RAID parity data and garbage collection data. The controller 101 may allocate 448KB of memory space from the parity buffer space to buffer the RAID parity data and garbage collection data. The portion of the memory space allocated from the parity buffer space to buffer the RAID parity data and garbage collection data can ensure the storage of the RAID parity data with priority, and the remaining memory space can be used to store the garbage collection data.

[0112] In the 448KB memory space in the parity buffer space, the controller 101 allocates 18PB memory space to store RAID parity data. Each PB occupies 16KB. If the first RAID parity data includes 18 groups of RAID parity data, in this case, the parity buffer space does not need to perform swap operation when buffering the RAID parity data, thereby realizing the continuity of buffering the RAID parity data, so that the write performance of the controller can be improved.

[0113] It should be noted that during the determination of the capacity of the first memory space, the availability of the write buffer space should be ensured first.

[0114] Optionally, the method may further include the following steps.

[0115] Step 805: The controller 101 stores the page data corresponding to the first word line through the page data corresponding to the (i+1)th word line in the second memory space of the write buffer space.

[0116] For example, the second memory space of the write buffer space may buffer data transferred between the host computer 11 and the three-dimensional nonvolatile memory 102, i.e., page data corresponding to multiple word lines. When the second memory space of the write buffer space buffers data, storage is performed in units of page data corresponding to one word line. Thus, during a read or write operation between the host computer 11 and the three-dimensional nonvolatile memory 102, the page data corresponding to multiple word lines is stored in the second memory space of the write buffer space, so that the speed at which the host computer 11 reads data from or writes data to the three-dimensional nonvolatile memory 102 may be increased.

[0117] The configuration priority of the second memory space of the write buffer space is higher than the configuration priority of the first memory space.

[0118] For example, while satisfying the amount of the second memory space required for buffering page data corresponding to multiple word lines, the controller 101 then allocates the first memory space to parity buffer space for buffering RAID parity data.

[0119] Additionally, in some embodiments of the present disclosure, if the sum of the capacity of the parity buffer space and the capacity of the first memory space is sufficient to buffer all the RAID parity data, the controller 101 can buffer all the RAID parity data without performing a swap operation, thereby improving the write performance of the controller.

[0120] In some embodiments of the present disclosure, if the sum of the capacity of the parity buffer space and the capacity of the first memory space may still be insufficient to buffer all RAID parity data, a swap operation may be performed to share the first memory space and the parity buffer space in a time-division manner.However, compared with the two-word line protection mode, the number of swap operations is reduced, so the write performance of the controller may still be improved.

[0121] In some embodiments of the present disclosure, the parity buffer space includes a parity data buffer space and a garbage collection buffer space, where the parity buffer space is used to buffer RAID parity data and the garbage collection buffer space is used to buffer garbage collection data, where the garbage collection data includes RAID parity data corresponding to data that needs to be collected in the page data.

[0122] In one embodiment, after allocating 128 KB of a first memory space for parity buffer space from the write buffer space, the controller 101 may allocate 10 PB for storing garbage collection data.

[0123] For example, the amount of invalid data stored in the multiple data blocks in the three-dimensional non-volatile memory 102 may increase with an increase in the processing of encoding commands from the host computer 11, so a GC operation may be performed to repeatedly use the data blocks to store such invalid data. For example, the controller 101 may perform a GC operation to modify the data blocks such that valid data is stored in the idle blocks. In addition, a setting may be made in the controller 101 such that a GC mechanism is triggered when the number of remaining idle blocks is equal to or less than a threshold. When the GC mechanism is triggered, the controller 101 may recognize closed blocks in the multiple data blocks in the three-dimensional non-volatile memory 102, and use the closed blocks in which the number of valid pages is less than a threshold in the closed blocks as victim blocks. The controller 101 may copy the valid data in the victim blocks and store the valid data in target blocks that have not undergone an encoding operation and are used as idle blocks. After the valid data is copied and stored in the target blocks, the controller 101 may erase the victim blocks.

[0124] During a GC operation, to move data from a closed block to an idle block in the three-dimensional nonvolatile memory 102, the controller 101 may read data from a closed block in the three-dimensional nonvolatile memory, load the read data into a buffer space, and write the data stored in the buffer space to an idle block. Because the controller 101 performs read / write operations on the three-dimensional nonvolatile memory 102, when performing a GC operation and simultaneously transferring a read command or a write command from the host computer 11, the controller 101 may stop the GC operation to perform the operation of the command.

[0125] During the execution of the GC mechanism, the controller 101 marks valid data and invalid data. The method for marking invalid data is called a garbage marking algorithm. The algorithm may include a reference counting algorithm and a route finding algorithm.

[0126] In the reference counting algorithm, a memory field is maintained for each datum to count the number of times the datum is referenced. When the datum is referenced, the counter is incremented by one, and when the reference becomes invalid, the counter is decremented by one. When the counter reaches zero, the datum is marked as invalid to await subsequent collection. In the root finding algorithm, a datum named "GC Roots" is used as the root starting point, the object graph is traversed through reference relationships, and the path explored is called a reference chain. When there is no reference chain between a datum and GC Roots, i.e., when the datum is not reachable from GC Roots, the datum is marked as invalid to await subsequent collection.

[0127] Optionally, as shown in FIG. 10, before step 801, the method may further include the following steps:

[0128] Step 806: The controller 101 performs a swap operation after power-on.

[0129] In one embodiment, after the controller 101 is powered on, the controller 101 may execute a procedure to load a swap operation to initialize the parity buffer space, the write buffer space, and the like.

[0130] In the embodiment of the present application, after the memory controller is powered on, a swap operation is performed. In the process of buffering RAID parity data, the parity buffer space can be filled with the RAID parity data obtained through calculation based on the page data corresponding to one word line. Therefore, the present application does not need to perform a swap operation in the process of buffering RAID parity data, thereby realizing the continuity of buffering RAID parity data and improving the write performance of the controller.

[0131] In some embodiments, the host computer 11 may send a reset signal to the controller 101. The reset signal is used to clear data that has been buffered in the buffer space.

[0132] Optionally, the method further includes continuing to perform a calculation operation on page data corresponding to the (i+1)th word line after the received page data corresponding to the i-th word line has been calculated.

[0133] As shown in FIG. 12, FIG. 12 is a flow chart of buffering data by a controller according to an embodiment of the present application. After the controller 101 is powered on, the controller 101 executes a procedure of loading a swap operation. After the swap operation is executed, steps such as waiting for calculation, calculating, and completing calculation are executed, and then the above steps are repeated. For example, for the i-th word line and the (i+1)-th word line, the controller 101 successively executes the steps of a. waiting for calculation of page data corresponding to the i-th word line, b. calculating page data corresponding to the i-th word line, c. completing calculation of page data corresponding to the i-th word line, d. waiting for calculation of page data corresponding to the (i+1)-th word line, e. calculating page data corresponding to the (i+1)-th word line, and f. completing calculation of page data corresponding to the (i+1)-th word line.

[0134] The (i+1)th RAID parity data is used to identify the page data corresponding to the first word line through the (i+1)th word line.

[0135] In an embodiment, when the (i+1)th word line is the last word line in the current data storage process, the controller 101 may store the (i+1)th RAID parity data in the three-dimensional non-volatile memory 102. In this case, the (i+1)th RAID parity data may be used to confirm the page data corresponding to the first word line to the (i+1)th word line. That is, if any data in the page data corresponding to the first word line to the (i+1)th word line is corrupted, the corrupted data may be restored according to the (i+1)th RAID parity data and other data corresponding to the first word line to the (i+1)th word line.

[0136] As shown in Figure 13, Figure 13 is a schematic structural diagram of an electronic device according to an embodiment of the present application. The electronic device 100 includes a host computer 11 and a memory system 10 in some embodiments of the present disclosure.

[0137] The memory system 10 may be integrated into various types of memory devices, for example, in the same package (e.g., a universal flash storage (UFS) package or an embedded multimedia card (eMMC) package), that is, the memory system 10 may be applied and packaged in different types of electronic products, for example, a mobile telephone (mobile phone), a desktop computer, a tablet computer, a laptop computer, a server, an in-vehicle device, a game console, a printer, a pointing device, a wearable device, a smart sensor, a power bank, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device with memory therein.

[0138] In some embodiments, memory system 10 may include a controller 101 and a three-dimensional non-volatile memory 102. Memory system 10 is integrated into a memory card.

[0139] The memory card may include any one of a PC card (Personal Computer Memory Card International Association, PCMCIA), a Compact Flash (CF) card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC), a Secure Digital (SD) memory card, or a UFS.

[0140] 1, a memory system 10 includes a memory controller 101 and a plurality of three-dimensional non-volatile memories 102. The memory system 10 is integrated with a solid-state drive (SSD).

[0141] In memory system 10, in some embodiments, memory controller 101 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0142] In some other embodiments, the controller 101 is configured to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs). SSDs and eMMCs are used as data storage for portable devices, such as smartphones, tablet computers, laptop computers, and enterprise storage arrays.

[0143] Some embodiments of the present disclosure further provide an electronic device, which may be a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, an in-vehicle device, a wearable device (e.g., a smart watch, a smart band, a smart glasses, etc.), a power bank, a game console, a digital multimedia player, etc.

[0144] The electronic device may include the storage system 10 described above, and may also include at least one of a central processing unit, a cache, and the like.

[0145] The above description is merely a specific implementation of the present disclosure, and is not intended to limit the scope of protection of the present disclosure. Any variation or replacement that can be easily understood by a person skilled in the art within the technical scope disclosed in the present disclosure shall be within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure shall be within the scope of protection of the claims. [Explanation of symbols]

[0146] 10 Memory System 11 Host Computer 20 NAND Flash Memory 100 Electronic Devices 101 Controller 102 3D Non-volatile Memory 201 Die 301 Round 0 302 Round 1 303 Round 16 901 Round 0 902 Round 1 903 Round 16

Claims

1. 1. A memory system comprising: a controller and a three dimensional non-volatile memory, the three dimensional non-volatile memory comprising a three dimensional memory array, the three dimensional memory array comprising a plurality of word lines and a plurality of pages coupled to each other, the controller coupled to the three dimensional non-volatile memory, the controller comprising: Calculate the received page data corresponding to the first word line in units of page data corresponding to one word line to obtain redundant array RAID parity data of the first independent disk, and store the first RAID parity data in a parity buffer space; Calculating the received page data and the i-th RAID parity data corresponding to the (i+1)-th word line to obtain the (i+1)-th RAID parity data, storing the (i+1)-th RAID parity data in the parity buffer space, and overwriting the i-th RAID parity data with the (i+1)-th parity data, where i is a positive integer equal to or greater than 1; It is configured as follows: A memory system comprising:

2. The controller further comprises: The memory system of claim 1, configured to write the wth RAID parity data to the three-dimensional nonvolatile memory when the value of i is w-1, where w is the number of word lines corresponding to one fund.

3. The controller further comprises:

2. The memory system of claim 1, further configured to set up a first memory space of a write buffer space for buffering RAID parity data if the parity buffer space is insufficient.

4. The controller further comprises:

4. The memory system of claim 3, configured to store the page data corresponding to the first word line through the page data corresponding to the (i+1) word line in a second memory space of the write buffer space.

5. 5. The memory system of claim 4, wherein the configuration priority of the second memory space of the write buffer space is higher than the configuration priority of the first memory space.

6. 5. The memory system of claim 4, wherein the parity buffer space includes a parity data buffer space and a garbage collection buffer space, the parity data buffer space is used to buffer the RAID parity data, the garbage collection buffer space is used to buffer garbage collection data, and the garbage collection data including the RAID parity data corresponds to data that needs to be collected in page data.

7. The memory system of claim 1 , wherein the controller is further configured to perform a swap operation after power-on.

8. The controller further comprises:

2. The memory system of claim 1, further configured to continue performing the calculation operation on the page data corresponding to the (i+1)th word line after the calculation of the received page data corresponding to the i-th word line is completed.

9. 2. The memory system according to claim 1, wherein the RAID parity data is obtained by performing an XOR operation on page data corresponding to one word line.

10. 2. The memory system of claim 1, wherein the (i+1) RAID parity data is used to verify the page data corresponding to the first word line through the (i+1) word line.

11. 1. A method of operating a memory system, the memory system comprising: a controller and a three dimensional non-volatile memory, the three dimensional non-volatile memory comprising a three dimensional memory array, the three dimensional memory array comprising a plurality of word lines and a plurality of pages coupled together, the controller coupled to the three dimensional non-volatile memory, the method comprising: Calculating the received page data corresponding to a first word line by the controller in units of page data corresponding to one word line to obtain redundant array RAID parity data of a first independent disk, and storing the first RAID parity data in a parity buffer space; calculating, by the controller, the received page data and the i-th RAID parity data corresponding to the (i+1)-th word line to obtain the (i+1)-th RAID parity data, and storing the (i+1)-th RAID parity data in the parity buffer space, where the (i+1)-th RAID parity data overwrites the i-th RAID parity data, where i is a positive integer equal to or greater than 1; 23. A method of operation comprising:

12. The method of claim 11, further comprising the step of writing, by the controller, the wth RAID parity data to the three-dimensional non-volatile memory when the value of i is w-1, where w is the number of word lines corresponding to one fund.

13. Prior to storing the first RAID parity data in the parity buffer space, the method further comprises:

12. The method of claim 11, further comprising the step of: configuring, by the controller, a first memory space of a write buffer space for buffering RAID parity data if the parity buffer space is insufficient.

14. The method further comprises:

14. The method of claim 13, further comprising storing, by the controller, the page data corresponding to the first word line through the page data corresponding to the (i+1) word line in a second memory space of the write buffer space.

15. 15. The method of claim 14, wherein a configuration priority of the second memory space of the write buffer space is higher than a configuration priority of the first memory space.

16. 15. The method of claim 14, wherein the parity buffer space includes a parity data buffer space and a garbage collection buffer space, the parity data buffer space is used to buffer the RAID parity data, the garbage collection buffer space is used to buffer garbage collection data, and the garbage collection data including the RAID parity data corresponds to data that needs to be collected in page data.

17. The method further comprises:

12. The method of claim 11, further comprising the step of performing, by the controller, a swap operation after power-on.

18. The method further comprises:

12. The method of claim 11, further comprising: after completing calculation of the received page data corresponding to the i-th word line, continuing to perform, by the controller, the calculation operation on the page data corresponding to the (i+1)th word line.

19. 12. The method of claim 11, wherein the RAID parity data is obtained by performing an XOR operation on page data corresponding to one word line.

20. 12. The method of claim 11, wherein the (i+1)th RAID parity data is used to verify the page data corresponding to the first word line through the (i+1)th word line.

21. An electronic system, characterized in that it comprises a host computer and the memory system according to any one of claims 1 to 10.

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