Schottky diode element and its manufacturing method

Abstract

The present application discloses a Schottky diode element and a method for manufacturing the same, the Schottky diode element comprising: an epitaxial wafer having an epitaxial layer, the epitaxial layer having a first surface and a second surface opposite to each other, the epitaxial wafer having a functional region on the first surface and trench regions located on both sides of the functional region; and a multi-step trench located in the trench region, the multi-step trench having a first ion implantation region in a surface of the epitaxial layer exposed from a sidewall and a bottom of the multi-step trench, includes a plurality of sub-trenches, the plurality of sub-trenches being a first stage sub-trench to an Nth stage sub-trench arranged in a first direction, the width of each of the sub-trenches increasing in the first direction in the same multi-step trench, and a sidewall of at least a first stage sub-trench includes a multi-step trench having a sidewall protection structure, and a first metal electrode filling the multi-step trench, the first metal electrode further covering a functional region of the first surface and having a Schottky contact with the functional region of the first surface.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to a Chinese patent application filed with the China Patent Office on May 25, 2022, bearing application number 202210575076.1 and entitled "Schottky diode element and manufacturing method thereof," the entire contents of which are incorporated herein by reference.

[0002] This application claims priority to a Chinese patent application filed with the China Patent Office on May 25, 2022, bearing application number 202221291724.2 and entitled "Schottky Diode Element," the entire contents of which are incorporated herein by reference. [Technical field]

[0003] The present application relates to the field of semiconductor device technology, and more particularly to Schottky barrier diodes (SBD) devices and methods for fabricating the same. [Background technology]

[0004] SiC is a wide bandgap semiconductor material that has been rapidly developed in the past decade. Compared with other semiconductor materials (such as Si, GaN, and GaAs), SiC materials have advantages such as a wide bandgap, high thermal conductivity, high carrier saturation mobility, and high power density. SiC can be thermally oxidized to produce silicon dioxide, which enables the realization of power elements and circuits such as SiC MOSFETs and SBDs. Since the 1990s, power elements such as SiC MOSFETs and SBDs have been widely used in switching constant voltage power supplies, high frequency heating, automotive electronics, and power amplifiers.

[0005] As shown in Fig. 1, Fig. 1 is a structural schematic diagram of a typical SiC Schottky diode element, which includes a substrate 11 and an epitaxial layer 12 disposed on the substrate 11, a functional region on the surface of the epitaxial layer 12 away from the substrate 11 and ion implantation regions 13 on both sides of the functional region, an anode on the surface of the epitaxial layer 12 away from the substrate 11, and a cathode on the film on the substrate 11 away from the epitaxial layer 12. Generally, the epitaxial layer is N-type doped SiC, and the ion implantation region 13 is P+ doped (high concentration P-type doping). For the element structure shown in FIG. 1, particularly for the high-voltage SBD element, the optimized designs of breakdown voltage and on-resistance affect and contradict each other, and it is generally difficult to obtain a low on-resistance when obtaining a high breakdown voltage. In particular, for a planar JBS (high-voltage junction barrier Schottky diode) element, the implantation depth of the P+ doped ion implantation region 13 during high-voltage design is limited by the process equipment, making it difficult to realize a deep P+ implantation of a junction of 1 um or more.

[0006] The trench SBD structure can achieve deep P+ implantation into the SiC epitaxial layer, but it is prone to high electric field regions at the bottom of the trench, which can cause early breakdown and leakage problems at the corners of the trench bottom. Summary of the Invention [Problem to be solved by the invention]

[0007] In view of this, the present application provides a Schottky diode element and a manufacturing method thereof, and the solutions are as follows. [Means for solving the problem]

[0008] A Schottky diode element, An epitaxial wafer having an epitaxial layer, the epitaxial layer having opposing first and second surfaces, the first surface having a functional region and trench regions located on both sides of the functional region; a multi-step trench located in the trench region, the multi-step trench having a first ion implanted region in a surface of the epitaxial layer exposed at a sidewall and a bottom of the multi-step trench; the multi-step trench includes a plurality of sub-trenches, the plurality of sub-trenches being a first stage sub-trench to an Nth stage sub-trench in a first direction, N being a positive integer greater than 1, the first direction being a direction in which the second surface faces the first surface, the width of each of the sub-trenches in the same multi-step trench increasing in the first direction, and a sidewall of at least a first stage sub-trench having a sidewall protection structure; A first metal electrode filling the multi-step trench, the first metal electrode further covering a functional region of the first surface and having a Schottky contact with the functional region of the first surface.

[0009] Preferably, in the Schottky diode element, the sidewall protection structure includes an opening for exposing a bottom of the multi-stage trench; an ohmic contact structure located in the opening; Here, the first metal electrode is electrically connected to the first ion-implanted region at the bottom of the multi-step trench via the ohmic contact structure.

[0010] Preferably, in the Schottky diode element, the epitaxial layer is a SiC layer, The ohmic contact structure is a metal complex formed on the SiC layer.

[0011] Preferably, in the above Schottky diode element, a height of the ohmic contact structure is smaller than a height of the first stage sub-trench in the first direction and smaller than a height of the sidewall protection structure.

[0012] Preferably, in the above Schottky diode element, a height of the sidewall protection structure in the first direction is equal to or less than a height of the first stage sub-trench.

[0013] Preferably, in the above Schottky diode element, the sidewall protection structure is a SiO2 layer or a SiN layer.

[0014] Preferably, in the above Schottky diode element, the epitaxial wafer includes a semiconductor substrate, and the second surface is disposed opposite to the semiconductor substrate; Here, the semiconductor substrate has a second metal electrode on a surface thereof facing away from the epitaxial layer.

[0015] Preferably, in the Schottky diode element, a second ion implantation region is provided in the first surface surrounding the multi-stage trench opening, the second ion implantation region being in contact with the first ion implantation region; Here, the second ion implantation region and the first ion implantation region are both doped in the opposite direction to the epitaxial layer.

[0016] The present application further provides a method for manufacturing a Schottky diode element, providing an epitaxial wafer having an epitaxial layer having opposing first and second surfaces, the epitaxial layer having a functional region in the first surface and trench regions on either side of the functional region; forming a multi-step trench in the trench region, the multi-step trench including a plurality of sub-trenches, the plurality of sub-trenches being a first sub-trench to an Nth sub-trench in sequence in a first direction, N being a positive integer greater than 1, the first direction being a direction from the second surface toward the first surface, and a width of each of the sub-trenches in the same multi-step trench increasing in sequence in the first direction; forming a first ion implantation region in a surface of the epitaxial layer exposed from the sidewalls and bottom of the multi-tiered trench; forming a sidewall protection structure on a sidewall of at least the first level sub-trench; and forming a first-level metal electrode in the multi-level trench, the first metal electrode further covering a functional area of ​​the first surface and having a Schottky contact with the functional area of ​​the first surface.

[0017] Preferably, in the above manufacturing method, the method of forming the sidewall protection structure includes: forming an insulating dielectric layer, the insulating dielectric layer covering the sidewalls and bottom of the multi-step trench and covering a functional area of ​​the first surface; forming an opening in the insulating dielectric layer in a region corresponding to a bottom of the multi-step trench to expose a portion of the bottom region of the multi-step trench; removing the insulating dielectric layer at the first surface and a portion of the insulating dielectric layer within the multi-step trench, the insulating dielectric layer retained within the multi-step trench being the sidewall protection feature.

[0018] Preferably, in the above manufacturing method, before removing the insulating dielectric layer on the first surface and a part of the insulating dielectric layer in the multi-step trench, further comprising: forming a first metal layer on a bottom of the opening; forming the ohmic contact structure based on the first metal layer. Effect of the Invention

[0019] As can be seen from the above description, in the Schottky diode element and the manufacturing method thereof provided in the technical solution of the present application, the Schottky diode element includes an epitaxial wafer having an epitaxial layer, the epitaxial layer having a first surface and a second surface opposite to each other, the epitaxial wafer having a functional region and trench regions located on both sides of the functional region on the first surface, and a multi-step trench located in the trench region, the multi-step trench having a first ion implantation region in a surface of the epitaxial layer exposed from a sidewall and a bottom of the multi-step trench, the multi-step trench including a plurality of sub-trenches. the plurality of sub-trenches are a first stage sub-trench to an Nth stage sub-trench arranged in a first direction, N being a positive integer greater than 1, the first direction being a direction in which the second surface faces the first surface, the width of each of the sub-trenches in the same multi-step trench increases in the first direction, and a sidewall of at least the first stage sub-trench includes a multi-step trench having a sidewall protection structure and a first metal electrode filling the multi-step trench, the first metal electrode further covering a functional region of the first surface and having a Schottky contact with the functional region of the first surface. The technical solution of the present application solves the problem that early breakdown and leakage problems are likely to occur at the trench corners of the multi-step trench by providing the sidewall protection structure. [Brief description of the drawings]

[0020] In order to more clearly describe the technical solutions in the embodiments of the present application or the related art, the following briefly introduces drawings that may be used in the description of the embodiments or the prior art. It should be apparent that the drawings described below are merely embodiments of the present application, and those skilled in the art can obtain other drawings based on the drawings provided without any creative efforts.

[0021] The structures, ratios, sizes, etc. depicted in the drawings of this specification are all used only to conform to the contents disclosed in the specification and are used for understanding and viewing by persons familiar with this technology, and are not used to limit the operable conditions of this application, and therefore do not have any substantial technical meaning. Any modification of the structures, changes in the ratio relationships, or adjustments in size will not affect the effects that can be generated and the objectives that can be achieved in this application, and all should still be within the scope of the technical content disclosed in this application. [Figure 1] FIG. 1 is a schematic diagram showing the structure of a conventional SiC Schottky diode element. [Diagram 2] FIG. 2 is a structural schematic diagram of a Schottky diode element provided in an embodiment of the present application. [Diagram 3] FIG. 2 is a structural schematic diagram of a Schottky diode element provided in an embodiment of the present application. [Figure 4] 1 is a process flow chart of a method for manufacturing a Schottky diode element provided in an embodiment of the present application. [Diagram 5] 1 is a process flow chart of a method for manufacturing a Schottky diode element provided in an embodiment of the present application. [Figure 6] 1 is a process flow chart of a method for manufacturing a Schottky diode element provided in an embodiment of the present application. [Figure 7] 1 is a process flow chart of a method for manufacturing a Schottky diode element provided in an embodiment of the present application. [Figure 8] 1 is a process flow chart of a method for manufacturing a Schottky diode element provided in an embodiment of the present application. [Figure 9] 1 is a process flow chart of a method for manufacturing a Schottky diode element provided in an embodiment of the present application. [Figure 10] 1 is a process flow chart of a method for manufacturing a Schottky diode element provided in an embodiment of the present application. [Figure 11] 1 is a process flow chart of a method for manufacturing a Schottky diode element provided in an embodiment of the present application. [Figure 12] 1 is a process flow chart of a method for manufacturing a Schottky diode element provided in an embodiment of the present application. [Figure 13] 1 is a process flow chart of a method for manufacturing a Schottky diode element provided in an embodiment of the present application. [Figure 14] 1 is a process flow chart of a method for manufacturing a Schottky diode element provided in an embodiment of the present application. [Figure 15] 1 is a process flow chart of a method for manufacturing a Schottky diode element provided in an embodiment of the present application. [Figure 16] 1 is a process flow chart of a method for manufacturing a Schottky diode element provided in an embodiment of the present application. [Figure 17] 1 is a process flow chart of a method for manufacturing a Schottky diode element provided in an embodiment of the present application. [Figure 18] 1 is a process flow chart of a method for manufacturing a Schottky diode element provided in an embodiment of the present application. [Figure 19] 1 is a process flow chart of a method for manufacturing a Schottky diode element provided in an embodiment of the present application. [Figure 20] 1 is a process flow chart of a method for manufacturing a Schottky diode element provided in an embodiment of the present application. [Figure 21] 1 is a process flow chart of a method for manufacturing a Schottky diode element provided in an embodiment of the present application. [Figure 22] 1 is a process flow chart of a method for manufacturing a Schottky diode element provided in an embodiment of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] Hereinafter, the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some of the embodiments of the present application, and are not all of the embodiments. Based on the embodiments of the present application, all other embodiments that a person skilled in the art can obtain without making creative efforts are all within the scope of protection of the present application.

[0023] In a trench SBD structure, a high electric field region is likely to occur at the bottom of the trench. In particular, if the bottom of the trench comes into direct contact with a metal electrode, a high electric field is likely to occur, causing premature breakdown or leakage of the device at the corners of the trench. Even if a metal electrode is formed directly on the bottom of the trench, a sharp metal tip is likely to be formed. Even if various efforts are made to carve the trench more smoothly, the problem of a high electric field at the bottom persists, making it difficult to stably mass-produce reliable devices.

[0024] In view of this, the technical solution of the present application provides a Schottky diode element and a manufacturing method thereof, and by providing the sidewall protection structure, the problem of premature breakdown or leakage of the element at the corner of the multi-step trench due to a high electric field can be solved.

[0025] Furthermore, an ohmic contact structure can be formed at the bottom of the multi-step trench, so that the first metal electrode is electrically connected to the first ion-implanted region via the ohmic contact structure. In this way, a composite filling structure is formed at the bottom of the multi-step trench, preventing the first metal electrode from directly contacting the bottom of the multi-step trench. This avoids leakage and breakdown problems caused by a high electric field at the trench corner due to the first metal electrode directly contacting the bottom of the multi-step trench, thereby improving the reliability of the device.

[0026] An ohmic contact structure is provided at the bottom of the multi-step trench, and a trench sidewall protection structure is provided on the sidewall of the first-stage sub-trench, thereby forming a composite filling at the bottom of the multi-step trench. This not only prevents direct contact between the first metal electrode and the bottom of the multi-step trench, but also ensures that the bottom of the first metal electrode is surrounded by the sidewall protection structure and the ohmic contact structure, thereby forming a MOS capacitance structure that does not affect the shielding of the Schottky region of the first ion implantation region against the electric field, and can alleviate the high electric field at the bottom of the multi-step trench, thereby preventing early breakdown and leakage at the bottom of the multi-step trench, and improving the manufacturability and reliability of the device.

[0027] In order to make the above objects, features and advantages of the present application more apparent and comprehensible, the present application will be described in more detail below with reference to the drawings and specific embodiments.

[0028] As shown in FIG. 2, FIG. 2 is a structural schematic diagram of a Schottky diode element provided in an embodiment of the present application, and the Schottky diode element shown includes: An epitaxial wafer having an epitaxial layer 21, the epitaxial layer 21 having a first surface S1 and a second surface S2 facing each other, the epitaxial wafer having a functional region S11 and trench regions S12 located on both sides of the functional region S11 on the first surface S1; a multi-step trench 22 located in the trench region S12, the multi-step trench 22 having a first ion implantation region 23 in a surface of the epitaxial layer exposed at a sidewall and a bottom of the multi-step trench 22; the multi-step trench 22 includes a plurality of sub-trenches, the plurality of sub-trenches being a first stage sub-trench to an Nth stage sub-trench in a first direction (a bottom-to-top direction in FIG. 2 ), N being a positive integer greater than 1, the first direction being a direction in which the second surface S2 faces the first surface S1, the width of each of the sub-trenches in the same multi-step trench 22 increasing in order in the first direction, and the sidewall of at least the first stage sub-trench having a sidewall protection structure 25; a first metal electrode 24 filling the multi-step trench 22, the first metal electrode 24 further covering a functional region S11 of the first surface S1 and having a Schottky contact with the functional region S11 of the first surface S1, wherein the contact surface between the first metal electrode 24 and the functional region S11 of the first surface S1 includes the first metal electrode 24 being a Schottky region.

[0029] In the embodiment of the present application, a multi-stage trench 22 is formed in the trench region S12 to form a deep trench, thereby realizing the formation of a deep first ion implantation region 23 in the epitaxial layer 21. When the epitaxial layer 21 is a SiC layer and the first ion implantation region 23 is a P+ doped ion implantation region, a deep P+ ion implantation can be realized in the SiC material without destroying the lattice structure of SiC without needing high energy and high dose ion implantation. In addition, the sidewall of at least the first stage sub-trench is set to have a sidewall protection structure 25, which can provide effective protection for the trench corner at the bottom of the multi-stage trench 22, and solves the problem that the trench corner of the multi-stage trench is prone to early destruction and leakage.

[0030] If the bottom of the multi-step trench 22 is in direct contact with the first metal electrode 24, a high electric field is likely to be generated, causing early breakdown or leakage of the element at the trench corner. By installing the sidewall protection structure 25, the withstand voltage and anti-leakage performance of the trench corner region can be improved to a certain extent.

[0031] In order to further improve the breakdown voltage and leakage resistance in the groove corner region of the element, the Schottky diode element may be further configured as shown in FIG.

[0032] As shown in FIG. 3, FIG. 3 is a structural schematic diagram of a Schottky diode element provided in an embodiment of the present application. Based on the scheme shown in FIG. 2, in the Schottky diode element shown in FIG. 3, the sidewall protection structure 25 has an opening for exposing the bottom of the multi-step trench 22 and an ohmic contact structure 26 located in the opening, where the first metal electrode 24 is electrically connected to the first ion-implanted region 23 at the bottom 22 of the multi-step trench via the ohmic contact structure 25.

[0033] In the scheme shown in FIG. 3 , an ohmic contact structure 26 is provided at the bottom of the multi-step trench 22, and a trench sidewall protection structure 25 is provided on the sidewall of the first-stage sub-trench, thereby forming a composite filling at the bottom of the multi-step trench 22. This not only prevents the first metal electrode 24 from directly contacting the bottom of the multi-step trench 22, but also ensures that the bottom of the first metal electrode 24 is surrounded by the sidewall protection structure 25 and the ohmic contact structure 26, thereby forming a MOS capacitance structure that does not affect the electric field shielding of the Schottky region of the first ion implantation region 23, and can alleviate the high electric field at the bottom of the multi-step trench 22, thereby avoiding premature breakdown and leakage at the bottom of the multi-step trench 22, and improving the manufacturability and reliability of the device.

[0034] In the embodiment of the present application, the epitaxial layer 21 is a SiC layer, and the ohmic contact structure 26 is a metal complex formed on the SiC layer 21. The use of a metal complex as the ohmic contact structure 26 can effectively improve device performance, and enhance the manufacturability and reliability of the device.

[0035] As shown in FIG. 3, the height of the ohmic contact structure 26 is set to be smaller than the height of the first-stage sub-trench in the first direction and smaller than the height of the sidewall protection structure 25. By adopting the thin ohmic contact structure 26, it is possible to meet the filling requirements for the bottom of the multi-stage trench 22, thereby reducing manufacturing costs and improving production efficiency.

[0036] In the Schottky diode element according to the embodiment of the present application, as shown in FIGS. 2 and 3, the height of the sidewall protection structure 25 is equal to or less than the height of the first-stage sub-trench in the first direction.

[0037] Optionally, the sidewall protection structure 25 is a SiO2 layer or a SiN layer. The material of the sidewall protection structure 25 can be selected according to requirements, and is not specifically limited in the embodiments of the present application.

[0038] 2 and 3, the epitaxial wafer includes a semiconductor substrate 20, and the second surface S2 is disposed opposite the semiconductor substrate 20, and has a second metal electrode 27 on the surface of the semiconductor substrate 20 away from the epitaxial layer 21. Here, the first metal electrode 24 is the anode of a Schottky diode element, and the second metal electrode 27 is the cathode of the Schottky diode element.

[0039] Due to the deep depth of the multi-step trench 22, the thickness of the first ion implantation region 23 in the second direction (horizontal direction in FIG. 2) gradually decreases along the first direction, and the second direction is parallel to the first surface S1. In particular, the thickness of the first ion implantation region 23 is the thinnest at a position close to the opening of the multi-step trench 22, and problems such as leakage and leakage or destruction due to electric field collection occur at this position, affecting the manufacturability and reliability of the device. To solve these problems, as shown in FIG. 2 and FIG. 3, the Schottky diode element has a second ion implantation region 28 surrounding the multi-step trench opening in the surface of the epitaxial layer 21 away from the semiconductor substrate 20, and the second ion implantation region 28 contacts the first ion implantation region 23. The second ion implantation region 28 can be a voltage buffer region, and realizes voltage buffering of the opening region of the multi-step trench 22.

[0040] Here, the second ion implantation region 28 and the first ion implantation region 23 are both doped in the opposite direction to the epitaxial layer 21. For example, the epitaxial layer 21 may be an N- (lightly N-type doped) epitaxial layer, and the second ion implantation region 28 and the first ion implantation region 23 may both be P+ ion implantation regions.

[0041] In the technical solution of the present application, the second ion implantation region 28 realizes voltage buffering at the opening region of the multi-step trench 22. The multi-step trench structure can avoid the contradiction between the forward conduction resistance of the device and the Schottky region voltage resistance and surface electric field reliability caused by a single-width trench, further improving the voltage resistance of the SBD device and maintaining a low forward conduction resistance. The second ion implantation region 28 can improve the process tolerance of the device, avoiding the problem of leakage occurring near the opening of the multi-step trench 22 in the Schottky contact process and leakage or destruction caused by electric field gathering, thereby improving the manufacturability and reliability of the device.

[0042] Another embodiment of the present application further provides a method for manufacturing a Schottky diode element, the method being shown in FIGS.

[0043] As shown in FIGS. 4 to 22, FIGS. 4 to 22 are process flow charts of a method for manufacturing a Schottky diode element provided in an embodiment of the present application, and the method includes:

[0044] In step S11, as shown in FIG. 4, an epitaxial wafer having an epitaxial layer 21 is provided.

[0045] The epitaxial layer 21 has opposing first and second surfaces S1 and S2, and the first surface S1 has a functional region S11 and trench regions S12 located on both sides of the functional region S11.

[0046] Here, the epitaxial wafer has a substrate 20, on which the epitaxial layer 21 is formed, and the second surface S2 is disposed opposite to the substrate 20. The substrate 20 may be an N+ (N-type highly doped) SiC substrate. The epitaxial layer 21 is an N- SiC epitaxial layer.

[0047] In step S12, as shown in FIG. 5, a multi-step trench 22 is formed in the trench region S12.

[0048] The multi-step trench includes a plurality of sub-trenches, which are arranged in a first direction from a first stage sub-trench to an Nth stage sub-trench, N being a positive integer greater than 1, the first direction being a direction in which the second surface S2 faces the first surface S1, and in the same multi-step trench 22, the width of each of the sub-trenches increases in the first direction.

[0049] The same multi-step trench 22 has a first sub-trench to an N-th sub-trench arranged in sequence in a first direction, and N is set to be a positive integer greater than 1. The value of N can be set as required, and the present application does not specifically limit it. In the embodiment of the present application, N=2 is taken as an example, that is, the multi-step trench 22 has a two-step trench.

[0050] On both sides of the functional region S11, in the two multi-stage trenches 22, the pitch between the sub-trenches of the i-th stage is L i And L i-1 L i , where i is a positive integer greater than 1 and less than or equal to N. Thus, in the same multi-stage trench 22, the width of the sub-trench of each stage decreases from top to bottom, and L iThe value of can be set according to requirements, and the embodiment of the present application does not specifically limit it. Take N=2 as an example, in two multi-step trenches 22, the pitch between the sub-trench of the first step is L1, the pitch between the sub-trench of the second step is L2, and L1 is greater than L2. In the same multi-step trench 22, the depth of the sub-trench of the i-th step is t i Taking N=2 as an example, in the same multi-stage trench 22, the depth of the first stage sub-trench is t1, and the depth of the i-th stage sub-trench is t2. i The value of can be set according to requirements, and the embodiment of the present application does not specifically limit it.

[0051] An epitaxial wafer is subjected to two or more photolithography and etching processes to form a multi-stage trench having two or more stages. Here, after the epitaxial wafer enters a process production line, an alignment mark needs to be made for alignment of the subsequent photolithography process. The technical solution of the present application manufactures a first stage sub-trench at the same time as making the alignment mark, and does not require an additional etching process, but multiplexes the etching process of the alignment mark to manufacture the first stage sub-trench, thereby reducing the manufacturing cost.

[0052] The multi-step trench 22 can be formed based on the mask layer 30 disposed on the first surface S1. The embodiment of the present application does not specifically limit the manner of the multi-step trench 22. After the multi-step trench 22 is formed, the mask layer 30 on the first surface S1 is removed.

[0053] In step S13, a first ion implantation region 23 is formed in the surface of the epitaxial layer exposed from the sidewall and bottom of the multi-step trench 22, as shown in FIGS.

[0054] Here, step S13 specifically includes:

[0055] First, as shown in Fig. 6, a sacrificial layer 31 including a first silicon dioxide layer 311, a polysilicon layer 312 and a second silicon dioxide layer 313 stacked in sequence is deposited on a first surface S1. After the sacrificial layer 31 is patterned in a subsequent process, it can be used as a mask structure for ion implantation. The P-type doping of SiC material generally adopts high-energy Al ion implantation, and the polysilicon layer 312 can form a mask effect for subsequent ion implantation.

[0056] 7, similarly to photolithography and dry etching, an opening is formed in the second silicon dioxide layer 313, and the first ion implantation region 23 is formed by subsequent ion implantation. First, an etching gas with a high selectivity of polycrystalline silicon, which is the etching silicon oxide, such as at least one of CF4, CHF3, CH2F2, or C4F8 is adopted to etch the second silicon dioxide layer 313 with a mixed gas formed of oxygen, nitrogen, and argon gas, and the etching is stopped on the surface of the polycrystalline silicon layer 312. The opening in the second silicon dioxide layer 313 is determined based on the mask substrate 32.

[0057] Furthermore, as shown in FIG. 8, an etching gas having a high selectivity to silicon oxide, which is polycrystalline silicon, such as a mixed gas of HBr and Ar, is used to etch the polycrystalline silicon layer 312.

[0058] 9, a gas having good etching properties for silicon oxide, such as at least one of CF4, CHF3, CH2F2, and C4F8, is used to etch the first silicon dioxide layer 311 together with a mixed gas formed of oxygen, nitrogen, and argon gas. Alternatively, an F-based gas such as CHF3 or CF4 is used to etch the first silicon dioxide layer 311.

[0059] Furthermore, as shown in FIG. 10, based on the patterned sacrificial layer 31, P ion implantation is performed on the sidewalls and bottom of the multi-step trench 22 to form a first ion implantation region 23, where the implanted ions are preferably Al ions.

[0060] Finally, the remaining sacrificial layer 31 is removed, as shown in Fig. 11. Optionally, dry etching and wet etching processes are employed to remove the remaining sacrificial layer 31 on the first surface S1.

[0061] Optionally, after forming the first ion implantation region 23 and before forming the sidewall protection structure 25, the manufacturing method further includes performing anneal activation and lattice repair on the ion implantation region. By adopting carbon film protection commonly used in silicon carbide device processes, anneal activation and lattice repair are performed on the implanted P-type ions, such as Al ions, in a high temperature furnace tube at 1500°C to 1900°C for 10 minutes to 30 minutes.

[0062] By providing the pattern structure of the sacrificial layer 31, the ion implantation window is larger than the opening in the first surface S1 of the multi-step trench 22, and a portion of the first surface S1 around the opening in the first surface S1 of the multi-step trench 22 is exposed. In this way, ion implantation can be performed to form the first ion implantation region 23, and at the same time, the second ion implantation region 28 can be simultaneously formed in the first surface S1.

[0063] In step S14, as shown in FIGS. 12 to 22, a sidewall protection structure 25 is formed on the sidewall of at least the first-stage sub-trench.

[0064] In step S14, the method includes the steps of forming an insulating dielectric layer, the insulating dielectric layer covering the sidewalls and bottom of the multi-step trench and covering a functional area of ​​the first surface; forming an opening in the insulating dielectric layer in a region corresponding to the bottom of the multi-step trench to expose a portion of the bottom region of the multi-step trench; and removing the insulating dielectric layer on the first surface and a portion of the insulating dielectric layer in the multi-step trench, the insulating dielectric layer retained in the multi-step trench being the sidewall protection structure.

[0065] Before removing the insulating dielectric layer at the first surface and a portion of the insulating dielectric layer within the multi-step trench, the method further includes forming a first metal layer at a bottom of the opening and forming the ohmic contact structure based on the first metal layer.

[0066] Specifically, the implementation method of step S14 includes the following:

[0067] First, as shown in FIG. 12, an insulating dielectric layer 250 is formed. The insulating dielectric layer is SiO2 or SiN. The insulating dielectric layer 250 covers the first surface S1 and the sidewall and bottom of the multi-step trench 22. The insulating dielectric layer 250 can be manufactured by adopting a CVD process or an LPCVD process, and the insulating dielectric layer 250 having good trench step coverage can be formed. As shown in FIG. 13, FIG. 13 is an SEM image of the multi-step trench 22 covered with the insulating dielectric layer 250, and as can be seen from FIG. 13, the insulating dielectric layer 250 having good trench step coverage can be formed on the surface of the multi-step trench 22.

[0068] 14, an opening is formed at the bottom of the insulating dielectric layer 250 corresponding to the multi-step trench 22, and a part of the bottom region of the multi-step trench 22 is exposed. The insulating dielectric layer 250 at the bottom of the multi-step trench 22 is opened by photolithography and etching, which makes it easy to form the ohmic contact structure 26 in the subsequent process. An opening can be formed in the insulating dielectric layer 250 based on the mask substrate 33. When forming the opening in the insulating dielectric layer 250, the etching depth to the lower epitaxial layer 21 is 500 nm or less.

[0069] 15, a metal layer 260 is deposited to cover the surface of the insulating dielectric layer 250 away from the epitaxial wafer and to cover the bottom of the multi-step trench 22 exposed from the insulating dielectric layer 250. A PVD or deposition process can be used to form the metal layer 260. The metal layer 260 is a material that can form a good ohmic contact with SiC through a complexation reaction, such as Ni.

[0070] 16, after forming the metal layer 260, a rapid annealing process (RTA) is performed, for example, at 800 to 1100° C. for 30 seconds to 5 minutes, so that a metal silicide reaction occurs at the contact portion between the metal layer 260 at the bottom of the trench and silicon carbide, forming a metal complex and converting it into an ohmic contact structure 26, and the metal layer 260 on the surface of the insulating dielectric layer 250 does not undergo a metal silicide reaction because the insulating dielectric layer 250 is separated. In the embodiment of the present application, the ohmic contact structure is a metal silicide.

[0071] Furthermore, as shown in Fig. 17, dry etching or wet etching, such as Ni etching solution, is used to etch the metal layer 260 where no metal silicide reaction occurs, leaving only the ohmic contact structure 26 at the bottom of the trench. As shown in Fig. 18, Fig. 18 is a SEM image after the ohmic contact structure 26 is formed. As can be seen from Fig. 18, a good ohmic contact effect can be formed.

[0072] Finally, as shown in Fig. 19, an etching method such as a combination of dry etching and wet etching is used to remove the insulating dielectric layer 250 in the planar region above the first surface, and the insulating dielectric layer 250 near the opening region in the multi-step trench 22, and at least the insulating dielectric layer 250 on the sidewall of the first sub-trench is retained. A method for forming an isolation ring in a CMOS process can be used to etch the insulating dielectric layer 250 to form the sidewall protection structure 25. As shown in Fig. 20, Fig. 20 is an SEM image after the sidewall protection structure 25 is formed, and as can be seen from Fig. 20, a sidewall protection structure 25 with a good shape can be formed at the bottom of the multi-step trench.

[0073] In addition, the degree of etching of the insulating dielectric layer 250 in the multi-stage trench 22 can be controlled, and a sidewall protection structure 25 with a different coating can be formed, which is not limited to covering only the sidewall of the first stage trench, but can also cover the sidewall or step structure of other sub-trenches above it.

[0074] In step S15, a first-stage metal electrode 24 is formed in the multi-stage trench, and the first metal electrode 24 further covers the functional region S11 of the first surface S1 and has a Schottky contact with the functional region S11 of the first surface S1, finally forming the Schottky diode element shown in Fig. 3. As shown in Fig. 21, Fig. 21 is a SEM image of the Schottky diode element finally formed by adopting the manufacturing method of the embodiment of the present application.

[0075] In step S15, a process such as PVD or evaporation can be adopted to form a first metal electrode 24 on the first surface S1, and a second metal electrode 27 can be formed on the lower surface of the semiconductor substrate 20. The first metal electrode 24 can be a composite metal layer structure formed of two or more metals, such as Ti or Al, or Ti / TiW / Mo / Pt / Al. The first metal electrode 24 forms a non-ohmic contact with the sidewall of the multi-step trench 22 and forms an ohmic contact with the bottom of the multi-step trench 22. The first metal electrode 24 needs to undergo RTA treatment and forms a Schottky contact with the functional region S11. After the first metal electrode 24 is formed, an electrode metal material can be deposited and etched by a process such as PVD to form a land, and the metal material can be a composite metal layer structure formed of two or more metals, such as Ti, Al, or Ti / TiW / Mo / Pt / Al.

[0076] The above manufacturing method will be described by taking the manufacturing of the element structure shown in Fig. 3 as an example. This obviously corresponds to the element structure shown in Fig. 2, and the manufacturing method thereof can be obtained by referring to the above process flow, and the description thereof will be omitted in the embodiments of the present application.

[0077] In the embodiment of the present application, it is not limited to fabricating a multi-step trench in the trench region S12, and a single-step trench may also be adopted. As shown in Fig. 22, Fig. 22 is a SEM image showing a single-step trench forming an ohmic contact structure and a sidewall protection structure.

[0078] As can be seen from the above description, the manufacturing method described in the technical solutions of the embodiments of the present application can form a multi-step trench Schottky diode element with sidewall protection (multi-step trench junction barrier diode with bottom corner spacer protection) cell structure, and by constructing a multi-step trench junction barrier Schottky diode element design with a sidewall protection structure in a silicon carbide SBD element cell, it is possible to avoid reliability problems such as leakage and breakdown caused by a high electric field at the trench corner due to a metal layer at the trench bottom of a trench JBS element directly contacting the trench corner at the bottom of the trench. By providing sidewall protection with a dielectric layer structure at the trench corners at the bottom of the multi-stage trench JBS, direct contact between the metal and the trench corners where the strong electric field at the bottom of the trench converges is avoided, which is advantageous to improving the reliability of trench-based devices. The metal layer filled in the trench and the sidewall protection structure form a MOS capacitance structure, which does not affect the shielding of the P-type region against the Schottky region electric field, and can mitigate the high electric field at the relatively weak trench corners at the bottom trench, thereby avoiding early breakdown and leakage at the bottom and improving the manufacturability and reliability of the device.

[0079] Each embodiment in this specification will be described in a progressive, parallel, or combination of progressive and parallel manner, and each embodiment will mainly describe the differences from other embodiments, and the same or similar parts between the embodiments may be referred to each other.

[0080] In the description of the present application, it should be understood that the drawings and the description of the embodiments are illustrative but not restrictive. Throughout the embodiments of the description, the same drawing symbols indicate the same structures. Also, the drawings may exaggerate the thickness of some layers, films, panels, regions, etc., for ease of understanding and explanation. Also, when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it is understood that the element may be directly on the other element or there may be intermediate elements. Also, "on" means that the element is positioned on or below the other element, but does not essentially mean that the element is positioned above the other element in the direction of gravity.

[0081] The indicated orientations or positions, such as the terms "upper", "lower", "top", "bottom", "inside", "outside", etc., are based on the orientations or positions shown in the drawings and are for ease of explanation and simplicity of description of the present application, and do not indicate or suggest that the devices or elements shown have a particular orientation or must be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. When one component is considered to be "connected" to another component, there may be a mixture of components that are directly connected to the other component or that are centrally located.

[0082] Still further, in this specification, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that any such actual relationship or order exists between those entities or operations. Also, the terms "comprise", "comprises", or any other variation thereof, are intended to include a non-exclusive inclusion, whereby an article or device that includes a set of elements not only includes those elements, but also includes other elements not expressly recited, or further includes elements inherent in such article or device. Absent more limitations, an element qualified by the sentence "comprises a ..." does not exclude the presence of further identical elements in the article or device that includes the said elements.

[0083] Given the above description of the disclosed embodiments, those skilled in the art can realize or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Thus, the present application is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An epitaxial wafer having an epitaxial layer, the epitaxial layer having a first surface and a second surface opposite to each other, the first surface having a functional region and trench regions located on both sides of the functional region; a multi-step trench located in the trench region, the multi-step trench having a first ion implanted region in a surface of the epitaxial layer exposed at a sidewall and a bottom of the multi-step trench; the multi-step trench includes a plurality of sub-trenches, the plurality of sub-trenches being a first stage sub-trench to an Nth stage sub-trench in sequence in a first direction, N being a positive integer greater than 1, the first direction being a direction in which the second surface faces the first surface, a width of each of the sub-trenches in the same multi-step trench successively increasing in the first direction, and a sidewall of at least a first stage sub-trench having a sidewall protection structure; a first metal electrode filling the multi-step trench, the first metal electrode further covering a functional region of the first surface and having a Schottky contact with the functional region of the first surface; 1. A Schottky diode element comprising:

2. The sidewall protection structure includes an opening for exposing a bottom portion of the multi-stage trench; an ohmic contact structure located in the opening; wherein the first metal electrode is electrically connected to the first ion implantation region at the bottom of the multi-step trench via the ohmic contact structure.

2. The Schottky diode element according to claim 1 .

3. the epitaxial layer is a SiC layer; The ohmic contact structure is a metal complex formed based on the SiC layer.

3. The Schottky diode element according to claim 2.

4. a height of the ohmic contact structure in the first direction that is less than a height of the first-level sub-trench and less than a height of the sidewall protection structure; 3. The Schottky diode element according to claim 2.

5. a height of the sidewall protection structure in the first direction that is equal to or less than a height of the first level sub-trench; 2. The Schottky diode element according to claim 1 .

6. The sidewall protection structure is made of SiO ２ layer or a SiN layer; 2. The Schottky diode element according to claim 1 .

7. the epitaxial wafer includes a semiconductor substrate, the second surface being disposed opposite the semiconductor substrate; a second metal electrode on a surface of the semiconductor substrate away from the epitaxial layer; 2. The Schottky diode element according to claim 1 .

8. a second ion implant region in the first surface surrounding the multi-tiered trench opening, the second ion implant region in contact with the first ion implant region; wherein the second ion implantation region and the first ion implantation region are both doped in the opposite direction to the epitaxial layer.

8. The Schottky diode element according to claim 1, wherein the Schottky diode element is a Schottky diode having a thickness of 100 nm or less.

9. providing an epitaxial wafer having an epitaxial layer having opposing first and second surfaces, the epitaxial layer having a functional region in the first surface and trench regions on either side of the functional region; forming a multi-step trench in the trench region, the multi-step trench including a plurality of sub-trenches, the plurality of sub-trenches being a first sub-trench to an Nth sub-trench in sequence in a first direction, N being a positive integer greater than 1, the first direction being a direction from the second surface toward the first surface, and a width of each of the sub-trenches in the same multi-step trench increasing in sequence in the first direction; forming a first ion implantation region in a surface of the epitaxial layer exposed from the sidewalls and bottom of the multi-tiered trench; forming a sidewall protection structure on a sidewall of at least the first level sub-trench; forming a first level metal electrode in the multi-level trench, the first metal electrode further covering a functional area of ​​the first surface and having a Schottky contact with the functional area of ​​the first surface; 2. A method for manufacturing a Schottky diode element comprising the steps of:

10. The method for forming the sidewall protection structure includes: forming an insulating dielectric layer, the insulating dielectric layer covering the sidewalls and bottom of the multi-step trench and covering a functional area of ​​the first surface; forming an opening in the insulating dielectric layer in a region corresponding to a bottom of the multi-step trench to expose a portion of the bottom region of the multi-step trench; removing the insulating dielectric layer at the first surface and a portion of the insulating dielectric layer within the multi-step trench, the insulating dielectric layer retained within the multi-step trench being the sidewall protection feature; The method according to claim 8 .

11. prior to removing the insulating dielectric layer at the first surface and the portion of the insulating dielectric layer within the multi-step trench, further comprising: forming a first metal layer on a bottom of the opening; forming the ohmic contact structure based on the first metal layer. The method according to claim 10 .

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