Semiconductor device and method for fabricating same

Abstract

Some embodiments of the present disclosure provide a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate, the surface of which has a first region, a second region, and a third region; a first dielectric layer applied to the first region and the third region of the substrate; a gate electrode, the gate electrode being coupled to the substrate and including a gate cap region and a contact region in contact with the second region of the substrate, the gate cap region being spaced apart from the first region of the substrate by a first distance via the first dielectric layer; and a second dielectric layer applied outside the gate electrode and the first dielectric layer, the second dielectric layer being spaced apart from the substrate by a second distance in the third region, the second distance being smaller than the first distance. By making the first distance that separates the gate cap region from the substrate larger than the second distance that separates the second dielectric layer from the substrate, the capacitance value of the parasitic capacitance can be reduced without changing other design structures. In this way, the gain characteristics of the semiconductor device at high frequencies can be improved.

Description

[Technical field]

[0001] TECHNICAL FIELD This disclosure relates to the field of semiconductor device fabrication, and more particularly to semiconductor devices having high gain and methods of fabricating same. [Background technology]

[0002] The semiconductor industry has experienced three generations of material changes. The first generation semiconductor materials include silicon (Si) and germanium (Ge). The second generation semiconductor materials include compound semiconductor materials such as gallium arsenide (GaAs) and indium antimonide (InSb). In recent years, the third generation compound semiconductor materials, represented by gallium nitride (GaN) and silicon carbide (SiC), have attracted widespread attention due to their excellent material properties. Gallium nitride-based devices have been widely used in the field of radio frequency devices due to the advantages of gallium nitride-based devices such as high mobility, strong breakdown resistance, and good heat dissipation properties.

[0003] A typical radio frequency gallium nitride device uses source-connected field plate technology to modulate the electric field and capacitance distribution between the gate and drain to achieve a certain high frequency gain index. However, based on the current structure of gallium nitride semiconductor devices in the conventional industry, there is a problem that the gain enhancement space is not sufficient. Summary of the Invention

[0004] The present disclosure relates to a technical solution for a semiconductor device, and in particular provides a semiconductor device and a method for fabricating the same. [Means for solving the problem]

[0005] According to a first aspect of the present disclosure, a semiconductor device is provided, the semiconductor device comprising: a substrate, the surface of which has a first region, a second region, and a third region; a first dielectric layer applied to the first region and the third region of the substrate; a gate electrode, the gate electrode being coupled to the substrate and including a gate cap region and a contact region in contact with the second region of the substrate, the gate cap region being spaced apart from the first region of the substrate by a first distance via the first dielectric layer; and a second dielectric layer applied outside the gate electrode and the first dielectric layer, the second dielectric layer being spaced apart from the substrate by a second distance in the third region, the second distance being smaller than the first distance.

[0006] By making the first distance separating the gate cap region from the substrate larger than the second distance separating the second dielectric layer from the substrate, the capacitance value of the parasitic capacitance can be reduced without modifying other design structures, thus improving the gain characteristics of the semiconductor device at high frequencies.

[0007] In some implementations, the difference between the first and second intervals is 20 nm to 500 nm. According to different requirements, the aforementioned range provides the flexibility to fabricate the semiconductor device.

[0008] In one implementation, the thermal component further includes a first dielectric layer including a blanket dielectric layer disposed in the first region and the third region, and a thickened dielectric layer disposed between the blanket dielectric layer and the first region or between the blanket dielectric layer and the gate cap region, the thickened dielectric layer having a thickness between 20 nm and 500 nm. The blanket dielectric layer and the thickened dielectric layer may be made of the same material or different materials. This can improve the flexibility of the fabrication of the semiconductor device. In addition, the fabrication process of the semiconductor device can take into account cost and reliability.

[0009] In one implementation, the semiconductor device further comprises a field plate locally applied outside the second dielectric layer, where the spacing between the field plate and the gate electrode is substantially the same as the spacing between the field plate and the first dielectric layer. Using source-connected field plate techniques, a particular high frequency gain figure can be achieved by modulating the electric field and capacitance distribution between the gate and drain.

[0010] In some implementations, the substrate comprises one of the following materials: silicon carbide, gallium nitride, gallium nitride on silicon carbide, gallium nitride on sapphire, gallium nitride on silicon, aluminum indium nitride, and aluminum nitride. A variety of materials can be used to fabricate the substrate, which allows for more flexibility in the fabrication of semiconductor devices.

[0011] In one implementation, the first dielectric layer or the second dielectric layer includes at least one of the following materials: silicon nitride, silicon oxynitride, silicon dioxide, aluminum nitride, aluminum oxide, and titanium dioxide. Similarly, multiple materials may be used to fabricate the first dielectric layer or the second dielectric layer, which provides more flexibility in fabricating semiconductor devices.

[0012] According to a second aspect of the present disclosure, a fabrication method for a semiconductor device is provided. The method includes the steps of: providing a substrate, the surface of which has a first region corresponding to a gate cap region of a gate electrode of the semiconductor device, a second region corresponding to a contact region of the gate electrode, and a third region other than the first and second regions; applying a first dielectric layer to the first and third regions; applying a gate electrode, whereby the contact region is in contact with the substrate and the gate cap region is spaced from the substrate by a first distance; and applying a second dielectric layer outside the gate electrode and the first dielectric layer, whereby in the third region, the second dielectric layer is spaced from the substrate by a second distance, the second distance being smaller than the first distance. The fabrication method can reliably fabricate a semiconductor device with high gain characteristics at high frequencies.

[0013] In some implementations, the method further includes locally applying a field plate to the outside of the second dielectric layer, where the spacing between the field plate and the gate electrode is substantially the same as the spacing between the field plate and the first dielectric layer. A semiconductor device thus fabricated can have a required high frequency gain index.

[0014] In some implementations, applying the first dielectric layer includes applying a thickened dielectric layer to the first region and the second region, applying a blanket dielectric layer to the third region and outside the thickened dielectric layer, and removing the blanket dielectric layer and the thickened dielectric layer outside the second region to expose the second region of the substrate.

[0015] In some implementations, applying the thickened dielectric layer includes applying the thickened dielectric layer over the entire substrate and removing the thickened dielectric layer outside the third region of the substrate to expose the third region.

[0016] In some implementations, applying the thickened dielectric layer includes applying photoresist to a third region of the substrate, applying a thickened dielectric layer to the first and second regions of the substrate and outside the photoresist, and removing the photoresist to expose the third region of the substrate.

[0017] In some implementations, applying the first dielectric layer and applying the gate electrode include applying a blanket dielectric layer outside the entire substrate, applying a thickened dielectric layer outside the blanket dielectric layer, removing the blanket dielectric layer and the thickened dielectric layer outside the second region to expose a second region of the substrate, applying the gate electrode, and using the gate electrode as a self-aligned mask to remove the thickened dielectric layer outside a third region.

[0018] In some implementations, the steps of applying the first dielectric layer and applying the gate electrode include applying the first dielectric layer outside the entire substrate, the first dielectric layer having a first thickness, the first thickness being equal to the first spacing; removing the first dielectric layer outside the second region to expose a second region of the substrate; applying the gate electrode; and using the gate electrode as a self-aligned mask to remove a portion of the first dielectric layer in a thickness direction outside a third region, whereby the first dielectric layer in the third region has a second thickness that is smaller than the first thickness, and the second thickness is equal to the second spacing.

[0019] It should be understood that the contents described in the "Summary" section are not intended to limit the key or important features of the present disclosure, nor are they intended to limit the scope of the present disclosure. The following description will facilitate an understanding of other features of the present disclosure.

[0020] The above and other objects, features, and advantages of embodiments of the present disclosure will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, in which several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation. [Brief description of the drawings]

[0021] [Figure 1] FIG. 1 exemplarily illustrates a diagram of a structure of a semiconductor device in a conventional solution; [Diagram 2] FIG. 1 is a diagram of a structure of a semiconductor device according to one embodiment of the present disclosure. [Diagram 3] 1 is a flow chart of a fabrication method for a semiconductor device according to one embodiment of the present disclosure. [Figure 4] 1A-1D are diagrams of stages in a process for making a semiconductor device according to different embodiments of the present disclosure. [Diagram 5] 1A-1D are diagrams of stages in a process for making a semiconductor device according to different embodiments of the present disclosure. [Figure 6] 1A-1D are diagrams of stages in a process for making a semiconductor device according to different embodiments of the present disclosure. [Figure 7] 1A-1D are diagrams of stages in a process for making a semiconductor device according to different embodiments of the present disclosure. [Figure 8] 1A-1D are diagrams of stages in a process for making a semiconductor device according to different embodiments of the present disclosure. [Figure 9] 1A-1D are diagrams of stages in a process for making a semiconductor device according to different embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] Throughout the accompanying drawings, the same or similar reference numbers represent the same or similar components.

[0023] Hereinafter, the principles and intent of the present disclosure will be described with reference to some exemplary embodiments shown in the accompanying drawings. It should be understood that these specific embodiments are merely described to enable those skilled in the art to better understand and practice the present disclosure, and are not intended to limit the scope of the present disclosure in any way. In the following description and claims, unless otherwise defined, all technical and scientific terms used herein have the meanings commonly understood by those skilled in the art to which the present disclosure belongs.

[0024] The term "comprising" and similar terms as used herein should be understood as open inclusion, i.e., "including, but not limited to." The term "based on" should be understood as "based at least in part on." The term "one embodiment" or "this embodiment" should be understood as "at least one embodiment." Terms such as "first," "second," and the like, can refer to different objects or the same object, and are used merely to distinguish the objects referred to, and do not imply a particular spatial order, temporal order, order of importance, or the like, of the objects referred to.

[0025] The term "circuitry" as used herein refers to one or more of: (a) hardware circuitry only implementations (such as analog and / or digital circuitry only implementations); (b) (where applicable) (i) combinations of analog hardware circuitry and / or digital hardware circuitry with software / firmware; and (ii) combinations of hardware circuitry and software, such as hardware processors and any portion of software (including digital signal processors, software, and memory that cooperate to enable an apparatus, such as a communication device or another electronic device, to perform various functions); and (c) hardware circuitry and / or processors, such as a microprocessor or portion of a microprocessor, that require software (such as firmware) to operate, but may not have software if software is not required for operation. The definition of circuitry is applicable to all usage scenarios of the term in this application (including the claims). In another example, the term "circuitry" as used herein also encompasses a hardware circuit or processor (or processors), or a portion of a hardware circuit or processor, or an associated software or firmware only implementation. For example, where applicable to particular claim elements, the term "circuitry" also encompasses a baseband integrated circuit or a processor integrated circuit, a network device, a terminal device, or a similar integrated circuit in another device.

[0026] Some semiconductor devices, such as gallium nitride semiconductor devices, are widely used in the field of radio frequency devices due to the advantages of semiconductor devices such as high mobility, strong breakdown resistance, and good heat dissipation characteristics. These semiconductor devices have high index requirements for gain characteristics at high frequencies. The gain characteristics at high frequencies mainly depend on whether the parasitic capacitance can perform efficient and rapid charging and discharging actions with the signal under high frequency operating conditions. At present, the industry generally reduces the capacitance value of the output capacitance by modifying the passivation layer under the field plate metal to modulate the channel capacitance under bias voltage. However, simply adjusting the parameters of the passivation layer may cause other adverse effects, such as electrostatic discharge (ESD) breakdown, metal-insulator-metal (MIM) capacitor breakdown, and degradation of breakdown characteristics.

[0027] Specifically, some problems in the conventional solution are described using an example in which a radio frequency gallium nitride device is used as the semiconductor device referred to in this application. It should be understood that in addition to the radio frequency gallium nitride device, the semiconductor device referred to in this specification may also be any other suitable semiconductor device. This will not be described in detail below. FIG. 1 shows a typical radio frequency gallium nitride semiconductor device. The semiconductor device uses a source-connected field plate technology. In the conventional solution, the electric field and capacitance distribution between the gate and the drain are modulated to achieve a certain high frequency gain index. As shown in FIG. 1, the conventional semiconductor device generally includes a substrate 501, a first dielectric layer 502, a gate electrode 503, a second dielectric layer 504, and a source-connected field plate 505. The gate electrode 503 and the field plate 505 are made of a metal material. In the semiconductor device, it is generally necessary to adjust three capacitances C1, C2, and C3 to optimize the gain index.

[0028] C1 represents the intrinsic capacitance between the gate and drain, and its determining factor is the length of the gate electrode. C2 represents the parasitic capacitance between the gate cap and drain, and its determining factors include the gate cap length of the gate electrode 503, the thickness of the first dielectric layer 502 (i.e., the distance between the gate cap and the substrate 501), and the dielectric constant of the first dielectric layer 502. C3 represents the capacitance under the field plate, and its determining factors include the length of the field plate, the position of the field plate, and the thickness and dielectric constant of the first dielectric layer 502 and the second dielectric layer 504.

[0029] In general, on the premise that the material of the substrate 501 is fixed, the parameters of the dielectric constant and thickness of the material of the first dielectric layer 502 and the second dielectric layer 504 are adjusted to generally affect the capacitance values ​​of the capacitors C1, C2, and C3 to further optimize the gain index. Specifically, in the semiconductor device shown in FIG. 1, in order to obtain a lower output capacitance and increase the gain, it is generally necessary to reduce the capacitances of C1 and C2 and increase the capacitance of C3.

[0030] However, it is obvious that, if the dielectric material is not changed, the thickness of the first dielectric layer 502 must be increased to reduce the capacitance of C2. However, as the thickness of the first dielectric layer 502 increases, the passivation thickness under the field plate 505 also increases, resulting in a decrease in the capacitance value of the capacitance C3. Therefore, simply increasing the thickness of the first dielectric layer 502 does not match the expected results and does not allow gain control to be achieved.

[0031] Similarly, the capacitance value of the capacitor C2 can be reduced by reducing the dielectric constant of the first dielectric layer 502, but the capacitance value of the capacitor C3 also becomes smaller. Therefore, there is a bottleneck in simply adjusting the physical properties such as the thickness and dielectric constant of the first dielectric layer 502 to increase the gain of the device.

[0032] If only the capacitance value of the capacitance C1 is to be adjusted, it is necessary to adjust it by adjusting the size of the gate electrode 503. However, the size of the gate electrode 503 is limited by the exposure limit of the lithography machine and cannot be adjusted greatly. Therefore, the adjustment of the capacitance value of the capacitance C1 and the increase in the gain of the device are extremely limited. In addition, the thickness of the second dielectric layer 504 is thinned to make it easier to increase the capacitance value of the capacitance C3 and increase the gain. However, when the second dielectric layer 504 is thinned, the distance between the gate electrode 503 and the field plate 505 is also shortened, which causes a problem that the withstand voltage characteristics between the gate electrode 503 and the field plate 505 are poor.

[0033] In addition, in the semiconductor device structure shown in FIG. 1, a transverse electric field stress distribution exists under a high voltage reverse bias stress state. In the transverse electric field, a high electric field peak is likely to occur at the position corresponding to the gate cap of the gate electrode 503 and the field plate 505. Under continuous high electric field stress, the time dependent dielectric breakdown (TDDB) phenomenon is likely to occur in the dielectric layer under the gate cap at the position corresponding to the electric field peak, resulting in a high reliability risk.

[0034] To solve or at least partially solve the above-mentioned or other potential problems present in semiconductor devices, embodiments of the present disclosure provide a semiconductor device 100 and a method for fabricating the same. FIG. 2 is a diagram of a structure of a semiconductor device 100 according to an embodiment of the present disclosure. As shown in FIG. 2, the semiconductor device 100 according to this embodiment of the present disclosure generally includes a substrate 101, a first dielectric layer 102, a gate electrode 103, and a second dielectric layer 104. The gate electrode 103 includes a portion that directly contacts the substrate 101 (hereinafter referred to as a contact region 1031) and a portion that is separated from the substrate 101 via the first dielectric layer 102 (hereinafter referred to as a gate cap region 1032). There are a number of different regions on the surface of the substrate 101 that correspond to the first dielectric layer 102, and the contact region 1031 and gate cap region 1032 of the gate electrode 103, respectively. In the following description, for convenience of explanation, these regions include a first region 1011 corresponding to the gate cap region 1032 of the gate electrode 103, a second region 1012 corresponding to the contact region 1031 of the gate electrode 103, and a third region 1013 other than the first region 1011 and the second region 1012. Here, the "corresponding relationship" refers to a region covered by a convex portion of the region (contact region 1031 and gate cap region 1032) corresponding to the gate electrode 103 in the vertical direction shown in FIG.

[0035] From FIG. 2, it can be seen that the first dielectric layer 102 is applied to the first region 1011 and the third region 1013 of the substrate 101. In this specification, "applying" may refer to disposing the first dielectric layer 102 in the corresponding region by using any suitable process step or steps, such as deposition, which will be further described below. The gate electrode 103 is bonded to the substrate 101, the contact region 1031 of the gate electrode 103 contacts the second region 1012 of the substrate 101, and the gate cap region 1032 is spaced apart from the first region 1011 of the substrate 101 by a certain distance (hereinafter referred to as the first distance D1 for ease of explanation) via the first dielectric layer 102. The second dielectric layer 104 is applied outside the gate electrode 103 and the first dielectric layer 102. Here, outside means that the second dielectric layer 104 covers the gate electrode 103 and the first dielectric layer 102. In the third region 1013, the second dielectric layer 104 is spaced apart from the substrate 101 by a second distance D2.

[0036] Unlike the conventional semiconductor device, in the semiconductor device 100 according to this embodiment of the present application, the second distance D2 is smaller than the first distance D1. This further increases the thickness between the gate cap and the substrate, which affects the parasitic capacitance C2 as mentioned above. In this way, the parasitic capacitance C2 is reduced. In addition, since the increase in the thickness of the first dielectric layer 102 is only kept in the gate cap region 1032 of the gate electrode and does not extend to other regions, the capacitance value of the capacitance C3 can still be maintained at a high level, which can eliminate the above-mentioned conflict caused by adjusting the capacitance values ​​of the capacitances C1, C2, and C3. In this way, the gain of the semiconductor device 100 can be effectively increased.

[0037] In addition, by only increasing the thickness of the first dielectric layer 102 corresponding to the gate cap region 1032 (i.e., the first region 1011), the potential and electric field distributions near the drain end of the gate electrode 103 can be readjusted. In this way, the electric field stress at the original site where TDDB breakdown is likely to occur is effectively weakened, thereby improving the overall reliability of the semiconductor device 100.

[0038] In some embodiments, as shown in FIG. 2, the semiconductor device 100 further includes a field plate 105. The field plate 105 is locally applied outside the second dielectric layer 104 to form a structure of a source-connected field plate 105. Since the second dielectric layer 104 has a substantially constant thickness, the vertical spacing between the field plate 105 and the gate electrode 103 and the vertical spacing between the field plate 105 and the first dielectric layer 102 are substantially the same. In this way, with respect to the increase in the thickness of the first dielectric layer 102 corresponding to the aforementioned gate cap region 1032, the parasitic capacitance of the gate electrode region is reduced. In addition, the capacitance value of the metal-to-channel capacitance of the field plate 105 is increased, which can more effectively increase the gain of the semiconductor device 100.

[0039] In some embodiments, the difference between the first distance D1 and the second distance D2 may be in the range of 20 nm to 500 nm, including the end values ​​of 20 nm and 500 nm. In other words, the thickness of the first dielectric layer 102 corresponding to the first region 1011 or the gate cap region 1032 of the substrate 101 is increased by a value of 20 nm to 500 nm. The specific thickness here can be appropriately selected from this range based on various aspects such as the required stability and cost of the semiconductor device 100, thereby improving the flexibility and cost-effectiveness in fabricating the semiconductor device 100.

[0040] The difference between the first distance D1 and the second distance D2 may be implemented by using a thickened dielectric layer 1021 of the first dielectric layer 102. The thickened dielectric layer 1021 is in the first dielectric layer 102 and is disposed in a portion corresponding to the first region 1011. In addition to the thickened dielectric layer 1021, the first dielectric layer 102 further includes a blanket dielectric layer 1022. The blanket dielectric layer 1022 is disposed in the first region 1011 and the third region 1013 of the substrate 101. In some embodiments, the blanket dielectric layer 1022 and the thickened dielectric layer 1021 may be formed by using the same dielectric material in the same fabrication step or different fabrication steps. In some alternative embodiments, the blanket dielectric layer 1022 and the thickened dielectric layer 1021 may also be formed in different fabrication processes by using different materials. This will be described in more detail below.

[0041] In some embodiments, the substrate 101 may be made of one of the following materials: silicon carbide, gallium nitride, gallium nitride on silicon carbide, gallium nitride on sapphire, gallium nitride on silicon, aluminum indium nitride, and aluminum nitride. Alternatively or additionally, in some embodiments, the first dielectric layer 102 or the second dielectric layer 104 may be made of at least one of the following materials: silicon nitride, silicon oxynitride, silicon dioxide, aluminum nitride, aluminum oxide, and titanium dioxide. Furthermore, in some embodiments, the gate electrode 103 and the field plate 105 may include at least one of the following metals or metal compounds: nickel, titanium, lead, platinum, gold, titanium nitride, tantalum nitride, and copper. It can be seen that the substrate 101, the first dielectric layer 102, the second dielectric layer 104, the gate electrode 103, and the field plate 105 can all be realized using multiple materials, which allows for greater flexibility and cost-effectiveness in fabricating the semiconductor device 100. Of course, it should be understood that the aforementioned materials for the substrate 101, the first dielectric layer 102, the second dielectric layer 104, the gate electrode 103, and the field plate 105 are not exhaustive and there may be other possible materials for fabricating the corresponding components.

[0042] An embodiment of the present disclosure further provides a fabrication method for the semiconductor device 100, for fabricating the above-mentioned semiconductor device 100. FIG. 3 is a flow chart of the fabrication method for the semiconductor device 100. FIG. 4 is a diagram of the structure of the semiconductor device 100 corresponding to each fabrication step in FIG. 3. As shown in FIG. 3 and FIG. 4, in block 410, a substrate 101 is provided, the surface of which has a first region 1011, a second region 1012, and a third region 1013. The substrate 101 may be, for example, a wafer as commonly referred to in the art. Then, in block 420, a first dielectric layer 102 is applied to the first region 1011 and the third region 1013 of the substrate 101. This may be performed in any suitable manner, which will be further described below with reference to the accompanying drawings. After the first dielectric layer 102 is formed in the first region 1011 and the third region 1013, in block 430, the gate electrode 103 is applied, so that the contact region 1031 of the gate electrode 103 contacts the substrate 101 in the second region 1012, and the gate cap region 1032 is spaced from the substrate 101 by a first distance D1. Then, in block 440, the second dielectric layer 104 is applied outside the gate electrode 103 and the first dielectric layer 102, so that the second dielectric layer 104 is spaced from the substrate 101 by a second distance D2 in the second region 1012, the second distance D2 being smaller than the first distance D1. The semiconductor device 100 thus formed can reduce the parasitic capacitance C2 between the field plate 105 and the substrate 101 and increase the capacitance C3, thereby improving the gain and reliability of the semiconductor device 100.

[0043] 4, the method may further include locally applying a field plate 105 on the outside of the second dielectric layer 104 to form a source-connected field plate 105. This may be performed by using any suitable process and method, such as photolithography and etching, which is not limited in this disclosure.

[0044] In addition, the step of forming the first dielectric layer 102 in the first region 1011 and the third region 1013 may be performed in any manner. Some exemplary embodiments are described below with reference to Figures 5 to 9. It should be understood that these exemplary embodiments are merely examples and are not exhaustive or limit the scope of protection of the present disclosure. The first dielectric layer 102 may instead be formed in any other suitable manner, which will not be described in detail herein.

[0045] In some embodiments, the thickened dielectric layer 1021 in the first dielectric layer 102 may be formed first. The step of applying the first dielectric layer 102 may include applying the thickened dielectric layer 1021 in the first region 1011 and the second region 1012, as shown in FIG. 5(2). In some embodiments, the step of applying the thickened dielectric layer 1021 in the first region 1011 and the second region 1012 may be performed using the following steps: Step 1: Deposit a dielectric layer material in a thickness range of 20 nm to 500 nm (endpoint value included) over the entire substrate 101, as shown in FIG. 6(1). The above-mentioned substrate 101 may include one of silicon carbide, gallium nitride, gallium nitride on silicon carbide, gallium nitride on sapphire, gallium nitride on silicon, aluminum indium nitride, and aluminum nitride, where silicon carbide includes but is not limited to 4H silicon carbide, 6H silicon carbide, 3C silicon carbide, etc. The material used to fabricate the thickened dielectric layer 1021 includes a single layer or multi-layer stack structure of dielectric materials such as silicon nitride, silicon oxynitride, silicon dioxide, aluminum nitride, aluminum oxide, or titanium dioxide. Step 2: As shown in FIG. 6 (2), perform lithography patterning to define a photoresist pattern covering the first region 1011 and the second region 1012.

[0046] Step 3: As shown in FIG. 6(3), the dielectric layer under the pattern defined by the photoresist is etched by dry / wet etching methods. Etching is a process of removing material from the surface of a material. The two main types of etching are wet etching and dry etching (e.g., plasma etching) as mentioned above. Etching processes that involve using liquid chemicals or etchants to remove material are called wet etching. In plasma etching processes, also called dry etching, plasma or etching gases are used to remove the substrate material. Dry etching produces gaseous products that must be diffused into a large volume of gas and evacuated using a vacuum system. There are three types of dry etching (e.g., plasma etching): chemical reaction (by using reactive plasma or gas), physical removal (usually by momentum transfer), and a combination of chemical reaction and physical removal. In addition, wet etching is simply a chemical process. Step 4: As shown in FIG. 6(4), the pattern defined by the photoresist is further etched using a dry / wet etchant to completely etch the dielectric layer in the area not covered by the photoresist pattern (i.e., the third area 1013) until the substrate 101 is exposed. Step 5: As shown in FIG. 6(5), the photoresist is removed by a dry / wet method. In this way, the state shown in FIG. 5(2) is formed. That is, in some embodiments, the step of applying the thickened dielectric layer 1021 may include the steps of applying the thickened dielectric layer 1021 to the entire substrate 101, and removing the thickened dielectric layer 1021 outside the third area 1013 (e.g., by using the above-mentioned means) to expose the third area 1013 of the substrate 101, thereby forming the state shown in FIG. 5(2).

[0047] In some alternative embodiments, the step of applying the thickened dielectric layer 1021 may be performed in the following manner. Step 1: Perform pattern definition of dual-layer photoresist on the surface of the substrate 101, as shown in FIG. 7(1). This includes applying a first photoresist layer 1061 and a second photoresist layer 1062 in the third region 1013. Step 2: Deposit a first layer of dielectric layer material with a thickness range of 20 nm to 500 nm on the entire surface of the substrate 101. The dielectric layer material covers the first region 1011 and the second region 1012 of the substrate 101 and the third region 1013 covered with dual-layer photoresist, as shown in FIG. 7(2). Step 3: Perform dry / wet removal on the dual-layer photoresist. Wet photoresist removal can be divided into photoresist removal using an organic solvent and photoresist removal using an inorganic solvent. Photoresist removal using an organic solvent mainly means removing the photoresist by dissolving the photoresist in an organic solvent. The photoresist removal using an inorganic solvent means that the carbon element in the photoresist is oxidized to carbon dioxide using some inorganic solvent to remove the photoresist, taking advantage of the characteristic that the photoresist is also an organic material. The dry photoresist removal means that the photoresist is removed using plasma. Then, in order to further remove the remaining dielectric material, the remaining dielectric layer material may be separately processed by a dry method and a wet method, and finally the case shown in FIG. 7 (3) or FIG. 5 (2) may be implemented. That is, in some embodiments, the step of applying the thickened dielectric layer 1021 may include the steps of applying a photoresist (including a first layer of photoresist 1061 and a second layer of photoresist 1062) to the third region 1013 of the substrate 101, applying the thickened dielectric layer 1021 to the first region 1011 and the second region 1012 of the substrate 101 and outside the photoresist, and removing the photoresist to expose the third region 1013 of the substrate 101.

[0048] Above, we first described the process of forming the thickened dielectric layer 1021 of the first dielectric layer 102. After forming the thickened dielectric layer 1021 in the first region 1011 and the second region 1012 as shown in FIG. 7(3) or FIG. 5(2), a second layer of dielectric layer material with a thickness ranging from 20 nm to 500 nm is deposited on the wafer surface as shown in FIG. 5(3) and FIG. 7(4). The second layer of dielectric layer material finally forms the blanket dielectric layer 1022 of the first dielectric layer 102. The material may include a single layer or multiple layer stack of dielectric materials such as silicon nitride, silicon oxynitride, silicon dioxide, aluminum nitride, aluminum oxide, or titanium dioxide. As mentioned above, the blanket dielectric layer 1022 and the thickened dielectric layer 1021 of the first dielectric layer 102 may be made of the same material or different materials. Then, as shown in FIG. 4 (2), FIG. 5 (4), and FIG. 7 (5), patterned etching is performed on the thickened dielectric layer 1021 and the blanket dielectric layer 1022 using lithography and etching processes until the first region 1011 of the substrate 101 is completely exposed, thereby forming the first dielectric layer 102 in the first region 1011 and the third region 1013.

[0049] After forming the first dielectric layer 102 in the first region 1011 and the third region 1013 of the substrate 101 by the above method, a process of applying the gate electrode 103 may be carried out next. Specifically, in some embodiments, a first layer of metal stack material with a thickness range of 20 nm to 1500 nm may be deposited outside the first region 1011 and the second region 1012 of the substrate 101 to form the gate electrode 103. Since the first region 1011 is covered by the blanket dielectric layer 1022 and the thickened dielectric layer 1021 of the first dielectric layer 102, the metal layer deposited in this region forms the gate cap region 1032, as shown in FIG. 4(3). Then, the second dielectric layer 104 is formed. Specifically, as shown in FIG. 4(4), a third layer of dielectric layer material with a thickness range of 20 nm to 500 nm is deposited outside the gate electrode 103 and the first dielectric layer 102 to finally form the second dielectric layer 104. Finally, in some embodiments, a metal layer material in the thickness range of 20 nm to 500 nm is locally deposited on the outside of the second dielectric layer 104 to form the field plate 105, as shown in FIG. 4(5).

[0050] Above, with reference to Figs. 4-7, different processes of first forming the thickened dielectric layer 1021 of the first dielectric layer 102, then forming the blanket dielectric layer 1022 of the first dielectric layer 102, and finally forming the entire semiconductor device 100 are described. It is understood that in some embodiments, in the finally formed semiconductor structure, the thickened dielectric layer 1021 of the first dielectric layer 102 may be disposed between the blanket dielectric layer 1022 and the substrate 101. Of course, it should be understood that this is merely an example and is not intended to limit the scope of protection of the present disclosure. The first dielectric layer 102 may instead be implemented in any other suitable manner. For example, in some alternative fabrication processes, the blanket dielectric layer 1022 may be formed first, and then the thickened dielectric layer 1021 may be formed.

[0051] Specifically, as shown in FIG. 8, in some embodiments, a layer of dielectric layer material is deposited over the entire substrate 101 with a thickness ranging from 20 nm to 500 nm. As shown in FIG. 8(1), the dielectric layer material eventually forms the blanket dielectric layer 1022 of the first dielectric layer 102. Both the materials used by the substrate 101 and the blanket dielectric layer 1022 of the first dielectric layer 102 are similar to those used in the above-mentioned embodiments, and the details are not separately described herein. In addition, the blanket dielectric layer 1022 is also a single layer or a multi-layer structure made of one of silicon nitride, silicon oxynitride, silicon dioxide, aluminum nitride, aluminum oxide, or titanium dioxide. Step 2: As shown in FIG. 8(2), a second layer of dielectric layer material is deposited over the entire substrate 101 with a thickness ranging from 20 nm to 500 nm. The second layer of dielectric layer material eventually forms the thickened dielectric layer 1021. To facilitate the subsequent etching process, the second layer of the dielectric layer has a different refractive index, deposition temperature, density, and degree of etching resistance from the first layer of the dielectric layer. Step: As shown in FIG. 8(3), by using lithography and etching process, perform patterned etching on the applied two dielectric layers until the second region 1012 of the substrate 101 is completely exposed.

[0052] Then, the gate electrode 103 is formed. Specifically, as shown in FIG. 8(4), a first layer of metal stack material with a thickness range of 20 nm to 1500 nm is deposited outside the areas corresponding to the first region 1011 and the second region 1012 of the substrate 101. The metal stack material finally forms the gate electrode 103. Then, as shown in FIG. 8(5), the patterned first layer of metal is used as a hard self-aligned mask to perform a dry / wet etching to a depth of 20 nm to 500 nm on the second layer of the dielectric layer, so that the etched surface remains at the interface position between the second layer of the dielectric layer and the first layer of the dielectric layer, thereby holding the second layer of the dielectric layer (i.e., the thickened dielectric layer 1021) under the gate cap region 1032 of the gate electrode 103. The following process is similar to the above-mentioned process of applying the second dielectric layer 104 and the field plate 105. That is, as shown in Figure 4(4), a third layer of dielectric layer material with a thickness in the range of 20 nm to 500 nm is deposited outside the gate electrode 103 and the first dielectric layer 102 to finally form the second dielectric layer 104. Finally, in some embodiments, as shown in Figure 4(5), a metal stack material with a thickness in the range of 20 nm to 500 nm is locally deposited outside the second dielectric layer 104 to form the field plate 105.

[0053] The thickened dielectric layer 1021 of the first dielectric layer 102 in the semiconductor device 100 thus formed is located between the gate cap region 1032 of the gate electrode 103 and the first dielectric layer 102, and is made of a different material than the thickened dielectric layer 1021 and the blanket dielectric layer 1022 to facilitate etching. In some embodiments, the thickened dielectric layer 1021 and the blanket dielectric layer 1022 in the first dielectric layer 102 may be made of the same material in the same process.

[0054] As shown in FIG. 9, in some embodiments, a dielectric layer material is deposited on the entire substrate 101 with a thickness ranging from 20 nm to 500 nm, as shown in FIG. 9(1). The dielectric layer has a first thickness, and the first thickness is substantially equal to the first distance D1 described above. Then, a patterned etch is performed on the dielectric layer by using lithography and etching processes until the second region 1012 of the substrate 101 is fully exposed, as shown in FIG. 9(2). A first layer of metal stack material with a thickness ranging from 20 nm to 1500 nm is deposited on the outside of the first region 1011 and the second region 1012 of the substrate 101 to form the gate electrode 103. The patterned metal first layer is used as a hard self-aligned mask to perform a dry / wet etching of the first layer of the dielectric layer with a depth of 20 nm to 500 nm. The etched dielectric layer corresponding to the third region 1013 has a second thickness, and the second thickness is equal to the second distance D2 described above. The following process is similar to the above process of applying the second dielectric layer 104 and the field plate 105. That is, as shown in FIG. 4(4), a third layer of dielectric layer material with a thickness range of 20 nm to 500 nm is deposited outside the gate electrode 103 and the first dielectric layer 102 to finally form the second dielectric layer 104. Finally, in some embodiments, as shown in FIG. 4(5), a metal stack material with a thickness range of 20 nm to 500 nm is locally deposited outside the second dielectric layer 104 to form the field plate 105.

[0055] In the semiconductor device 100 fabricated using the above-mentioned different fabrication process, the above-mentioned thickness between the gate cap and the substrate, which affects the parasitic capacitance C2, is further increased. In this way, the parasitic capacitance C2 is reduced. In addition, since the increase in the thickness of the first dielectric layer 102 is only kept in the gate cap region 1032 of the gate electrode and does not extend to other regions, the capacitance value of the capacitance C3 can still be maintained at a high level, which can eliminate the above-mentioned conflict caused by adjusting the capacitance values ​​of the capacitances C1, C2, and C3. In this way, the gain of the semiconductor device 100 can be effectively increased.

[0056] In addition, by only increasing the thickness of the first dielectric layer 102 corresponding to the gate cap region 1032 (i.e., the first region 1011), the potential and electric field distributions near the drain end of the gate electrode 103 can be readjusted. In this way, the electric field stress at the original site where TDDB breakdown is likely to occur is effectively weakened, thereby improving the overall reliability of the device.

[0057] Although the present application has been described in language specific to structural features and / or methodological actions, it is to be understood that the subject matter defined in the appended claims is not limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as example forms of implementing the claims. [Explanation of symbols]

[0058] C1 capacity C2 capacity C3 capacity D1 First distance (distance) D2 Second interval 100 Semiconductor Devices 101 Substrate 102 First Dielectric Layer 103 Gate electrode 104 Second dielectric layer 105 Field Plate 1011 First Area 1012 Second Area 1013 The Third Region 1021 Thickened dielectric layer 1022 Blanket Dielectric Layer 1031 Contact area 1032 Gate Cap Area 1061 First photoresist layer 1062 Second Photoresist Layer 410 Block 420 Block 430 Block 440 Block 501 Substrate 502 First Dielectric Layer 503 Gate electrode 504 Second Dielectric Layer 505 source connected field plate

Claims

1. A substrate (101), the surface of which has a first region (1011), a second region (1012), and a third region (1013); a first dielectric layer (102) applied to the first region (1011) and the third region (1013) of the substrate (101); a gate electrode (103) coupled to the substrate (101), the gate electrode (103) comprising a gate cap region (1032) and a contact region (1031) in contact with the second region (1012) of the substrate (101), the gate cap region (1032) being spaced apart from the first region (1011) of the substrate (101) by a first distance (D1) via the first dielectric layer (102); a second dielectric layer (104) applied outside the gate electrode (103) and the first dielectric layer (102), the second dielectric layer (104) being spaced apart from the substrate (101) by a second distance (D2) in the third region (1013), the second distance (D2) being smaller than the first distance (D1); A semiconductor device comprising:

2. 2. The semiconductor device of claim 1, wherein the difference between the first distance (D1) and the second distance (D2) is between 20 nm and 500 nm.

3. The first dielectric layer (102) a blanket dielectric layer (1022) disposed in the first region (1011) and the third region (1013); a thickened dielectric layer (1021) disposed between said blanket dielectric layer (1022) and said first region (1011) or between said blanket dielectric layer (1022) and said gate cap region (1032), said thickened dielectric layer (1021) having a thickness between 20 nm and 500 nm; The semiconductor device according to claim 1 or 2, comprising:

4. 4. The semiconductor device of claim 1, further comprising a field plate (105) applied locally outside the second dielectric layer (104), the spacing between the field plate (105) and the gate electrode (103) being substantially the same as the spacing between the field plate (105) and the first dielectric layer (102).

5. 5. The semiconductor device of claim 1, wherein the substrate (101) comprises one of the following materials: silicon carbide, gallium nitride, gallium nitride on silicon carbide, gallium nitride on sapphire, gallium nitride on silicon, aluminum indium nitride, and aluminum nitride.

6. 6. The semiconductor device of claim 1, wherein the first dielectric layer (102) or the second dielectric layer (104) comprises at least one of the following materials: silicon nitride, silicon oxynitride, silicon dioxide, aluminum nitride, aluminum oxide, and titanium dioxide.

7. 7. The semiconductor device of claim 4, wherein the gate electrode and the field plate comprise at least one of the following materials: nickel, titanium, lead, platinum, gold, titanium nitride, tantalum nitride, and copper.

8. 1. A fabrication method for a semiconductor device, comprising: providing a substrate (101), the surface of the substrate (101) including a first region (1011) corresponding to a gate cap region (1032) of a gate electrode (103) of the semiconductor device, a second region (1012) corresponding to a contact region (1031) of the gate electrode (103), and a third region (1013) other than the first region (1011) and the second region (1012); applying a first dielectric layer (102) to the first region (1011) and to the third region (1013); applying the gate electrode (103), wherein the contact region (1031) is in contact with the substrate (101) and the gate cap region (1032) is spaced from the substrate (101) by a first distance (D1); applying a second dielectric layer (104) outside the gate electrode (103) and the first dielectric layer (102), wherein in the third region, the second dielectric layer (104) is spaced apart from the substrate (101) by a second distance (D2), the second distance (D2) being smaller than the first distance (D1); A method comprising:

9. 9. The method of claim 8, further comprising the step of locally applying a field plate (105) outside the second dielectric layer (104), the spacing between the field plate (105) and the gate electrode (103) being substantially the same as the spacing between the field plate (105) and the first dielectric layer (102).

10. The step of applying a first dielectric layer (102) comprises: applying a thickened dielectric layer (1021) to said first region (1011) and to said second region (1012); applying a blanket dielectric layer (1022) outside said third region (1013) and said thickened dielectric layer (1021); removing the blanket dielectric layer (1022) and the thickened dielectric layer (1021) outside the second region (1012) of the substrate (101) to expose the second region (1012); The method of claim 8 or 9, comprising:

11. said step of applying a thickened dielectric layer (1021) applying said thickened dielectric layer (1021) over said substrate (101); removing the thickened dielectric layer (1021) outside the third region (1013) of the substrate (101) to expose the third region (1013); The method of claim 10, comprising:

12. said step of applying a thickened dielectric layer (1021) applying a photoresist (106) to the third region (1013) of the substrate (101); applying said thickened dielectric layer (1021) outside said first area (1011) and said second area (1012) of said substrate (101) and outside said photoresist (106); removing the photoresist (106) to expose the third region (1013) of the substrate (101); The method of claim 10, comprising:

13. The steps of applying a first dielectric layer (102) and applying the gate electrode (103) include: applying said blanket dielectric layer (1022) to the exterior of the entire substrate (101); applying said thickened dielectric layer (1021) outwardly of said blanket dielectric layer (1022); removing the blanket dielectric layer (1022) and the thickened dielectric layer (1021) outside the second region (1012) of the substrate (101) to expose the second region (1012); applying said gate electrode (103); using the gate electrode (103) as a self-aligned mask to remove the thickened dielectric layer (1021) outside the third region (1013); The method of claim 8 or 9, comprising:

14. The steps of applying a first dielectric layer (102) and applying the gate electrode (103) include: applying the first dielectric layer (102) to the outside of the entire substrate (101), the first dielectric layer (102) having a first thickness, the first thickness being equal to the first spacing (D1); removing the first dielectric layer (102) outside the second area (1012) of the substrate (101) to expose the second area (1012); applying said gate electrode (103); using the gate electrode (103) as a self-aligned mask to remove a portion of the first dielectric layer (102) in a thickness direction outside the third region (1013), the first dielectric layer (102) in the third region (1013) having a second thickness smaller than the first thickness, the second thickness being equal to the second distance (D2); The method of claim 8 or 9, comprising:

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