Array substrate, display panel, and method of manufacturing array substrate

Abstract

The present application provides an array substrate, a display panel, and a manufacturing method thereof, comprising a base substrate and a protective layer, the protective layer being disposed above the base substrate and covering the base substrate, and the protective layer further includes a first through hole for discharging water vapor. The present application provides a through hole in the protective layer to discharge water vapor, thereby improving the stability of the thin film transistor in the array substrate, and at the same time improving the phenomenon of negative bias and leakage current of the display panel without the need to add other structures and without changing the spatial arrangement.

Description

[Technical field]

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a display panel, and a method for manufacturing the array substrate. [Background technology]

[0002] In the mask process for the display panel 8 containing oxide, a large amount of water vapor is generated during the manufacturing process.

[0003] Summary of the Invention [Problem to be solved by the invention]

[0004] The oxide is sensitive to water vapor, which affects the electrical properties of the device; the TFT is turned on under negative pressure, which causes a series of problems, such as pixel leakage in the panel, and the TFT design failure due to situations such as ESD, and the inability to realize electrostatic discharge of the display panel. [Means for solving the problem]

[0005] The present application aims to provide an array substrate, a display panel and a method for manufacturing the array substrate, which solves the problems of negative bias and leakage current of the display panel caused by water vapor during the manufacturing of the display panel in the prior art.

[0006] According to a first aspect, the present application provides an array substrate, the array substrate comprising: a base substrate including a thin film transistor layer including a channel region; and a protective layer disposed above the base substrate and covering the base substrate, the protective layer further having a first through hole formed therein for discharging water vapor, the first through hole being disposed adjacent to the channel region.

[0007] In some possible embodiments, the protective layer is a polymer film, and the polymer film is formed with the first through-holes for discharging water vapor.

[0008] In some possible embodiments, the protective layer includes a polymer film and a first passivation layer, the first passivation layer being disposed above and covering the polymer film; The first passivation layer has the first through-hole formed therein for discharging water vapor.

[0009] In some possible embodiments, the protective layer includes a polymer film and a first passivation layer, the first passivation layer being disposed above and covering the polymer film; The first through hole includes a second through hole formed in the polymer film and a third through hole formed in the first passivation layer, the second through hole and the third through hole being in communication with each other.

[0010] In some possible embodiments, the protective layer includes a second passivation layer, a polymer film, and a first passivation layer, which are stacked in sequence, and the second passivation layer is placed above the base substrate.

[0011] In some possible embodiments, the first through hole includes a first via hole formed in the second passivation layer, a second through hole formed in the polymer film, and a third through hole formed in the first passivation layer, and the first via hole, the second through hole, and the third through hole are in communication with each other.

[0012] In some possible embodiments, the first through-holes are filled with a water absorbing material.

[0013] In some possible embodiments, the first through-hole is multiple, and the multiple first through-holes are disposed surrounding the channel region.

[0014] In some possible embodiments, in the vertical direction, the cross-sectional shape of the first through hole is a trapezoidal structure that is wider at the top and narrower at the bottom.

[0015] In some possible embodiments, the first through hole has a horizontal and vertical height of at least 7 microns.

[0016] According to a second aspect, the present application provides a display panel including an array substrate, the array substrate comprising: a base substrate including a thin film transistor layer including a channel region; and a protective layer disposed above the base substrate and covering the base substrate, the protective layer further having a first through hole formed therein for discharging water vapor, the first through hole being disposed adjacent to the channel region.

[0017] In some possible embodiments, the protective layer is a polymer film, and the polymer film is formed with the first through-holes for discharging water vapor.

[0018] In some possible embodiments, the protective layer includes a polymer film and a first passivation layer, the first passivation layer being disposed above and covering the polymer film; The first passivation layer has the first through-hole formed therein for discharging water vapor.

[0019] In some possible embodiments, the protective layer includes a polymer film and a first passivation layer, the first passivation layer being disposed above and covering the polymer film; The first through hole includes a second through hole formed in the polymer film and a third through hole formed in the first passivation layer, the second through hole and the third through hole being in communication with each other.

[0020] In some possible embodiments, the protective layer includes a second passivation layer, a polymer film, and a first passivation layer, which are stacked in sequence, and the second passivation layer is placed above the base substrate.

[0021] In some possible embodiments, the first through hole includes a first via hole formed in the second passivation layer, a second through hole formed in the polymer film, and a third through hole formed in the first passivation layer, and the first via hole, the second through hole, and the third through hole are in communication with each other.

[0022] In some possible embodiments, the first through-holes are filled with a water absorbing material.

[0023] In some possible embodiments, the first through-hole is multiple, and the multiple first through-holes are disposed surrounding the channel region.

[0024] In some possible embodiments, the display panel further includes an opposing substrate and a liquid crystal layer, the opposing substrate being disposed opposite and spaced apart from the array substrate, and the liquid crystal layer being disposed between the opposing substrate and the array substrate.

[0025] According to a third aspect, an embodiment of the present application provides a method for manufacturing an array substrate, the method comprising: providing a base substrate including a thin film transistor layer including a channel region; Producing a protective layer above the base substrate to cover the base substrate; and fabricating a first through hole on the protective layer at a location corresponding to the channel region. Effect of the Invention

[0026] The present application provides an array substrate, a display panel, and a manufacturing method thereof, comprising a base substrate and a protective layer, the protective layer being disposed above the base substrate and covering the base substrate, and the protective layer further includes a first through hole for discharging water vapor. The present application provides a through hole in the protective layer to discharge water vapor, thereby improving the stability of the thin film transistor in the array substrate, and at the same time improving the phenomenon of negative bias and leakage current of the display panel without the need to add other structures and without changing the spatial arrangement. [Brief description of the drawings]

[0027] In order to more clearly explain the technical solutions in the embodiments of the present application, the drawings necessary for the description of the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without exerting creative efforts.

[0028] [Figure 1] 1 is a structural schematic diagram of an embodiment of an array substrate according to an embodiment of the present application; [Diagram 2] 1 is a structural schematic diagram of another embodiment of an array substrate according to an embodiment of the present application; [Diagram 3] 1 is a structural schematic diagram of another embodiment of an array substrate according to an embodiment of the present application; [Figure 4] FIG. 2 is a structural schematic diagram of another embodiment of an array substrate according to the present application; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] Hereinafter, the technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application. It is obvious that the described embodiments are only some of the embodiments of the present application, and are not all of the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without any creative effort are within the scope of protection of the present application.

[0030] In the description of this application, it should be understood that the orientations or positional relationships indicated by terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are based on the orientations or positional relationships shown in the drawings, and are merely for the purpose of facilitating and simplifying the description of this application, and do not indicate or imply that the devices or elements shown have a particular orientation, are configured, or must be operated in a particular orientation, and should not be understood as limitations on this application. In addition, terms such as "first", "second", etc. are used for descriptive purposes only, and should not be understood as expressing or suggesting relative importance or as implicitly indicating the number of technical features shown. Thus, a feature qualified with "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "plurality" means two or more, unless otherwise clearly and specifically limited.

[0031] In this application, the term "exemplary" means "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as preferred or superior over other embodiments. The following description is provided to enable those skilled in the art to realize and use the present application. In the following description, details are given for the purpose of interpretation. As will be understood by those skilled in the art, the present application can be realized without these specific details. In other instances, detailed descriptions of well-known structures and processes are omitted to avoid obscuring the description of the present application with unnecessary details. Thus, the present application is not limited to the embodiments shown, but is accorded the widest scope consistent with the principles and features disclosed herein.

[0032] The embodiments of the present application provide an array substrate, a display panel and a manufacturing method for the array substrate, which will be described in detail below.

[0033] Referring to FIG. 1, FIG. 1 is a structural schematic diagram of an embodiment of an array substrate according to an embodiment of the present application. In the embodiment shown in FIG. 1, the array substrate includes a base substrate 10 including a thin film transistor layer including a channel region, and a protective layer 20 disposed above the base substrate 10 and covering the base substrate 10. In addition, a first through hole is further formed in the protective layer 20 for discharging water vapor during the manufacture of the array substrate, and the first through hole is disposed adjacent to the channel region and is mainly used to discharge water vapor in the channel region of the thin film transistor to protect the thin film transistor. The specific process of discharging water vapor will be described in the following embodiment.

[0034] The array substrate according to the embodiment of the present application includes a base substrate and a protective layer, the protective layer is disposed above the base substrate and covers the base substrate, and the protective layer further includes a first through hole for discharging water vapor. The present application improves the stability of the thin film transistor in the array substrate by discharging water vapor through the through hole in the protective layer, and improves the phenomenon of negative bias and leakage current of the display panel without requiring additional structures or changing the spatial arrangement.

[0035] The structure of the array substrate according to the present invention is mainly suitable for an oxide array substrate having a fringe field switching (FFS) structure. Such an array substrate includes a polymer film layer, and a large amount of water vapor is generated during the process of manufacturing the polymer film. The channel in the array substrate is sensitive to hydrogen ions in the water vapor, and if there are too many hydrogen ions, the charge carriers in the channel will increase, causing a negative bias in the thin film transistor TFT. When the pixel unit is turned on at a low voltage, it will cause leakage of the pixel unit and display abnormality of the display panel. Therefore, the present invention provides a through hole to discharge the water vapor and reduce the amount of hydrogen ions.

[0036] In FIG. 1, the protective layer 20 disposed above the base substrate 10 may be a single polymer film. The first through hole may be disposed in the polymer film alone. By disposing the through hole in the protective layer (also called the polymer film), the water vapor can directly overflow through the through hole, and the water vapor is further discharged. Generally, a part of the water vapor can be discharged only by disposing the via hole, but in order to increase the efficiency of discharging the water vapor, a through hole penetrating the entire protective layer is generally disposed. Specifically, compared with the via hole, the through hole is closer to the thin film transistor TFT, which is susceptible to influences in the array substrate, in the vertical direction, and the water vapor is more likely to overflow from the through hole. In addition, the water vapor dissipation area of ​​the through hole is larger, which is more advantageous for dissipating the water vapor.

[0037] For the array substrate shown in FIG. 1, water vapor remains during the manufacture of the polymer film. However, since the polymer film has through-holes, the water vapor in the polymer film can be discharged from the array substrate through the through-holes during the subsequent baking process, thereby preventing the hydrogen ions in the water vapor from entering the channels of the array substrate.

[0038] In the embodiment of the present application, the material of the polymer film includes, but is not limited to, soluble polytetrafluoroethylene (Polyfluoroalkoxy, PFA), which has good chemical corrosion resistance and high temperature resistance, and the protective layer can be a transparent protective layer.

[0039] In another embodiment of the present application, the protective layer may have a multi-layer structure. As shown in FIG. 2, FIG. 2 is a structural schematic diagram of another embodiment of an array substrate according to an embodiment of the present application. In the schematic diagram of the array substrate shown in FIG. 2, the protective layer 20 may include a polymer film 201 and a first passivation layer 202, where the first passivation layer 202 is disposed above the polymer film and covers the polymer film 201. At the same time, a first through-hole is formed in the first passivation layer 202 for discharging water vapor.

[0040] Similar to the array substrate shown in FIG. 1, through holes are formed in another film layer structure above the base substrate to allow water vapor to escape. However, the protective layer 20 in FIG. 2 includes a polymer film 201 and a first passivation layer 202, whereas the protective layer in FIG. 1 includes only a polymer film. At this time, by opening through holes in the first passivation layer 202, water vapor remaining during the manufacture of the polymer film can be similarly removed. The first passivation layer 202 can protect the array substrate, and such an arrangement can remove excess water vapor while protecting the array substrate.

[0041] 2, the protective layer 20 at this time includes a polymer film and a first passivation layer 202, but a through-hole is provided only on the first passivation layer 202. In the process of manufacturing the array substrate shown in FIG. 2, an air extraction process is performed when manufacturing the polymer film, and some water vapor can be volatilized at this time. Then, an electrode layer is further manufactured, and a baking process occurs when manufacturing the electrode layer, and the water vapor in the polymer film layer can also be volatilized through the through-hole provided on the first passivation layer 202.

[0042] Of course, it should be explained that the electrode layer to be manufactured includes a common electrode layer and a pixel electrode layer, and the electrode layer needs to be disposed to avoid the through-hole on the protective layer when manufactured. The material of the electrode layer includes, but is not limited to, one or more of indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, and indium germanium zinc oxide.

[0043] As shown in Fig. 3, Fig. 3 is a structural schematic diagram of another embodiment of an array substrate according to an embodiment of the present application. In Fig. 3, the protective layer 20 also includes a polymer film 201 and a first passivation layer 202, but the difference from the embodiment shown in Fig. 2 is that in the array substrate shown in Fig. 3, a second through hole is formed in the polymer film, and a third through hole is formed in the first passivation layer 202. That is, in the embodiment shown in Fig. 3, both the polymer film 201 and the first passivation layer 202 have through holes, and the second through hole on the polymer film 201 and the third through hole on the first passivation layer 202 are connected to each other. As shown in FIG. 3, the position of the second through hole on the polymer film 201 is the same as the position of the third through hole on the first passivation layer 202, thereby connecting the second through hole and the third through hole, and the first through hole at this time actually includes the second through hole formed in the polymer film and the third through hole formed in the first passivation layer.

[0044] 2, the array substrate shown in Fig. 3 has a third through-hole formed in the first passivation layer 202, and further has a second through-hole formed in the polymer film 201 at a position corresponding to the third through-hole. By providing a through-hole in both film layer structures and arranging the positions of the two through-holes in a corresponding manner, a complete through-hole is formed that penetrates the entire protective layer, which greatly increases the water vapor dissipation area of ​​the through-hole and effectively improves the efficiency of water vapor volatilization.

[0045] As shown in FIG. 4, FIG. 4 is a structural schematic diagram of another embodiment of the array substrate according to the present application. In the embodiment shown in FIG. 4, the protective layer is also a multi-layer structure, and the protective layer may specifically include a second passivation layer 203, a polymer film 201, and a first passivation layer 202 that are stacked, and the second passivation layer 203 is disposed above the base substrate to protect the base substrate. In the embodiment shown in FIG. 4, the first through hole may include a first via hole formed in the second passivation layer 203, a second through hole formed in the polymer film, and a third through hole formed in the first passivation layer, and the first via hole, the second through hole, and the third through hole are connected to each other to obtain a complete passage for water vapor escape.

[0046] The second passivation layer is the structure of the protective layer closest to the thin film transistor layer, and the second passivation layer also has a via hole to achieve the function of water vapor dissipation under the premise of protecting the thin film transistor layer. However, in order to protect the thin film transistor layer, the via hole in the second passivation layer generally cannot penetrate the entire second passivation layer, that is, the second passivation layer is provided with a via hole rather than a through hole.

[0047] For the array substrate shown in FIG. 4, this arrangement further increases the area of ​​the through holes compared with the array substrates in other embodiments, that is, increases the area for water vapor dissipation, thereby improving the efficiency of water vapor dissipation.

[0048] In the embodiment shown in FIG. 1 to FIG. 4, the base substrate in the array substrate has the following structure: A glass substrate 101; A gate metal layer 102 disposed above a glass substrate 101; a gate insulating layer 103 disposed above the gate metal layer 102 and covering the gate metal layer 102; a metal oxide layer 104 disposed above the gate insulating layer 103 and corresponding to the position of the gate metal layer 102; The semiconductor device may further include a source / drain layer 105 disposed above the metal oxide layer 104 and including a source and a drain that are independent of each other.

[0049] In the above-mentioned embodiments of the array substrate, the first through hole generally needs to be located close to the thin film transistor in the array substrate, or close to the channel region in the thin film transistor layer of the array substrate. Because the channel in the array substrate is sensitive to hydrogen ions in water vapor, it is necessary to prevent the hydrogen ions in water vapor from entering the channel as much as possible, and by locating the through hole close to the channel, the water vapor near the channel can be discharged as much as possible to avoid affecting the TFT.

[0050] In addition, the number of through holes described in the above embodiment is one, but in another embodiment, the number of first through holes on the protective layer may be multiple, and the positions of the multiple first through holes can be set according to actual needs, for example, they can be set around the channel region of the thin film transistor layer, or they can be set at the position where water vapor is concentrated according to the actual water vapor situation.

[0051] In the above embodiment, the number and position of the first through holes can be set according to actual needs. In addition, in the vertical direction, the first through holes are generally through holes that penetrate the protective layer (assuming that the thin film transistor is not destroyed), while in the horizontal direction, the size of the first through holes can be set according to the actual size of the array substrate. In one specific embodiment, the horizontal width and vertical height of the first through holes are both 7 microns or more.

[0052] In the embodiment of the present application, the cross-sectional shape of the first through-hole opened vertically in the protective layer 20 may be a trapezoidal structure that is wider at the top and narrower at the bottom, and this arrangement can further increase the area of ​​water vapor dissipation compared to a rectangular structure, thereby improving the efficiency of water vapor dissipation. The cross-sectional shape of the first through-hole may be a circle, a rectangle, or other shape.

[0053] It should be noted that, in the array substrate of the present application, in addition to the above structure, the array substrate further includes other film layers, but generally, water vapor can be completely discharged during the process of manufacturing the array substrate. Therefore, in order to finally manufacture a complete array substrate structure, the through-holes on the protective layer are not connected to the outside, thereby preventing the outside water vapor from re-entering the inside of the array substrate through the through-holes. Specifically, the first through-holes may be filled with a water-absorbing material, which can not only ensure the flatness of the upper surface of the array substrate, but also prevent the outside water vapor from entering the array substrate.

[0054] An embodiment of the present application further provides a display panel, which includes the array substrate according to any one of the above. The display panel may further include an opposing substrate and a liquid crystal layer, where the opposing substrate faces the array substrate at a distance, and the liquid crystal layer is disposed between the opposing substrate and the array substrate. The display panel may be a COA type panel or a non-COA type panel.

[0055] The present application further provides a method for manufacturing an array substrate, the method comprising: The method may include providing a base substrate including a thin film transistor layer including a channel region, fabricating a protective layer above the base substrate to cover the base substrate, and fabricating a first through hole on the protective layer at a position corresponding to the channel region.

[0056] In some embodiments, the protective layer may be a multi-layer laminated structure, and the vertical height of the first through hole may be changed based on the number of film layers of the protective layer. The array substrate manufacturing method according to the present application can manufacture the array substrate described in any one of the above. The specific manufacturing methods of the different film layers and the first through hole of the array substrate in the present application may refer to the prior art and are not limited here.

[0057] In the above embodiments, the description of each embodiment has its own emphasis, and for the parts of an embodiment that are not detailed, reference may be made to the detailed description of other embodiments in the preceding paragraph, and no further description will be given here.

[0058] In concrete implementation, each of the above units or structures may be realized as an independent entity, or may be arbitrarily combined and realized as the same or several entities. For concrete implementation of each of the above units or structures, please refer to the method embodiment in the preceding paragraph, and no further description will be given here.

[0059] For the specific implementation of each of the above operations, please refer to the above embodiment, and no further description will be given here.

[0060] The above provides a detailed introduction to the array substrate, display panel, and array substrate manufacturing method according to the embodiments of the present application. In this specification, the principles and embodiments of the present application are described using specific examples. However, the explanation of the above examples is merely intended to facilitate understanding of the method and core idea of ​​the present application. Furthermore, a person skilled in the art may modify the specific embodiments and application scope based on the idea of ​​the present application. As such, the contents of this specification should not be construed as limiting the present application.

Claims

1. An array substrate, a base substrate including a thin film transistor layer including a channel region; a protective layer disposed above the base substrate and covering the base substrate, the protective layer further having a first through hole for discharging water vapor, the first through hole being disposed adjacent to the channel region.

2. 2. The array substrate according to claim 1, wherein the protective layer is a polymer film, and the first through-hole for discharging water vapor is formed in the polymer film.

3. The protective layer includes a polymer film and a first passivation layer, the first passivation layer being disposed above the polymer film and covering the polymer film; The array substrate according to claim 1 , wherein the first passivation layer is formed with the first through-hole for discharging water vapor.

4. The protective layer includes a polymer film and a first passivation layer, the first passivation layer being disposed above the polymer film and covering the polymer film; 2. The array substrate according to claim 1, wherein the first through hole includes a second through hole formed in the polymer film and a third through hole formed in the first passivation layer, the second through hole and the third through hole being connected to each other.

5. 2. The array substrate according to claim 1, wherein the protective layer includes a second passivation layer, a polymer film, and a first passivation layer, which are stacked in order, and the second passivation layer is disposed above the base substrate.

6. 6. The array substrate of claim 5, wherein the first through hole includes a first via hole formed in the second passivation layer, a second through hole formed in the polymer film, and a third through hole formed in the first passivation layer, and the first via hole, the second through hole, and the third through hole are connected to each other.

7. The array substrate according to claim 1 , wherein the first through holes are filled with a water-absorbing material.

8. The array substrate according to claim 1 , wherein the number of said first through holes is more than one, and the plurality of first through holes are disposed surrounding the channel region.

9. 2. The array substrate according to claim 1, wherein the cross-sectional shape of the first through-hole in the vertical direction is a trapezoidal structure that is wider at the top and narrower at the bottom.

10. 2. The array substrate according to claim 1, wherein the first through-hole has a horizontal and vertical height of at least 7 microns.

11. A display panel including an array substrate, the array substrate comprising: a base substrate including a thin film transistor layer including a channel region; a protective layer disposed above the base substrate and covering the base substrate, the protective layer further having a first through hole for discharging water vapor, the first through hole being disposed adjacent to the channel region.

12. The display panel according to claim 11 , wherein the protective layer is a polymer film, and the first through-hole for discharging water vapor is formed in the polymer film.

13. The protective layer includes a polymer film and a first passivation layer, the first passivation layer being disposed above the polymer film and covering the polymer film; The display panel according to claim 11 , wherein the first passivation layer is formed with the first through-hole for discharging water vapor.

14. The protective layer includes a polymer film and a first passivation layer, the first passivation layer being disposed above the polymer film and covering the polymer film; The display panel of claim 11, wherein the first through hole includes a second through hole formed in the polymer film and a third through hole formed in the first passivation layer, the second through hole and the third through hole being connected to each other.

15. The display panel of claim 11 , wherein the protective layer includes a second passivation layer, a polymer film, and a first passivation layer, which are stacked in sequence, and the second passivation layer is disposed above the base substrate.

16. The display panel of claim 15, wherein the first through hole includes a first via hole formed in the second passivation layer, a second through hole formed in the polymer film, and a third through hole formed in the first passivation layer, and the first via hole, the second through hole, and the third through hole are connected to each other.

17. The display panel according to claim 11 , wherein the first through-holes are filled with a water-absorbing material.

18. The display panel according to claim 11 , wherein the number of the first through holes is multiple, and the multiple first through holes are disposed surrounding the channel region.

19. The display panel of claim 11, wherein the display panel further includes an opposing substrate and a liquid crystal layer, the opposing substrate being disposed opposite the array substrate at a distance, and the liquid crystal layer being disposed between the opposing substrate and the array substrate.

20. A method for manufacturing an array substrate, comprising the steps of: providing a base substrate including a thin film transistor layer including a channel region; Producing a protective layer above the base substrate to cover the base substrate; and forming a first through hole on the protection layer at a position corresponding to the channel region.

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