Checkerboard Mask Optimization for Occlusion Culling

Abstract

Aspects presented herein relate to a method and device for graphics processing including an apparatus, e.g., a GPU or a CPU. The apparatus may obtain pixel information for a plurality of pixels in at least one frame included in a plurality of frames in a scene. The apparatus may also calculate a depth value for each of a first set of pixels. Further, the apparatus may identify whether each of the first set of pixels or the second set of pixels, or both, are occluded by at least one occluding object in the scene. The apparatus may configure a pattern mask configuration associated with a visibility mask for the plurality of pixels. The apparatus may also output, based on the pattern mask configuration, a depth value for the first set of pixels and an indication of coverage information for the first set of pixels or the second set of pixels.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority to International Application No. PCT / CN2022 / 078568, entitled "CHECKERBOARD MASK OPTIMIZATION IN OCCLUSION CULLING," filed March 1, 2022, which is expressly incorporated by reference in its entirety.

[0002] The present disclosure relates generally to processing systems, and more particularly to one or more techniques for graphics processing. [Background technology]

[0003]

[0003] Computing devices often perform graphics and / or display processing (e.g., utilizing a graphics processing unit (GPU), a central processing unit (CPU), a display processor, etc.) to render and display visual content. Such computing devices may include, for example, computer workstations, mobile phones such as smartphones, embedded systems, personal computers, tablet computers, and video game consoles. A GPU is configured to execute a graphics processing pipeline that includes one or more processing stages that work together to execute graphics processing commands and output frames. A central processing unit (CPU) may control the operation of the GPU by issuing one or more graphics processing commands to the GPU. Modern CPUs are typically capable of simultaneously executing multiple applications, each of which may need to utilize the GPU during execution. The display processor is configured to convert digital information received from the CPU into analog values ​​and may issue commands to a display panel to display visual content. A device that provides content for visual presentation on a display may utilize a GPU and / or a display processor.

[0004]

[0004] A GPU of a device may be configured to perform processes in a graphics processing pipeline. Further, a display processor or display processing unit (DPU) may be configured to perform processes for display processing. However, with the advent of wireless communications and smaller handheld devices, there is an increasing need for improved graphics processing or display processing. Summary of the Invention

[0005]

[0005] The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, nor is it intended to identify key or critical elements of all aspects, nor to delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.

[0006]

[0006] In one aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a graphics processing unit (GPU), a central processing unit (CPU), or any apparatus capable of performing graphics processing. The apparatus may obtain pixel information for a plurality of pixels in at least one frame, the at least one frame being included in a plurality of frames in a scene. The apparatus may also calculate a depth value for each of a first set of pixels of the plurality of pixels. In addition, the apparatus may identify whether each of the first set of pixels, or a second set of pixels, the second set of pixels being included in the plurality of pixels, or both, are occluded by at least one occluding object in the scene. The apparatus may also configure a visibility mask before configuring a pattern mask configuration associated with the visibility mask. The apparatus may also configure a pattern mask configuration associated with a visibility mask for a plurality of pixels, the pattern mask configuration including a first pattern portion corresponding to the first set of pixels and a second pattern portion corresponding to the second set of pixels. Further, the apparatus may generate a binary coverage mask before outputting the indication of coverage information for each of the first set of pixels and each of the second set of pixels, and outputting the indication of coverage information for each of the first set of pixels and each of the second set of pixels includes storing the binary coverage mask. The apparatus may also output, based on the pattern mask configuration, a depth value for each of the first set of pixels and an indication of coverage information for each of the first set of pixels or each of the second set of pixels, or both, where the coverage information is associated with whether each of the first set of pixels or each of the second set of pixels, or both, is occluded by at least one occluding object in the scene. Further, the apparatus may retrieve the depth value for the first set of pixels and the coverage information for the first set of pixels and the second set of pixels.The apparatus may also perform an occlusion culling calculation based on the depth values ​​for the first set of pixels and coverage information for the first set of pixels and the second set of pixels, the occlusion culling calculation being associated with whether any of the first set of pixels or any of the second set of pixels is not occluded by at least one occluding object in the scene, where each of the first set of pixels is not occluded by the at least one occluding object if the depth value of the pixel is closer to a viewpoint of the scene than the occlusion depth map value, and each of the second set of pixels is not occluded by the at least one occluding object if the coverage information of the pixel is a non-zero value.

[0007]

[0007] The details of one or more examples of this disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will become apparent from the description and drawings, and from the claims. [Brief description of the drawings]

[0008] [Figure 1]

[0008] FIG. 1 is a block diagram illustrating an exemplary content generation system. [Diagram 2]

[0009] 1 is an exemplary graphics processing unit (GPU). [Diagram 3]

[0010] FIG. 1 illustrates an example image or surface used in graphics processing. [Figure 4]

[0011] FIG. 1 illustrates an exemplary image or scene in graphics processing. [Diagram 5]

[0012] FIG. 2 illustrates an example occlusion depth map for graphics processing. [Figure 6]

[0013] FIG. 1 illustrates an exemplary pattern mask configuration for graphics processing. [Figure 7A]

[0014] FIG. 2 illustrates an example occlusion depth map for graphics processing. [Figure 7B]

[0015] FIG. 2 illustrates an example occlusion depth map for graphics processing. [Figure 8]

[0016] FIG. 2 illustrates an example occlusion depth map for graphics processing. [Figure 9]

[0017] FIG. 2 is a communication flow diagram illustrating exemplary communications between a CPU, a GPU, and a memory. [Figure 10]

[0018] 1 is a flowchart of an exemplary method of graphics processing. [Figure 11]

[0019] 1 is a flowchart of an exemplary method of graphics processing. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009]

[0020] Some aspects of graphics processing may utilize occlusion culling, a feature that disables the rendering of objects when they are not currently seen by the camera because they are occluded (i.e., occluded) by other objects. For example, occlusion culling may remove objects in a scene from the camera rendering workload if they are completely occluded by objects closer to the camera. In some aspects, the occlusion culling process may traverse a scene with a virtual camera to build a hierarchy of a potentially visible set of objects. This data may be used by each camera in a graphics processing application to identify which objects are visible or not visible. Occlusion culling may increase rendering performance (e.g., GPU rendering) by simply not rendering objects that are outside the camera's field of view or that are hidden by other objects closer to the camera. In one example, the occlusion culling process may be defined as follows: Given a set of occluders (i.e., objects that occlude other objects) and a set of occludees (i.e., objects that are occluded by other objects) for a camera view in a scene, the visibility of the occluders may be derived or determined. Different areas in the occluder depth map may correspond to data for different pixels. Thus, a pixel in the occluder depth map may be associated with a particular type of pixel information. For example, a pixel in the occluder depth map may include information related to whether the pixel is covered by an occluding object or an occluder. In addition, a pixel in the occluder depth map may include information related to a depth value of the pixel. This pixel information in the occluder depth map may correspond to a type of scene in the graphics processing. Some types of scenes in the graphics processing may be complex, which may cause a large number of pixels to exist in the scene. Thus, there may be a large amount of pixel information associated with the occluder depth map because a large number of pixels may exist in the scene.A large amount of pixel information in an occlusion depth map may correspond to a large amount of memory that may be required to store the pixel information. Furthermore, a large amount of pixel information in an occlusion depth map may correspond to a long rendering time for all the pixel information. Aspects of the present disclosure may reduce the amount of pixel information and / or storage space associated with an occlusion depth map. Aspects of the present disclosure may also reduce the amount of processing or rendering time associated with pixel information for an occlusion depth map. For example, aspects of the present disclosure may utilize a particular type of configuration associated with an occlusion depth map. That is, aspects presented herein may utilize different mask configurations associated with an occlusion depth map.

[0010]

[0021] Aspects of the present disclosure may include several benefits or advantages. For example, aspects presented herein may result in improved speed for rendering and depth rasterization. That is, checkerboard optimization may result in faster final depth rasterization because a certain amount of pixels (e.g., half of the pixels) may require derivation of depth information. Therefore, the total occluder rendering time may be reduced by a certain percentage (e.g., reduced by 5-20% on mobile platforms). As described above, checkerboard mask optimization may result in an evenly distributed error of less than one pixel. The occluder query results may be the same as compared to the default approach. The checkerboard mask configuration may also optimize the amount of depth buffer memory utilized to store pixel data. For example, the checkerboard mask optimization described herein may reduce the depth buffer memory by a certain amount (e.g., a 43.75% reduction).

[0011]

[0022] Various aspects of the system, device, computer program product, and method are described more fully below with reference to the accompanying drawings. However, the present disclosure may be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout the present disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Based on the teachings herein, those skilled in the art should understand that the scope of the present disclosure encompasses any aspect of the system, device, computer program product, and method disclosed herein, whether implemented independently of or in combination with other aspects of the present disclosure. For example, an apparatus can be implemented or a method can be practiced using any number of the aspects described herein. It is intended that the scope of the present disclosure encompasses such an apparatus or method that is practiced using other structure, functionality, or structure and functionality in addition to or other than the various aspects of the present disclosure described herein. Any aspect disclosed herein may be embodied by one or more elements of a claim.

[0012]

[0023] Although various aspects are described herein, many variations and permutations of these aspects fall within the scope of the disclosure. Although some potential benefits and advantages of aspects of the disclosure are described, the scope of the disclosure is not limited to any particular benefit, use, or purpose. Rather, aspects of the disclosure are broadly applicable to different wireless technologies, system configurations, networks, and transmission protocols, some of which are illustrated by way of example in the figures and the following description. The detailed description and drawings are merely illustrative of the disclosure, rather than limiting, the scope of the disclosure being defined by the appended claims.

[0013]

[0024] Certain aspects are presented with reference to various apparatus and methods that are described in the following detailed description and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, and the like (collectively referred to as "elements"). These elements may be implemented using electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends on the particular application and design constraints imposed on the overall system.

[0014]

[0025] As an example, the elements, or any portion of the elements, or any combination of the elements, may be implemented as a "processing system" (sometimes referred to as a processing unit) that includes one or more processors. Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), general purpose GPUs (GPGPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, systems-on-chip (SOC), baseband processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gate logic, discrete hardware circuits, and other suitable hardware configured to perform various functions described throughout this disclosure. The one or more processors in the processing system may execute software. Software may be broadly construed to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software components, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The term application may refer to software. As described herein, one or more techniques may refer to an application, i.e., software configured to perform one or more functions.In such examples, the application may be stored on a memory, such as an on-chip memory of a processor, a system memory, or any other memory. Hardware described herein, such as a processor, may be configured to execute the application. For example, an application may be described as including code that, when executed by the hardware, causes the hardware to perform one or more techniques described herein. As an example, the hardware may access code from a memory and execute the code accessed from the memory to perform one or more techniques described herein. In some examples, components are identified in this disclosure. In such examples, the components may be hardware, software, or a combination thereof. The components may be separate components or subcomponents of a single component.

[0015]

[0026] Thus, in one or more examples described herein, the functions described may be implemented in hardware, software, or any combination thereof. If implemented in software, the functions may be stored or encoded as one or more instructions or code on a computer-readable medium. Computer-readable media includes computer storage media. A storage medium may be any available medium that may be accessed by a computer. By way of example and not limitation, such computer-readable media may comprise random-access memory (RAM), read-only memory (ROM), electrically erasable programmable ROM (EEPROM), optical disk storage, magnetic disk storage, other magnetic storage devices, combinations of the above types of computer-readable media, or any other medium that may be used to store computer-executable code in the form of instructions or data structures that may be accessed by a computer.

[0016]

[0027] In general, this disclosure describes techniques for improving the rendering of graphical content and / or reducing the load on a processing unit, i.e., any processing unit configured to perform one or more techniques described herein, such as a GPU, having a graphics processing pipeline in a device or multiple devices. For example, this disclosure describes techniques for graphics processing in any device that utilizes graphics processing. Other example benefits are described throughout this disclosure.

[0017]

[0028] Instances of the term "content" as used herein may refer to "graphical content," "images," and vice versa. This is true whether the terms are used as adjectives, nouns, or other parts of speech. In some examples, the term "graphical content" as used herein may refer to content produced by one or more processes of a graphics processing pipeline. In some examples, the term "graphical content" as used herein may refer to content produced by a processing unit configured to perform graphics processing. In some examples, the term "graphical content" as used herein may refer to content produced by a graphics processing unit.

[0018]

[0029] In some examples, the term "display content" as used herein may refer to content generated by a processing unit configured to perform display processing. In some examples, the term "display content" as used herein may refer to content generated by a display processing unit. Graphical content may be processed to become display content. For example, a graphics processing unit may output graphical content, such as a frame, to a buffer (sometimes referred to as a frame buffer). The display processing unit may read graphical content, such as one or more frames, from the buffer and perform one or more display processing techniques thereon to generate the display content. For example, a display processing unit may be configured to perform compositing on one or more rendered layers to generate a frame. As another example, a display processing unit may be configured to composite, blend, or otherwise combine two or more layers together into a single frame. A display processing unit may be configured to perform scaling, e.g., upscaling or downscaling, on a frame. In some examples, a frame may refer to a layer. In other examples, a frame may refer to two or more layers that have already been blended together to form a frame, i.e., a frame includes two or more layers, and a frame including two or more layers may be blended later.

[0019]

[0030] FIG. 1 is a block diagram illustrating an example content generation system 100 configured to implement one or more techniques of the present disclosure. The content generation system 100 includes a device 104. The device 104 may include one or more components or circuits for performing various functions described herein. In some examples, one or more components of the device 104 may be components of a SOC. The device 104 may include one or more components configured to perform one or more techniques of the present disclosure. In the illustrated example, the device 104 may include a processing unit 120, a content encoder / decoder 122, and a system memory 124. In some aspects, the device 104 may include several components, such as a communication interface 126, a transceiver 132, a receiver 128, a transmitter 130, a display processor 127, and one or more displays 131. References to the display 131 may refer to one or more displays 131. For example, the display 131 may include a single display or multiple displays. Display 131 may include a first display and a second display. The first display may be a left-eye display and the second display may be a right-eye display. In some examples, the first and second displays may receive different frames for presentation thereon. In other examples, the first and second displays may receive the same frames for presentation thereon. In further examples, the results of the graphics processing may not be displayed on the device, e.g., the first and second displays may not receive any frames for presentation thereon. Instead, the frames or graphics processing results may be forwarded to another device. In some aspects, this may be referred to as split rendering.

[0020]

[0031] Processing unit 120 may include internal memory 121. Processing unit 120 may be configured to perform graphics processing, such as in graphics processing pipeline 107. Content encoder / decoder 122 may include internal memory 123. In some examples, device 104 may include a display processor, such as display processor 127, to perform one or more display processing techniques on one or more frames generated by processing unit 120 prior to presentation by one or more displays 131. Display processor 127 may be configured to perform display processing. For example, display processor 127 may be configured to perform one or more display processing techniques on one or more frames generated by processing unit 120. One or more displays 131 may be configured to display or otherwise present frames processed by display processor 127. In some examples, the one or more displays 131 may include one or more of a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, a projection display device, an augmented reality display device, a virtual reality display device, a head-mounted display, or any other type of display device.

[0021]

[0032] Memory external to the processing unit 120 and the content encoder / decoder 122, such as a system memory 124, may be accessible to the processing unit 120 and the content encoder / decoder 122. For example, the processing unit 120 and the content encoder / decoder 122 may be configured to read from and / or write to an external memory, such as the system memory 124. The processing unit 120 and the content encoder / decoder 122 may be communicatively coupled to the system memory 124 via a bus. In some examples, the processing unit 120 and the content encoder / decoder 122 may be communicatively coupled to each other via a bus or a different connection.

[0022]

[0033] The content encoder / decoder 122 may be configured to receive graphical content from any source, such as the system memory 124 and / or the communications interface 126. The system memory 124 may be configured to store the received encoded or decoded graphical content. The content encoder / decoder 122 may be configured to receive the encoded or decoded graphical content, for example, in the form of encoded pixel data, from the system memory 124 and / or the communications interface 126. The content encoder / decoder 122 may be configured to encode or decode any graphical content.

[0023]

[0034] The internal memory 121 or the system memory 124 may include one or more volatile or non-volatile memories or storage devices. In some examples, the internal memory 121 or the system memory 124 may include RAM, SRAM, DRAM, erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, magnetic or optical data media, or any other type of memory.

[0024]

[0035] The internal memory 121 or the system memory 124 may be a non-transitory storage medium, according to some examples. The term "non-transitory" may indicate that the storage medium is not embodied in a carrier wave or a propagated signal. However, the term "non-transitory" should not be interpreted to mean that the internal memory 121 or the system memory 124 are non-movable or that their contents are static. As one example, the system memory 124 may be removed from the device 104 and moved to another device. As another example, the system memory 124 may not be removable from the device 104.

[0025]

[0036] Processing unit 120 may be a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or any other processing unit that may be configured to perform graphics processing. In some examples, processing unit 120 may be integrated into the motherboard of device 104. In some examples, processing unit 120 may reside on a graphics card installed into a port in the motherboard of device 104, or may be otherwise integrated into a peripheral device configured to interoperate with device 104. Processing unit 120 may include one or more processors, such as one or more microprocessors, GPUs, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the techniques are implemented partially in software, the processing unit 120 may store instructions for the software in a suitable non-transitory computer-readable storage medium, such as internal memory 121, and execute the instructions in hardware using one or more processors to perform the techniques of this disclosure. Any of the above, including hardware, software, combinations of hardware and software, etc., may be considered to be one or more processors.

[0026]

[0037] The content encoder / decoder 122 may be any processing unit configured to perform content decoding. In some examples, the content encoder / decoder 122 may be integrated into the motherboard of the device 104. The content encoder / decoder 122 may include one or more processors, such as one or more microprocessors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), video processors, discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the techniques are implemented partially in software, the content encoder / decoder 122 may store instructions for the software in a suitable non-transitory computer-readable storage medium, such as the internal memory 123, and may execute the instructions in the hardware using one or more processors to perform the techniques of this disclosure. Any of the above, including hardware, software, combinations of hardware and software, etc., may be considered to be one or more processors.

[0027]

[0038] In some aspects, the content generation system 100 may include a communication interface 126. The communication interface 126 may include a receiver 128 and a transmitter 130. The receiver 128 may be configured to perform any receiving function described herein with respect to the device 104. Additionally, the receiver 128 may be configured to receive information from another device, such as eye or head position information, rendering commands, or location information. The transmitter 130 may be configured to perform any transmitting function described herein with respect to the device 104. For example, the transmitter 130 may be configured to transmit information to another device, which may include a request for content. The receiver 128 and the transmitter 130 may be combined into a transceiver 132. In such an example, the transceiver 132 may be configured to perform any receiving and / or transmitting functions described herein with respect to the device 104.

[0028]

[0039] Referring again to FIG. 1, in certain aspects, the processing unit 120 may include a mask component 198 configured to obtain pixel information for a plurality of pixels in at least one frame, the at least one frame being included within a plurality of frames in a scene. The mask component 198 may also be configured to calculate a depth value for each of a first set of pixels of the plurality of pixels. The mask component 198 may also be configured to identify whether each of the first set of pixels, or a second set of pixels, the second set of pixels being included within the plurality of pixels, or both, are occluded by at least one occluding object in the scene. The mask component 198 may also be configured to configure a visibility mask prior to configuring a pattern mask configuration associated with the visibility mask. The mask component 198 may also be configured to configure a pattern mask configuration associated with a visibility mask for a plurality of pixels, the pattern mask configuration including a first pattern portion corresponding to the first set of pixels and a second pattern portion corresponding to the second set of pixels. The mask component 198 may also be configured to generate a binary coverage mask prior to outputting the indication of coverage information for each of the first set of pixels and each of the second set of pixels, and outputting the indication of coverage information for each of the first set of pixels and each of the second set of pixels, or both, includes storing the binary coverage mask. The mask component 198 may also be configured to output a depth value for each of the first set of pixels based on the pattern mask configuration, and an indication of coverage information for each of the first set of pixels or each of the second set of pixels, or both, where the coverage information is associated with whether the first set of pixels or each of the second set of pixels, or both, is occluded by at least one occluding object in the scene.The mask component 198 may also be configured to retrieve depth values ​​for the first set of pixels and coverage information for the first set of pixels and the second set of pixels. The mask component 198 may also be configured to perform an occlusion culling calculation based on the depth values ​​for the first set of pixels and the coverage information for the first set of pixels and the second set of pixels, the occlusion culling calculation being associated with whether any of the first set of pixels or any of the second set of pixels are not occluded by at least one occluding object in the scene, where each of the first set of pixels is not occluded by at least one occluding object if the depth value of the pixel is closer to the viewpoint of the scene than the occlusion depth map value, and each of the second set of pixels is not occluded by at least one occluding object if the coverage information of the pixel is a non-zero value. The following description may focus on display processing, but the concepts described herein may be applicable to other similar processing techniques.

[0029]

[0040] As described herein, a device, such as device 104, may refer to any device, apparatus, or system configured to perform one or more techniques described herein. For example, a device may be a server, a base station, a user equipment, a client device, a station, an access point, a computer, such as a personal computer, a desktop computer, a laptop computer, a tablet computer, a computer workstation, or a mainframe computer, an end product, an apparatus, a phone, a smartphone, a server, a video game platform or console, a handheld device, such as a portable video game device or a personal digital assistant (PDA), a wearable computing device, such as a smart watch, an augmented reality device, or a virtual reality device, a non-wearable device, a display or display device, a television, a television set-top box, an intermediate network device, a digital media player, a video streaming device, a content streaming device, an in-vehicle computer, any mobile device, any device configured to generate graphical content, or any device configured to perform one or more techniques described herein. Although the processes herein may be described as being performed by particular components (e.g., a GPU), in further embodiments, they may be performed using other components (e.g., a CPU) consistent with the disclosed embodiments.

[0030]

[0041] A GPU may process multiple types of data or data packets in a GPU pipeline. For example, in some aspects, a GPU may process two types of data or data packets, e.g., context register packets and draw call data. A context register packet may be global state information, e.g., information about global registers, shading programs, or a set of constant data, that may adjust how a graphics context is to be processed. For example, a context register packet may include information about a color format. In some aspects of a context register packet, there may be a bit that indicates which workload belongs to the context register. There may also be multiple functions or programming running simultaneously and / or in parallel. For example, a function or programming may represent a certain operation, e.g., a color mode or color format. Thus, a context register may define multiple states of the GPU.

[0031]

[0042] The context state may be utilized to determine how individual processing units function, e.g., a vertex fetcher (VFD), a vertex shader (VS), a shader processor, or a geometry processor, and / or in what mode the processing units function. To do so, the GPU may use context registers and programming data. In some aspects, the GPU may generate workloads, e.g., vertex or pixel workloads, in a pipeline based on the context register definition of a mode or state. Some processing units, e.g., VFDs, may use these states to determine how some functions, e.g., vertices, are assembled. Because these modes or states may change, the GPU may need to modify the corresponding context. Furthermore, the workloads corresponding to a mode or state may follow the changing mode or state.

[0032]

[0043] 2 illustrates an example GPU 200 in accordance with one or more techniques of the present disclosure. As illustrated in FIG. 2, the GPU 200 includes a command processor (CP) 210, a draw call packet 212, a VFD 220, a VS 222, a vertex cache (VPC) 224, a triangle setup engine (TSE) 226, a rasterizer (RAS) 228, a Z process engine (ZPE) 230, a pixel interpolator (PI) 232, a fragment shader (FS) 234, a render backend (RB) 236, a level 2 (L2) cache (UCHE) 238, and a system memory 240. 2 shows GPU 200 including processing units 220-238, GPU 200 may include several additional processing units. Additionally, processing units 220-238 are merely an example, and any combination or order of processing units may be used by a GPU in accordance with this disclosure. GPU 200 also includes command buffer 250, context register packet 260, and context state 261.

[0033]

[0044] 2, the GPU may utilize a CP, e.g., CP 210, or a hardware accelerator to parse the command buffer into context register packets, e.g., context register packet 260, and / or draw call data packets, e.g., draw call packet 212. CP 210 may then send the context register packet 260 or draw call packet 212 through separate paths to processing units or blocks in the GPU. Furthermore, command buffer 250 may alternate between different states of context registers and draw calls. For example, a command buffer may be constructed as follows: context register for context N, draw call for context N, context register for context N+1, and draw call(s) for context N+1.

[0034]

[0045] A GPU may render an image in a variety of different ways. In some cases, a GPU may render an image using tile rendering and / or tile rendering. In a tile rendering GPU, an image may be divided or separated into different sections or tiles. After dividing the image, each section or tile may be rendered separately. A tile rendering GPU may divide a computer graphics image into a grid format, such that each portion of the grid, i.e., a tile, is rendered separately. In some aspects, during a binning pass, an image may be divided into different bins or tiles. In some aspects, during the binning pass, a visibility stream may be constructed, in which visible primitives or draw calls may be identified. In contrast to tile rendering, direct rendering does not divide a frame into smaller bins or tiles. Rather, in direct rendering, the entire frame is rendered at one time. Furthermore, some types of GPUs may enable both tile rendering and direct rendering.

[0035]

[0046] In some aspects of tile rendering, there may be multiple processing phases or passes. For example, rendering may be performed in two passes, e.g., a visibility or bin visibility pass, and a rendering or bin rendering pass. During the visibility pass, the GPU may input the rendering workload, record the positions of primitives or triangles, and then determine which primitives or triangles fall into which bins or areas. In some aspects of the visibility pass, the GPU may also identify or mark the visibility of each primitive or triangle in the visibility stream. During the rendering pass, the GPU may input the visibility stream and process one bin or area at a time. In some aspects, the visibility stream may be analyzed to determine which primitives, or vertices of primitives, are visible or not visible. Thus, the primitives, or vertices of primitives, that are visible may be processed. By doing so, the GPU may reduce the unnecessary workload of processing or rendering primitives or triangles that are not visible. In some aspects, during the visibility pass, some types of primitive geometry, e.g., position-only geometry, may be processed. Furthermore, primitives may be sorted into different bins or areas depending on the position or location of the primitives or triangles. In some cases, sorting primitives or triangles into different bins may be performed by determining visibility information for these primitives or triangles. For example, the GPU may determine or write, e.g., in system memory, visibility information for each of the primitives in each bin or area. This visibility information may be used to determine or generate a visibility stream. In a rendering pass, the primitives in each bin may be rendered separately. In these cases, the visibility stream may be fetched from memory that is used to drop the primitives that are not visible for that bin.

[0036]

[0047] Some aspects of a GPU or GPU architecture may provide several different options for rendering, e.g., software rendering and hardware rendering. In software rendering, the driver or CPU may replicate the entire frame geometry by processing each view once. Furthermore, several different states may be changed depending on the view. Thus, in software rendering, the software may replicate the entire workload by modifying several states that may be utilized to render for each viewpoint in the image. In some aspects, there may be an increased amount of overhead since the GPU may be submitting the same workload multiple times for each viewpoint in the image. In hardware rendering, the hardware or GPU may be responsible for replicating or processing the geometry for each viewpoint in the image. Thus, the hardware may manage the replication or processing of primitives or triangles for each viewpoint in the image.

[0037]

[0048] FIG. 3 illustrates an image or surface 300 that includes a number of primitives divided into a number of bins. As shown in FIG. 3, the image or surface 300 includes an area 302, which includes primitives 321, 322, 323, and 324. The primitives 321, 322, 323, and 324 are placed in different bins, e.g., bins 310, 311, 312, 313, 314, and 315. FIG. 3 illustrates an example of tiled rendering using multiple viewpoints for primitives 321-324. For example, primitives 321-324 are in a first viewpoint 350 and a second viewpoint 351. Thus, a GPU that processes or renders the image or surface 300 that includes the area 302 may utilize multiple viewpoints or multi-view rendering.

[0038]

[0049] As shown herein, a GPU or graphics processor unit may use a tiled rendering architecture to reduce power consumption or conserve memory bandwidth. As further described above, this rendering method may include a visibility pass that divides a scene into multiple bins and identifies triangles that are visible in each bin. Thus, in tiled rendering, a full screen may be divided into multiple bins or tiles. A scene may then be rendered multiple times, for example, once or multiple times per bin. In graphics rendering aspects, some graphics applications may render to a single target, i.e., a render target, once or multiple times. For example, in graphics rendering, a frame buffer on a system memory may be updated multiple times. A frame buffer may be a portion of memory or random access memory (RAM), including, for example, a bitmap or storage, to help store display data for a GPU. A frame buffer may also be a memory buffer that contains a complete frame of data. Furthermore, a frame buffer may be a logical buffer. In some aspects, updating the frame buffer may be performed in bin or tile rendering, where the surface is divided into multiple bins or tiles, as described above, and each bin or tile may then be rendered separately. Additionally, in tile rendering, the frame buffer may be partitioned into multiple bins or tiles.

[0039]

[0050] In some aspects of graphics processing, rendering may be performed in multiple locations and / or on multiple devices, e.g., to split the rendering workload among different devices. For example, rendering may be split between a server and a client device, which may be referred to as "split rendering." In some cases, split rendering may be a method for bringing content to user devices or head mounted displays (HMDs), and a portion of the graphics processing may be performed outside the device or HMD, e.g., at a server. Split rendering may be performed for several different types of applications, e.g., virtual reality (VR) applications, augmented reality (AR) applications, and / or extended reality (XR) applications. In VR applications, content displayed at the user device may correspond to artificial or animated content, e.g., content rendered at a server or at the user device. In AR or XR content, some of the content displayed at the user device may correspond to real-world content, e.g., objects in the real world, and some of the content may be artificial or animated content. Additionally, the synthetic or animated content and the real-world content may be displayed on an optical see-through or video see-through device such that a user can simultaneously view the real-world objects and the synthetic or animated content, in some aspects the synthetic or animated content may be referred to as augmented content, or vice versa.

[0040]

[0051] In certain types of graphics processing, such as augmented reality (AR) applications, virtual reality (VR) applications, or three-dimensional (3D) games, objects may occlude (i.e., hide, cover, block, or obstruct) other objects from the user device's viewpoint. Different types of occlusions may also exist within AR / VR applications or 3D games. For example, augmented content may occlude real-world content, e.g., a rendered object may partially occlude a real object. Also, real-world content may occlude augmented content, e.g., a real object may partially occlude a rendered object. This overlap of real-world content and augmented content, which creates the above-mentioned occlusions, is one reason why augmented content and real-world content may blend very seamlessly in AR. This may also result in difficulty in resolving occlusions of augmented content and real-world content, which may cause edges of augmented and real-world content to overlap inaccurately.

[0041]

[0052] In some aspects, the augmented content or augmentation may be rendered on top of the real-world or see-through content. Therefore, the augmentation may occlude any objects behind the augmentation from the user device's perspective. For example, pixels without occlusion material, i.e., red (R), green (G), blue (B) (RGB) values ​​not equal to (0,0,0), may be rendered to occlude real-world objects. Thus, augmentations with certain values ​​(e.g., non-zero values) may occlude real-world objects behind the augmentation. In a video see-through system, the same effect may be achieved by compositing the augmentation layer into the foreground. Thus, the augmentation may occlude the rendered content or real-world content, or vice versa. As indicated above, accurately capturing occlusions may be a challenge when utilizing VR / AR systems or 3D games. Moreover, this may be especially true for VR / AR systems or 3D games that have latency challenges. In some aspects, it may be difficult to accurately capture augmented content that is occluding other augmented content, or to accurately capture real-world objects that are occluding augmented content. Accurate occlusion of augmented content or real-world content as well as occluded augmented content can help users obtain a more realistic and immersive VR / AR or 3D gaming experience.

[0042]

[0053] FIG. 4 shows a diagram 400 of an example image or scene in graphics processing. The diagram 400 includes an augmented content 410 and an object 420 including an edge 422, where the object 420 can be an augmented content or a real-world content. More specifically, FIG. 4 shows an object 420, e.g., a door, occluding the augmented content 410, e.g., a person. In fact, the augmented content 410 is occluded by the object 420. As indicated above, FIG. 4 shows that it may be difficult to accurately achieve the effect of a certain content occluding the augmented content in an AR / VR system or a 3D game. As shown in FIG. 4, an AR / VR system or a 3D game may have difficulty accurately reflecting when an object occludes the augmented content or vice versa. In fact, some AR systems or 3D games may have difficulty quickly and accurately processing the edge of two objects when the objects are real-world content and augmented content.

[0043]

[0054] Some aspects of graphics processing may utilize occlusion culling, a feature that disables the rendering of objects when they are not currently seen by the camera because they are obscured (i.e., occluded) by other objects. For example, occlusion culling may remove objects in a scene from the camera rendering workload if they are completely occluded by objects closer to the camera. The occlusion culling process may refer to that, given a set of occluders (i.e., objects that occlude other objects) and a set of occluders (i.e., objects that are occluded by other objects) for a camera field of view in a scene, the visibility of the occluders may be derived or determined based on the relative locations of the occluders. An occlusion culling calculation may refer to the calculation of occlusion culling in a scene or image. For example, the occlusion culling calculation may be associated with whether any pixel in a scene is occluded by an occluding object in the scene. In some aspects, the occlusion culling process may traverse a scene with a virtual camera to build a hierarchy of a potentially visible set of objects. This data may be used by each camera in a graphics processing application to identify which objects are visible or not visible. Occlusion culling may increase rendering performance (e.g., GPU rendering performance) by simply not rendering objects that are outside the camera's field of view or that are hidden by other objects closer to the camera. In one example, the occlusion culling process may be defined as follows: Given a set of occluders (i.e., objects that occlude other objects) and a set of occluders (i.e., objects that are occluded by other objects) for a camera field of view in a scene, the visibility of the occluders may be derived or determined based on the relative locations of the occluders. For example, if a wall in a scene is closer to the camera than a set of barrels behind the wall and there is a hole in the wall, the occlusion culling process may determine which barrels are visible through the hole in the wall.

[0044]

[0055] Some types of occlusion culling in graphics processing (e.g., occlusion culling for CPU or GPU) may include software occlusion culling. For example, in software occlusion culling, for each occluder and each primitive / triangle in a scene, the primitive / triangle may be rasterized to generate an occluder depth map. Also, for each occluder in a scene, a projected axis-aligned bounding box (AABB) area in the occluder depth map and the closest depth value of the occluded object may be determined. In addition, the closest depth value of the occluded object within the projected AABB area may be determined on the occluder depth map. In a setting where closer objects have larger depth values, an occluded object may be determined to be visible if its closest depth value is greater than any depth value inside the AABB area. Otherwise, if the closest depth value of the occluded object is not greater than all depth values ​​inside the AABB area, the occluded object may be determined to be invisible.

[0045]

[0056] In addition, there are other types of occlusion culling (e.g., occlusion culling in CPU or GPU) used in graphics processing. For example, there is a type of software occlusion culling that utilizes CPU single instruction multiple data (SIMD) components. This SIMD optimized software occlusion culling may correspond to an optimized version of an open source project. This type of software occlusion culling may render depth maps (e.g., occlusion depth maps) more accurately and faster (e.g., 2-16 times faster) than other types of software occlusion culling. SIMD optimized software occlusion culling may also be more accurate than GPU hardware occlusion culling (HWOC). For example, SIMD optimized software occlusion culling may achieve zero frame latency throughout the rendering process, while GPU hardware occlusion culling may cause latency issues for at least one frame throughout the rendering process. Additionally, SIMD optimized software occlusion culling may result in a smaller amount of draw calls compared to other types of software occlusion culling.

[0046]

[0057] FIG. 5 illustrates a diagram 500 including an example of an occlusion depth map utilized in graphics processing. More specifically, the diagram 500 in FIG. 5 illustrates an occlusion depth map 502 for a scene in graphics processing. As shown in FIG. 5, the diagram 500 includes an occlusion depth map 502 having occluded areas 510 and non-occluded areas 520. For example, as shown in FIG. 5, white (or light gray) areas in the occlusion depth map 502 are occluded areas 510 that correspond to pixels that are covered by an occluding object (e.g., a house) at a depth relative to the camera. Similarly, as shown in FIG. 5, black areas in the occlusion depth map 502 are non-occluded areas 520 that correspond to pixels that are not covered by an occluding object (e.g., a house) at a depth relative to the camera. Thus, the white colors in the occluded areas 510 correspond to pixels that are covered by the house at a depth, while the black colors in the unoccluded areas 520 correspond to pixels that are not covered by the house at a depth.

[0047]

[0058] As shown in FIG. 5, different areas in an occlusion depth map (e.g., occlusion depth map 502) may correspond to data for different pixels. Thus, a pixel in an occlusion depth map may be associated with a particular type of pixel information. For example, a pixel in an occlusion depth map may include information related to whether the pixel is covered by an occlusion object or an occluder. For example, in FIG. 5, occluded area 510 may correspond to information for a pixel covered by a house. In addition, a pixel in an occlusion depth map may include information related to a depth value of the pixel. This pixel information in an occlusion depth map may correspond to a type of scene in a graphics process. Pixel information may refer to information associated with a pixel or set of pixels in a scene. An occlusion depth map may refer to a map of the corresponding depths of all occluders in a scene. A mask may refer to a configuration or method of hiding or filtering data. For example, when a mask is applied to data, the result is a new set of data that is a filtered version of the original data.

[0048]

[0059] Some types of scenes in graphics processing may be complex, which may result in a large number of pixels being present in the scene. Thus, since a large number of pixels may be present in the scene, there may be a large amount of pixel information associated with the occlusion depth map. The large amount of pixel information in the occlusion depth map may correspond to a large amount of memory that may be required to store the pixel information. Furthermore, the large amount of pixel information in the occlusion depth map may correspond to a long rendering time for all the pixel information. In light of the above, it may be beneficial to reduce the amount of pixel information associated with the occlusion depth map. It may also be beneficial to reduce the amount of storage space utilized to store the pixel information associated with the occlusion depth map. It may also be beneficial to reduce the amount of processing or rendering time associated with the pixel information for the occlusion depth map. To do so, it may be beneficial to utilize a particular type of configuration or mask associated with the occlusion depth map.

[0049]

[0060] Aspects of the present disclosure may reduce the amount of pixel information associated with an occlusion depth map. Additionally, aspects of the present disclosure may reduce the amount of storage space utilized to store pixel information associated with an occlusion depth map. Aspects of the present disclosure may also reduce the amount of processing or rendering time associated with pixel information for an occlusion depth map. For example, aspects of the present disclosure may utilize a particular type of configuration associated with an occlusion depth map. That is, aspects presented herein may utilize different mask configurations associated with an occlusion depth map.

[0050]

[0061] Aspects presented herein may utilize different pattern mask configurations in the occlusion depth map. For example, because occlusion culling may not require the occlusion depth map to have precise pixel data for each pixel, aspects presented herein may utilize configurations or masks that do not represent all pixels. For example, aspects of the present disclosure may utilize a checkerboard mask configuration for the occlusion depth map. In some aspects, when utilizing a checkerboard mask configuration, aspects presented herein may calculate depth values ​​for a certain amount of pixels (e.g., half of the total pixels). The depth value may refer to the depth value of the pixel in the frame or scene. In addition, when utilizing a checkerboard mask configuration, for another portion of the pixels (e.g., half of the pixels), aspects presented herein may determine or derive whether the pixel is covered by an occluding object (i.e., an occluder). Furthermore, aspects presented herein may determine whether the pixel is covered by an occluding object or an occluder for all of the total pixels. Furthermore, the pattern mask configuration may correspond to a visibility mask. A pattern mask configuration may refer to a configuration for a pattern mask (i.e., a mask associated with a pattern). A visibility mask may refer to a mask for visibility data. A pixel may also be associated with coverage information within a frame or scene. The coverage information may indicate whether a pixel is occluded by an occluding object in a scene or frame.

[0051]

[0062] By utilizing a pattern mask configuration (e.g., a checkerboard mask configuration), aspects presented herein may increase the amount of calculation error associated with the occluder depth map. A checkerboard mask configuration may refer to a configuration for a checkerboard mask (i.e., a mask associated with a checkerboard pattern). Also, in a checkerboard configuration, a first pixel (e.g., a black pixel) may be interleaved with a second pixel (e.g., a white pixel). That is, the first pixel may alternate with the second pixel in a checkerboard pattern. For example, by utilizing a checkerboard mask configuration, aspects presented herein may distribute possible errors more evenly, which may make the increase in error in the occluder depth map during the occluder query process negligible. In some instances, when utilizing a pattern mask configuration (e.g., a checkerboard mask configuration), aspects presented herein may calculate and store an amount of data (e.g., a total amount of data) associated with a particular pixel (e.g., a black or white pixel in a checkerboard mask configuration). The amount of data may correspond to a depth value for each of these pixels (e.g., half of the total pixels). In addition, when utilizing a pattern mask configuration (e.g., a checkerboard mask configuration), aspects presented herein may calculate and store information regarding whether a pixel is covered by an occluder (e.g., whether a white pixel in a checkerboard mask configuration is covered by an occluder). This information regarding whether a pixel is covered by an occluder may be stored for a certain amount of pixels (e.g., half of the total pixels). In some instances, information regarding whether a pixel is covered by an occluder may be stored for all of the pixels.

[0052]

[0063] FIG. 6 illustrates a diagram 600 including an example of a pattern mask configuration for graphics processing. More specifically, the diagram 600 in FIG. 6 illustrates a checkerboard mask configuration 610 for use with an occluder depth map in graphics processing. The diagram 600 in FIG. 6 includes the checkerboard mask configuration 610, a set of first pixels 612 (e.g., white pixels), and a set of second pixels 614 (e.g., black pixels). As illustrated in FIG. 6, the first pixels 612 may correspond to half of the total pixel amount, and the second pixels 614 may correspond to the other half of the total pixel amount. The embodiments presented herein may calculate and store depth values ​​for the first pixels 612 (e.g., white pixels) or the second pixels 614 (e.g., black pixels). In addition, the embodiments presented herein may calculate and store information regarding whether each of the first pixels 612 (e.g., white pixels) or the second pixels 614 (e.g., black pixels) is covered by an occluder. The embodiments presented herein may also calculate and store information regarding whether all of the first pixel 612 and the second pixel 614 are covered by an occluder.

[0053]

[0064] In some cases of occlusion culling, the corresponding depth values ​​for each pixel may be stored in a memory or buffer. For example, a particular number of bits (e.g., 16 bits (2 bytes), 24 bits, or 32 bits) may be stored for the depth value of each pixel. In some aspects, depth values ​​for a block of pixels (e.g., a block of 8x8 pixels) may be stored simultaneously. For example, for a block of 8x8 pixels (e.g., 64 pixels), 128 bytes (e.g., 128 bytes = 8x8x2) of memory may be required to store depth values ​​for all pixels in the block. Using the checkerboard mask optimization described above, aspects presented herein may store a reduced number of bytes (e.g., 64 + 8 = 72 bytes). For example, the total data including depth values ​​for black pixels in a checkerboard mask configuration may equal (8x8 / 2)x2 = 64 bytes. Also, to store information regarding whether a particular pixel (e.g., a white pixel) is covered by an occluder, aspects presented herein may store a reduced number of bits or bytes (e.g., 8×8 / 2=32 bits=4 bytes). In some cases, the entire block coverage mask (e.g., an 8×8 block coverage mask) may be stored, which may correspond to a particular number of bits / bytes (e.g., 8×8=64 bits=8 bytes). It may be more convenient to use the above calculations for occluded object queries during occluded object AABB checks.

[0054]

[0065] The aspects presented herein are flexible and may calculate depth data or pixel information for a particular pixel with or without utilizing checkerboard mask optimization. That is, the optimization of the checkerboard mask configuration may be utilized (i.e., turned on) or not utilized (i.e., turned off). Thus, the checkerboard mask configuration may have an on / off capability. In some cases, when the checkerboard mask configuration is off, the aspects presented herein may store all of the depth data for all of the pixels, whereby no coverage mask is utilized and stored to update the depth data. In other cases, when the checkerboard mask configuration is utilized (i.e., checkerboard mask optimization is on), the aspects presented herein may store a depth value (e.g., 16 bits) for each of the first set of pixels (e.g., all of the black pixels in the checkerboard mask configuration). In addition, when the checkerboard mask configuration is turned on, the aspects presented herein may utilize a binary coverage mask for the entire image or scene. A coverage mask may refer to a mask of pixel coverage in an image (i.e., whether a pixel is occluded by an object in the image). A binary coverage mask may refer to a coverage mask expressed in binary terms.

[0055]

[0066] 7A and 7B show diagrams 700 and 750 of example occluder depth maps without and with a checkerboard mask configuration, respectively. FIG. 7A shows diagram 700 including an occluder depth map without a checkerboard mask configuration. More specifically, diagram 700 in FIG. 7A shows an occluder depth map 702 including unoccluded areas 711 and unoccluded areas 712. As shown in FIG. 7A, the black portions in the occluder depth map 702 correspond to unoccluded areas (e.g., unoccluded areas 711 and unoccluded areas 712) and the horizontal stripes correspond to occluded areas (e.g., occluded areas 720). FIG. 7B shows diagram 750 including an occluder depth map using a checkerboard mask configuration. More specifically, diagram 750 in Figure 7B illustrates an occluder depth map 752 including unoccluded areas 761, unoccluded areas 762, and a checkerboard mask configuration 770. As shown in Figure 7B, the black portions in the occluder depth map 752 correspond to unoccluded areas (e.g., unoccluded areas 761 and unoccluded areas 762) and the checkerboard portions correspond to occluded areas (i.e., the black / white checkerboard patterned areas shown covered by the checkerboard mask configuration 770). Figures 7A and 7B illustrate the difference between not utilizing a checkerboard mask configuration (i.e., Figure 7A) and utilizing a checkerboard mask configuration (i.e., Figure 7B, which includes the checkerboard mask configuration 770).

[0056]

[0067] In addition, by utilizing a checkerboard mask configuration, aspects presented herein may optimize data storage for use with an occluder depth map. For example, when a checkerboard mask configuration is utilized, real occluder data may be stored for depth values ​​of a block of pixels. For example, depth data may be stored for a particular number of pixels (e.g., half of the pixels) that may correspond to black or white pixels in the checkerboard mask configuration. Also, when a checkerboard mask configuration is utilized, real occluder data may be stored for a binary coverage mask. In some instances, particular pixels (e.g., white pixels) in the checkerboard mask configuration may correspond to pixels that are covered by an occluding object or occluder. Similarly, other particular pixels (e.g., black pixels) in the checkerboard mask configuration may correspond to pixels that are not covered by an occluding object or occluder. Furthermore, when a checkerboard mask configuration is utilized, it may affect occluded queries (i.e., queries about objects that are occluded by other objects). For example, when a checkerboard mask configuration is utilized, it may correspond to the occluded pixel having the maximum depth value (eg, the depth value closest to the camera).

[0057]

[0068] FIG. 8 illustrates a diagram 800 including an example of an occlusion depth map. More specifically, diagram 800 in FIG. 8 illustrates an occlusion depth map including a checkerboard mask configuration. As shown in FIG. 8, diagram 800 includes an occlusion depth map 802 including unoccluded area 811, unoccluded area 812, unoccluded area 813, and checkerboard mask configuration 820. FIG. 8 illustrates that the black portions in the occlusion depth map 802 correspond to unoccluded areas (e.g., unoccluded areas 811-813) and the checkerboard portions correspond to occluded areas (i.e., black / white checkerboard patterned areas shown covered by checkerboard mask configuration 820). Diagram 800 in FIG. 8 also includes different regions (e.g., region 830 and region 840), each of which refers to a particular region in occlusion depth map 802.

[0058]

[0069] As shown in FIG. 8, region 830 is a particular area in occluder depth map 802 that includes both occluded and unoccluded areas 812. Region 830 may correspond to an axis-aligned bounding box (AABB) of a projected occluder (i.e., an object that is occluded by another object). In occluder depth map 802, region 830 (e.g., AABB) may encompass black pixels in unoccluded areas 812, meaning that occluded objects may potentially be visible from those black pixels in unoccluded areas 812. Thus, occluded objects in region 830 may be treated as visible during occlusion culling calculations. Therefore, as illustrated with region 830, aspects presented herein may utilize a binary coverage mask in occluder visibility queries.

[0059]

[0070] 8, region 840 is a particular area in the occluder depth map 802 that contains an occluded area. Region 840 may also correspond to an axis-aligned bounding box (AABB) of a projected occluded object. Region 840 may correspond to a particular depth value (e.g., 47360=185 * 256), but other pixels with depth data in the occluder depth map 802 may have a different depth value (e.g., 51968=203 * The depth values ​​may include depth values ​​around 256 (depth values ​​of 256). Thus, because these depth values ​​may differ, the occluded object may be determined to be not visible. Therefore, as shown with region 840, aspects presented herein may utilize depth data in occluded object visibility queries.

[0060]

[0071] As described herein, a checkerboard mask optimization may be utilized for occluder culling to reduce memory usage and improve performance with evenly distributed error. In some aspects (e.g., 16 bits per depth configuration), this optimization may save frame buffer memory (e.g., 9 / 16 of the frame buffer memory) and time (e.g., 5-20% of the total time). In some cases, this optimization may produce the same query results as the ground truth approach. Also, this optimization may produce incorrect culling results when an occluder occupies one pixel, as well as when an occluder occupies 5-20% of the pixel's depth frame buffer memory and the total time. In addition, this optimization may produce incorrect culling results when an occluder occupies one pixel and the pixel's depth information is skipped. In some cases, aspects presented herein may expand the covered pixel area of ​​an occluder to at least two pixels to force a depth check.

[0061]

[0072] Aspects of the present disclosure may include several benefits or advantages. For example, aspects presented herein may result in improved speed for rendering and depth rasterization. That is, checkerboard optimization may result in faster final depth rasterization because a certain amount of pixels (e.g., half of the pixels) may require derivation of depth information. Therefore, the total occluder rendering time may be reduced by a certain percentage (e.g., reduced by 5-20% on mobile platforms). As described above, checkerboard mask optimization may result in evenly distributed errors smaller than one pixel. The occluder query results may be the same as compared to the default approach. The checkerboard mask configuration may also optimize the amount of depth buffer memory utilized to store pixel data. For example, the checkerboard mask optimization described herein may reduce the depth buffer memory by a certain amount (e.g., 128-72) / 128=7 / 16=43.75% reduction).

[0062]

[0073] 9 is a communication flow diagram 900 of graphics processing in accordance with one or more techniques of the present disclosure. As shown in FIG. 9, diagram 900 includes example communications between a CPU 902, a GPU 904, and a memory 906 (e.g., system memory, double data rate (DDR) memory, or video memory) in accordance with one or more techniques of the present disclosure.

[0063]

[0074] At 910, the CPU 902 may obtain pixel information (e.g., information 912 from the GPU 904) for a plurality of pixels in at least one frame, the at least one frame being included within a plurality of frames in a scene.

[0064]

[0075] At 920, the CPU 902 may calculate a depth value for each of the first set of pixels of the plurality of pixels. In some aspects, calculating the depth value for each of the first set of pixels may further include calculating a quantity of bits for the depth value for each of the first set of pixels.

[0065]

[0076] At 930, the CPU 902 may identify whether the first set of pixels, or each of the second set of pixels, where the second set of pixels is included in the plurality of pixels, or both, are occluded by at least one occluding object in the scene. In some cases, if the pixel is covered by at least one occluding object in the occluder depth map, then each of the first set of pixels, or each of the second set of pixels, or both, may be occluded by at least one occluding object or occluder depth. Also, the amount of the first set of pixels may be substantially equal to half of the plurality of pixels, and the amount of the second set of pixels may be substantially equal to half of the plurality of pixels, such that the amount of the first set of pixels is substantially equal to the amount of the second set of pixels. In some aspects, substantially equal may correspond to being within a threshold percentage of a value. For example, the first amount of pixels may be substantially equal to the second amount of pixels if the first amount of pixels is 10% of the second amount of pixels.

[0066]

[0077] At 940, the CPU 902 may configure the visibility mask before configuring the pattern mask configuration associated with the visibility mask.

[0067]

[0078] At 950, the CPU 902 may configure a pattern mask configuration associated with a visibility mask for a plurality of pixels, the pattern mask configuration including a first pattern portion corresponding to a first set of pixels and a second pattern portion corresponding to a second set of pixels. In some aspects, the pattern mask configuration may be a checkerboard mask configuration (e.g., a checkerboard mask configuration including a set of odd rows, a set of even rows, a set of odd columns, and a set of even columns), the first pattern portion may be a first checkerboard portion, the second pattern portion may be a second checkerboard portion, and each of the first set of pixels may include a first pair of pixel coordinates in the set of pixel coordinates and each of the second set of pixels may include a second pair of pixel coordinates in the set of pixel coordinates. The first checkerboard portion may correspond to one or more first pixels (e.g., black pixels) of the checkerboard mask configuration and the second checkerboard portion may correspond to one or more second pixels (e.g., white pixels) of the checkerboard mask configuration, or the first checkerboard portion may correspond to one or more second pixels (e.g., white pixels) of the checkerboard mask configuration and the second checkerboard portion may correspond to one or more first pixels (e.g., black pixels) of the checkerboard mask configuration, and the one or more first pixels may be interleaved with the one or more second pixels, such that the one or more first pixels and the one or more second pixels may be distributed in an interleaved pattern. In some aspects, the sum of the first pair of pixel coordinates for each of the first set of pixels may be equal to an odd value and the sum of the second pair of pixel coordinates for each of the second set of pixels may be equal to an even value. Further, a sum of a first pair of pixel coordinates for each of the first set of pixels may be equal to an even value, and a sum of a second pair of pixel coordinates for each of the second set of pixels may be equal to an odd value. In some cases, the first checkerboard portion may correspond to a set of odd rows and a set of odd columns, and the second checkerboard portion may correspond to a set of even rows and a set of even columns.Also, a first checkerboard portion may correspond to a set of even rows and a set of even columns, and a second checkerboard portion may correspond to a set of odd rows and a set of odd columns.

[0068]

[0079] At 960, the CPU 902 may generate a binary coverage mask prior to outputting the indication of coverage information for each of the first set of pixels and each of the second set of pixels, and outputting the indication of coverage information for each of the first set of pixels and each of the second set of pixels may include storing the binary coverage mask. The coverage information for each of the first set of pixels and each of the second set of pixels occluded by the at least one occluding object may correspond to a first value in the binary coverage mask, and the coverage information for each of the first set of pixels and each of the second set of pixels not occluded by the at least one occluding object may correspond to a second value in the binary coverage mask. Also, the first value in the binary coverage mask may correspond to a bit value of 1, and the second value in the binary coverage mask may correspond to a bit value of 0.

[0069]

[0080] At 970, the CPU 902 may output a depth value for each of the first set of pixels and an indication of coverage information for each of the first set of pixels or each of the second set of pixels, or both, based on the pattern mask configuration, the coverage information being associated with whether the first set of pixels or each of the second set of pixels, or both, are occluded by at least one occluding object in the scene (e.g., output indication 972 to memory 906 and / or output indication 974 to GPU 904). In some cases, the coverage information for each of the first set of pixels and each of the second set of pixels may correspond to a binary coverage mask. The depth value for each of the first set of pixels and the coverage information for each of the first set of pixels or each of the second set of pixels, or both, may be stored in a system memory. In some aspects, outputting the indication of the depth value for each of the first set of pixels and the coverage information for each of the first set of pixels or the second set of pixels, or both, may include storing in a system memory the depth value for each of the first set of pixels and the coverage information for each of the first set of pixels or the second set of pixels, or both. That is, the CPU may store in the system memory the depth value for each of the first set of pixels and the coverage information for each of the first set of pixels or the second set of pixels, or both. Also, in some aspects, outputting the indication of the depth value for each of the first set of pixels and the coverage information for each of the first set of pixels or the second set of pixels, or both, may include transmitting to at least one component of a graphics processing unit (GPU) or a central processing unit (CPU) the indication of the depth value for each of the first set of pixels and the coverage information for each of the first set of pixels or the second set of pixels, or both.That is, the CPU may transmit to at least one component of a graphics processing unit (GPU) or a central processing unit (CPU) a depth value for each of the first set of pixels and an indication of coverage information for each of the first set of pixels or each of the second set of pixels, or both. Additionally, in some aspects outputting the depth value for each of the first set of pixels and an indication of coverage information for each of the first set of pixels or each of the second set of pixels, or both, may include outputting, via at least one of an antenna or a transceiver, a depth value for each of the first set of pixels and an indication of coverage information for each of the first set of pixels or each of the second set of pixels, or both.

[0070]

[0081] At 980, the CPU 902 may retrieve depth values ​​for the first set of pixels and coverage information for the first set of pixels and / or the second set of pixels, or both (e.g., retrieve data 982 from memory 906).

[0071]

[0082] At 990, the CPU 902 may perform an occlusion culling calculation based on the depth values ​​for the first set of pixels and coverage information for the first set of pixels and the second set of pixels, the occlusion culling calculation being associated with whether any of the first set of pixels or any of the second set of pixels is not occluded by at least one occluding object in the scene, where each of the first set of pixels is not occluded by the at least one occluding object if the depth value of the pixel is closer to a viewpoint (e.g., camera) of the scene than the occlusion depth map value, and each of the second set of pixels is not occluded by the at least one occluding object if the coverage information of the pixel is a non-zero value.

[0072]

[0083] 10 is a flowchart 1000 of an example method of graphics processing in accordance with one or more techniques of this disclosure. The method may be performed by a CPU, a GPU, e.g., an apparatus for graphics processing, a graphics processor, a wireless communication device, and / or any apparatus capable of performing graphics processing as used with respect to the examples of FIGS. 1-9. The methods described herein may provide several benefits, such as improved communication signaling, resource utilization, and / or power conservation.

[0073]

[0084] At 1002, as described with respect to the examples in Figures 1-9, a CPU may obtain pixel information for a plurality of pixels in at least one frame, the at least one frame being included within a plurality of frames in a scene. For example, as described at 910 in Figure 9, a CPU 902 may obtain pixel information for a plurality of pixels in at least one frame, the at least one frame being included within a plurality of frames in a scene. Furthermore, step 1002 may be performed by processing unit 120 of Figure 1.

[0074]

[0085] At 1004, the CPU may calculate a depth value for each of the first set of pixels of the plurality of pixels, as described with respect to the examples in Figures 1-9. For example, the CPU 902 may calculate a depth value for each of the first set of pixels of the plurality of pixels, as described at 920 in Figure 9. Furthermore, step 1004 may be performed by the processing unit 120 of Figure 1. In some aspects, calculating the depth value for each of the first set of pixels may further include calculating a bit quantity for the depth value for each of the first set of pixels.

[0075]

[0086] At 1006, as described with respect to the examples in FIGS. 1-9, the CPU may identify whether the first set of pixels, or each of the second set of pixels, where the second set of pixels is included within a plurality of pixels, or both, are occluded by at least one occluding object in the scene. For example, as described at 930 in FIG. 9, the CPU 902 may identify whether the first set of pixels, or each of the second set of pixels, where the second set of pixels is included within a plurality of pixels, or both, are occluded by at least one occluding object in the scene. Furthermore, step 1006 may be performed by the processing unit 120 of FIG. 1. In some cases, if the pixel is covered by at least one occluding object in the occluder depth map, then each of the first set of pixels, or each of the second set of pixels, or both, may be occluded by at least one occluding object or occluder depth. Also, the amount of the first set of pixels may be substantially equal to half the plurality of pixels, and the amount of the second set of pixels may be substantially equal to half the plurality of pixels, such that the amount of the first set of pixels is substantially equal to the amount of the second set of pixels.

[0076]

[0087] At 1010, as described with respect to the examples in Figures 1-9, the CPU may configure a pattern mask configuration associated with a visibility mask for a plurality of pixels, the pattern mask configuration including a first pattern portion corresponding to a first set of pixels and a second pattern portion corresponding to a second set of pixels. For example, as described at 950 in Figure 9, the CPU 902 may configure a pattern mask configuration associated with a visibility mask for a plurality of pixels, the pattern mask configuration including a first pattern portion corresponding to the first set of pixels and a second pattern portion corresponding to the second set of pixels. Furthermore, step 1010 may be performed by the processing unit 120 of Figure 1. In some aspects, the pattern mask configuration may be a checkerboard mask configuration (e.g., a checkerboard mask configuration including a set of odd rows, a set of even rows, a set of odd columns, and a set of even columns), the first pattern portion may be a first checkerboard portion, the second pattern portion may be a second checkerboard portion, each of the first set of pixels may include a first pair of pixel coordinates in the set of pixel coordinates, and each of the second set of pixels may include a second pair of pixel coordinates in the set of pixel coordinates. The first checkerboard portion may correspond to one or more first pixels (e.g., black pixels) of the checkerboard mask configuration and the second checkerboard portion may correspond to one or more second pixels (e.g., white pixels) of the checkerboard mask configuration, or the first checkerboard portion may correspond to one or more second pixels (e.g., white pixels) of the checkerboard mask configuration and the second checkerboard portion may correspond to one or more first pixels (e.g., black pixels) of the checkerboard mask configuration, and the one or more first pixels may be interleaved with the one or more second pixels, such that the one or more first pixels and the one or more second pixels may be distributed in an interleaved pattern.In some aspects, the sum of the first pair of pixel coordinates for each of the first set of pixels may be equal to an odd value, and the sum of the second pair of pixel coordinates for each of the second set of pixels may be equal to an even value. Further, the sum of the first pair of pixel coordinates for each of the first set of pixels may be equal to an even value, and the sum of the second pair of pixel coordinates for each of the second set of pixels may be equal to an odd value. In some instances, the first checkerboard portion may correspond to a set of odd rows and a set of odd columns, and the second checkerboard portion may correspond to a set of even rows and a set of even columns. Also, the first checkerboard portion may correspond to a set of even rows and a set of even columns, and the second checkerboard portion may correspond to a set of odd rows and a set of odd columns.

[0077]

[0088] At 1014, as described with respect to the examples in FIG. 1-9, the CPU may output, based on the pattern mask configuration, a depth value for each of the first set of pixels and an indication of coverage information for each of the first set of pixels or each of the second set of pixels, or both, where the coverage information is associated with whether the first set of pixels or each of the second set of pixels, or both, is occluded by at least one occluding object in the scene. For example, as described at 970 in FIG. 9, the CPU 902 may output, based on the pattern mask configuration, a depth value for each of the first set of pixels and an indication of coverage information for each of the first set of pixels or each of the second set of pixels, or both, where the coverage information is associated with whether the first set of pixels or each of the second set of pixels, or both, is occluded by at least one occluding object in the scene. Furthermore, step 1014 may be performed by the processing unit 120 of FIG. 1. In some cases, the coverage information for each of the first set of pixels and each of the second set of pixels may correspond to a binary coverage mask. The depth values ​​for each of the first set of pixels and the coverage information for each of the first set of pixels or the second set of pixels, or both, may be stored in a system memory. In some aspects, outputting an indication of the depth values ​​for each of the first set of pixels and the coverage information for each of the first set of pixels or the second set of pixels, or both, may include storing in the system memory the depth values ​​for each of the first set of pixels and the coverage information for each of the first set of pixels or the second set of pixels, or both. That is, the CPU may store in the system memory the depth values ​​for each of the first set of pixels and the coverage information for each of the first set of pixels or the second set of pixels, or both.Also, in some aspects, outputting the depth value for each of the first set of pixels and an indication of coverage information for each of the first set of pixels or the second set of pixels, or both, may include transmitting the depth value for each of the first set of pixels and an indication of coverage information for each of the first set of pixels or the second set of pixels, or both, to at least one component of a graphics processing unit (GPU) or a central processing unit (CPU). That is, the CPU may transmit the depth value for each of the first set of pixels and an indication of coverage information for each of the first set of pixels or the second set of pixels, or both, to at least one component of a graphics processing unit (GPU) or a central processing unit (CPU). Additionally, in some aspects outputting a depth value for each of the first set of pixels and an indication of coverage information for each of the first set of pixels or the second set of pixels, or both, may include outputting, via at least one of the antenna or the transceiver, a depth value for each of the first set of pixels and an indication of coverage information for each of the first set of pixels or the second set of pixels, or both.

[0078]

[0089] 11 is a flowchart 1100 of an example method of graphics processing in accordance with one or more techniques of this disclosure. The method may be performed by a CPU, a GPU, e.g., an apparatus for graphics processing, a graphics processor, a wireless communication device, and / or any apparatus capable of performing graphics processing as used with respect to the examples of FIGS. 1-9. The methods described herein may provide several benefits, such as improved communication signaling, resource utilization, and / or power savings.

[0079]

[0090] At 1102, the CPU may obtain pixel information for a plurality of pixels in at least one frame, the at least one frame being included within a plurality of frames in a scene, as described with respect to the examples in Figures 1-9. For example, as described at 910 in Figure 9, the CPU 902 may obtain pixel information for a plurality of pixels in at least one frame, the at least one frame being included within a plurality of frames in a scene. Furthermore, step 1102 may be performed by processing unit 120 of Figure 1.

[0080]

[0091] At 1104, the CPU may calculate a depth value for each of the first set of pixels of the plurality of pixels, as described with respect to the examples in Figures 1-9. For example, the CPU 902 may calculate a depth value for each of the first set of pixels of the plurality of pixels, as described at 920 in Figure 9. Furthermore, step 1104 may be performed by the processing unit 120 of Figure 1. In some aspects, calculating the depth value for each of the first set of pixels may further include calculating a bit quantity for the depth value for each of the first set of pixels.

[0081]

[0092] At 1106, as described with respect to the examples in FIGS. 1-9, the CPU may identify whether the first set of pixels, or each of the second set of pixels, where the second set of pixels is included within a plurality of pixels, or both, are occluded by at least one occluding object in the scene. For example, as described at 930 in FIG. 9, the CPU 902 may identify whether the first set of pixels, or each of the second set of pixels, where the second set of pixels is included within a plurality of pixels, or both, are occluded by at least one occluding object in the scene. Furthermore, step 1106 may be performed by the processing unit 120 of FIG. 1. In some cases, if the pixel is covered by at least one occluding object in the occluder depth map, then each of the first set of pixels, or each of the second set of pixels, or both, may be occluded by at least one occluding object or occluder depth. Also, the amount of the first set of pixels may be substantially equal to half the plurality of pixels, and the amount of the second set of pixels may be substantially equal to half the plurality of pixels, such that the amount of the first set of pixels is substantially equal to the amount of the second set of pixels.

[0082]

[0093] At 1108, the CPU may configure the visibility mask before configuring the pattern mask configuration associated with the visibility mask, as described with respect to the examples in Figures 1-9. For example, the CPU 902 may configure the visibility mask before configuring the pattern mask configuration associated with the visibility mask, as described in 940 of Figure 9. Furthermore, step 1108 may be performed by the processing unit 120 of Figure 1.

[0083]

[0094] At 1110, as described with respect to the examples in Figures 1-9, the CPU may configure a pattern mask configuration associated with a visibility mask for a plurality of pixels, the pattern mask configuration including a first pattern portion corresponding to a first set of pixels and a second pattern portion corresponding to a second set of pixels. For example, as described at 950 in Figure 9, the CPU 902 may configure a pattern mask configuration associated with a visibility mask for a plurality of pixels, the pattern mask configuration including a first pattern portion corresponding to a first set of pixels and a second pattern portion corresponding to a second set of pixels. Furthermore, step 1110 may be performed by the processing unit 120 of Figure 1. In some aspects, the pattern mask configuration may be a checkerboard mask configuration (e.g., a checkerboard mask configuration including a set of odd rows, a set of even rows, a set of odd columns, and a set of even columns), the first pattern portion may be a first checkerboard portion, the second pattern portion may be a second checkerboard portion, each of the first set of pixels may include a first pair of pixel coordinates in the set of pixel coordinates, and each of the second set of pixels may include a second pair of pixel coordinates in the set of pixel coordinates. The first checkerboard portion may correspond to one or more first pixels (e.g., black pixels) of the checkerboard mask configuration and the second checkerboard portion may correspond to one or more second pixels (e.g., white pixels) of the checkerboard mask configuration, or the first checkerboard portion may correspond to one or more second pixels (e.g., white pixels) of the checkerboard mask configuration and the second checkerboard portion may correspond to one or more first pixels (e.g., black pixels) of the checkerboard mask configuration, and the one or more first pixels may be interleaved with the one or more second pixels, such that the one or more first pixels and the one or more second pixels may be distributed in an interleaved pattern.In some aspects, the sum of the first pair of pixel coordinates for each of the first set of pixels may be equal to an odd value, and the sum of the second pair of pixel coordinates for each of the second set of pixels may be equal to an even value. Further, the sum of the first pair of pixel coordinates for each of the first set of pixels may be equal to an even value, and the sum of the second pair of pixel coordinates for each of the second set of pixels may be equal to an odd value. In some instances, the first checkerboard portion may correspond to a set of odd rows and a set of odd columns, and the second checkerboard portion may correspond to a set of even rows and a set of even columns. Also, the first checkerboard portion may correspond to a set of even rows and a set of even columns, and the second checkerboard portion may correspond to a set of odd rows and a set of odd columns.

[0084]

[0095] At 1112, as described with respect to the examples in Figures 1-9, the CPU may generate a binary coverage mask before outputting an indication of coverage information for each of the first set of pixels and each of the second set of pixels, and outputting the indication of coverage information for each of the first set of pixels and each of the second set of pixels may include storing the binary coverage mask. For example, as described at 960 in Figure 9, the CPU 902 may generate a binary coverage mask before storing the coverage information for each of the first set of pixels or each of the second set of pixels, or both, and storing the coverage information for each of the first set of pixels or each of the second set of pixels, or both may include storing the binary coverage mask. Furthermore, step 1112 may be performed by the processing unit 120 of Figure 1. The coverage information for each of the first set of pixels and each of the second set of pixels occluded by the at least one occluding object may correspond to a first value in the binary coverage mask, and the coverage information for each of the first set of pixels and each of the second set of pixels not occluded by the at least one occluding object may correspond to a second value in the binary coverage mask, and the first value in the binary coverage mask may correspond to a bit value of 1, and the second value in the binary coverage mask may correspond to a bit value of 0.

[0085]

[0096] At 1114, as described with respect to the examples in FIG. 1-9, the CPU may output, based on the pattern mask configuration, a depth value for each of the first set of pixels and an indication of coverage information for each of the first set of pixels or each of the second set of pixels, or both, where the coverage information is associated with whether the first set of pixels or each of the second set of pixels, or both, is occluded by at least one occluding object in the scene. For example, as described at 970 in FIG. 9, the CPU 902 may output, based on the pattern mask configuration, a depth value for each of the first set of pixels and an indication of coverage information for each of the first set of pixels or each of the second set of pixels, or both, where the coverage information is associated with whether the first set of pixels or each of the second set of pixels, or both, is occluded by at least one occluding object in the scene. Furthermore, step 1114 may be performed by the processing unit 120 of FIG. 1. In some cases, the coverage information for each of the first set of pixels and each of the second set of pixels may correspond to a binary coverage mask. The depth values ​​for each of the first set of pixels and the coverage information for each of the first set of pixels or the second set of pixels, or both, may be stored in a system memory. In some aspects, outputting an indication of the depth values ​​for each of the first set of pixels and the coverage information for each of the first set of pixels or the second set of pixels, or both, may include storing in the system memory the depth values ​​for each of the first set of pixels and the coverage information for each of the first set of pixels or the second set of pixels, or both. That is, the CPU may store in the system memory the depth values ​​for each of the first set of pixels and the coverage information for each of the first set of pixels or the second set of pixels, or both.Also, in some aspects, outputting the depth value for each of the first set of pixels and an indication of coverage information for each of the first set of pixels or the second set of pixels, or both, may include transmitting the depth value for each of the first set of pixels and an indication of coverage information for each of the first set of pixels or the second set of pixels, or both, to at least one component of a graphics processing unit (GPU) or a central processing unit (CPU). That is, the CPU may transmit the depth value for each of the first set of pixels and an indication of coverage information for each of the first set of pixels or the second set of pixels, or both, to at least one component of a graphics processing unit (GPU) or a central processing unit (CPU). Additionally, in some aspects outputting a depth value for each of the first set of pixels and an indication of coverage information for each of the first set of pixels or the second set of pixels, or both, may include outputting, via at least one of the antenna or the transceiver, a depth value for each of the first set of pixels and an indication of coverage information for each of the first set of pixels or the second set of pixels, or both.

[0086]

[0097] At 1116, the CPU may retrieve depth values ​​for the first set of pixels and coverage information for the first set of pixels and / or the second set of pixels, or both, as described with respect to the examples in Figures 1-9. For example, as described at 980 in Figure 9, the CPU 902 may retrieve depth values ​​for each of the first set of pixels and coverage information for each of the first set of pixels or the second set of pixels, or both. Furthermore, step 1116 may be performed by the processing unit 120 of Figure 1.

[0087]

[0098] At 1118, as described with respect to the examples in FIGS. 1-9 , the CPU may perform an occlusion culling calculation based on the depth values ​​for the first set of pixels and coverage information for the first set of pixels and the second set of pixels, the occlusion culling calculation being associated with whether any of the first set of pixels or any of the second set of pixels are not occluded by at least one occluding object in the scene, where each of the first set of pixels is not occluded by the at least one occluding object if the depth value of the pixel is closer to the viewpoint of the scene than the occlusion depth map value, and each of the second set of pixels is not occluded by the at least one occluding object if the coverage information of the pixel is a non-zero value. For example, as illustrated in 990 of Figure 9, CPU 902 may perform an occlusion culling calculation based on depth values ​​for the first set of pixels and coverage information for the first set of pixels and the second set of pixels, the occlusion culling calculation being associated with whether any of the first set of pixels or any of the second set of pixels are not occluded by at least one occluding object in the scene, where each of the first set of pixels is not occluded by at least one occluding object if the depth value of the pixel is closer to the viewpoint of the scene than the occlusion depth map value, and each of the second set of pixels is not occluded by at least one occluding object if the coverage information of the pixel is a non-zero value. Further, step 1118 may be performed by processing unit 120 of Figure 1.

[0088]

[0099] In an arrangement, a method or apparatus for graphics processing is provided. The apparatus may be a CPU, a GPU, a graphics processor, or some other processor capable of performing graphics processing. In an aspect, the apparatus may be a processing unit 120 in the device 104, or some other hardware in the device 104 or another device. The apparatus, e.g., the processing unit 120, may include means for obtaining pixel information for a plurality of pixels in at least one frame, the at least one frame being included within a plurality of frames in a scene. The apparatus, e.g., the processing unit 120, may also include means for calculating a depth value for each of a first set of pixels of the plurality of pixels. The apparatus, e.g., the processing unit 120, may also include means for identifying whether each of the first set of pixels, or a second set of pixels, the second set of pixels being included within the plurality of pixels, or both, are occluded by at least one occluding object in the scene. The apparatus, e.g., processing unit 120, may also include means for configuring a pattern mask configuration associated with a visibility mask for the plurality of pixels, the pattern mask configuration including a first pattern portion corresponding to the first set of pixels and a second pattern portion corresponding to the second set of pixels. The apparatus, e.g., processing unit 120, may also include means for outputting, based on the pattern mask configuration, a depth value for each of the first set of pixels and an indication of coverage information for each of the first set of pixels or each of the second set of pixels, or both, where the coverage information is associated with whether the first set of pixels or each of the second set of pixels, or both, is occluded by at least one occluding object in the scene.The apparatus, e.g., processing unit 120, may also include means for generating a binary coverage mask prior to storing coverage information for each of the first set of pixels or each of the second set of pixels, or both, where storing the coverage information for the first set of pixels or each of the second set of pixels, or both, includes storing the binary coverage mask, and means for retrieving depth values ​​for each of the first set of pixels and the coverage information for the first set of pixels or each of the second set of pixels, or both. The apparatus, e.g., processing unit 120, may also include means for performing an occlusion culling calculation based on the depth values ​​for each of the first set of pixels and the coverage information for the first set of pixels or each of the second set of pixels, or both, where the occlusion culling calculation is associated with whether the first set of pixels or each of the second set of pixels, or both, is occluded by at least one occluding object in the scene. The apparatus, eg, processing unit 120, may also include means for configuring the visibility mask prior to configuring the pattern mask configuration associated with the visibility mask.

[0089]

[0100] The subject matter described herein may be implemented to realize one or more benefits or advantages. For example, the graphics processing techniques described above may be used by a CPU, GPU, graphics processor, or any other processor that may perform graphics processing to implement the checkerboard mask optimization techniques described herein. This may also be accomplished at a low cost compared to other graphics processing techniques. Furthermore, the graphics processing techniques herein may improve or accelerate data processing or execution. Furthermore, the graphics processing techniques herein may improve resource or data utilization and / or resource efficiency. In addition, aspects of the present disclosure may utilize checkerboard mask optimization techniques to improve memory bandwidth efficiency and / or increase processing speed in a CPU or GPU.

[0090]

[0101] It should be understood that the particular order or hierarchy of the blocks in the disclosed processes / flow charts is an example of an example approach. It should be understood that the particular order or hierarchy of the blocks in those processes / flow charts can be rearranged based on design preferences. Further, some blocks can be combined or omitted. The accompanying method claims present elements of the various blocks in an example order, and are not meant to be limited to the particular order or hierarchy presented.

[0091]

[0102] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Thus, the claims are not limited to the aspects set forth herein but are to be accorded the full scope consistent with the claim language, and reference to an element in the singular does not mean "the only one" unless so expressly stated, but rather means "one or more." The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other aspects.

[0092]

[0103] Unless otherwise specified, the term "some" refers to one or more, and the term "or" may be interpreted as "and / or" unless the context dictates otherwise. Combinations such as "at least one of A, B, or C," "one or more of A, B, or C," "at least one of A, B, and C," "one or more of A, B, and C," and "A, B, C, or any combination thereof" include any combination of A, B, and / or C, and may include multiple As, multiple Bs, or multiple Cs. Specifically, combinations such as "at least one of A, B, or C," "one or more of A, B, or C," "at least one of A, B, and C," "one or more of A, B, and C," and "A, B, C, or any combination thereof" may be A only, B only, C only, A and B, A and C, B and C, or A and B and C, and any such combination may include one or more elements of A, B, or C. All structural and functional equivalents of the elements of the various aspects described throughout this disclosure that are known or that later become known to those of skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Furthermore, nothing disclosed herein is intended to be made public, regardless of whether such disclosure is expressly recited in the claims. Words such as "module," "mechanism," "element," "device," and the like may not be substitutes for the word "means." Therefore, no element of a claim should be construed as a means-plus-function unless the element is expressly recited using the phrase "means for."

[0093]

[0104] In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term "processing unit" is used throughout this disclosure, such a processing unit may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique, or other module described herein is implemented in software, the function, processing unit, technique, or other module described herein may be stored on or transmitted over as one or more instructions or code on a computer-readable medium.

[0094]

[0105] In accordance with the present disclosure, the term "or" may be interpreted as "and / or" unless the context dictates otherwise. In addition, phrases such as "one or more" or "at least one" may be used with respect to some features disclosed herein and not with respect to other features, but the features where such language is not used may be interpreted as having such implied meaning unless the context dictates otherwise.

[0095]

[0106] In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term "processing unit" is used throughout this disclosure, such a processing unit may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique, or other module described herein is implemented in software, the function, processing unit, technique, or other module described herein may be stored on or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media may include computer data storage media or communication media, including any medium that facilitates transfer of a computer program from one place to another. In this manner, computer-readable media may generally correspond to (1) a tangible computer-readable storage medium that is non-transitory, or (2) a communication medium, such as a signal or carrier wave. Data storage media may be any available medium that can be accessed by one or more computers or one or more processors to retrieve instructions, code, and / or data structures for implementing the techniques described in this disclosure. By way of example and not limitation, such computer readable media may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices. As used herein, disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks typically reproduce data magnetically and discs reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer readable media. A computer program product may include a computer readable medium.

[0096]

[0107] The code may be executed by one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application specific integrated circuits (ASICs), arithmetic logic units (ALUs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuitry. Thus, the term "processor" as used herein may refer to any of the above structures, or any other structure suitable for implementing the techniques described herein. The techniques may also be implemented entirely in one or more circuits or logic elements.

[0097]

[0108] The techniques of the present disclosure may be implemented in a wide variety of devices or apparatuses, including wireless handsets, integrated circuits (ICs) or sets of ICs, e.g., chipsets. In this disclosure, various components, modules or units have been described to highlight functional aspects of devices configured to implement the disclosed techniques, but the components, modules or units do not necessarily require realization by different hardware units. Rather, as described above, the various units may be combined in a codec hardware unit or may be provided by a collection of interoperable hardware units including one or more processors as described above, together with appropriate software and / or firmware. Thus, the term "processor" as used herein may refer to any of the above structures or any other structures suitable for implementing the techniques described herein. Also, the techniques may be fully implemented in one or more circuits or logic elements.

[0098]

[0109] The following aspects are exemplary only and can be combined with other aspects or teachings described herein without limitation.

[0099]

[0110]

[0013] Aspect 1 is an apparatus for graphics processing including at least one processor coupled to a memory, wherein based at least in part on first information stored in the memory, the at least one processor obtains pixel information for a plurality of pixels in at least one frame, the at least one frame being included within a plurality of frames in a scene, calculates a depth value for each of a first set of pixels of the plurality of pixels, and identifies whether the first set of pixels, or each of a second set of pixels, the second set of pixels being included within the plurality of pixels, or both, are occluded by at least one occluding object in the scene. , configuring a pattern mask configuration associated with a visibility mask for a plurality of pixels, the pattern mask configuration including a first pattern portion corresponding to a first set of pixels and a second pattern portion corresponding to a second set of pixels, and outputting, based on the pattern mask configuration, a depth value for each of the first set of pixels and an indication of coverage information for each of the first set of pixels or each of the second set of pixels, or both, where the coverage information is associated with whether the first set of pixels or each of the second set of pixels, or both, is occluded by at least one occluding object in the scene.

[0100]

[0111] Example 2 is the apparatus of example 1, wherein the pattern mask configuration is a checkerboard mask configuration, the first pattern portion is a first checkerboard portion, the second pattern portion is a second checkerboard portion, each of the first set of pixels includes a first pair of pixel coordinates within the set of pixel coordinates, and each of the second set of pixels includes a second pair of pixel coordinates within the set of pixel coordinates.

[0101]

[0112] Example 3 is the apparatus of example 2, wherein the first checkerboard portion corresponds to one or more first pixels of the checkerboard mask configuration and the second checkerboard portion corresponds to one or more second pixels of the checkerboard mask configuration, or the first checkerboard portion corresponds to one or more second pixels of the checkerboard mask configuration and the second checkerboard portion corresponds to one or more first pixels of the checkerboard mask configuration, and the one or more first pixels are interleaved with the one or more second pixels, thereby distributing the one or more first pixels and the one or more second pixels in an interleaved pattern.

[0102]

[0113] Example 4 is the apparatus of example 2 or 3, wherein a sum of a first pair of pixel coordinates for each of the first set of pixels is equal to an odd value, and a sum of a second pair of pixel coordinates for each of the second set of pixels is equal to an even value.

[0103]

[0114] Example 5 is the apparatus of any of Examples 2-4, wherein a sum of a first pair of pixel coordinates for each of the first set of pixels is equal to an even value, and a sum of a second pair of pixel coordinates for each of the second set of pixels is equal to an odd value.

[0104]

[0115] Example 6 is the apparatus of any of Examples 1-5, wherein the coverage information for each of the first set of pixels and each of the second set of pixels corresponds to a binary coverage mask.

[0105]

[0116] Example 7 is the apparatus of example 6, wherein the at least one processor is further configured to generate a binary coverage mask prior to outputting the indication of coverage information for each of the first set of pixels and each of the second set of pixels, and wherein the at least one processor is configured to store the binary coverage mask for outputting the indication of coverage information for each of the first set of pixels and each of the second set of pixels.

[0106]

[0117] Example 8 is the apparatus of example 6 or 7, wherein the coverage information for each of the first set of pixels and each of the second set of pixels that are occluded by the at least one occluding object corresponds to a first value in the binary coverage mask, and the coverage information for each of the first set of pixels and each of the second set of pixels that are not occluded by the at least one occluding object corresponds to a second value in the binary coverage mask.

[0107]

[0118] Example 9 is the apparatus of any of Examples 6-8, wherein a first value in the binary coverage mask corresponds to a bit value of one and a second value in the binary coverage mask corresponds to a bit value of zero.

[0108]

[0119] Example 10 is the device of any of Examples 1-9, wherein the at least one processor is further configured to extract depth values ​​for the first set of pixels, and coverage information for the first set of pixels and the second set of pixels.

[0109]

[0120] Example 11 is the apparatus of example 10, wherein the at least one processor is further configured to perform occlusion culling calculations based on depth values ​​for the first set of pixels and coverage information for the first set of pixels and the second set of pixels, the occlusion culling calculations being associated with whether any of the first set of pixels or any of the second set of pixels are not occluded by at least one occluding object in the scene, and each of the first set of pixels is not occluded by the at least one occluding object if the depth value of the pixel is closer to a viewpoint of the scene than the occlusion depth map value, and each of the second set of pixels is not occluded by the at least one occluding object if the coverage information of the pixel is a non-zero value.

[0110]

[0121] Example 12 is the apparatus of any of Examples 1 to 11, wherein if the pixel is covered by at least one occluding object in the occluder depth map, then each of the first set of pixels or each of the second set of pixels, or both, are occluded by at least one occluding object or occluder depth map.

[0111]

[0122] Example 13 is the apparatus of any of Examples 1-12, wherein the at least one processor is further configured to configure the visibility mask prior to configuring the pattern mask configuration associated with the visibility mask.

[0112]

[0123] Example 14 is the device of any of Examples 1-13, wherein an amount of the first set of pixels is substantially equal to half of the plurality of pixels, and an amount of the second set of pixels is substantially equal to half of the plurality of pixels, thereby causing the amount of the first set of pixels to be substantially equal to the amount of the second set of pixels.

[0113]

[0124] Example 15 is the apparatus of any of examples 1 to 14, wherein to calculate a depth value for each of the first set of pixels, at least one processor is configured to calculate a bit amount for the depth value for each of the first set of pixels.

[0114]

[0125] Example 16 is the apparatus of any of examples 1-15, wherein at least one processor is configured to store, in the system memory, a depth value for each of the first set of pixels and coverage information for each of the first set of pixels or each of the second set of pixels, or both, to output an indication of a depth value for each of the first set of pixels and coverage information for either the first set of pixels or the second set of pixels, or both.

[0115]

[0126] Example 17 is the apparatus of any of Examples 1-16, wherein the at least one processor is configured to transmit, to at least one component of a graphics processing unit (GPU) or a central processing unit (CPU), a depth value for each of the first set of pixels and an indication of coverage information for either the first set of pixels or the second set of pixels, or both, to output a depth value for each of the first set of pixels and an indication of coverage information for either the first set of pixels or the second set of pixels, or both.

[0116]

[0127] Example 18 is the apparatus of any of Examples 1-17, wherein the apparatus is a wireless communications device and further includes at least one of an antenna or a transceiver coupled to the at least one processor, and wherein the at least one processor is configured to output, via the at least one of the antenna or transceiver, a depth value for each of the first set of pixels and an indication of coverage information for either the first set of pixels or each of the second set of pixels, or both, a depth value for each of the first set of pixels and an indication of coverage information for either the first set of pixels or each of the second set of pixels, or both.

[0117]

[0128] A nineteenth aspect is a graphics processing method for implementing any one of the first to eighteenth aspects.

[0118]

[0129] A twenty-first embodiment is an apparatus for graphics processing including means for implementing any one of the first to eighteenth embodiments.

[0119]

[0130] Example 21 is a computer-readable medium (e.g., a non-transitory computer-readable medium) storing computer-executable code that, when executed by at least one processor, causes the at least one processor to perform any of Examples 1-18.

Claims

1. 1. An apparatus for graphics processing, comprising: Memory, at least one processor coupled to the memory, wherein based at least in part on the first information stored in the memory, the at least one processor: Obtain pixel information for a plurality of pixels in at least one frame, the at least one frame being included within a plurality of frames in a scene; Calculating a depth value for each of a first set of pixels of the plurality of pixels; identifying whether each of the first set of pixels, or a second set of pixels, where the second set of pixels is included in the plurality of pixels, or both, is occluded by at least one occluding object in the scene; configuring a pattern mask arrangement associated with a visibility mask for the plurality of pixels, the pattern mask arrangement including a first pattern portion corresponding to the first set of pixels and a second pattern portion corresponding to the second set of pixels; outputting, based on the pattern-mask configuration, the depth value for each of the first set of pixels and an indication of coverage information for each of the first set of pixels or the second set of pixels, or both, the coverage information being associated with whether the first set of pixels or each of the second set of pixels, or both, is occluded by the at least one occluding object in the scene. The apparatus is configured to:

2. 2. The apparatus of claim 1, wherein the pattern mask configuration is a checkerboard mask configuration, the first pattern portion is a first checkerboard portion, the second pattern portion is a second checkerboard portion, each of the first set of pixels comprises a first pair of pixel coordinates within a set of pixel coordinates, and each of the second set of pixels comprises a second pair of pixel coordinates within the set of pixel coordinates.

3. 3. The apparatus of claim 2, wherein the first checkerboard portion corresponds to one or more first pixels of the checkerboard mask configuration and the second checkerboard portion corresponds to one or more second pixels of the checkerboard mask configuration, or the first checkerboard portion corresponds to the one or more second pixels of the checkerboard mask configuration and the second checkerboard portion corresponds to the one or more first pixels of the checkerboard mask configuration, and the one or more first pixels are interleaved with the one or more second pixels, such that the one or more first pixels and the one or more second pixels are distributed in an interleaved pattern.

4. 3. The apparatus of claim 2, wherein a sum of the first pair of pixel coordinates for each of the first set of pixels is equal to an odd value and a sum of the second pair of pixel coordinates for each of the second set of pixels is equal to an even value.

5. 3. The apparatus of claim 2, wherein a sum of the first pair of pixel coordinates for each of the first set of pixels is equal to an even value and a sum of the second pair of pixel coordinates for each of the second set of pixels is equal to an odd value.

6. The apparatus of claim 1 , wherein the coverage information for each of the first set of pixels and each of the second set of pixels corresponds to a binary coverage mask.

7. The at least one processor:

7. The apparatus of claim 6, further configured to generate the binary coverage mask prior to the output of the indication of the coverage information for each of the first set of pixels and each of the second set of pixels, and wherein the at least one processor is configured to store the binary coverage mask in order to output the indication of the coverage information for each of the first set of pixels and each of the second set of pixels.

8. 7. The apparatus of claim 6, wherein the coverage information for each of the first set of pixels and each of the second set of pixels occluded by the at least one occluding object corresponds to a first value in the binary coverage mask, and the coverage information for each of the first set of pixels and each of the second set of pixels not occluded by the at least one occluding object corresponds to a second value in the binary coverage mask.

9. 9. The apparatus of claim 8, wherein the first value in the binary coverage mask corresponds to a bit value of one and the second value in the binary coverage mask corresponds to a bit value of zero.

10. The at least one processor: The apparatus of claim 1 , further configured to retrieve the depth values ​​for the first set of pixels and the coverage information for the first set of pixels and the second set of pixels.

11. The at least one processor:

11. The apparatus of claim 10, further configured to perform an occlusion culling calculation based on the depth value for the first set of pixels and the coverage information for the first set of pixels and the second set of pixels, the occlusion culling calculation being associated with whether any of the first set of pixels or any of the second set of pixels is not occluded by the at least one occluding object in the scene, wherein each of the first set of pixels is not occluded by the at least one occluding object if the depth value of the pixel is closer to a viewpoint of the scene than an occlusion depth map value, and each of the second set of pixels is not occluded by the at least one occluding object if the coverage information of the pixel is a non-zero value.

12. 2. The apparatus of claim 1 , wherein if the pixel is covered by the at least one occluding object in an occluder depth map, then each of the first set of pixels or each of the second set of pixels, or both, are occluded by the at least one occluding object or the occluder depth map.

13. The at least one processor: The apparatus of claim 1 , further configured to configure the visibility mask prior to the configuration of the pattern mask configuration associated with the visibility mask.

14. 2. The apparatus of claim 1, wherein an amount of the first set of pixels is substantially equal to half of the plurality of pixels and an amount of the second set of pixels is substantially equal to half of the plurality of pixels, whereby the amount of the first set of pixels is substantially equal to the amount of the second set of pixels.

15. 2. The apparatus of claim 1 , wherein to calculate the depth value for each of the first set of pixels, the at least one processor is configured to calculate a quantity of bits for the depth value for each of the first set of pixels.

16. 2. The apparatus of claim 1, wherein the at least one processor is configured to store in a system memory the depth values ​​for each of the first set of pixels and the coverage information for each of the first set of pixels or the second set of pixels, or both, and to output the indication of the depth values ​​for each of the first set of pixels and the coverage information for each of the first set of pixels or the second set of pixels, or both.

17. 2. The apparatus of claim 1, wherein the at least one processor is configured to transmit the depth values ​​for each of the first set of pixels and the indication of the coverage information for each of the first set of pixels or the second set of pixels, or both, to at least one component of a graphics processing unit (GPU) or a central processing unit (CPU) to output the depth values ​​for each of the first set of pixels and the indication of the coverage information for each of the first set of pixels or the second set of pixels, or both.

18. 2. The apparatus of claim 1, wherein the apparatus is a wireless communications device and further comprises at least one of an antenna or a transceiver coupled to the at least one processor, wherein the at least one processor is configured to output, via at least one of the antenna or the transceiver, the depth values ​​for each of the first set of pixels and the indication of the coverage information for each of the first set of pixels or each of the second set of pixels, or both, the depth values ​​for each of the first set of pixels and the indication of the coverage information for each of the first set of pixels or each of the second set of pixels, or both.

19. 1. A method of graphics processing, comprising: obtaining pixel information for a plurality of pixels in at least one frame, the at least one frame being included within a plurality of frames in a scene; calculating a depth value for each of a first set of pixels of the plurality of pixels; identifying whether each of the first set of pixels, or a second set of pixels, where the second set of pixels is included in the plurality of pixels, or both, is occluded by at least one occluding object in the scene; configuring a pattern mask configuration associated with a visibility mask for the plurality of pixels, the pattern mask configuration including a first pattern portion corresponding to the first set of pixels and a second pattern portion corresponding to the second set of pixels; outputting, based on the pattern mask configuration, the depth value for each of the first set of pixels and an indication of coverage information for each of the first set of pixels or each of the second set of pixels, or both, the coverage information being associated with whether the first set of pixels or each of the second set of pixels, or both, is occluded by the at least one occluding object in the scene; A method comprising:

20. 20. The method of claim 19, wherein the pattern mask configuration is a checkerboard mask configuration, the first pattern portion is a first checkerboard portion, the second pattern portion is a second checkerboard portion, each of the first set of pixels comprises a first pair of pixel coordinates within a set of pixel coordinates, and each of the second set of pixels comprises a second pair of pixel coordinates within the set of pixel coordinates.

21. 21. The method of claim 20, wherein the first checkerboard portion corresponds to one or more first pixels of the checkerboard mask configuration and the second checkerboard portion corresponds to one or more second pixels of the checkerboard mask configuration, or the first checkerboard portion corresponds to the one or more second pixels of the checkerboard mask configuration and the second checkerboard portion corresponds to the one or more first pixels of the checkerboard mask configuration, and the one or more first pixels are interleaved with the one or more second pixels, whereby the one or more first pixels and the one or more second pixels are distributed in an interleaved pattern.

22. 21. The method of claim 20, wherein a sum of the first pair of pixel coordinates for each of the first set of pixels is equal to a first odd-valued value and a sum of the second pair of pixel coordinates for each of the second set of pixels is equal to a first even-valued value, or wherein a sum of the first pair of pixel coordinates for each of the first set of pixels is equal to a second even-valued value and a sum of the second pair of pixel coordinates for each of the second set of pixels is equal to a second odd-valued value.

23. 20. The method of claim 19, wherein the coverage information for each of the first set of pixels and each of the second set of pixels corresponds to a binary coverage mask.

24. 24. The method of claim 23, further comprising generating the binary coverage mask prior to outputting the indication of the coverage information for each of the first set of pixels and each of the second set of pixels, and wherein outputting the indication of the coverage information for each of the first set of pixels and each of the second set of pixels comprises storing the binary coverage mask.

25. 24. The method of claim 23, wherein the coverage information for each of the first set of pixels and each of the second set of pixels occluded by the at least one occluding object corresponds to a first value in the binary coverage mask, and the coverage information for each of the first set of pixels and each of the second set of pixels not occluded by the at least one occluding object corresponds to a second value in the binary coverage mask, the first value in the binary coverage mask corresponding to a bit value of 1 and the second value in the binary coverage mask corresponding to a bit value of 0.

26. The method further comprising: retrieving the depth values ​​for the first set of pixels and the coverage information for the first set of pixels and the second set of pixels; 20. The method of claim 19, further comprising: performing an occlusion culling calculation based on the depth value for each of the first set of pixels and the coverage information for the first set of pixels and the second set of pixels, wherein the occlusion culling calculation is associated with whether any of the first set of pixels or any of the second set of pixels is not occluded by the at least one occluding object in the scene, wherein each of the first set of pixels is not occluded by the at least one occluding object if the depth value of the pixel is closer to a viewpoint of the scene than an occlusion depth map value, and each of the second set of pixels is not occluded by the at least one occluding object if the coverage information of the pixel is a non-zero value.

27. 20. The method of claim 19, wherein if the pixel is covered by the at least one occluding object in an occluder depth map, then each of the first set of pixels or each of the second set of pixels, or both, are occluded by the at least one occluding object or the occluder depth map.

28. The method further comprising:

20. The method of claim 19, further comprising: configuring the visibility mask prior to configuring the pattern mask configuration associated with the visibility mask; and wherein calculating the depth values ​​for each of the first set of pixels further comprises calculating a quantity of bits for the depth values ​​for each of the first set of pixels.

29. 1. An apparatus for graphics processing, comprising: means for obtaining pixel information for a plurality of pixels in at least one frame, the at least one frame being included within a plurality of frames in a scene; means for calculating a depth value for each of a first set of pixels of the plurality of pixels; means for identifying whether each of the first set of pixels, or a second set of pixels, where the second set of pixels is included in the plurality of pixels, or both, is occluded by at least one occluding object in the scene; means for configuring a pattern mask arrangement associated with a visibility mask for the plurality of pixels, the pattern mask arrangement including a first pattern portion corresponding to the first set of pixels and a second pattern portion corresponding to the second set of pixels; means for outputting, based on the pattern-mask configuration, an indication of the depth value for each of the first set of pixels and coverage information for each of the first set of pixels or each of the second set of pixels, or both, wherein the coverage information is associated with whether the first set of pixels or each of the second set of pixels, or both, are occluded by the at least one occluding object in the scene; An apparatus comprising:

30. 1. A computer-readable medium comprising computer-executable code for graphics processing, the code, when executed by a processor, causing the processor to: obtaining pixel information for a plurality of pixels in at least one frame, the at least one frame being included within a plurality of frames in a scene; calculating a depth value for each of a first set of pixels of the plurality of pixels; identifying whether each of the first set of pixels, or a second set of pixels, where the second set of pixels is included in the plurality of pixels, or both, are occluded by at least one occluding object in the scene; configuring a pattern mask arrangement associated with a visibility mask for the plurality of pixels, the pattern mask arrangement including a first pattern portion corresponding to the first set of pixels and a second pattern portion corresponding to the second set of pixels; a computer-readable medium storing computer-executable code for outputting, based on the pattern mask configuration, an indication of the depth value for each of the first set of pixels, and coverage information for each of the first set of pixels or the second set of pixels, or both, wherein the coverage information is associated with whether the first set of pixels or each of the second set of pixels, or both, are occluded by the at least one occluding object in the scene.

Images