Differential current buffer circuit and DC and AC power supply including the same

Abstract

The differential current buffer circuit comprises a differential input stage supplied from a first positive power supply voltage and a first negative power supply voltage. The input stage has a first input circuit connected between a first current path of a first current and a second mirror connected between a second positive and negative power supply voltage. The second input circuit is connected between first current paths of third and fourth current mirrors connected between the second positive and negative power supply voltages. The second positive voltage is higher than the first positive power supply voltage and the second negative voltage is lower than the first negative power supply voltage. The first and second outputs of the differential current buffer circuit are tapped off between the second current paths of the first and second current mirrors and the second current paths of the third and fourth current mirrors, respectively.

Description

[Technical field]

[0001] The present invention relates to a fully differential current source apparatus for electrical stimulation of a patient, and more particularly to a wideband high voltage buffer circuit for DC and AC power sources to inject current over a wide range of frequencies into patient tissue for electrical stimulation or electrical bioimpedance measurements. [Background technology]

[0002] The injection or application of electric current into a patient's tissue has been used for several years for electrical bioimpedance measurements and electrical stimulation to investigate and treat, among other things, muscle and brain disorders. The use of electric current allows precise control of the charge injected into the tissue and eliminates the effects of electrical resistance between the electrode and the tissue.

[0003] Such currents must be applied over a wide range of frequencies and tightly controlled with respect to frequency, amplitude, and phase in order to obtain reproducible results under a variety of circumstances, e.g., with different conductivities of a patient's skin and underlying tissue in different sessions or between different patients.

[0004] A widely used current source design for this purpose is the Howland current source, which is an op-amp in a specific feedback design. An example of a Howland current source is shown in Figure 1a. The non-inverting input of op-amp 10 is connected to the positive input of the Howland current source through a first resistor R1. The output signal of op-amp 10 is fed back to the non-inverting input of op-amp 10 through a second resistor R2. The non-inverting input of op-amp 10 is connected to the positive input of the Howland current source through a load Z L The output node V of the Howland current source to which X The output signal of op amp 10 is also provided to the inverting input of op amp 10 through a fourth resistor R4. The inverting input of op amp 10 is also connected to the negative input of the Howland current source through a third resistor R3. The strength of the feedback from the output to both the "+" and "-" inputs is equal, i.e., the ratios of R1 / R2 and R3 / R4 are equal.

[0005] The "output" node V, which is the "+" input of the op-amp X It is easy to see that when Vin+ and Vin- are both grounded, the "gain" is equal to 1 / R1, i.e., the output current per change in input voltage. Resistors R2, R3, and R4 have no effect when the output is grounded and only the "+" input voltage is active. When the "-" input is moved upwards, the gain to the ground output node is -R4 / R3 x 1 / R2. The ratio of the resistors is defined as R1 / R2=R3 / R4, so its gain is also equal to -1 / R1. Note that the gain is inverted with respect to the "-" input. Thus, when both Vin+ and Vin- are moved together, I out It is easy to see that there is no change in Vin+, i.e. common mode signals are rejected. When Vin+ rises, the "gain" to the output node is 1 / R1. In that case, the "-" input also has a gain of 1 / R1, but with a negative sign. Thus, this current pump can accept either positive or negative inputs, i.e. it has a true differential input.

[0006] As shown below, the output impedance is high so that the gain is correct for all output voltages and impedances as well as all inputs. Using this analysis, it is easy to see that the output impedance is very high. When both signal inputs are grounded, and when the "output" node V X If Vin+ or Vin- is being pulled up, then some source is driving resistor "R1". But when the + input of the op-amp is pulled up, the - input must also rise, and the output will rise, providing enough current through R2 to offset the current through R1, and thus making the output impedance very high indeed. The principle of linear superposition tells us that no matter what Vin+ or Vin- is, Z L Whatever it is, V out Whatever the current I out is (Vin+-Vin-)×1 / R1.

[0007] Detailed information regarding the Howland current source can be found, for example, in Texas Instruments™ application report AN-1515, SNOA474A - January 2008 - April 2013 revision, entitled "A Comprehensive Study of the Howland Current Source."

[0008] While the Howland current source is limited in its range and gain options, the improved or modified Howland current source increases the gain and higher output current options by using a differential amplifier to apply a voltage across a shunt resistor Rs to form a current source capable of driving a wide range of load resistances. More information can be found in Texas Instruments' application SBOA437-October 2020 entitled "Analysis of Improved Howland Current Pump Configurations."

[0009] For electrical stimulation where multiple currents are applied between multiple electrode pairs, the simple current source of Figure 1a is not applicable and a fully differential design is required to ensure that current flows between the desired electrode pairs. Two Howland current sources fed in antiphase are a suitable solution, preferably the 4-feedback enhanced Howland current source with fully differential op-amp of Figure 1b is utilized.

[0010] The difficulty here is that commercially available fully differential op-amps have limitations regarding the maximum voltage or current they can provide at their output or available bandwidth. In practice, this means that relatively low voltage swings are available over a wider frequency range, severely limiting the application of integrated op-amps to applications where voltages below 35 volts are acceptable.

[0011] It may be possible to build an op-amp using discrete components with higher voltage ratings, but this would necessarily result in reduced accuracy, second to the prohibitively high cost due to component binning, and especially due to the poor thermal coupling that can be achieved for the large number of transistors in a practical design. [Prior art documents] [Non-patent literature]

[0012] [Non-Patent Document 1] Texas Instruments, "A Comprehensive Study of the Howland Current Source", Application Report AN-1515, SNOA474A, January 2008, revised April 2013 [Non-Patent Document 2] Texas Instruments, “Analysis of Improved Howland Current Pump Configurations”, Application Report SBOA437, October 2020 Summary of the Invention [Problem to be solved by the invention]

[0013] Therefore, it is desirable to design a differential current buffer with wide bandwidth, high accuracy, linearity, and high output impedance that can provide a high voltage output swing. It is also desirable to design DC and AC power supplies that implement the differential current buffer circuit. [Means for solving the problem]

[0014] This object is achieved by a differential current buffer circuit according to claim 1 and by a DC and AC power supply according to claim 8. Advantageous embodiments and developments are set forth in the dependent claims.

[0015] According to a first aspect of the present invention, a differential current buffer circuit comprises a differential input stage supplied from a first positive power supply voltage and a first negative power supply voltage. The differential input stage has a first input circuit connected between a first current path of a first output current mirror connected to a second positive power supply voltage and a first current path of a second output current mirror connected to a second negative power supply voltage. The differential input stage further has a second input circuit connected between a first current path of a third output current mirror connected to the second positive power supply voltage and a first current path of a fourth output current mirror connected to the second negative power supply voltage. With reference to a reference potential, e.g., ground potential, the second positive power supply voltage is higher than the first positive power supply voltage and the second negative power supply voltage is lower than the first negative power supply voltage. The first output of the differential current buffer circuit is tapped off between the second current paths of each of the first and second output current mirrors, and the second output of the differential current buffer circuit is tapped off between the second current paths of each of the third and fourth output current mirrors.

[0016] In one or more embodiments of the differential current buffer circuit, the first and second input circuits each comprise two complementary current mirrors connected in series, and the input node is located at the junction of the two complementary current mirrors.

[0017] In one or more embodiments of the differential current buffer circuit, the first input circuit and the second input circuit of the differential input stage are connected to a shared bias leg to form a differential translinear input cell, the shared bias leg being connected between a first positive power supply voltage and a first negative power supply voltage. The translinear input cell may comprise two pairs of transistors, the control electrodes of each respective pair of transistors being coupled together and connected to upper and lower bias potentials, respectively.

[0018] In one or more embodiments of the differential current buffer circuit, the positive and negative bias currents of the input stage are set by a single current source coupled upstream and downstream of the first current paths of two current mirrors, with the first bias current mirror connected to a first positive power supply and the second bias current mirror connected to a first negative power supply voltage. The second current paths of the bias current mirrors provide the positive and negative bias currents to the input stage. The series connection of the current mirrors and the single current source makes it easy to set identical bias currents in the positive and negative power supplies, allowing the bias currents to be set very accurately when high-precision current mirrors such as Wilson current mirrors are used.

[0019] In one or more embodiments of the differential current buffer circuit, the series-connected complementary current mirrors of the first and second input circuits each include its own bias leg, i.e., each of the first and second input circuits has one bias leg. Each bias leg is connected between a first positive power supply voltage and a first negative power supply voltage. An input node is disposed at a junction of the complementary current mirror in the respective bias leg. An output of the complementary current mirror is connected to a first current path of an associated output current mirror. A junction of the complementary current mirror in the output current path is tied to a reference potential, e.g., ground.

[0020] In one or more embodiments of the differential current buffer circuit, one or more of the first through fourth output current mirrors is a cascode current mirror, a Wilson current mirror, or a modified Wilson current mirror.

[0021] According to a second aspect of the invention, the DC and AC power supplies comprise differential operational amplifiers connected in a Howland current source configuration, the differential outputs of which are connected to the inputs of a differential current buffer circuit according to the first aspect of the invention as hereinbefore described. Respective first feedback signals to the non-inverting and inverting inputs of the amplifiers are tapped off from the load side terminals of respective output resistors of the differential current buffer circuit.

[0022] In one or more embodiments of the DC and AC power supplies, a differential op-amp is connected in a four-feedback enhanced Howland current source configuration, with each additional second feedback signal to the non-inverting and inverting inputs of the amplifier being tapped off at a buffer-side terminal of each opposing output resistor of the differential current buffer circuit. [Brief description of the drawings]

[0023] In the following section, the invention is described with reference to the accompanying drawings. [Figure 1a] FIG. 1 is a schematic circuit diagram of a known Howland current source. [Figure 1b] FIG. 1 is a schematic circuit diagram of a known four feedback enhanced Howland current source; [Diagram 2] FIG. 2 is a schematic circuit diagram of a translinear input cell. [Diagram 3] FIG. 2 is a circuit diagram of a first exemplary differential current buffer circuit according to a first aspect of the present invention. [Figure 4] FIG. 4 is a circuit diagram of a second exemplary differential current buffer circuit according to a first aspect of the present invention. [Diagram 5] 4 shows a circuit diagram of a DC and AC power supply comprising the first exemplary differential current buffer circuit of FIG. 3 connected to an op-amp in a four-feedback enhanced Howland current source circuit configuration. [Figure 6] FIG. 5 shows a circuit diagram of a DC and AC power supply comprising the second exemplary differential current buffer circuit of FIG. 4 connected to an op-amp in a four-feedback enhanced Howland current source circuit configuration. In the drawings, identical or similar elements may be referenced using the same reference numerals. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] 1a and 1b have been explained in the Background section and will not be explained again.

[0025] FIG. 2 shows a schematic circuit diagram of a translinear input cell 20. The base electrodes of two pairs of transistors T1, T2, T3, and T4 are connected together and also connected to a respective bias potential. The bias potential is provided by the bias leg of the translinear input cell. In this example, the bias leg is connected in series with a current I connected upstream and downstream, respectively, of two diodes D1 and D2 connected in series in the forward direction. o The input cell comprises two current sources each providing a current source and a current source connected in series between a positive voltage V and a negative voltage -V. To provide a proper centering of the translinear input cell, the connection between the two diodes D1 and D2 is connected to a reference potential Z, e.g. ground.

[0026] Two pairs of transistors T1, T2 and T3, T4, respectively, are "stacked" on top of each other such that the respective "sides" of the transistor pairs are connected, i.e., the emitter electrodes of transistors T1 and T3 are connected and the emitter electrodes of transistors T2 and T4 are connected. A differential input signal is connected to input nodes X and Y formed between the respective emitter electrode connections. Output currents I1-I4 flow through the collector electrodes of transistors T1, T3 and T2, T4, respectively, in response to input signals applied to input nodes X, Y and further circuitry connected thereto.

[0027] 3 shows a circuit diagram of a first exemplary differential current buffer circuit 100 according to a first embodiment of the present invention. Figure 3a) shows the bias power supply circuit 200 and Figure 3b) shows the input stage 300 and the output stage of the differential current buffer circuit.

[0028] The bias power supply circuit 200 shown in FIG. 3a) comprises a first bias current mirror whose first current path 210 is connected to a first positive supply voltage +V1 and a first terminal of a current source 220. The bias power supply circuit 200 further comprises a second bias current mirror whose first current path 214 is connected between a second terminal of the current source 220 and a first negative supply voltage −V1. It should be noted that throughout this specification the first and second positive and negative supply voltages are referred to as reference potentials, e.g. ground, and are preferably symmetrical. The second current paths 212 and 216 of the first and second bias current mirrors respectively form bias current outputs that power the differential input stage 300. The bias power supply circuit 200 advantageously requires only one current source to set the bias current, the bias current mirror simply copies the set current to the positive and negative supply rails.

[0029] The differential current buffer shown in FIG. 3b) has a differential input stage 300 similar to the translinear input cell 20 described with reference to FIG. 2. Unlike the translinear input cell of FIG. 2, the emitters of transistors Q1, Q5, and Q3, Q4, respectively, are not directly connected, but are connected via two resistors R25, R30, and R27, R28, respectively, connected in series. Input nodes I1 and I2 are formed between the two respective resistors. Power to the differential input stage is provided by a first positive supply voltage +V1 and a first negative supply voltage −V1. In this differential input circuit, power is provided to the bias circuit from a bias power supply circuit 200. The diodes D1 and D2 in the bias leg of the circuit of FIG. 2 are replaced by diode-connected transistors Q2 and Q6, which are preferably of the same type as transistors Q1, Q3, and Q4, Q5, respectively, and even more preferably from the same manufacturing lot. Furthermore, these diodes are not connected directly to each other, but through two resistors R26, R29 connected in series, which act to supply the bias current I OThe corresponding setting of the emitter degeneration provides for stabilizing the operating point of the input stage in the light of transistor variations. The connection between the two resistors R26, R29 is connected to ground for the reference potential. Transistors Q3 and Q4 form the first input circuit together with emitter degeneration resistors R27 and R28, and transistors Q1 and Q5 form the second input circuit together with emitter degeneration resistors R25 and R30.

[0030] The output of the first input circuit is connected between a first current path 318 of a first output current mirror circuit, which is connected to a second positive power supply voltage +V2, and a first current path 322 of a second output current mirror circuit, which is connected to a second negative power supply voltage -V2.

[0031] The output of the second input circuit is connected between a first current path 310 of a third output current mirror circuit, which is connected to a second positive power supply voltage +V2, and a first current path 314 of a fourth output current mirror circuit, which is connected to a second negative power supply voltage -V2.

[0032] A first output O1 of the differential buffer circuit 100 is tapped off between the second current paths 320, 324 of the first and second output current mirrors, which are tied together and powered by a second positive power supply voltage +V2 and a second negative power supply voltage −V1, respectively.

[0033] A second output O2 of the differential buffer circuit 100 is tied together and tapped off between second current paths 312, 316 of respective third and fourth output current mirrors which are powered by a second positive power supply voltage +V2 and a second negative power supply voltage -V1, respectively.

[0034] The first and second input circuits each form a series-connected complementary current mirror having a shared bias leg, with a respective output current controlled by a current applied to a respective input node I1 or I2. The input current modifies a respective current through each of the complementary current mirrors connected to the first current path of an associated output current mirror. The current through the first current path of the output current mirror is matched in the respective second path of the output current mirror and is available at the corresponding output O1 and O2, respectively.

[0035] 4 is a circuit diagram of a second exemplary differential current buffer circuit according to the first embodiment of the present invention. The output stage of the differential current buffer circuit corresponds to that described with reference to FIG. 3b). The input stage 300 is of a different design, where the individual bias legs of each input circuit of the input stage 300 are directly powered from the first positive and negative supply voltages +V1, −V1, respectively.

[0036] A first input circuit comprising transistors Q2, Q3, Q4, and Q6 and resistors R26, R27, R28, R29, R30, and R31 has its input node in the bias leg, more specifically in the center point of the series connection of resistors R26 and R29 connecting diode-connected transistors Q2 and Q6. The "anode" of diode-connected transistor Q2 is connected to a first positive supply voltage +V1 through resistor R31, and the "cathode" of diode-connected transistor Q6 is connected to a first negative supply voltage -V1 through resistor R30. Resistors R26, R29, R30, and R31 set the bias current in the bias leg of the first input circuit. The ratios of R31 / R26 and R30 / R29 set the gain of the current buffer, and for correct operation R30=R31 and R26=R27=R28=R29.

[0037] The output of the first input circuit is connected between a first current path 318 of a first output current mirror circuit connected to a second positive power supply voltage +V2 and a first current path 322 of a second output current mirror circuit connected to a second negative power supply voltage -V2. The output of the first input circuit is formed by the collector electrodes of transistors Q3 and Q4, respectively, whose emitter electrodes are connected to a reference potential, here ground, via resistors R27 and R28, respectively.

[0038] The second input circuit, comprising transistors Q1, Q5, Q17, and Q20 and resistors R9, R10, R11, R14, R19, and R25, similarly has its input node in the bias leg, more specifically in the center point of the series connection of resistors R10 and R19 connecting diode-connected transistors Q1 and Q20. The "anode" of diode-connected transistor Q1 is connected to the first positive supply voltage +V1 through resistor R9, and the "cathode" of diode-connected transistor Q20 is connected to the first negative supply voltage -V1 through resistor R25. Resistors R9, R10, R19, and R25 set the bias current in the bias leg of the second input circuit. The ratios of R25 / R19 and R9 / R10 set the gain of the current buffer, and for correct operation R9=R25 and R10=R11=R14=R19.

[0039] The output of the second input circuit is connected between a first current path 310 of a third output current mirror circuit connected to a second positive power supply voltage +V2 and a first current path 314 of a fourth output current mirror circuit connected to a second negative power supply voltage -V2. The output of the second input circuit is formed by the collector electrodes of transistors Q5 and Q17, respectively, whose emitter electrodes are connected to a reference potential, here ground, via resistors R11 and R148, respectively.

[0040] The first and second input circuits each form a series-connected complementary current mirror, with the respective output currents controlled by a voltage applied to a respective input node I1 or I2. The input voltage modifies a respective current through each of the complementary current mirrors connected to the first current path of an associated output current mirror. The current through the first current path of the output current mirror is copied in the second path of each of the output current mirrors and is available at the corresponding outputs O1 and O2, respectively.

[0041] 3, the first output O1 of the differential buffer circuit 100 is tapped off between the second current paths 320, 324 of the first and second output current mirrors that are tied together and powered by a second positive power supply voltage +V2 and a second negative power supply voltage −V1, respectively. The second output O2 of the differential buffer circuit 100 is tapped off between the second current paths 312, 316 of the third and fourth output current mirrors that are tied together and powered by a second positive power supply voltage +V2 and a second negative power supply voltage −V1, respectively.

[0042] 5 shows a circuit diagram of a DC and AC power supply 400 comprising the first exemplary differential current buffer circuit 100 of FIG. 3 connected to a fully differential op-amp 10 in a four-feedback enhanced Howland current source topology. The differential current buffer circuit 100 comprises a bias power supply circuit 200 as shown in FIG. 3a) and an actual buffer circuit as shown in FIG. 3b).

[0043] A first output O1 of the differential current buffer circuit 100 is connected to a load represented by R3 through an output resistor R6 functioning as a current sense resistor. A second output O2 of the differential current buffer circuit 100 is connected to a load through an output resistor R7 functioning as a current sense resistor.

[0044] The first negative feedback signal NF1 is tapped between the load R3 and the load terminal of the output resistor R6. The first negative feedback signal NF1 is provided to the inverting input of the operational amplifier 10 via a resistor R19. The first positive feedback signal PF1 is tapped between the load R3 and the load terminal of the output resistor R7. The first positive feedback signal PF1 is provided to the non-inverting input of the operational amplifier 10 via a resistor R14.

[0045] A second negative feedback signal NF2 is tapped between the second output O2 of the differential current buffer circuit 100 and the buffer side terminal of the output resistor R7. The second negative feedback signal NF2 is provided to the inverting input of the operational amplifier 10 via a voltage divider to ground comprising resistors R15 and R16. A second positive feedback signal PF2 is tapped between the first output O1 of the differential current buffer circuit 100 and the buffer side terminal of the output resistor R6. The second positive feedback signal PF2 is provided to the non-inverting input of the operational amplifier 10 via a voltage divider to a signal source SIG comprising resistors R17 and R18. The signal source SIG is referenced to ground, is a voltage source, and represents the ground connection of the second positive feedback signal PF2.

[0046] The op-amp 10 may be powered from positive and negative power supply voltages Vcc and Vee, respectively, which may be independent of the first power supply voltages +V1 and -V1. The common mode offset at the output may be trimmed using a corresponding trim voltage VCOM at a corresponding input of the op-amp 10.

[0047] Resistors R10 and R11 may be required for stability between the output of the operational amplifier 10 and the first and second inputs I1 and I2, respectively, of the differential current buffer circuit 100. However, they may require a higher output swing from the operational amplifier 10 to generate the necessary input currents at the inputs I1 and I2 of the differential current buffer circuit 100. These resistors may need to be appropriately selected for optimal step response and minimal ringing or overshoot, i.e., resistors with low parasitic inductance may be preferred.

[0048] Resistors R4 and R5, connected to ground, provide a path to ground across load R3 and are effectively part of a voltage divider that allows the output voltage to be monitored. However, resistors R4 and R5 also limit the maximum output impedance of current source 400 to the sum of the values ​​of resistors R4 and R5. The frequency response of the current source is limited by the input capacitance of op amp 10, which is typically only a few pF.

[0049] By closing the four feedback loops around the entire circuit, as shown in the figure, the lowest possible distortion of the output signal applied to the load is ensured.

[0050] FIG. 6 shows a circuit diagram of a DC and AC power supply 400 comprising the second exemplary differential current buffer circuit 100 of FIG. 4 connected to an op-amp in a four-feedback enhanced Howland current source circuit configuration.

[0051] As with the DC and AC current sources in Figure 5, feedback is applied throughout the circuit. R6 and R7 are current sensing resistors, and the feedback goes back to the input of the driving stage of the fully differential op-amp 10. Again, applying feedback throughout the circuit ensures the lowest possible distortion.

[0052] Unlike the circuit of Figure 5, in this circuit there is no resistance at the output of the op amp because the differential buffer requires a voltage drive. Any output common-mode offset voltage can be trimmed using the VCOM input to op amp 10.

[0053] As in the circuit of Figure 5, resistors R4 and R5 connected to ground provide a path to ground across load R3, effectively becoming part of a voltage divider that allows the output voltage to be monitored. Similarly, resistors R4 and R5 also limit the maximum output impedance of DC and AC power supply 400 to the sum of the values ​​of resistors R4 and R5. The frequency response of the current source is limited by the input capacitance of op amp 10, which is typically only a few pF. The output DC offset is controlled using the VCOM input to the fully differential op amp 10.

[0054] For highest accuracy, the differential current buffer circuit 100 preferably operates in Class A mode, which can be achieved by appropriately adjusting the respective bias currents.

[0055] In this circuit, the first positive and negative power supply voltages +V1, -V1 of the differential current buffer circuit 100 are the same power supply voltages Vcc and Vee, respectively, that power the operational amplifier 10.

[0056] The output current mirror may be implemented as a cascode current mirror, as shown in Figures 3 and 4. In a simple current mirror, the output current depends on the output voltage because the output resistance of the transistors is finite. A cascode current mirror can greatly reduce this dependence. [Explanation of symbols]

[0057] 10 Operational Amplifiers 20 Translinear Input Cell 100 Differential Current Buffer 200 Bias power supply 210 First current path of the first bias current mirror 212 Second current path of the first bias current mirror 214 First current path of the second bias current mirror 216 Second current path of the second bias current mirror 300 Differential Input Stage 318 First current path of the first output current mirror 320 Second current path of the first output current mirror 322 First current path of the second output current mirror 324 Second current path of the second output current mirror 310 the first current path of the third output current mirror 312 Second current path of the third output current mirror 314 First current path of the fourth output current mirror 316 Second current path of the fourth output current mirror 400 AC power supply D1, D2 Diode I1-I4 Output current I O Bias Current I1 First input I2 Second input NF1 First negative feedback signal NF2 Second Negative Feedback Signal O1 First output O2 Second Output PF1 First positive feedback signal PF2 Second positive feedback signal Q1-Q36 Transistors R1-R30 Resistor SIG signal source T1-T4 transistors +V1 First positive power supply voltage +V2 Second positive power supply voltage -V1 First negative power supply voltage -V2 Second negative supply voltage Vcc Op-amp positive supply voltage VCOM Common Mode Trim Vee Op Amp Negative Supply Voltage V X Output Node X,Y Input Node Z reference potential Z L load

Claims

1. A differential current buffer circuit (100) comprising a differential input stage (300) powered by a first positive power supply voltage (+V1) and a first negative power supply voltage (-V1), wherein the differential input stage (300) comprises a first input circuit whose output is connected between a first current path (318) of a first output current mirror connected to a second positive power supply voltage (+V2) and a first current path (322) of a second mirror connected to a second negative power supply voltage (-V2), and between a first current path (310) of a third output current mirror connected to the second positive power supply voltage (+V2) and a first current path (314) of a fourth output current mirror connected to the second negative power supply voltage (-V2). A differential current buffer circuit (100) having a second input circuit with an output connected to it, wherein, with reference to a reference potential, the second positive power supply voltage (+V2) is higher than the first positive power supply voltage (+V1), and the second negative power supply voltage (-V2) is lower than the first negative power supply voltage (-V1), the first output (O1) of the differential current buffer circuit (100) is tapped off between the second current paths (320, 324) of the first and second output current mirrors, and the second output (O2) of the differential current buffer circuit (100) is tapped off between the second current paths (312, 316) of the third and fourth output current mirrors.

2. The differential current buffer circuit (100) according to claim 1, wherein the first and second input circuits each include two complementary current mirrors connected in series, and the input nodes (I1, I2) are located at the connection point of the two complementary current mirrors.

3. The differential current buffer circuit (100) according to claim 2, wherein the first input circuit and the second input circuit of the differential input stage (300) are connected to a shared bias leg to form a differential translinear input cell, and the bias leg is powered by the first positive power supply voltage (+V1) and the first negative power supply voltage (-V1).

4. The differential current buffer circuit (100) according to claim 3, wherein the differential bias power supply is connected to the first positive power supply voltage (+V1) via a first bias current source and to the first negative power supply voltage (-V1) via a second bias current source.

5. The first bias current source corresponds to the second current path (212) of the first bias current mirror, and the second bias current source corresponds to the second current path (216) of the second bias current mirror, and the input stage bias (I ０ The differential current buffer circuit (100) according to claim 4, wherein the current is set by current sources (220) coupled upstream and downstream of the first current paths (210, 214) of the first and second bias current mirrors, respectively.

6. The differential current buffer circuit (100) according to claim 2, wherein the series-connected complementary current mirrors of the first input circuit and the second input circuit each have their own bias legs, each bias leg connected between the first positive power supply voltage (+V1) and the first negative power supply voltage (-V1), the input nodes (I1, I2) are located at the connections of the complementary current mirrors in the respective bias legs, the output of the complementary current mirror is connected to the first current path (310, 314, 318, 322) of the associated output current mirror, and the connections of the complementary current mirror in the output current path are linked to a reference potential.

7. A differential current buffer circuit (100) according to any one of claims 1 to 6, wherein one or more of the bias current mirror and / or the output current mirrors are a cascode current mirror, a Wilson current mirror, or an improved Wilson current mirror using a bipolar or field-effect transistor.

8. A DC and AC power supply (400) comprising a differential operational amplifier (10) connected in a differential Howland current source configuration, wherein the differential output is connected to corresponding input nodes (I1, I2) of a differential current buffer circuit (100) according to any one of claims 1 to 6, and first feedback signals (NF1, PF1) to the non-inverting and inverting inputs of the amplifier are tapped off from the load-side terminals of the respective output resistors (R6, R7) connected between the outputs (O1, O2) of the differential current buffer circuit (100) and the load (R3), the load-side terminals representing the actual output of the AC power supply (400).

9. The DC and AC power supply (400) according to claim 8, wherein the differential operational amplifier (10) is connected in a four-feedback enhanced Howland current source configuration, and additional second feedback signals (NF2, PF2) to the non-inverting and inverting inputs of the operational amplifier (10) are tapped off at the buffer-side terminals of the respective opposing output resistors (R6, R7).

Images