Information transposition using shadow and active latches for efficient die area in processing systems - Patents.com

Abstract

A system and method for transposing information using shadow and active latches for efficient die area in a processing system. An exemplary storage device includes a group of active and shadow latches, where the active / shadow storage device receives a first matrix including values, and the active latches are enabled for a first clock cycle such that the values ​​are stored in the active latches. The shadow latches replicate the values ​​stored in the active latches. The replicated values ​​in the shadow latches are read for a second clock cycle, and at least one value included in the second matrix is ​​stored in at least one active latch for the second clock cycle.

Description

[Technical field]

[0001] [CROSS REFERENCE TO RELATED APPLICATIONS] This application claims priority to U.S. Provisional Application No. 63 / 362,876, entitled "TRANSPOSING INFORMATION USING SHADOW LATCHES AND ACTIVE LATCHES FOR EFFICIENT DIE AREA IN PROCESSING SYSTEM," filed April 12, 2022, the disclosure of which is incorporated by reference in its entirety herein.

[0002] The present disclosure relates to transposing information using hardware elements, and more particularly, to transposing information using latches. [Background technology]

[0003] Neural networks rely on entirely different applications and increasingly form the basis of technology. For example, neural networks can be utilized to perform object classification on images acquired via a user device (e.g., a smartphone). In this example, the neural network can represent a convolutional neural network that applies convolutional layers, pooling layers, and one or more fully connected layers to classify objects depicted in the images. As another example, neural networks can be utilized for translation of text between languages. In this example, the neural network can represent a recurrent neural network.

[0004] Typically, information may need to be transposed as part of training a neural network or during inference. For example, a first matrix may be used to store information such as input data, weight data, etc. In this example, the first matrix may be multiplied by a second matrix or vector (e.g., a column vector). As can be appreciated, multiplying a first matrix by a second matrix or multiplying a first matrix by a column vector requires that the number of columns of the first matrix be equal to the number of rows of the second matrix or column vector. Thus, for certain multiplications, it may be necessary to transpose the first matrix to switch the row and column indexes of the matrix.

[0005] Currently, hardware techniques for transposing matrices, for example in a streaming context, require large arrays of hardware elements that consume significant die area. [Brief description of the drawings]

[0006] [Figure 1A] FIG. 2 is a block diagram illustrating a matrix processor system including an exemplary active / shadow storage device for transposing data and an exemplary matrix processor for processing the data.

[0007] [Figure 1B] FIG. 2 is a block diagram showing details of an exemplary active / shadow storage device included in a matrix processor system.

[0008] [Figure 1C] FIG. 2 is a block diagram showing details of data input to the active / shadow storage devices.

[0009] [Figure 1D] FIG. 2 is a block diagram showing details of reading transposed data from the active / shadow storage devices.

[0010] [Figure 2A]FIG. 2 is a block diagram illustrating an example of writing data to an active latch included in an exemplary active / shadow storage device.

[0011] [Figure 2B] 2 is a block diagram illustrating an example of storing data in a shadow latch included in an exemplary active / shadow storage device.

[0012] [Figure 2C] FIG. 2 is a block diagram illustrating an example of writing new data to an active latch and reading data from a shadow latch.

[0013] [Diagram 3] 1 is a flowchart of an exemplary process for transposing data using active / shadow storage devices.

[0014] [Figure 4] 1 is a block diagram illustrating an example vehicle including a queue processor system.

[0015] The embodiments of the present disclosure and their advantages are best understood by referring to the following detailed description: Like reference numerals have been used to identify like elements shown in one or more of the drawings, and it should be understood that the indications therein are for the purpose of illustrating embodiments of the present disclosure and are not intended to limit the disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] This application describes techniques that enable transposing data in a streaming context while efficiently utilizing die area. As described below, information may be streamed during operation of the processor, and the information is transposed quickly when needed. The processor may be, for example, a matrix processor used to perform neural network processing. It will be appreciated that matrices such as portions of an input image, feature maps, filters or kernels may need to be transposed so that the matrix can be multiplied by another matrix or vector. Thus, transposing information may be a necessary step during processing of a layer such as a convolutional layer in a neural network. As will be explained, the techniques described herein utilize an array or combination of active and shadow latches (referred to herein as active / shadow storage) to efficiently transpose information while limiting the amount of die area required to be spent on the transposition.

[0017] To transpose data such as a matrix using hardware elements, an exemplary technique may use an array or combination of flip-flops (e.g., a 2D set of flip-flops). Each flip-flop may be used to store a bit contained in the matrix. Thus, if the matrix is ​​a 4x3 matrix containing 12 values, 12 flip-flops may be used to store the values. As can be appreciated, 12 values ​​may require multiple bits and therefore more than 12 flip-flops may be used to store the values. To transpose a 4x3 matrix, the outputs of the flip-flops may be ordered such that the values ​​rotate around the diagonal of the matrix. In this manner, a 4x3 matrix may be output (e.g., read out) as a 3x4 matrix.

[0018] Using a single flip-flop for each bit contained in a matrix allows data to be transposed, but this is not possible in a streaming context. For example, assuming that a matrix cannot be read and written in a certain number of clock cycles (e.g., a single clock cycle, a clock cycle per row of the matrix, etc.), full pipelining cannot be used. As known to those skilled in the art, the inability to function in a streaming context prevents the use of this technique, since new inputs cannot be written until all outputs have been read. Thus, throughput and overall processing speed are limited.

[0019] Another exemplary technique for transposing data may include using two flip-flops for each bit. This may allow for transposing data in a streaming context, such as allowing new information to be written while old information is being read. As an example, the two flip-flops for each bit may include a first flip-flop and a second flip-flop. The second flip-flop may receive a copy of information from the first flip-flop after the information is written to the flip-flop. And, information may be read from the second flip-flop while new information is being written to the first flip-flop. However, this exemplary technique may substantially increase the required die area allocated to the transposing data. The increased complexity and cost, potentially coupled with reducing space for other hardware elements in the processor, may make the use of two flip-flops for each bit undesirable.

[0020] The techniques described herein advantageously allow two latches to be used for each bit of the matrix to be transposed. A latch, such as an SR latch, may require substantially less die area than a flip-flop that may be formed from two latches, as an example. Furthermore, the regular structure may lend itself to scripted physical placement, such that manufacturing of the active / shadow storage may be enhanced.

[0021] As described below, the two latches may include an active latch and a shadow latch. For example, a value contained in a matrix may be written to the active latch over one or more clock cycles. In this example, the value may be stored in the shadow latch. A new value contained in a new matrix may then be written to the active latch, while the value is read from the shadow latch. In this manner, the techniques described herein allow streaming of information that is transposed during operation of the processor.

[0022] Different clock gates can be used to control the operation of the active and shadow latches. For example, the active latch may be controlled via a first clock gate signal, while the shadow latch may be controlled via a second clock gate signal. Thus, in this example, the active and shadow latches may be enabled at specific times to ensure proper operation of the active / shadow storage device.

[0023] In some embodiments, the active latch may be transparent at the high phase of the clock when the input data is ready. The shadow latch may be transparent at the low phase of the clock when data is ready to be moved from the active latch to the shadow latch. Thus, in some embodiments, the same clock may be used (e.g., at least as described in FIG. 1B).

[0024] In some embodiments, the innovations may be used for algorithms other than pure transposition. For example, the circuitry may read out the diagonal elements of the array one by one. Without the techniques described herein, this could not simply be done without postponing the line writes until the diagonal reads have been performed. Block Diagram

[0025] 1A is a block diagram illustrating a matrix processor system 100 including an exemplary active / shadow storage device 110 for transposing data and an exemplary matrix processor 120 for processing data. The matrix processor system 100 may be used, for example, to compute a forward pass through layers of a neural network. In some embodiments, the neural network may represent a convolutional neural network in which image or video information is processed.

[0026] In the illustrated example, input data 102A is provided to the matrix processor system 100. The input data 102A may represent an input image, one or more feature maps, or a portion thereof, as described above. For example, the portion may represent a particular window of input data that is multiplied by weight data (e.g., one or more kernels or filters). The input data 102A may also represent information input to a layer of a neural network, such as a convolution, transformer, or fully connected network, that is multiplied with weight information (e.g., a weight matrix).

[0027] As known to those skilled in the art, the input data 102A may need to be transposed in order to multiply the input data 102A with other input data 102B. For example, the input data 102A may represent a 20×10 matrix containing 120 values. For example, the input data 102B may represent a 20×4 matrix containing 80 values. Therefore, in order to multiply these matrices, the input data 102A is transposed to a 10×20 matrix.

[0028] The matrix processor system 100 includes an active / shadow storage device 110 for transposing the input data 102A into transposed data 112. As mentioned above and will be described in more detail, the active / shadow storage device 110 includes a number of active latches and shadow latches. Each active latch may be connected to an individual shadow latch in the storage device 110. In some embodiments, the active / shadow storage device 110 may include an array of active latches and shadow latches. For example, there may be an array of groups of active latches and shadow latches organized into rows and columns. In this example, the groups of active latches and shadow latches may be 32×32, 20×20, 36×48, etc.

[0029] The input data 102A may be written to the active latches over one or more clock cycles. For example, in each clock cycle, a certain amount of data (e.g., obtained from an external memory) may be written to the active / shadow storage device 110. In some embodiments, the amount of data may be 8 bits, 10 bits, 16 bits, 32 bits, etc. In some embodiments, the number of clock cycles may correspond to the number of rows included in the input data 102A, as described below with respect to FIG. 1B.

[0030] In this manner, matrix processor 120 may determine processing results 122 associated with multiplying input data 102A and input data 102B. Processing results 122 may represent, for example, outputs associated with multiplication of input data and weights in a layer of a neural network. Processing results 122 may represent, for example, outputs associated with a portion of the processing performed in a layer of a neural network. In some embodiments, processing results 122 may represent one or more windows of input information (e.g., an input image, feature maps, etc.) convolved with one or more filters or kernels.

[0031] While FIG. 1A shows input data 102A being transposed, for example, via active / shadow storage device 110, in some embodiments input data B 102B may also be transposed.

[0032] An exemplary matrix processor 120 is described in more detail in U.S. Pat. Nos. 11,157,287, 11,409,692 and 11,157,441, which are incorporated by reference in their entireties and form part of the present disclosure as if set forth herein.

[0033] 1B is a block diagram illustrating details of an exemplary active / shadow store 110 included in matrix processor system 120. Active / shadow store 110 includes a number of latches that can be characterized as either active latches (e.g., "A" latches) or shadow latches (e.g., "B" latches). In some embodiments, individual active latches can be associated with individual shadow latches to form groups of latches, such as active latch 160 and shadow latch 162. Each group of latches may be used for an individual bit of input data (e.g., a matrix of values) such that each bit of input data is associated with two latches included in active / shadow store 110.

[0034] An active latch, such as active latch 160, can receive a respective bit of input data. For example, the input data can include a matrix of values ​​to be transposed. In this example, each value of the matrix (e.g., a particular row and column element of the matrix) can be represented by one or more bits. Thus, each active latch can receive one of the bits for storage.

[0035] In some embodiments, active latch 160 may represent a group of active latches. For example, each active latch in a group of active latches may be used to store one bit associated with a larger value (e.g., a byte, a word, an integer, a floating point, etc.). Similarly, shadow latch 162 may represent a group of shadow latches that receive information from a group of active latches. In this manner, active / shadow storage device 110 may be used to transpose matrices of values ​​that are bytes, words, integers, etc.

[0036] As can be appreciated, the values ​​included in the matrix of values ​​may be provided to the active / shadow storage device 110 over one or more cycles. For example, the values ​​may be obtained from an element (e.g., a memory not shown in FIG. 1B) and provided to the active / shadow storage device 110 over a bus. The bus may have a width or bandwidth that allows the values ​​to be provided over more than one clock cycle. In some embodiments, the number of clock cycles may be based on the size of the matrix. For example, the number of clock cycles may correspond to the number of rows included in the matrix. In this example, active latches included in or otherwise assigned or associated with the same column of the active / shadow storage device 110 may receive their respective bits in the same clock cycle (e.g., because the data is transposed, active latches in the same column may be associated with rows included in the matrix). As another example, the number of clock cycles may correspond to the number of columns included in the matrix. In this example, active latches included in or otherwise assigned or associated with the same row of the active / shadow storage device 110 may receive their respective bits in the same clock cycle.

[0037] When bits included in the matrix of values ​​are stored in an active latch, a shadow latch can store a copy of the bits. For example, shadow latch 162 can receive the bits stored in active latch 160. As described in Figures 2A-2C, the shadow latch can duplicate the information in the active latch on a particular clock edge (e.g., rising clock edge, falling clock edge). For example, shadow latch 162 can be enabled substantially simultaneously to store the bits included in the matrix of values.

[0038] The information stored in the shadow latches may then be read over one or more clock cycles. For example, each row of shadow latches included in active / shadow storage device 110 may be addressed and the bits stored therein may be read from the shadow latches. As another example, each column of shadow latches included in active / shadow storage device 110 may be addressed and the bits stored therein may be read from the shadow latches. As shown, the matrix of values ​​may be read such that the matrix is ​​transposed. For example, the values ​​may be flipped across the diagonal of the matrix.

[0039] The number of clock cycles to read information may optionally be based on the number of columns in the matrix of values. For example, if the matrix of values ​​is an MxN matrix and each value is a bit, there may be M clock cycles to write N bits of information to the active latch. In this example, there may be N clock cycles to read M bits of information from the shadow latch.

[0040] As can be appreciated, new information (e.g., a new matrix of values) can be stored in the active latches for one or more clock cycles while the information stored in the shadow latches is read. During operation of the active / shadow storage device 110, e.g., during steady state operation, the active latches can be written while the shadow latches are read. Advantageously, the active and shadow latches can store different data such that during steady state operation the matrix can be streamed to the storage device 110 and then transposed into the streaming context.

[0041] In some embodiments, the active / shadow storage device 110 can write information to the active latches in each clock cycle and read information from the shadow latches in the same clock cycle. For example, a square matrix can have as many writes performed as there are reads. For the above example of an MxN matrix, if M is the same as N, there can be M clock cycles to write M bits of information to the active latches and M clock cycles to read M bits of information from the shadow latches. However, in some embodiments, a non-square matrix can have a different number of writes performed than the number of reads. For an MxN matrix where M is 10 and N is 16, there can be 10 cycles of 16-bit writes to the active latches and 16 cycles of 10-bit reads from the shadow latches. Thus, the pipelining (e.g., streaming) of the matrix can be adjusted depending on the dimensions of the matrix. For example, the storage device 110 may limit the extent to which new information is written to the active latches (e.g., the storage device 110 can write 10 every 16 clock cycles for the above example).

[0042] To allow for the use of latches and therefore reduce die area compared to the use of alternative techniques for transposing matrices (e.g., flip-flops), the clock 150 may be gated separately for the active and shadow latches. For example, clock gate 152A may be switched on or off to enable or disable the active latches. As another example, clock gate 152B may be switched on or off to enable or disable the shadow latches. In the illustrated embodiment, the same clock is used such that the active and shadow latches use opposite edges (e.g., high phase, low phase) of the clock.

[0043] In this manner, the active and shadow latches can be controlled separately. In some embodiments, the clock gates 152A and 152B may be switched according to instructions being executed by the matrix processor system 100. In some embodiments, the active and shadow latches may be set to be active on opposite edges of the clock 150. For example, the active latches may be enabled based on a rising edge of the clock 150, while the shadow latches may be enabled based on a falling edge of the clock 150 (e.g., or vice versa). Figures 2A-2C describe additional details associated with switching the active and shadow latches on or off.

[0044] 1C is a block diagram illustrating details of data input to active / shadow storage device 110. Exemplary input data 170 is included in FIG. 1C, where input data 170 represents a 3×3 matrix. As can be appreciated, the dimensions of the matrices and latches included in storage device 110 may be arbitrary, and the techniques described herein may be applied to different data structures. Input data 170 includes values ​​R-Z, where each value represents a bit, byte, word, etc., as discussed above.

[0045] An exemplary implementation is shown for inputting input data 170 into memory device 110. In this example, a first row of values ​​is input into the top row of active latches. A second row of values ​​is input into the middle row of active latches. A third row of values ​​is input into the bottom row of active latches.

[0046] 1D is a block diagram illustrating details of reading transposed data 172 from active / shadow storage device 110. As shown, information may be read from storage device 110 such that input data 170 is transposed into transposed data 172. As described above, information may be input to storage device 110 over one or more cycles. For example, a first row of values ​​as described above may be input during one clock step and a second row may be input during the next clock step. Values ​​input to storage device 110 and thus stored in the active latches described herein may be stored by shadow latches.

[0047] In the illustrated example, the top row of permuted data 172 is read from the left-most shadow latch. The middle row of permuted data 172 is read from the middle shadow latch. The bottom of permuted data 172 is read from the right-most shadow latch. As can be appreciated, as described herein, new data (e.g., new input data to be transposed) can be stored in the active latches while data is being read from the shadow latches. In this manner, data can be transposed in a streaming manner.

[0048] 2A is a block diagram illustrating an example of writing data to an active latch 210 included in an exemplary active / shadow storage device 110. The active latch 210 (e.g., "A" latch) may represent an individual active latch included in the storage device 110, such as active latch 160. In the illustrated example, a value A 202 is written to the active latch 210. As described herein, the value A 202 may be a bit included in a matrix of values. For example, the matrix may be an MxN matrix of bits (e.g., M*N bits). In this example, there may be at least MxN active latches and MxN shadow latches (e.g., 2*M*N latches). As another example, the matrix may be separated into two or more matrices depending on the number of latches included in the active / shadow storage device 110.

[0049] To store value A 202 in active latch 210, clock gate 152A may be enabled. As shown, clock gate 152A is set to enable such that active latch 210 can store value A 202. One or more clock cycles may be required to write the matrix of values ​​to active latch 110. In FIG. 2A, multiple clock cycles of clock 150 are shown in which rising edges 210A-210N enable the active latches. For example, clock gate 152A may be set to enable (e.g., logic "1") and the active latch is enabled (e.g., logic "1") based on the clock being positive.

[0050] 2A, the shadow latch is disabled (e.g., logic "0") based on clock gate 152B being set to disabled. As described below, shadow latch 220 can be enabled to replicate value A 202.

[0051] 2B is a block diagram illustrating an example of storing data in a shadow latch 220 included in an exemplary active / shadow storage device 110. When an active latch is written to the active / shadow storage device 110, such as active latch 210, a shadow latch may be enabled to store a copy of the information stored in the active latch.

[0052] In the illustrated example, clock gate 152B is set to be enabled (e.g., logic "1") such that shadow latches 220 are enabled on falling edge 212 of clock 150. In addition to shadow latches 220, in some embodiments, all shadow latches 220 may be enabled to replicate values ​​in their corresponding active latches. Clock gate 152A is optionally set to be disabled such that new information (e.g., a new matrix of values) is not written to the active latches.

[0053] 2C is a block diagram illustrating an example of writing new data to the active latch 210 and reading data from the shadow latch 220. As illustrated in FIG 2B, the shadow latch 220 stores a value A 202 at the falling edge 212 of the clock 150. To ensure that the active / shadow storage device 110 operates in a streaming context, new information can be written to the active latch 210 while old information is read from the shadow latch 220 such that information can be written / read during the same clock cycle during steady-state operation.

[0054] In the illustrated example, clock gate 152A is set to enable while clock gate 152B is set to disable. This allows new information (e.g., value B 204) to be written to active latch 210. For example, at rising edge 214A of clock 150, value B 204 may be stored in active latch 210. When clock gate 152B is set to disable, at the subsequent falling edge of clock 150, shadow latch 220 may hold value A 202. Advantageously, value A 202 may be read during a clock cycle such that new information (e.g., value B 204) is written while old information (e.g., value A 202) is read.

[0055] For steady state operation, as can be appreciated, new information values ​​may be written to the active latches over one or more clock cycles, while old information may be read from the shadow latches during these clock cycles. Exemplary Flowchart

[0056] 3 is a flow chart of an exemplary process 300 for transposing data using active / shadow storage. For convenience, the process 300 is described as being performed by the matrix processor system 100.

[0057] In block 302, the system causes input data to be stored in active latches of an active / shadow storage device. During operation of the system, input data to be transposed may be obtained (e.g., based on an instruction, such as a software instruction). This information may be provided to an active / shadow storage device that includes multiple groups of active latches and shadow latches. Each group of active latches and shadow latches may be associated with a bit of input data. As described in FIG. 2A, the input data may be stored in the active latches for one or more clock cycles. For example, the active latches may be enabled via a first clock gate signal that is set to be enabled.

[0058] In block 304, the system copies the active latch data to a shadow latch. The second clock gate signal may be enabled, and optionally the first clock gate signal is set to be disabled, thereby enabling the shadow latch. When enabled, the shadow latch can store (e.g., duplicate or copy) the information stored in the active latch.

[0059] In block 306, the system reads data from the shadow latches while the new data is being written to at least some of the active latches. As described in FIG. 2C, the information stored in the shadow latches may be read over one or more clock cycles. The information may be read such that the values ​​obtained in block 302 may be transposed (e.g., diagonally flipped). While the information is being read, at least some of the active latches may be enabled for one or more clock cycles such that the new information is stored in the active latches. Vehicle block diagram

[0060] 4 illustrates a block diagram of a vehicle 400 (e.g., vehicle 102). The vehicle 400 may include one or more electric motors 402 that cause the vehicle 400 to move. The electric motors 402 may include, for example, induction motors, permanent magnet motors, etc. As known to those skilled in the art, batteries 404 (e.g., one or more battery packs each including multiple batteries) may be used to power the electric motors 402.

[0061] The vehicle 400 further includes a propulsion system 406 that can be used to set the gear (e.g., propulsion direction) of the vehicle. For an electric vehicle, the propulsion system 406 can regulate the operation of the electric motor 402 to change the propulsion direction.

[0062] Additionally, the vehicle includes a matrix processor system 100 configured to transpose information as described herein. The matrix processor system 100 can process data such as images received from image sensors (e.g., cameras 104A-104N) positioned around the vehicle 400. The matrix processor system 100 can additionally output information to a display 408 included in the vehicle 400 and receive information (e.g., user input) therefrom. Other embodiments

[0063] All of the processes described herein may be embodied and fully automated via software code modules executed by a computing system including one or more computers or processors. The code modules may be stored in any type of non-transitory computer readable medium or other computer storage device. Some or all of the methods may be embodied in dedicated computer hardware.

[0064] Many other variations beyond those described herein will be apparent from the present disclosure. For example, depending on the embodiment, certain operations, events, or functions of any of the algorithms described herein may be performed in a different order, or may be added, merged, or omitted entirely (e.g., not all acts or events described may be necessary to the implementation of an algorithm). Furthermore, in certain embodiments, operations or events may be performed simultaneously rather than sequentially, for example, via multi-threaded processing, interrupt processing, or multiple processors or processor cores, or on other parallel architectures. Furthermore, different tasks or processes may be performed by different machines and / or computing systems that can function together.

[0065] The various exemplary logic blocks, modules and engines described in connection with the embodiments disclosed herein may be implemented or executed by a machine such as a processing unit or processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in alternative examples, the processor may be a controller, a microcontroller, or a state machine, combinations thereof, and the like. The processor may include electrical circuitry configured to process computer-executable instructions. In another embodiment, the processor includes an FPGA or other programmable device that performs logical operations without processing computer-executable instructions. The processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in combination with a DSP core, or any other such configuration. Although described herein primarily with respect to digital technology, the processor may also include primarily analog components. For example, some or all of the signal processing algorithms described herein may be implemented in analog circuitry or mixed analog and digital circuitry. The computing environment may include any type of computer system, including, but not limited to, a computer system based on a computational engine within a microprocessor, mainframe computer, digital signal processor, portable computing device, device controller, or appliance, to name a few.

[0066] In particular, conditional language such as "can, could," "might, may," and the like, unless otherwise specified, is understood within the context in which it is generally used to convey that certain embodiments include certain features, elements, and / or steps, while other embodiments do not. Thus, such conditional language is not generally intended to imply that the features, elements, and / or steps are somehow required in one or more embodiments, or that one or more embodiments necessarily include logic for determining whether or not those features, elements, and / or steps should be included in or performed in any particular embodiment, with or without user input or prompting.

[0067] Disjunctive language, such as the phrase "at least one of X, Y, or Z," is understood within the context in which it is generally used to state that an item, term, etc. can be either X, Y, or Z, or any combination thereof (e.g., X, Y and / or Z), unless otherwise indicated. Thus, such disjunctive language is generally not intended to, and should not, imply that a particular embodiment requires at least one of X, at least one of Y, or at least one of Z, respectively, to be present.

[0068] Any process descriptions, elements or blocks in the flow diagrams described herein and / or illustrated in the accompanying drawings should be understood as potentially representing modules, segments or portions of code that include one or more executable instructions for implementing a particular logical function or element in the process. As will be appreciated by those skilled in the art, alternative implementations in which elements or functions may be omitted or performed in a different order than that shown or described, including substantially simultaneously or in reverse order, depending on the functionality involved, are included within the scope of the embodiments described herein.

[0069] Unless otherwise noted, articles such as "a" or "an" should generally be construed to include one or more of the listed items. Thus, a phrase such as "a device configured to" is intended to include one or more of the listed devices. Such one or more listed devices may also be collectively configured to perform the stated enumeration. For example, "a processor configured to perform enumerations A, B, and C" may include a first processor configured to perform enumeration A working in conjunction with a second processor configured to perform enumerations B and C.

[0070] It should be emphasized that many variations and modifications can be made to the above-described embodiments, and that the elements are to be understood as being among the other acceptable examples, and all such modifications and variations are intended to be included within the scope of the present disclosure.

Claims

1. 1. A matrix processor system comprising:

1. An active / shadow storage device comprising a group of active latches and shadow latches, said active / shadow storage device comprising: Receiving a first matrix including a plurality of values; enabling the active latch for one or more first clock cycles such that the value is stored in the active latch; causing the shadow latch to duplicate the value stored in the active latch; 2. A matrix processor system configured to read the values ​​replicated in the shadow latch from the shadow latch over one or more second clock cycles, the values ​​being transposed compared to the first matrix, and at least one value contained in the second matrix being stored in at least one active latch over the one or more second clock cycles.

2. 2. The system of claim 1, wherein the active latch is configured to be enabled on a first edge of a clock signal.

3. 3. The system of claim 2, wherein the shadow latch is configured to be enabled on a second edge of the clock signal opposite the first edge.

4. 2. The system of claim 1, wherein the active latch is associated with a first clock gate and the shadow latch is associated with a second clock gate.

5. 5. The system of claim 4, wherein the first clock gate and the second clock gate are enabled on opposite edges of a clock signal.

6. The system of claim 4 , wherein an instruction sets the first clock gate and the second clock gate.

7. The system of claim 1 , wherein the values ​​are respective bits.

8. 2. The system of claim 1, wherein the active latch is enabled and the shadow latch is disabled based on a particular clock gate that is set to be enabled.

9. 2. The system of claim 1, wherein the shadow latch replicates the value based on a particular clock gate being set to be enabled and the active latch being disabled.

10. 2. The system of claim 1, wherein the value is read based on a first clock gate being set to disabled, the particular clock gate being associated with the shadow latch, and a second clock gate associated with the active latch being set to enabled.

11. 2. The system of claim 1, wherein each group includes a respective active latch connected to a respective shadow latch.

12. The system of claim 1 , wherein the first matrix is ​​associated with an input to a neural network layer.

13. The system of claim 1 , wherein the transposed values ​​are provided as input to a matrix processor.

14. 1. A method implemented by a matrix processor system configured to transpose input data, comprising: storing said input data in active latches included in an active / shadow storage device of said matrix processor system, said active / shadow storage device including a plurality of groups of active latches and shadow latches, each group including an individual active latch connected to an individual shadow latch; copying information stored in the active latch to the shadow latch; storing new input data into the active latches for at least some of the active latches while the copied information is being read from the shadow latches, the copied information being read from the shadow latches being transposed compared to the input data; A method comprising:

15. 15. The method of claim 14, wherein information stored in the active latch is copied based on a particular clock gate that is set to be enabled, the particular clock gate being associated with the shadow latch.

16. 15. The method of claim 14, wherein the input data is stored in the active latch based on a particular clock gate being set to be enabled, the particular clock gate being associated with the active latch.

17. 17. The method of claim 16, wherein the new input data is stored in the active latch based on the particular clock gate being set to be enabled and a different clock gate associated with the shadow latch being set to be disabled.

18. The method of claim 14 , wherein the input data is associated with an input to a neural network layer.

19. The method of claim 14 , wherein the transposed and copied information is provided as input to a matrix processor.

20. 15. The method of claim 14, wherein the active latch is associated with a first clock gate and the shadow latch is associated with a second clock gate.

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