Matrix multiplication performed using a convolution engine that contains an array of processing elements

Abstract

An exemplary matrix processor includes processing elements arranged as a grid, the matrix processor configured to receive a first matrix and a second matrix, where the first matrix is ​​to be multiplied with the second matrix, transpose the second matrix, organize the second matrix into a number of columns, where each column is a row of the second matrix, and sequentially provide, over one or more cycles, the columns of the second matrix and the rows of the first matrix to the processing elements, where the processing elements are configured as multiply-accumulate units (MAC units), and where processing results are stored in the processing elements.

Description

[Technical field]

[0001] [CROSS REFERENCE TO RELATED APPLICATIONS] This application claims priority to U.S. Provisional Patent Application No. 63 / 336,586, entitled "MATRIX MULTIPLICATION PERFORMED USING CONVOLUTION ENGINE WITH INCLUDES ARRAY OF PROCESSING ELEMENTS," filed April 29, 2022, the disclosure of which is incorporated by reference in its entirety herein.

[0002] The present disclosure relates to matrix multiplication using hardware elements, and more particularly, to matrix multiplication using a convolution engine. [Background technology]

[0003] Neural networks are relied upon in disparate applications and increasingly form the basis of technology. For example, neural networks can be utilized to perform object classification on images acquired via a user device (e.g., a smartphone). In this example, the neural network may represent a convolutional neural network that applies convolutional layers, pooling layers, and one or more fully connected layers to classify objects depicted in the image. As another example, neural networks may be utilized for translation of text between languages. In this example, the neural network may represent a recurrent neural network.

[0004] Certain processors are typically used in neural network applications to increase the speed at which neural networks can be trained or used, for example, during inference. Exemplary processors may include graphics processing units (GPUs), which allow for rapid computation of operations involving matrices, tensors, and the like. Although GPUs can substantially speed up the processing of neural networks, as compared to, for example, central processing units (CPUs), they are typically designed to perform general linear algebra operations. Thus, they are not designed to specifically speed up the processing of neural networks. [Brief description of the drawings]

[0005] [Figure 1A] FIG. 2 is a block diagram illustrating an example matrix processor (convolution engine) included in an example matrix processor system.

[0006] [Figure 1B] FIG. 13 is a block diagram illustrating the adjustment of certain matrices to enable matrix multiplication via an exemplary matrix processor.

[0007] [Figure 2A] FIG. 2 illustrates two matrices to be multiplied via an exemplary matrix processor.

[0008] [Figure 2B] FIG. 13 illustrates the formatting of two matrices to allow matrix multiplication.

[0009] [Figure 2C] FIG. 1 illustrates the processing of two matrices to enable matrix multiplication.

[0010] [Diagram 3] 1 is a flowchart of an exemplary process for matrix multiplication using a convolution engine.

[0011] [Figure 4]1 is a block diagram illustrating an example vehicle including a queue processor system.

[0012] The embodiments of the present disclosure and their advantages are best understood by referring to the following detailed description: Like reference numerals have been used to identify like elements shown in one or more of the figures, and it should be understood that the indications therein are for the purpose of illustrating the embodiments of the present disclosure and are not intended to limit the disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] This application describes techniques that allow for matrix multiplication using a convolution engine. As described below, matrices can be multiplied using a matrix processor that includes a grid or array of processing elements. Exemplary processing elements may include multiply-accumulator units (MAC units) arranged in a grid or array. In some embodiments, the grid or array may be a non-systolic array such that each MAC unit computes information locally without moving data within the grid or array.

[0014] The convolution engine may rely on an array or grid of MAC units to efficiently compute the convolution between the input data and the weight data. Exemplary input data may include an input image, an input feature map, and the like. As known to those skilled in the art, the input data may have one or more input channels. For example, an input image may have three channels, each associated with a particular color (e.g., red, green, blue). As another example, an input feature map may have 32, 64, 512, etc. channels, formed based on application of a filter or kernel having 32, 64, 512 output channels. Similarly, the weight data may be associated with a number of output channels. Thus, when convolving the input data with the weight data, the output may be associated with a number of output channels.

[0015] As a simplified case, convolution allows a two-dimensional filter to be convolved with a two-dimensional input. For example, the filter may be a 3×3 filter or kernel, and the input may be a 12×12 input. In this example, the filter may be convolved with a 3×3 window in the input (e.g., the top left portion of the input). As an example, the values ​​contained in the 3×3 filter are multiplied with the corresponding values ​​in the 3×3 window. These multiplications are summed, and the resulting values ​​are determined at the output (e.g., a 12×12 output assuming a stride of 1). The resulting values ​​may be placed at the top left of the output. The filter is then moved, etc., slid across subsequent 3×3 windows in the input, resulting in the values ​​determined for those windows.

[0016] In the above examples, multiplications and additions are used to convolve the filter or kernel with the input. Certain processors, such as graphics processing units (GPUs), may be designed for fast matrix operations. For example, these GPUs may be designed to quickly compute multiplications between matrices. However, neural networks (e.g., convolutional neural networks) require additional hardware or software complexity associated with fast computation convolution. For example, the additional hardware or software complexity may result from the use of sliding filters or kernels over the input data. Typically, matrix multiplications are performed between the respective rows and columns of two matrices. However, in convolutions, the filters are multiplied element-wise with respective subsets of the input matrices. As another example, the additional hardware or software complexity may result from the use of a large number of input and output channels, which complicates the techniques for organizing and subsequently processing the input data and weight data.

[0017] Thus, a matrix processor may be used that is at least partially designed to efficiently and quickly process data of a convolutional neural network. A matrix processor, such as a convolution engine, may use input data associated with a first number of input channels and output data associated with a second number of output channels to compute a convolution. As an example, the matrix processor may use input data and weight data that are organized or formatted to facilitate larger convolution operations. For example, the input data may be in the form of a three-dimensional matrix (e.g., two-dimensional data across multiple input channels). In this example, the output data may be across multiple outer channels. Thus, the matrix processor may process larger input data by merging or flattening each two-dimensional output channel into a vector, so that an entire channel or a significant portion thereof may be processed by the matrix processor. As another example, data may be efficiently reused such that weight data may be shared across convolutions.

[0018] In some embodiments, the techniques described herein may apply the example matrix processors described in U.S. Pat. No. 11,157,287, U.S. Patent Publication No. 2019 / 0026250, and U.S. Pat. No. 11,157,441, which are incorporated by reference in their entireties and form part of this disclosure as if set forth herein.

[0019] While convolution engines such as the matrix processors described above are efficient for processing convolutional neural networks, their specialized design may complicate other processing operations. As described above, GPUs may be designed for specific operations (e.g., matrix multiplication). To enable efficient computation of neural networks, GPUs may need to have additional hardware and / or software complexity. Similarly, matrix processors may be designed for efficient computation of neural networks and may require additional hardware and / or software complexity to perform other operations (e.g., matrix multiplication).

[0020] Described herein are examples of adjusting the operation of a convolution engine, such as a matrix processor, to perform matrix multiplication on an arbitrary matrix. For example, the matrix processor may calculate a matrix multiplication of a first matrix with a second matrix. In this example, the first matrix may be adjusted to be formatted in a similar manner as the weight data. The matrix processor may then proceed normally using the particular convolution parameters to quickly generate a processing result (e.g., an output matrix). An example of the convolution parameters may include a filter size, a number of input or output channels, etc. Block Diagram

[0021] FIG. 1A is a block diagram illustrating an example matrix processor 110 (eg, an example convolution engine) included in an example matrix processor system 100.

[0022] The matrix processor system 100 may be used, for example, to compute a forward pass through a layer of a neural network. In some embodiments, the neural network may represent a convolutional neural network in which image or video information is processed. In the illustrated example, input data 130 is provided to the matrix processor 100, which includes an array or grid of processing elements 132. The processing elements may be, for example, multiply-accumulator units (MACs). In some embodiments, the array may be non-systolic such that each processing element multiplies and accumulates information over one or more cycles (e.g., clock cycles or processing cycles).

[0023] The input data 130 may represent an input image, one or more feature maps, or a portion thereof. For example, the portion may represent a particular window of input data to be multiplied with weight data (e.g., one or more kernels or filters). The input data 130 may also represent information being input to a layer of a neural network, such as a convolution, transformer, or fully connected network, to be multiplied with weight information (e.g., a weight matrix). The weight data 120 may represent one or more filters or kernels for one or more input channels. The weight data 120 may be loaded during a cycle, and optionally, in a subsequent cycle, different weight data 120 for different output channels may be loaded.

[0024] The matrix processor 110 may determine a processing result 112 associated with the input data 130 and the weight data 120. The processing result 122 may represent, for example, an output associated with one or more convolutions between the weight data 120 and the input data 130.

[0025] Additional description of exemplary matrix processors is included in U.S. Pat. No. 11,157,287, U.S. Patent Publication No. 2019 / 0026250, and U.S. Pat. No. 11,157,441, each of which is incorporated by reference in its entirety and forms part of this disclosure as if set forth herein.

[0026] 1B is a block diagram illustrating adjusting particular matrices to enable matrix multiplication via an exemplary matrix processor 110. The matrix processor 110 may be configured as a convolution engine to efficiently compute convolutions related to input data and weight data, as described above. Thus, the matrix processor 110 may be configured to operate based on convolution parameters specified or determined according to the data being processed, based on the particular convolution layer being processed, based on instructions, etc.

[0027] Exemplary convolution parameters may include a size associated with a filter along with information identifying the number of input channels, output channels, etc. For example, a convolution layer included in a convolutional neural network may apply a volume of filters (e.g., a 3×3×512 volume of filters). Thus, in this example, the convolution layer may apply a 3×3 filter to each input channel, resulting in 512 channels of output. These filters may be formatted or organized as weight data 120 such that columns of weight data may be provided sequentially (e.g., over sequential clock cycles or processing cycles) to processing elements. In some embodiments, each column may represent a filter associated with an output channel. Input data 130 may be similarly formatted or organized as rows, with each row corresponding to a pixel or element associated with an output channel.

[0028] Due to the above formatting or organization of information for weight data 120 and input data 130, multiplying two matrices (e.g., A matrix 140A and B matrix 140B) may not be easily suited for matrix processor 110. For example, due to the order or arrangement of weight data 120, B matrix 140B may not be aligned for multiplication with input data 130.

[0029] In some embodiments, the matrix processor 110 may be configured to scale the B matrix 140B and multiply the A matrix 140A and the B matrix 140B based on optionally setting certain convolution parameters. For example, the convolution parameters may be set such that the size associated with the filter is 1×1. Additionally, the B matrix 140B may be transposed 150 and optionally padded 152 (e.g., padded with zeros, also referred to herein as applied weighting).

[0030] 2A-2C, the B matrix 140B is transposed such that a portion of the transposed B matrix 140B may be arranged as weight data 120. For example, the rows of the transposed B matrix 140B may be arranged as respective columns that are to be applied sequentially as weight data 120. In some embodiments, the transposition 150 may be required such that the rows of the B matrix 140B may be used as weight data. In some embodiments, the matrix processor system 100 may provide row data as opposed to column data, such that such columns of the B matrix 140B cannot be readily provided as weight data.

[0031] For example, the weight data 120 and input data 130 (e.g., [Y,X] matrices) may be flattened in memory (e.g., SRAM, DRAM, etc.) such that strips of X are contiguous. Thus, in hardware, reading strips of X may be an easy contiguous read, but reading strips of Y may be more difficult and require complex strided loads. For example, the first read from the input data 120 in the first cycle may be a natural read (e.g., [B00, B01, B02, ...] in FIG. 2B) that may be contiguous bytes in memory. Similarly for the second cycle reads [B10, B11, B12, ...]. However, the first read from the weight data (e.g., [A00, A10, A20, ...] in FIG. 2B) may not be contiguous in memory. Thus, for a large matrix, e.g., 1000×1000, each element may be a stride of 1000 from the previous element in memory, as an example. Thus, in some embodiments, the weight data is transposed so that it is easier to read (e.g., similar to the input data). In some embodiments, the weight data is not transposed and memory fetches may be efficient for arbitrarily large stride loads and / or it may be possible to fetch columns of data.

[0032] Additionally, the B matrix 140B may optionally be padded or weighted based on the size of the information that the matrix processor 110 is configured to receive as the weight data 120. For example, in some embodiments, the B matrix 140B may have a particular number of elements or a particular number of bits. In this example, the B matrix 140B may be padded to bring the total number of elements or bits to a particular value (e.g., 32 bits, 32 elements). In some embodiments, if the total number of elements or bits is less than a first threshold number of elements or bits (e.g., 32, 48, etc.), the B matrix 140B may be padded to bring the total number of elements or bits to the first threshold. In some embodiments, if the total number of elements or bits is less than a second threshold number of elements or bits (e.g., 64, 96, etc.) but greater than the first threshold, the B matrix 140B may be padded to bring the total number of elements or bits to the second threshold.

[0033] In some embodiments, if B matrix 140B is larger than a second threshold number of elements or bits as described above, B matrix 140B may be sliced ​​or otherwise separated so that two sub-matrices are used. Each sub-matrix may include a portion of B matrix 140B separated along a particular dimension (e.g., a sub-matrix may include several columns of data). In some embodiments, each sub-matrix may be of a size according to the second threshold. The remaining portion may be padded as described above.

[0034] Blocks 150 and 152 may be implemented as hardware elements of the matrix processor system 100. For example, the hardware elements may be used to transpose the B matrix 140B (e.g., in a streaming context). In some embodiments, the matrix processor system 100 may receive a transposed 150 and optionally padded 152 matrix B 140B for processing.

[0035] Thus, for example, a processing element in a first cycle may receive information from weight data 120 and input data 130. For example, a first portion of A matrix 140A may be provided to processing element 132. In this example, the first portion may represent a first row of A matrix 140A. As an example, if the first row has four elements, the processing element in the first column 134A receives a first value for that row, the processing element in the second column 134B receives a second value for that row, the processing element in the third column 134C receives a third value for that row, and the processing element in the fourth column 134D receives a fourth value for that row.

[0036] Similarly, in a first cycle, the processing elements may receive a first portion of the transposed B matrix 140B. For example, a first column of the transposed B matrix 140B may be provided to the processing elements. In this example, the processing elements in the first row 136A may receive a first value in that column, the processing elements in the second row 136B may receive a second value in that column, the processing elements in the third row 136C may receive a third value in that column, and the processing elements in the fourth row 136B may receive a fourth value in that column.

[0037] Processing element 132 may then multiply the received values ​​from A matrix 140A with the received values ​​from transposed B matrix 140B. The remaining portions of A matrix 140A and transposed B matrix 140B may then be sequentially provided to the processing elements for multiplication and accumulation.

[0038] 2A shows two matrices to be multiplied via an exemplary matrix processor. In the illustrated example, A matrix 202A is shown as being a 4×4 matrix and B matrix 202B is shown as being another 4×4 matrix. As can be appreciated, the A and B matrices may be of different dimensions without adjusting the operation of the techniques described herein.

[0039] The A matrix 202A is shown as being transposed, i.e., the elements of the A matrix are flipped across the diagonal.

[0040] As shown, the result of the multiplication is B matrix 202B*A matrix 202A (eg, the order of matrix multiplication).

[0041] 2B illustrates the formatting of two matrices to allow for matrix multiplication. The matrix processor 110 is shown in this example with processing elements arranged as an array of a grid. For example, processing element 250 is shown as being at the top left of the array or grid.

[0042] The elements of the A matrix 202A are shown as being formatted as weight data. For example, the first column 252 of weight data to be provided to the processing elements represents the first row (e.g., the top row) of the transposed A matrix 202A shown in FIG. 2A. As shown, the columns of weight data represent respective rows of the transposed A matrix 202A. These columns may be queued or fetched sequentially. Additionally, the B matrix 202B is formatted such that the first row (e.g., the top row) of the B matrix 202A is the first row 254 of data to be provided to the processing elements. As shown, the rows represent the rows of the B matrix 202A that are queued or fetched sequentially.

[0043] Thus, with respect to processing element 250, element 250 may receive values ​​A(00) and B(00). These values ​​may be multiplied, for example, by a multiplier-accumulator unit. In the next cycle shown in FIG. 2C, the result of the multiplication may be added to a subsequent multiplication between A(01) and B(10).

[0044] 2C illustrates the processing of two matrices to enable matrix multiplication. In the illustrated example, the next row of the transposed A matrix 202A is provided to the matrix processor 110 as column 262. Additionally, the next row of the B matrix 202B is provided to the matrix processor 110 as row 264.

[0045] Thus, processing element 250 calculates the multiplication of A(01) and B(10). This multiplication is accumulated, so that processing element 250 stores the result A(00)*B(00)+A(01)*B(10). Although not shown, as can be understood, processing can continue such that all of columns 270 and all of rows 280 are received by the processing elements of matrix processor 110 (e.g., the values ​​of columns 270 and rows 280 are loaded into the processing elements).

[0046] Thus, each processing element may store an output value associated with the multiplication of A matrix 202A and B matrix 202B. For example, processing element 250 stores the result of A(00)*B(00)+A(01)*B(10)+A(02)*B(20)+A(03)*B(30). The output value stored in the processing element may then be read out as the processing result associated with the multiplication. For example, the values ​​stored in each row of the processing element may be read out sequentially. As another example, the values ​​stored in a threshold number of rows may be read out sequentially (e.g., 8 rows, 16 rows, etc.). flowchart

[0047] 3 is a flow chart of an exemplary process 300 of matrix multiplication using a convolution engine. For convenience, the process 300 is described as being performed by the matrix processing system 100.

[0048] In block 302, the system obtains a first matrix and a second matrix to be multiplied. The system may obtain the first matrix and the second matrix based on instructions being executed. For example, software being executed by the system may cause the first matrix to be fetched (e.g., from a memory).

[0049] In block 304, the system transposes and optionally pads the second matrix. The system transposes the second matrix as described in FIG. 1B-FIG. 2A. Specifically, the result of the multiplication between the first matrix and the second matrix represents the first matrix * the second matrix. Thus, the second matrix may be designated as the latter of the matrices in the order of multiplication. Furthermore, based on the size associated with the second matrix, the system may pad the second matrix as described above.

[0050] At block 306, the system configures convolution parameters associated with the matrix processor. As described above, the system may set the parameters to indicate a filter size of 1×1. In some embodiments, the system may perform the multiplication using a matrix having multiple channels. In these embodiments, the system may perform the multiplication as described above across individual channels. Thus, these channels may be processed separately.

[0051] In block 308, the system obtains the processing result. As described in Figures 2A-2C, the system formats or otherwise organizes the values ​​of the first matrix and the second matrix so that they can be provided to the matrix processor as weight data and input data. The multiplication may be performed over one or more cycles to obtain the processing result. Vehicle block diagram

[0052] 4 illustrates a block diagram of a vehicle 400 (e.g., vehicle 102). The vehicle 400 may include one or more electric motors 402 that cause movement of the vehicle 400. The electric motors 402 may include, for example, induction motors, permanent magnet motors, etc. As known to those skilled in the art, batteries 404 (e.g., one or more battery packs each comprising multiple batteries) may be used to power the electric motors 402.

[0053] The vehicle 400 further includes a propulsion system 406 that can be used to set the gear (e.g., propulsion direction) of the vehicle. For an electric vehicle, the propulsion system 406 can regulate the operation of the electric motor 402 to change the propulsion direction.

[0054] Additionally, the vehicle includes a matrix processor system 100 configured to perform matrix multiplication using a convolution engine (e.g., matrix processor 110). The matrix processor system 100 can process data such as images received from image sensors (e.g., cameras) positioned around the vehicle 400. The matrix processor system 100 can additionally output information to a display 408 included in the vehicle 400 and receive information (e.g., user input) therefrom. Other embodiments

[0055] All of the processes described herein may be embodied and fully automated via software code modules executed by a computing system including one or more computers or processors. The code modules may be stored in any type of non-transitory computer-readable medium or other computer storage device. Some or all of the methods may be embodied in dedicated computer hardware.

[0056] Many variations beyond those described herein will be apparent from this disclosure. For example, depending on the embodiment, certain operations, events, or functions of any of the algorithms described herein may be performed in a different order, or may be added, merged, or omitted entirely (e.g., not all acts or events described may be necessary to the implementation of an algorithm). Furthermore, in certain embodiments, operations or events may be performed simultaneously rather than sequentially, for example, via multi-threading, interrupt processing, or multiple processors or processor cores, or on other parallel architectures. In addition, different tasks or processes may be performed by different machines and / or computing systems that can function together.

[0057] The various example logic blocks, modules, and engines described in connection with the embodiments disclosed herein may be implemented or executed by a machine such as a processing unit or processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in alternative examples, the processor may be a controller, a microcontroller, or a state machine, combinations thereof, and the like. The processor may include electrical circuitry configured to process computer-executable instructions. In another embodiment, the processor includes an FPGA or other programmable device that performs logical operations without processing computer-executable instructions. The processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in combination with a DSP core, or any other such configuration. Although described herein primarily with respect to digital technology, the processor may also include primarily analog components. For example, some or all of the signal processing algorithms described herein may be implemented in analog circuitry or mixed analog and digital circuitry. The computing environment may include any type of computer system, including, but not limited to, a computer system based on a computational engine within a microprocessor, mainframe computer, digital signal processor, portable computing device, device controller, or appliance, to name a few.

[0058] Conditional language, particularly "can," "could," "might," or "may," is understood in its commonly used context to convey that certain embodiments include certain features, elements, and / or steps, but other embodiments do not, unless otherwise indicated. Thus, such conditional language is not intended to generally imply that the features, elements, and / or steps are somehow required in one or more embodiments, or that one or more embodiments necessarily include logic for determining whether those features, elements, and / or steps should be included in or performed in any particular embodiment, with or without user input or prompting.

[0059] Disjunctive language, such as the phrase "at least one of X, Y, or Z," is understood in the context of common usage to indicate that an item, term, etc. can be either X, Y, or Z, or any combination thereof (e.g., X, Y, and / or Z), unless otherwise indicated. Thus, such disjunctive language is generally not intended to, and should not, imply that a particular embodiment requires at least one of X, at least one of Y, or at least one of Z to each be present.

[0060] Any process descriptions, elements or blocks in the flow diagrams described herein and / or shown in the accompanying figures should be understood as potentially representing modules, segments or portions of code that contain one or more executable instructions for implementing a particular logical function or element in the process. As will be appreciated by those skilled in the art, alternative implementations in which elements or functions may be omitted, performed or described in a different order than that shown, including substantially simultaneously or in reverse order, depending on the functionality involved, are included within the scope of the embodiments described herein.

[0061] Unless otherwise noted, articles such as "a" or "an" should generally be construed to include one or more of the listed items. Thus, a phrase such as "a device configured to" is intended to include one or more of the enumerated devices. Such one or more enumerated devices may also be collectively configured to perform the stated enumeration. For example, "a processor configured to perform enumerations A, B, and C" may include a first processor configured to perform enumeration A working in conjunction with a second processor configured to perform enumerations B and C.

[0062] It should be emphasized that many variations and modifications can be made to the above-described embodiments, and that the elements are to be understood as being among the other acceptable examples, and all such modifications and variations are intended to be included herein within the scope of the present disclosure.

Claims

1. 1. A matrix processor comprising a plurality of processing elements arranged as a grid, said matrix processor comprising: receiving a first matrix and a second matrix, the first matrix to be multiplied with the second matrix; transposing the second matrix; organizing the second matrix into a number of columns, each column being a row of the second matrix; providing, sequentially over one or more cycles, columns of the second matrix and rows of the first matrix to the processing elements, where processing results are stored in the processing elements; A matrix processor configured to execute:

2. 2. A matrix processor as claimed in claim 1, wherein the order of multiplication is the first matrix * second matrix.

3. 2. A matrix processor as claimed in claim 1, wherein the second matrix is ​​padded based on a size associated with the second matrix.

4. 2. A matrix processor as claimed in claim 1, wherein the matrix processor is a convolution engine and convolution parameters are set for the matrix processor.

5. 5. A matrix processor as claimed in claim 4, wherein said convolution parameters indicate a filter of size 1x1.

6. A matrix processor as claimed in claim 5, wherein the convolution parameters indicate a single input and / or output channel.

7. 2. The matrix processor of claim 1, wherein the array of processing elements is non-systolic.

8. The matrix processor of claim 1 , wherein each processing element stores an element of the multiplication.

9. The matrix processor of claim 1 , wherein the processing elements are configured as multiply-accumulate units (MAC units).

10. 2. The matrix processor of claim 1, wherein the second matrix is ​​a subset of a larger matrix, the larger matrix being separated into a plurality of subsets based on a size of the second matrix exceeding a size associated with the processing elements.

11. 1. A method performed by a matrix processor comprising an array of processing elements, comprising: obtaining a first matrix and a second matrix, the first matrix being to be multiplied with the second matrix; transposing the second matrix; organizing the second matrix into a number of columns, each column being a row of the second matrix; providing, sequentially over one or more cycles, columns of the second matrix and rows of the first matrix to the processing elements, where processing results are stored in the processing elements; A method comprising:

12. The method of claim 11 , wherein the order of multiplication is the first matrix * second matrix.

13. The method of claim 11 , wherein the second matrix is ​​padded based on a size associated with the second matrix.

14. The method of claim 11 , wherein the matrix processor is a convolution engine and convolution parameters are set for the matrix processor.

15. The method of claim 14 , wherein the convolution parameters indicate a filter of size 1×1.

16. The method of claim 15 , wherein the convolution parameters are indicative of a single input and / or output channel.

17. The method of claim 11 , wherein the array of processing elements is non-systolic.

18. The method of claim 11 , wherein each processing element stores an element of the multiplication.

19. The method of claim 11 , wherein the processing elements are configured as multiply-accumulate units (MAC units).

20. 12. The method of claim 11, wherein the second matrix is ​​a subset of a larger matrix, the larger matrix being separated into a plurality of subsets based on a size of the second matrix exceeding a size associated with the processing elements.

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