Tools and Processes for Electrochemical Etching

Abstract

A method for fabricating high aspect ratio nanostructures in any functional material. An (N+1)th layer of substrate material is deposited on top of the existing N layers of nanostructures, where N is a natural number. The substrate material in the (N+1)th layer is then patterned and etched to create auxiliary nanostructures in the substrate material. Further, conformal coating of gap fill material, sealing layer, and functional material onto the auxiliary nanostructures is performed to create functional material nanostructures in the (N+1)th layer. A set of selective etches to the substrate material is then performed to leave multiple layers of high aspect ratio nanostructures in the functional material.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Patent Application No. 63 / 328,510, entitled "Tool and Processes for Electrochemical Etching," filed April 7, 2022, which is incorporated by reference in its entirety.

[0002] This application further claims priority to U.S. Provisional Patent Application No. 63 / 343,003, entitled "Creating Tapered High-Aspect Ratio Holes in Valve Metals," filed May 17, 2022, which is incorporated by reference in its entirety.

[0003] This application additionally claims priority to U.S. Provisional Patent Application No. 63 / 342,699, entitled "Metal Assisted Chemical Etch of Polycrystalline Silicon," filed May 17, 2022, the entire contents of which are incorporated by reference herein.

[0004] This application additionally claims priority to U.S. Provisional Patent Application No. 63 / 342,717, entitled "In-Situ Process Monitoring and Control System," filed May 17, 2022, the entire contents of which are incorporated herein by reference.

[0005] This application additionally claims priority to U.S. Provisional Patent Application No. 63 / 349,946, entitled "Tool and Processes for Electrochemical Etching," filed June 7, 2022, the entire contents of which are incorporated herein by reference.

[0006] The present invention relates generally to electrochemical etching, and more specifically to creating arbitrary high aspect ratio nanostructures on a variety of substrates. [Background technology]

[0007] Electrochemical etching is a type of etching technique used to transfer information into substrate materials, conductive metals, etc., using the principles of simple electrolysis. Electrochemical etching is also an imprinting method that etches a perfect, high-contrast, permanent imprint into any material that conducts electricity. It does not heat the material and does not weaken or alter the material's microstructure.

[0008] Electrochemical etching is an extremely fast and much cheaper process than other marking methods. It is known to produce high definition along with fast batch setup. These properties have made electrochemical etching a popular marking method for medical devices, aircraft parts, tools, tableware, etc. [Prior art documents] [Non-patent literature]

[0009] [Non-Patent Document 1] Lee et al., “Porous Anodic Aluminum Oxide: Anodization and Templated Synthesis of Functional Nanostructures,” Chemical Reviews, Vol. 114, No. 15, 2014, pp. 7487-7556 [Non-Patent Document 2] Ruhl et al., “A Non-Thermal Laser-Driven Mixed Fuel Nuclear Fusion Reactor Concept,” arXiv:2202.03170, 2022. [Non-Patent Document 3] Kim et al., “Self-Anchored Catalyst Interface Enables Ordered Via Array Formation from Submicrometer to Millimeter Scale for Polycrystalline and Single-Crystalline Silicon,” ACS Applied Materials and Interfaces, Vol. 10, No. 10, 2018, pp. 9116-9122 Summary of the Invention [Problem to be solved by the invention]

[0010] Unfortunately, currently the tools and processes for electrochemical etching are inadequate to create arbitrarily high aspect ratio nanostructures in a variety of substrates such as silicon, aluminum oxide, and the like. [Means for solving the problem]

[0011] In one aspect of the disclosure, a method for fabricating high aspect ratio nanostructures in any functional material comprises depositing an (N+1)th layer of substrate material on an existing Nth layer of nanostructures, where N is a natural number. The method further comprises patterning and etching in the (N+1)th layer of substrate material to create auxiliary nanostructures in the substrate material. The method additionally comprises performing conformal coating of a gap fill material, an encapsulation layer, and a functional material on the auxiliary nanostructures to create functional material nanostructures in the (N+1)th layer. Furthermore, the method comprises performing a set of selective etches on the substrate material to leave multiple layers of high aspect ratio nanostructures in the functional material.

[0012] The foregoing has outlined rather generally the features and technical advantages of one or more embodiments of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the present disclosure that may form the subject of the claims of the present disclosure will be described hereinafter.

[0013] A further understanding of the present disclosure can be obtained from the following detailed description when considered in conjunction with the following drawings. [Brief description of the drawings]

[0014] [Figure 1A] 1A-1D illustrate exemplary nanostructures formed in anodized aluminum oxide (AAO) using an exemplary anodization process, according to certain embodiments of the present disclosure. [Figure 1B] 1A-1D illustrate exemplary nanostructures formed in anodized aluminum oxide (AAO) using an exemplary anodization process, according to certain embodiments of the present disclosure. [Diagram 2] 1 is a flowchart of a method for performing an atomic precision electrochemical etching (AE2) process, according to an embodiment of the present disclosure. [Figure 3A] 3 is a cross-sectional view for performing an AE2 process using the steps described in FIG. 2 according to an embodiment of the present disclosure. [Figure 3B] 3 is a cross-sectional view for performing an AE2 process using the steps described in FIG. 2 according to an embodiment of the present disclosure. [Figure 3C] 3 is a cross-sectional view for performing an AE2 process using the steps described in FIG. 2 according to an embodiment of the present disclosure. [Figure 3D] 3 is a cross-sectional view for performing an AE2 process using the steps described in FIG. 2 according to an embodiment of the present disclosure. [Figure 3E] 3 is a cross-sectional view for performing an AE2 process using the steps described in FIG. 2 according to an embodiment of the present disclosure. [Figure 3F] 3 is a cross-sectional view for performing an AE2 process using the steps described in FIG. 2 according to an embodiment of the present disclosure. [Figure 4] FIG. 1 illustrates an exemplary roll-to-roll (R2R) AE2 process, according to an embodiment of the present disclosure. [Figure 5A]FIG. 2 illustrates an exemplary design of lateral etchant flow according to an embodiment of the present disclosure. [Figure 5B] FIG. 2 illustrates an exemplary design of lateral etchant flow according to an embodiment of the present disclosure. [Figure 6] FIG. 2 illustrates an exemplary design for introduction and evacuation of etchant across the area of ​​a process substrate, according to an embodiment of the present disclosure. [Figure 7A] FIG. 1 illustrates an exemplary spin-spray type etchant flow system with an eccentric rotating etchant spray arm and passive gravity-driven etchant outflow, according to an embodiment of the present disclosure. [Figure 7B] FIG. 1 illustrates an exemplary spin-spray type etchant flow system with an eccentric rotating etchant spray arm and passive gravity-driven etchant outflow, according to an embodiment of the present disclosure. [Figure 8] 1A-1C illustrate exemplary designs for a sliding etch zone, according to certain embodiments of the present disclosure. [Figure 9A] FIG. 1 illustrates an exemplary dual-axis, double-arm assembly for etchant agitation, according to certain embodiments of the present disclosure. [Figure 9B] FIG. 1 illustrates an exemplary dual-axis, double-arm assembly for etchant agitation, according to certain embodiments of the present disclosure. [Figure 10] FIG. 1 illustrates an overall etchant flow assembly with process chamber, mixing chamber, precursor reservoir, pump assembly, and etchant and precursor status sensing and actuation mechanisms according to an embodiment of the present disclosure. [Figure 11] FIG. 1 illustrates a vacuum-based degassing strategy according to an embodiment of the present disclosure. [Figure 12A] FIG. 1 illustrates an exemplary etchant freeze-based reaction inhibition according to certain embodiments of the present disclosure. [Figure 12B] FIG. 1 illustrates an exemplary etchant freeze-based reaction inhibition according to certain embodiments of the present disclosure. [Figure 12C]FIG. 1 illustrates an exemplary etchant freeze-based reaction inhibition according to certain embodiments of the present disclosure. [Figure 12D] FIG. 1 illustrates an exemplary etchant freeze-based reaction inhibition according to certain embodiments of the present disclosure. [Figure 13A] FIG. 1 illustrates inhibition of reactions based on freezing and sublimation of etchants according to certain embodiments of the present disclosure. [Figure 13B] FIG. 1 illustrates inhibition of reactions based on freezing and sublimation of etchants according to certain embodiments of the present disclosure. [Figure 13C] FIG. 1 illustrates inhibition of reactions based on freezing and sublimation of etchants according to certain embodiments of the present disclosure. [Figure 13D] FIG. 1 illustrates inhibition of reactions based on freezing and sublimation of etchants according to certain embodiments of the present disclosure. [Figure 14] FIG. 1 illustrates an exemplary design for thermal compensation during inhibition and initiation of a reaction, according to an embodiment of the present disclosure. [Figure 15A] FIG. 1 illustrates an exemplary in-situ metrology system for full substrate coverage, in accordance with an embodiment of the present disclosure. [Figure 15B] FIG. 1 illustrates an exemplary in-situ metrology system for full substrate coverage, in accordance with an embodiment of the present disclosure. [Figure 16] FIG. 1 illustrates an exemplary in-situ metrology system with scannable optics, according to an embodiment of the present disclosure. [Figure 17] FIG. 1 illustrates an exemplary system for digital micromirror device (DVD) modulated substrate thermal control, according to an embodiment of the present disclosure. [Figure 18] FIG. 1 is a cross-sectional view of an AE2 tool for electric field control according to an embodiment of the present disclosure. [Figure 19A] 1A-1C illustrate an exemplary edge contact design showing a front side seal contacting the outer edge of a process substrate according to an embodiment of the present disclosure. [Figure 19B]1A-1C illustrate an exemplary edge contact design showing a front side seal contacting the outer edge of a process substrate according to an embodiment of the present disclosure. [Figure 20] 1A-1C illustrate exemplary backside contact with a backside fluid according to certain embodiments of the present disclosure. [Figure 21] 1A-1C illustrate an exemplary backside contact using a vacuum chuck according to an embodiment of the present disclosure. [Figure 22] 1 is a flow chart of a method for forming nanowires of a functional material according to an embodiment of the present disclosure. [Figure 23A] 23A-23C are cross-sectional views for forming nanowires of functional material using the steps described in FIG. 22 according to certain embodiments of the present disclosure. [Figure 23B] 23A-23C are cross-sectional views for forming nanowires of functional material using the steps described in FIG. 22 according to certain embodiments of the present disclosure. [Figure 23C] 23A-23C are cross-sectional views for forming nanowires of functional material using the steps described in FIG. 22 according to certain embodiments of the present disclosure. [Figure 24A] 1A-1D are cross-sectional views of a functional material during a process of forming nanowires of the functional material according to certain embodiments of the present disclosure. [Figure 24B] 1A-1D are cross-sectional views of a functional material during a process of forming nanowires of the functional material according to certain embodiments of the present disclosure. [Figure 24C] 1A-1D are cross-sectional views of a functional material during a process of forming nanowires of the functional material according to certain embodiments of the present disclosure. [Diagram 25] 1 is a flowchart of a method for forming nanowires of a functional material (eg, boron) according to an embodiment of the present disclosure. [Figure 26A] FIG. 26 illustrates one version of the final structure resulting from utilizing the method of FIG. 25, according to one embodiment of the present disclosure. [Figure 26B] FIG. 26 illustrates one version of the final structure resulting from utilizing the method of FIG. 25, according to one embodiment of the present disclosure. [Figure 26C]FIG. 26 illustrates one version of the final structure resulting from utilizing the method of FIG. 25, according to one embodiment of the present disclosure. [Figure 27A] FIG. 26B is a cross-sectional view of the final structure of FIG. 26A according to an embodiment of the present disclosure. [Figure 27B] FIG. 26C is a cross-sectional view of the final structure of FIG. 26B according to an embodiment of the present disclosure. [Figure 27C] FIG. 26D is a cross-sectional view of the final structure of FIG. 26C according to an embodiment of the present disclosure. [Figure 28] 1 is a flowchart of a method for forming nanowires of a functional material according to an embodiment of the present disclosure. [Figure 29A] FIG. 29 illustrates the final structure using the method of FIG. 28 when no pulse anodization technique is utilized, according to an embodiment of the present disclosure. [Figure 29B] FIG. 29 illustrates a final structure using the method of FIG. 28 when a pulse anodization technique is utilized, according to an embodiment of the present disclosure. [Figure 30A] FIG. 13 is a diagram for preventing collapse and / or restoring collapsed nanostructures according to an embodiment of the present disclosure. [Figure 30B] FIG. 13 is a diagram for preventing collapse and / or restoring collapsed nanostructures according to an embodiment of the present disclosure. [Diagram 31] 1 is a flow chart of a method for forming nanowires of boron (or any other functional material) according to an embodiment of the present disclosure. [Figure 32A] 32A-32C are cross-sectional views for forming nanowires of boron (or any other functional material) using the steps described in FIG. 31 according to an embodiment of the present disclosure. [Figure 32B] 32A-32C are cross-sectional views for forming nanowires of boron (or any other functional material) using the steps described in FIG. 31 according to an embodiment of the present disclosure. [Figure 32C] 32A-32C are cross-sectional views for forming nanowires of boron (or any other functional material) using the steps described in FIG. 31 according to an embodiment of the present disclosure. [Fig. 32D] FIG. 32 is a cross-sectional view for forming nanowires of boron (or any other functional material) using the steps described in FIG. 31 according to an embodiment of the present disclosure. [Diagram 33] 1 is a flowchart of a method for fabricating silicon and polysilicon structures using MACE and metal interruption techniques according to an embodiment of the present disclosure. [Figure 34A] 34A-34C are cross-sectional views for fabricating silicon and polysilicon structures using MACE and metal interruption techniques using the steps described in FIG. 33 according to an embodiment of the present disclosure. [Figure 34B] 34A-34C are cross-sectional views for fabricating silicon and polysilicon structures using MACE and metal interruption techniques using the steps described in FIG. 33 according to an embodiment of the present disclosure. [Figure 34C] 34A-34C are cross-sectional views for fabricating silicon and polysilicon structures using MACE and metal interruption techniques using the steps described in FIG. 33 according to an embodiment of the present disclosure. [Fig. 34D] 34A-34C are cross-sectional views for fabricating silicon and polysilicon structures using MACE and metal interruption techniques using the steps described in FIG. 33 according to an embodiment of the present disclosure. [Figure 35A] 1 is an SEM image of a cross-section of a polysilicon pillar according to an embodiment of the present disclosure (scale bar is 200 nm). [Figure 35B] 1 is a SEM image of a tilted cross-section of a polysilicon pillar according to an embodiment of the present disclosure (scale bar is 1 micrometer). [Diagram 36] 1 is a flowchart of a method for creating a reverse tone imprint template according to an embodiment of the present disclosure. [Figure 37A] 37 is a cross-sectional view for creating a reverse-toned imprint template using the steps described in FIG. 36 according to an embodiment of the present disclosure. [Figure 37B]37 is a cross-sectional view for creating a reverse-toned imprint template using the steps described in FIG. 36 according to an embodiment of the present disclosure. [Figure 37C] 37 is a cross-sectional view for creating a reverse-toned imprint template using the steps described in FIG. 36 according to an embodiment of the present disclosure. [Figure 38A] 1 is a SEM image of a cross section of polysilicon pillars spaced approximately 170 nm apart (scale bar 200 nm) according to an embodiment of the present disclosure. [Figure 38B] 1 is a SEM image of a cross section of polysilicon pillars spaced approximately 30 nm apart after removal of the resist cap according to an embodiment of the present disclosure (scale bar 200 nm). [Figure 39A] 37 is a cross-sectional SEM image of polysilicon diamond-shaped pillars fabricated using MACE using the steps of FIG. 36 according to an embodiment of the present disclosure (scale bar 400 nm). [Figure 39B] 37 is a top-down SEM image of polysilicon diamond-shaped pillars fabricated using MACE using the steps of FIG. 36 according to an embodiment of the present disclosure (scale bar 500 nm). [Figure 39C] FIG. 37 is a top-down SEM image of polysilicon diamond-shaped pillars fabricated using MACE using the steps of FIG. 36 according to an embodiment of the present disclosure (scale bar 100 nm). [Diagram 40] 1 is a cross-sectional SEM of a fin etched beyond the polysilicon film interface with silicon according to an embodiment of the present disclosure (scale bar 800 nm). [Diagram 41] FIG. 1 illustrates mitigating disturbances in a residue layer according to certain embodiments of the present disclosure. [Diagram 42] FIG. 1 illustrates an in-situ monitoring and control process according to an embodiment of the present disclosure. [Figure 43A] FIG. 2 illustrates an exemplary AE2 process, according to an embodiment of the present disclosure. [Figure 43B] 1 illustrates a perforated carrier according to an embodiment of the present disclosure. [Diagram 44] 1 is a flowchart of a method for creating high aspect ratio nanostructures of functional materials with tethers for stability, according to an embodiment of the present disclosure. [Figure 45A] FIG. 45 is a cross-sectional view for creating high aspect ratio nanostructures of functional materials with tethers for stability using the steps described in FIG. 44 according to one embodiment of the present disclosure. [Figure 45B] FIG. 45 is a cross-sectional view for creating high aspect ratio nanostructures of functional materials with tethers for stability using the steps described in FIG. 44 according to one embodiment of the present disclosure. [Figure 45C] FIG. 45 is a cross-sectional view for creating high aspect ratio nanostructures of functional materials with tethers for stability using the steps described in FIG. 44 according to one embodiment of the present disclosure. [Figure 45D] FIG. 45 is a cross-sectional view for creating high aspect ratio nanostructures of functional materials with tethers for stability using the steps described in FIG. 44 according to one embodiment of the present disclosure. [Figure 45E] FIG. 45 is a cross-sectional view for creating high aspect ratio nanostructures of functional materials with tethers for stability using the steps described in FIG. 44 according to one embodiment of the present disclosure. [Figure 46] 1 is a flowchart of an alternative method for creating high aspect ratio nanostructures of functional materials with tethers for stability, according to an embodiment of the present disclosure. [Figure 47A] FIG. 47 is a cross-sectional view for creating high aspect ratio nanostructures of functional materials with tethers for stability using the steps described in FIG. 46 according to an embodiment of the present disclosure. [Figure 47B] FIG. 47 is a cross-sectional view for creating high aspect ratio nanostructures of functional materials with tethers for stability using the steps described in FIG. 46 according to an embodiment of the present disclosure. [Figure 47C]FIG. 47 is a cross-sectional view for creating high aspect ratio nanostructures of functional materials with tethers for stability using the steps described in FIG. 46 according to an embodiment of the present disclosure. [Figure 47D] FIG. 47 is a cross-sectional view for creating high aspect ratio nanostructures of functional materials with tethers for stability using the steps described in FIG. 46 according to an embodiment of the present disclosure. [Figure 47E] FIG. 47 is a cross-sectional view for creating high aspect ratio nanostructures of functional materials with tethers for stability using the steps described in FIG. 46 according to an embodiment of the present disclosure. [Fig.47F] FIG. 47 is a cross-sectional view for creating high aspect ratio nanostructures of functional materials with tethers for stability using the steps described in FIG. 46 according to an embodiment of the present disclosure. [Figure 47G] FIG. 47 is a cross-sectional view for creating high aspect ratio nanostructures of functional materials with tethers for stability using the steps described in FIG. 46 according to an embodiment of the present disclosure. [Figure 48] FIG. 1 illustrates a method for a RIE-based process for the fabrication of nanostructures of functional materials according to an embodiment of the present disclosure. [Figure 49] 1 is a flow chart of a method for creating nanostructures of functional materials using CVD-based hole filling, according to an embodiment of the present disclosure. [Figure 50] 1 is a flowchart of a method for creating nanostructures of functional materials using ALD-based hole filling, according to an embodiment of the present disclosure. [Figure 51] 1 is a flow chart of a method for spin-coating a functional material including a polymer for hole filling according to an embodiment of the present disclosure. [Figure 52] 1 is a flow chart of a method for growth of confined / shaped VLS / VS functional materials according to an embodiment of the present disclosure. [Diagram 53] 1 is a flowchart of a method for a multi-layer process according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] As mentioned in the background section, electrochemical etching is a type of etching technique used to transfer information into substrate materials, conductive metals, etc., using the principles of simple electrolysis. Electrochemical etching is also an imprinting method that etches a permanent, high-contrast imprint perfectly into any material that conducts electricity. It does not heat the material and does not weaken or alter the microstructure of the material.

[0016] Electrochemical etching is an extremely fast and much cheaper process than other marking methods. It is known to produce high definition along with fast batch setup. These properties have made electrochemical etching a popular marking method for medical devices, aircraft parts, tools, tableware, etc.

[0017] Unfortunately, currently the tools and processes for electrochemical etching are inadequate to create arbitrarily high aspect ratio nanostructures in a variety of substrates such as silicon, aluminum oxide, and the like.

[0018] Embodiments of the present disclosure provide tools and processes for utilizing electrochemical etching in creating arbitrary high aspect ratio nanostructures in a variety of substrates such as silicon, aluminum oxide, etc., as discussed below.

[0019] The following describes tools and processes for an atomic precision electrochemical etching (AE2) process. AE2 can be used to create arbitrary high aspect ratio nanostructures in a variety of substrates including silicon, aluminum oxide, etc.

[0020] AE2 includes a method for creating such nanostructures in silicon (and other substrates) using a catalyst influenced chemical etching (CICE) process (called metal assisted chemical etching (MACE), MacEtch, or AToMM).

[0021] AE2 can also be used to create nanostructures in valve metal oxides (wherein valve metals include Al, Mg, Zr, Nb, Sn, Hf, Ta, W, Bi, etc.). Such nanostructures are created using electrochemical etching (or anodization) of valve metal films. Details regarding reaction schemes for the creation of nanostructures in valve metal oxides are discussed in Lee et al., "Porous Anodic Aluminum Oxide: Anodization and Templated Synthesis of Functional Nanostructures," Chemical Reviews, Vol. 114, No. 15, 2014, pp. 7487-7556, which is incorporated herein by reference in its entirety. As discussed further below, anodized valve metal oxides are referred to as AVOs (anodic valve metal oxides). In one embodiment, anodized aluminum oxide (AAO) is an exemplary AVO. Generally, AVO with deep nanostructured pores is formed in acid electrolytes (alternatively called etchants) in which the anodic oxide is slightly soluble, such as selenic, sulfuric, oxalic, phosphoric, chromic, malonic, tartaric, citric, and malic acids. AVO nanostructures can be formed under both potentiostatic and galvanostatic conditions. The current density (j) in pore-forming anodization under potentiostatic conditions remains approximately constant within a certain range of values ​​during the anodization process. The thickness of the resulting porous oxide film is linearly proportional to the total amount of charge involved in the electrochemical reaction (i.e., the anodization time t).

[0022] 1A-1B show exemplary nanostructures formed in an AAO using an exemplary anodization process, according to certain embodiments of the present disclosure.

[0023] Referring to Figures 1A-1B, Figure 1A shows a top view of nanostructures formed in an AAO, while Figure 1B shows a side view of a separate nanostructure.

[0024] Reference is now made to Figure 2, which is a flow chart of a method 200 for performing an AE2 process, according to an embodiment of the present disclosure. Figures 3A-3F show cross-sectional views for performing an AE2 process using the steps described in Figure 2, according to an embodiment of the present disclosure.

[0025] 2 in conjunction with Figures 3A-3F, in step 201, a mask layer 301 is formed on a valve metal 302 (e.g., aluminum), optionally overlying a support material 303, as shown in Figure 3A. In one embodiment, the mask layer 301 corresponds to carbon pillars, as shown in Figure 3A. In one embodiment, such carbon pillars are created by depositing a resist using nanoimprint lithography, followed by plasma etching.

[0026] 3B, a plasma etch is performed on the valve metal 302. For example, in embodiments in which the valve metal 302 comprises aluminum, the aluminum may be etched using a chlorine-based plasma.

[0027] In step 203, the mask layer 301 is stripped, as shown in FIG. 3C.

[0028] In step 204, in one embodiment, AVO scaffolds 305 of AVO nanostructures 304 are fabricated on a support material 303 (which is optional) using the AE2 process, as shown in Figure 3D. An exemplary hole morphology of AVO scaffold 305 is also shown in Figure 3D. In one embodiment, support material 303 is aluminum in roll form.

[0029] In step 205, as shown in FIG. 3E, a functional material 306 is optionally deposited onto the AVO nanostructure 304 (which optionally includes an array of holes as shown in element 305).

[0030] In step 206, the structure of FIG. 3E is optionally attached to the other side of a support material (final support material) 303, and the AVO nanostructures 304 are etched and peeled off, as shown in FIG. 3F. For example, in one embodiment, the AVO nanostructures 304 are etched and peeled off using NaOH, KOH, H 3 PO 4 Etchants such as SiO 2 and HF can be utilized to etch and strip the AVO nanostructures 304 .

[0031] As previously discussed, Figures 2 and 3A-3F show an exemplary AE2 process. Optional collapse prevention of nanostructures 304 in the functional material (after the AVO scaffold 305 is removed) may be performed using one or more of the following techniques. In a first technique, a first metal is deposited at the base of the scaffold 305, followed by an insulator, followed by the functional material (e.g., functional material 306). The deposition may be performed using atomic layer deposition (ALD), chemical vapor deposition (CVD), low pressure CVD (LPCVD), atmospheric pressure CVD (APCVD), physical vapor deposition (PVD), electrochemical deposition, etc. In one embodiment, a metal insulating layer is used to create electrostatic repulsion between independent nanostructures in the functional material.

[0032] In a second technique, a first partial etch of the AVO (e.g., AVO scaffold 305) is performed, followed by depositing one or more support materials (resistant to the AVO etchant) around the exposed portions of the functional material nanostructures 304 using ALD, CVD, LPCVD, APCVD, PVD, electrochemical deposition techniques, etc. The AVO nanostructures 304 are then removed using an AVO etchant.

[0033] In a third technique, a first partial etch of the AVO (eg, AVO scaffold 305 ) is performed, leaving the AVO as a support material for the functional material nanostructures 304 .

[0034] In one embodiment, the walls of the nanostructures 304 created in the AVO have a predefined taper. In one embodiment, the taper is continuous. In another embodiment, the taper is stepwise. In one embodiment, the continuous taper is created by varying the current (at constant voltage conditions) and / or by varying the voltage (at constant current conditions). In one embodiment, such change is gradual. In another embodiment, such change is monotonic. In one embodiment, the taper is created in a manner that aids in gap-free deposition of the functional material in the AVO nanostructures 304.

[0035] In one embodiment, high aspect ratio holes are created in the valve metal 302. In one embodiment, a seed pattern is first created on the surface of the valve metal 302. In one embodiment, the seed pattern is created using a combination of nanoimprint lithography and etching (which can be wet or dry etching). The valve metal 302 is then anodized in a pore-forming manner, and the time of etching determines the depth of the hole. In one embodiment, the hole is tapered. In one embodiment, the taper is continuous. In another embodiment, the taper is stepwise. In one embodiment, the taper is monotonic. In one embodiment, the valve metal 302 is aluminum. In one embodiment, a functional material (e.g., functional material 306) is deposited into the high aspect ratio holes after anodization. In one embodiment, the deposition is performed using CVD, PECVD, LPCVD, APCVD, ALD, PVD, electrochemical deposition, etc.

[0036] In one embodiment, the functional material is deposited / grown / filled into the high aspect ratio holes after anodization, in one embodiment, the deposition / growth / filling is performed using CVD, PECVD, LPCVD, APCVD, ALD, PVD, electrochemical deposition, electroplating, electroless plating, electrochemical ALD, etc.

[0037] In one embodiment, after anodization, a barrier material is conformally deposited to protect the functional material (e.g., from oxidation). Exemplary barrier materials include, but are not limited to, silicon, silicon dioxide, silicon nitride, silicon carbide, carbon, metals, platinum, gold, ruthenium, polymers, and the like. In one embodiment, electroplating is followed by conformally depositing a seed layer. In one embodiment, the conformal seed layer is connected to an electrode (e.g., on one side of the substrate). Additives such as polyethylene glycol (PEG) are utilized to encourage growth of the functional material from underneath and to reduce the likelihood of gap formation during deposition.

[0038] Alternatively, a bilayer stack of a valve metal (different from aluminum) and aluminum is utilized during anodization. Anodized aluminum oxide (AAO) formed on valve metals other than aluminum (Ti, W, Nb, Zr, Ta, etc.) is known to contain a valve metal oxide (different from aluminum oxide) at the bottom of the etched structure. In one embodiment, the valve metal oxide is then selectively removed (with respect to aluminum oxide) using a suitable wet etching process. Then, in one embodiment, an area-selective atomic layer deposition (ALD) process is utilized to coat a barrier layer only on the sides of the etched holes, and not on the bottom where exposed valve metal is present. For example, with tungsten as the valve metal above, Al instead of tungsten is deposited. 2 O 3 Selectively coats SiO 2 There exists an area-selective process for electroplating the functional material in a gapless manner. The uncovered tungsten can then be used as a seed layer to electroplate the functional material in a gapless manner. Alternatively, instead of the area-selective ALD of the barrier layer, a conformal coating of the barrier layer is performed, followed by etching away (e.g., using reactive ion etching) the base of the conformal barrier coating to open up the valve metal layer (previously buried under the conformal barrier layer). The uncovered valve metal layer can then be used as a seed layer to electroplate the functional material in a gapless manner. After removal of the AAO scaffold and the valve metal, a final barrier layer deposition is performed to cover the bottom of the functional material.

[0039] Generally, in one embodiment, the seed layer for electroplating is one or more of gold, bismuth, cadmium, copper, lead, antimony, tellurium, zinc, silver, beryllium, cobalt, chromium, iron, molybdenum, niobium, palladium, platinum, tantalum, thorium, titanium, vanadium, tungsten, and zirconium.

[0040] In one embodiment, hole tapering is utilized to reduce the tendency of electroplating to form gaps, hi one embodiment, the electroplating is performed in a roll-to-roll fashion.

[0041] Reference is now made to FIG. 4, which illustrates an exemplary roll-to-roll (R2R) AE2 process, according to an embodiment of the present disclosure.

[0042] As shown in Figure 4, Figure 4 shows a nanoimprint lithography (NIL) template roll 401 as well as a source substrate roll 402. Additionally, Figure 4 shows an optional roll-to-roll (R2R) nanoimprint lithography (NIL) 403.

[0043] Additionally, Figure 4 shows a close-up of the template (see element 404) and optional R2R reactive ion etch (RIE) / descum etch 405. Furthermore, Figure 4 shows R2R AE2 406 with optional tapering in the nanostructure to enable a subsequent optional high aspect ratio chemical vapor deposition (CVD) step.

[0044] Additionally, FIG. 4 shows optional R2R deposition 407, optional in-situ functional metrology 408, and optional transfer onto a final roll 409.

[0045] The AE2 process can be used to fabricate novel devices including DRAM, NAND flash, SRAM, FinFETs, Deterministic Lateral Displacement (DLD) devices, supercapacitors, and more.

[0046] In one embodiment, the tool for the AE2 process has the objective of etching nanoscale features using the AE2 process at a target yield (or higher) and a target throughput (or higher), hi one embodiment, the tool is specifically optimized for AVO nanopore creation.

[0047] To achieve a target yield, the etch height variation needs to be less than a certain percentage of the etch height (e.g., 30% in one embodiment, 20%, 10%, 5%, or less in other embodiments). Achieving this objective requires several subsystems and capabilities, including, but not limited to, the ability to handle the corrosive AE2 etchant without filtering contaminants (metal or otherwise). Copolymers such as polytetrafluoroethylene (PTFE), perfluoroalkoxyalkanes (PFA), and high density polyethylene (HDPE) meet such requirements.

[0048] Further, in one embodiment, the achievement of the objectives discussed above requires several subsystems and capabilities, including the ability to handle substrate sizes of 300 mm or more. This requires automatic loading and unloading of 300 mm substrates between the internal chambers of the tool and between the internal chambers of the tool and the inlets / outlets. In addition, this also requires the tool chambers to be sized to handle 300 mm substrates. Automatic substrate handling and tool processing strategies that meet these requirements are available. In one embodiment, the process substrate is processed in a vertical configuration, but once the etch is performed, the substrate is rotated to a horizontal configuration to be handled, for example, using a horizontal articulated robot (SCARA) type robot arm. In one embodiment, the AE2 process is performed on a roll-to-roll substrate. In subsequent designs, the wafer and / or substrate is replaced with a roll substrate. In one embodiment, the roll substrate is processed repeatedly in a stepwise manner, where the roll substrate is processed in a current location, then the chamber is unsealed, the roll substrate is advanced to a new location, the chamber is resealed, processing is performed in the new location, and so on. In another embodiment, the roll substrate is processed continuously. In one embodiment, the seal between the roll substrate and the etching chamber is a sliding seal.

[0049] Additionally, in one embodiment, achieving the objectives discussed above requires several subsystems and capabilities, including front side etchant control. On the side of the process substrate where the AE2 process occurs, the reactants for the AE2 process need to be maintained at uniform concentrations across the area of ​​the process substrate while also ensuring that the products of the AE2 process are continually removed from the reaction site. Uniform reactant concentrations can be maintained by continuous or intermittent etchant circulation, using design features that improve etchant uniformity, and using in-chamber etchant agitation methods that prevent stagnant areas.

[0050] In one embodiment, etchant circulation can be achieved by several methods. If peripheral contact is used in the front side chamber for etchant contamination (assuming this is the side where the AE2 process takes place), one or more groups of inlets (which can be in the form of nozzles) may be used to introduce the etchant into the chamber, and one or more groups of outlets may be used to exit the chamber. In one embodiment, the groups of inlets and outlets are fabricated integrally with the front side chamber. In one embodiment, design optimization techniques are used in conjunction with computational fluid dynamics (CFD) based fluid simulations to ensure minimal flow non-uniformity and stagnation. Figures 5A-5B and 6 show two exemplary designs.

[0051] 5A-5B show exemplary designs for lateral etchant flow according to certain embodiments of the present disclosure. FIG 6 shows exemplary designs for introduction and evacuation of etchant across an area of ​​a process substrate according to certain embodiments of the present disclosure.

[0052] Referring to Figure 5A, Figure 5A shows a process chamber 501 filled with an etchant, along with an inlet manifold 502 and an outlet manifold 503. In addition, Figure 5A shows a process wafer 504.

[0053] Referring to FIG. 5B, FIG. 5B shows a cross section of the inlet manifold 502 and the outlet manifold 503 .

[0054] 6, which shows a multi-layer front cover 601, a process wafer 602, an etch product 603, as well as an etchant inlet 604 and an etchant outlet 605. Additionally, the local etchant flow direction is specified by element 606.

[0055] As shown in Figure 5, fluids are introduced and exhausted from the sides of the chamber 501 (see 502, 503). In Figure 6, fluids are introduced and exhausted using inlets and outlets (see 604, 605) located throughout the walls of the chamber. Manufacturing of these designs is possible using standard computer numerical control (CNC) machines. In one embodiment, the multi-layered front cover 601 is manufactured by joining multiple 2D machined pieces, for example using polymer welding of machined polytetrafluoroethylene (PTFE) pieces.

[0056] In one embodiment, a spin-spray type system is used to deliver and circulate the etchant to the front side. In one embodiment of the system, a rotating arm is used to apply new etchant to the process substrate, which is kept stationary. To remove the used etchant from the substrate surface, an active strategy may be used, where a second arm, integrated with the first arm or others, may be used to centrifugally move the used etchant out. Alternatively, a passive strategy may be used, where the substrate is kept vertical and gravity is used to pull the used etchant down into a collection chamber. The axis of rotation of the arm may be fixed, movable coaxially with the process substrate, or eccentric. In a second embodiment, the etchant application arm is fixed and the process substrate itself is rotated. In all embodiments of the spin-spray type system, an AE2 compatible chamber is used to surround the entire front side of the process substrate and to store any etchant that is sprayed in different directions by the rotating process substrate and / or the etchant application arm. One illustration of the embodiment described above is shown in Figures 7A-7B.

[0057] 7A-7B show an exemplary spin-and-spray etchant flow system with an eccentric rotating etchant spray arm and passive gravity-driven etchant flow, according to certain embodiments of the present disclosure. Specifically, FIG. 7A shows a cross-section of a side view of the spin-and-spray etchant flow system, and FIG. 7B shows a top view of the spin-and-spray etchant flow system.

[0058] Referring to Figure 7A, such a system includes a front cover 701, an eccentric rotating etchant spray arm 702, an etchant inlet 703, and a gravity driven etchant outlet 704. Figure 7A also shows an etchant 705 and a fixed and vertical process wafer 706.

[0059] FIG. 7B also shows the eccentric rotating etchant spray arm 703 and process wafer 706, as well as the direction of rotation of spray arm 702 (see 707).

[0060] In one embodiment, a system with a sliding etching zone is used. In one embodiment, a group of inlet and outlet nozzles located close to each other are used to create a localized circulating etchant zone. In one embodiment, the group of nozzles is scanned across the substrate to etch the entire substrate, as shown in FIG.

[0061] FIG. 8 illustrates an exemplary design with a sliding etch zone, according to an embodiment of the present disclosure.

[0062] As shown in Fig. 8, the process wafer 801 is fixed and horizontal. Additionally, the design of Fig. 8 includes a sliding etching zone 802 with etchant 803, etchant inlet 804, and etchant outlet 805. Additionally, Fig. 8 shows a front side cover 806 and a scannable group of inlets and outlets 807.

[0063] In one embodiment, geometric elements such as baffles and fins are placed inside the etchant chamber to ensure the desired fluid flow. In one embodiment, these are fabricated integrally with the front side chamber. In one embodiment, design optimization techniques are used in conjunction with computational fluid dynamics (CFD) based fluid simulations to design these geometric elements.

[0064] In one embodiment, for active etchant agitation, movable assemblies within the chamber are used to agitate the etchant and prevent stagnant zones. In one embodiment, these assemblies are in the form of groups of intersecting arms. In another embodiment, these assemblies are groups of arms with separate centers of rotation. In another embodiment, the movable assemblies are the inlets and outlets for the etchant. In another embodiment, the movable assemblies have geometric elements such as baffles and fins. In one embodiment, the actuation mechanisms of these assemblies are indirect (such as actuating the assemblies with integral magnets using a rotating external magnetic field), or direct (such as using direct drive motors), or using fluid reaction and impact forces (in a manner similar to reaction and impulse turbines). An exemplary two-axis double arm assembly with fluid actuation is shown in Figures 9A-9B.

[0065] 9A and 9B show an exemplary two-axis, double arm assembly for etchant agitation, according to certain embodiments of the present disclosure, specifically, FIG 9A shows a cross-section of a side view of the assembly, and FIG 9B shows a top view of the assembly.

[0066] As shown in FIG. 9A, such an assembly includes a front cover 901, a process wafer 902, counter rotating etchant agitation arms 903, etchant 904, and an etchant outlet 905.

[0067] Referring to FIG. 9B, FIG. 9B shows a top view of an assembly including a process wafer 902 and an etchant inlet jet 906.

[0068] In one embodiment, the etchant (e.g., etchant 904) circulating in the etching chamber is mixed and stored in a mixing chamber. In one embodiment, the mixing chamber is located remotely from the etching chamber and connected to the etching chamber using AE2 compatible tubing. In one embodiment, the mixing chamber has various monitors of the etchant conditions, such as concentration monitors, flow monitors, temperature monitors, impurity / precipitant / particle monitors, and pressure monitors. In one embodiment, the mixing chamber has various actuation mechanisms to change the etchant conditions, such as an etchant inlet (e.g., etchant inlet jet 906) for the etchant precursor to dynamically change the etchant concentration, and a heating assembly to change the etchant temperature. The flow of etchant between the mixing chamber and the process chamber and between the mixing chamber and the precursor reservoirs can be handled using AE2 compatible pumps.

[0069] In one embodiment, the etchant precursor is stored in a vessel such as a mixing chamber, and the precursor reservoir has precursor condition monitors such as concentration monitors, temperature monitors, impurity / precipitant monitors, pressure monitors, and precursor condition actuation mechanisms such as inlets for dynamically varying precursor concentration, heating assemblies for varying precursor temperature.

[0070] FIG. 10 shows an overall etchant flow assembly 1000 with process chamber, mixing chamber, precursor reservoir, pump assembly, and etchant and precursor status sensing and actuation mechanisms according to an embodiment of the present disclosure.

[0071] 10, the assembly 1000 includes a process wafer 1001, a front side cover 1002, an etchant inlet 1003, and an etchant outlet 1004. Additionally, the assembly 1000 includes a mixing chamber 1005 with a catalytically influenced chemical etching (CICE) compatible etchant pump 1006, an etchant status sensor 1007, and thermal actuation of the mixing chamber etchant (see element 1008). Additionally, the assembly 1000 includes precursor storage units 1009A-1009N along with a precursor status sensor 1010, where N is a positive integer.

[0072] With regard to degassing, one or more of the products of the AE2 process may be gas. Heavy production of gas during AE2 may lead to bubble formation in the etchant in the vicinity of the reaction site, which may result in non-uniformity in the etchant concentration, reduce visibility through the etchant for in-situ measurements, and may hinder or reduce the efficiency of the etchant flow system, for example. It is noted that the bubbles do not need to be completely removed, but only controlled to the extent that they do not hinder the in-situ measurements, the etchant flow, and the uniformity of the reaction. As discussed below, several methods may be used to reduce bubble formation in the AE2 process.

[0073] In one embodiment, certain AE2 regimes lead to the production of more air bubbles, therefore operating in a regime that releases less gas can reduce the air bubble problem.

[0074] In one embodiment, a lower etch rate can also reduce the rate of bubble generation. In one embodiment, a lower etch rate is achieved, for example, by lowering the etchant concentration or by the concentration of a rate-limiting etchant precursor. It can also be achieved by lowering the temperature of the etchant.

[0075] In one embodiment, increasing the etchant pressure increases the solubility of gases in the etchant, reducing the formation of gas bubbles.

[0076] In one embodiment, lowering the etchant temperature increases the solubility of gases in the etchant and can be used to reduce the formation of gas bubbles.

[0077] In one embodiment, a membrane degasser, i.e., a PTFE-based AE2 compatible gas-liquid separation membrane, on the process chamber walls or elsewhere in the etchant path, can be used to selectively extract gas from the etchant and reduce bubble formation.

[0078] In one embodiment, ultrasonic treatment is used to dislodge air bubbles attached to the process substrate surface and drive them into the bulk etchant. Ultrasonic treatment can be accomplished, for example, by piezoelectric elements integrated into the front and / or back covers.

[0079] In one embodiment, a vacuum-based degassing chamber is used as part of the mixing chamber to reduce the amount of dissolved gas in the etchant solution. Such a strategy is discussed below with respect to FIG.

[0080] In one embodiment, the tool is operated so that the process substrate is vertical during the AE2 process, so that bubbles move against gravity to the top of the tool rather than moving towards the front of the tool in a horizontal configuration and obstructing the view for in-situ metrology that can be performed.

[0081] In one embodiment, air bubbles attached to the surface of the process substrate are released using a movable arm with a knife edge that moves across the surface of the process substrate while maintaining a small gap (on the order of millimeters or less) between the substrate and the knife edge.

[0082] Reference is now made to FIG. 11, which illustrates a vacuum-based degassing strategy according to an embodiment of the present disclosure.

[0083] As shown in FIG. 11, H in the etching solution of the process wafer 11022 The bubbles 1101 travel through the etchant outlet 1103 and into the degassing chamber 1104, and then into the etchant solution through the etchant inlet 1105. Additionally, as shown in FIG. 2 There is a vacuum or partial vacuum for (see element 1106). In addition, FIG.

[0084] In one embodiment, for uniform etching across the substrate, spatial variations in the initiation and termination of the AE2 process need to be carefully controlled for reaction inhibition and initiation. For example, in a wet process, if a reaction inhibition fluid (e.g., water) is injected at one end of the process substrate and it takes 5 seconds for the front of the inhibition fluid to cover the entire substrate with a sample etch rate of 1 μm / min, this results in an etch height variation of approximately 80 nm across the substrate. Similarly, if an etchant is injected at one end of the process substrate at the beginning of the AE2 process and it takes 5 seconds for the front of the etchant to cover the entire substrate with a sample etch rate of 1 μm / min, this results in an etch height variation of approximately 80 nm across the substrate. Several methods can be used to reduce the etch height variation during reaction inhibition and initiation.

[0085] With regard to reducing the etch rate, reducing the etch rate before or throughout the etch suppression can reduce the etch height variation. In one embodiment, reducing the etch rate is accomplished by changing the relative concentrations of the etchant precursors (in the mixing chamber) or by reducing the temperature of the substrate (which leads to a corresponding reduction in the etch rate).

[0086] In one embodiment, with respect to injection of the etchant and inhibiting fluids from the front side of the substrate, by introducing the etchant and inhibiting fluids from the front side of the substrate, the flow path of the etchant is reduced. This reduces the time that stray etchant remains in the process chamber, thus reducing the reaction inhibition time and corresponding etch non-uniformity. Similarly, it reduces the time it takes for the etchant to be introduced at the start of the etch. Many of the methods described above in connection with the etch cycle can be used for the front side introduction of the etchant and inhibiting fluids. For example, the design shown in FIG. 6 can be utilized.

[0087] With regard to etchant freezing, for example, the process substrate may be cooled using a Peltier element, which causes a thin layer of etchant to the right of the substrate to freeze (which also stops the AE2 reaction). The bulk of the unfrozen etchant may then be replaced with a reaction inhibitor fluid, such as water, while the etchant to the right of the substrate is still frozen. In one embodiment, the thin layer of frozen etchant is then superheated so that it melts and diffuses into the bulk of the inhibitor fluid to its right. An illustration of such a process is shown in Figures 12A-12D.

[0088] 12A-12D illustrate an exemplary etchant freeze-based reaction inhibition according to certain embodiments of the present disclosure.

[0089] Specifically, FIG. 12A shows a wafer chuck 1201, a process wafer 1202, a thermoelectric cooler (TEC) 1203 at sub-zero temperatures, a front cover 1204, an etchant inlet 1205, an etchant outlet 1206, and a seal 1207.

[0090] As shown in Figure 12B, Figure 12B shows a thin layer of frozen etchant (see element 1208). Figure 12C shows the replacement of the bulk etchant solution with an inhibiting fluid (see element 1209). Figure 12D shows a thin layer of melted etchant (see element 1210) and a TEC placed against the heat (see element 1211).

[0091] Alternatively, after the freezing process, the bulk of the fluid is replaced with air, which is then evacuated so that this frozen layer of etchant sublimes. In one embodiment, this evacuation is accomplished by placing the entire etching chamber in a larger AE2 compatible vacuum chamber, or alternatively, by connecting an AE2 compatible vacuum pump, such as a bellows pump, to the reaction chamber itself to draw off the charged air. An illustration of such an embodiment is shown in Figures 13A-13D.

[0092] 13A-13D illustrate the inhibition of reactions based on freezing and sublimation of etchants according to certain embodiments of the present disclosure.

[0093] As shown in Figure 13A, Figure 13A shows a wafer chuck 1301, a process wafer 1302, a thermoelectric cooler (TEC) 1303 at sub-zero temperatures, a front cover 1304, an etchant inlet 1305, an etchant outlet 1306, and a seal 1307. Additionally, Figure 13A shows a large vacuum chamber 1308.

[0094] Figure 13B shows a thin layer of frozen etchant 1309. Figure 13C shows the displacement of the bulk etchant solution with air (see element 1310). Figure 13D shows a thin layer of sublimating etchant (see element 1311) and a TEC (see element 1312) positioned against the heat. Additionally, Figure 13D shows the operation of a vacuum (see element 1313).

[0095] With regard to thermal compensation, an array of thermal actuators can be used to actively compensate for any etch rate variations caused during the initiation and inhibition of etching. Several methods can be used to achieve thermal actuation. An exemplary design for thermal compensation is given in FIG.

[0096] FIG. 14 illustrates an exemplary design for thermal compensation during inhibition and initiation of a reaction, according to an embodiment of the present disclosure.

[0097] As shown in Figure 14, Figure 14 shows a wafer chuck 1401, a process wafer 1402, a front side cover 1403, an etchant inlet 1404, and an etchant outlet 1405. Additionally, as shown in Figure 14, Figure 14 shows a grid of independently controllable thermoelectric coolers 1406.

[0098] With regard to evaporation of etchants in a vacuum, for example when a thin sheet of reactant is used, the entire etchant in the reaction chamber can be evaporated rapidly using a vacuum. This evaporation can be achieved by placing the entire etching chamber in a larger AE2 compatible vacuum chamber, or alternatively by connecting an AE2 compatible vacuum pump, such as a bellows pump, to the reaction chamber itself to draw off the air charge.

[0099] In one embodiment, for process variation control, spatial variations in etchant and etch product concentrations, local etchant flow rates, etchant temperatures, pattern density variations, and substrate edge effects can lead to variations in etch quality (degree of porosity, wall surface roughness, wall angle) as well as variations in etch rate. In one embodiment, a feedback-based system is used to control process variations. In another embodiment, a purely feed-forward approach is used, where possible process variations are known in advance, and local actuation methods (such as thermal actuation) are used in an open-loop manner to correct for known process variations. In another embodiment, a hybrid approach is used, where known process variations are combined with real-time process variation measurements to control process actuators.

[0100] In terms of metrology, a key feature of the AE2 process is the uniformity and control of etch depth. The etch depth as well as any porous layers formed during AE2 can be measured and characterized using a number of destructive and non-destructive methods, including scanning electron microscopy (SEM), transmission electron microscopy (TEM), atomic force microscopy (AFM), optical scatterometry, ellipsometry, small angle x-ray scatterometry, through-focus scanning optical microscopy (TSOM), helium ion microscopy, and proton microscopy.

[0101] For in-situ measurement of the etch profile, in one embodiment, the design of the AE2 tool ensures that the front as well as the back of the substrate can be imaged using one or more wavelengths of light. In one embodiment, the design of the AE2 tool considers the transmission of light through the components and electrolyte to the back of the wafer to create an ohmic contact, and to the front of the wafer for optical metrology. In one embodiment, this can be accomplished by using sapphire windows on each side of the process chamber, or by using fiber optic cables. The sapphire windows and / or fiber optic components can be coated with an etchant resistant material such as Teflon or aluminum oxide while maintaining transparency to the substrate. In one embodiment, the electrodes are made of platinum wires, platinum mesh, indium tin oxide with an etchant resistant coating, doped silicon wafers with optional coatings of etchant resistant materials such as carbon, diamond, aluminum oxide, Cr, etc. In one embodiment, the etchant resistant material can be further doped to improve electrical conductivity. In one embodiment, the electrode geometry is optimized to ensure a uniform electric field while also ensuring that light passes through, such as with annular rings. Mirrors such as chrome coated silicon or thin chrome plates may also be used to direct light onto the substrate. In one embodiment, one or more electrodes are used on each side of the wafer in the process chamber.

[0102] In one embodiment, the optical properties of silicon nanostructures lead to a wide spectrum and hue change of light and are therefore used in-situ to inspect the substrate during the etching process.

[0103] In one embodiment, an optical imaging system is used to measure the reflectance over a large sample area in real time. The sample is illuminated with light with known spectral content. The light may be white light, colored light, a single wavelength, in a narrow or broad spectral band, etc. A camera can then image the sample reflecting this light. The camera can be monochrome, color (RGB), multispectral, hyperspectral, etc. The multi-megapixel resolution found in modern cameras allows millions of points on the sample to be observed simultaneously. The video frame rate allows for in-situ real-time measurements. Each image can be divided by an image of a reference or used as is to calculate a reflectance image of the sample. Image processing algorithms determine the completion of the process and gather data on the heterogeneity of the CICE both within and between samples.

[0104] Visible wavelengths of light from the backside of the wafer cannot detect etch depth during AE2. Instead, infrared (IR) spectroscopy may be used since it is a fast and non-destructive in-situ method of etch status detection. Visible light images obtained from the front side of the wafer during etching may be used along with images obtained using IR metrology from the backside of the wafer to create a 3D image of the etch front and substrate before, during, and after etching. This may be used to detect process deviations and etch progress in-situ. In one embodiment, snapshots are taken at regular time intervals, which may be less than 1 minute and as little as 1 ms. These snapshots, when taken at 100 kHz or faster, can be used for real-time process control, with feedback being used to locally and / or globally control or improve one of the control variables, such as electric field, temperature, etchant concentration, magnetic field, irradiation, vapor pressure, etc. Such snapshots can also be used at the end of etching the wafer to reconstruct the 3D geometry of the final etched substrate, which may include non-porous materials, porous materials, and multiple materials (SiGe), etc. Such information can be used for quality control or automatic process control, with feedback provided on a wafer-by-wafer basis.

[0105] In one embodiment, the spatial variation of the etch rate or a surrogate thereof (a unique spectral feature corresponding to the height of a given etch feature) can be monitored in-situ. This can be accomplished, for example, using in-situ spectroscopic metrology of the process substrate. The metrology can be either reflective or transmissive. In one embodiment, IR wavelengths are used when transmissive measurements are required. The metrology can be performed either in real-time (synchronous) or asynchronous with the AE2 process. Depending on whether the metrology is reflective or transmissive, the front and / or back covers can be fabricated using AE2 compatible transparent materials. Crystalline sapphire is one such material, which is available in substrate form. In one embodiment, the thickness of the etchant sheet is maintained such that the majority of the incident radiation passes through the etchant (e.g., 90% transmission, 80%, 70%, 60%, etc.). Figures 15A-15B and 16 show two exemplary systems.

[0106] 15A-15B show an exemplary in-situ metrology system 1500 with full substrate coverage, according to certain embodiments of the present disclosure. Since both the front and back sides of the process substrate 1501 are covered, metrology is available in both transmissive and reflective modes.

[0107] 15A, which shows the front and back of an in-situ metrology system 1500, including focusing optics 1502, an imager 1503, sapphire front and back covers 1504, a light source 1505, an optical filter 1506, a backside fluid inlet 1507, a backside fluid outlet 1508, an etchant inlet 1509, and an etchant outlet 1510. Additionally, FIG. 15A shows a surface of curvature R optics 15 shows that the finite radius 1511 and overlapping fields of view of the optics allow for gap-free measurement and actuation (see element 1512).

[0108] FIG. 15B shows a top view illustrating the scope of the measurement system 1500.

[0109] FIG. 16 illustrates an exemplary in-situ metrology system 1600 with scannable optics, according to an embodiment of the present disclosure.

[0110] As shown in FIG. 16, an in-situ metrology system 1600 includes an imaging device assembly 1601 on an XY stage as well as showing a process wafer 1602 .

[0111] In one embodiment, spatial variation in AE2 etching or a surrogate thereof (a unique spectral feature corresponding to the height of a given etch feature) may be measured ex-situ. The measurements may be either reflective or transmissive. In one embodiment, IR wavelengths are used when transmissive measurements are required. In one embodiment, an ex-situ metrology chamber is placed near the etch chamber to allow for rapid movement of the substrate being processed. In one embodiment, the metrology system itself is not made of AE2 compatible materials, but is housed in a larger AE2 compatible chamber.

[0112] In one embodiment, for thermal actuation, controlled variations in local temperature are used to create corresponding variations in the etch rate of the process substrate. In one embodiment, thermal actuation of the etch rate is used to actively control spatial variations in the etch rate. In one embodiment, thermal actuation is achieved using contact-based strategies such as thermoelectric cooling or non-contact strategies such as heating using DMD-modulated light at visible or IR wavelengths. In one embodiment, the thermal actuators are distributed throughout the area of ​​the process substrate or span a portion of the process substrate, and can be optionally scanned across the process substrate. In one embodiment, thermal actuation is performed from the front side, back side, or both sides of the process substrate. Figures 14 and 17 show two such exemplary systems.

[0113] FIG. 17 illustrates an exemplary system for digital micromirror device (DMD) modulated substrate thermal control, according to an embodiment of the present disclosure.

[0114] As shown in Figure 17, Figure 17 shows focusing optics 1502, imager 1503, sapphire front and backside covers 1504, optical filter 1506, backside fluid inlet 1507, backside fluid outlet 1508, etchant inlet 1509, and etchant outlet 1510. Additionally, Figure 17 shows light source and DMD assembly 1701 along with backside fluid 1702, which can be used to set the temperature across the wafer.

[0115] In one embodiment, an electric field is used to control nanopore dimensions during the AE2 process. In one embodiment, an array of electrodes patterned on the front and back covers is used to generate local electric fields to control local pore parameters in the process substrate. AE2 compatible electrode materials are available. An exemplary system for electric field control is shown in FIG.

[0116] FIG. 18 shows a cross section of an AE2 tool for electric field control according to an embodiment of the present disclosure.

[0117] As shown in FIG. 18, FIG. 18 shows a process wafer 1801, a front side transparent electrode 1802, a back side transparent electrode 1803, and a back side illumination 1804.

[0118] In one embodiment, the variations in pattern density are accommodated. In one embodiment, the variations in pattern density and their possible effects on the etch rate and etch quality are addressed using the various methods described above. In one embodiment, a denser array of process actuators is used in areas with higher pattern density. In another embodiment, a sliding etch zone that can locally change the etchant concentration is used to account for the variations in pattern density.

[0119] In one embodiment, with respect to the substrate edge effect, sudden changes in the fluid meniscus, etchant concentration, electric field, etc., near the edge of the process substrate can lead to large variations in the etching characteristics near that edge. In one embodiment, such variations in the etching characteristics are addressed by carefully designing the substrate edge exclusion zone so that the majority of the etching variations are outside of that exclusion zone. In one embodiment, a front cover seal contacts the outside of the substrate periphery as shown in Figures 19A-19B. In another embodiment, a spin spray type system is used without a periphery seal on the substrate front side.

[0120] 19A-19B illustrate an exemplary edge contact design showing a front side seal contacting the outer edge of a process substrate according to an embodiment of the present disclosure.

[0121] Referring to Figure 19A, Figure 19A shows a wafer chuck 1901, a process wafer 1902, and a front side cover 1903. Figure 19B shows a close-up view of the device area on the process wafer (see element 1904). Figure 19B further shows an edge exclusion zone 1905, a front side seal contact 1906 that contacts the outer edge of the process wafer 1902, and an area of ​​high etch variation 1907. As shown in Figure 19B, the edge exclusion zone 1905 is larger compared to the area of ​​high etch variation 1907 associated with the substrate edge.

[0122] In one embodiment, the backside contact is established using a chuck made of an AE2 compatible material such as fluoropolymer or sapphire. In one embodiment, the chuck has a pin-type contact, a ring-type contact, or a flat surface contact with the substrate backside. In one embodiment, the substrate is held against the backside chuck using clamps attached to the edge of the substrate, using vacuum, or using static electricity. In one embodiment, the space between the process substrate and the backside chuck (if present) is filled with a fluid, which may be an etchant or a common electrolyte. In one embodiment, a backside fluid is used to help control the electric field during the AE2 process. The backside fluid may be either static or circulating. In one embodiment, the frontside etchant flow strategy (described above) is also used for the backside fluid flow. Figures 20 and 21 show exemplary designs for the backside contact.

[0123] FIG. 20 illustrates an exemplary backside contact with a backside fluid according to an embodiment of the present disclosure.

[0124] As shown in Figure 20, Figure 20 shows a process wafer 2001, a wafer chuck (pin type) 2002, chuck pins 2003, and a backside contact fluid 2004. In one embodiment, the backside contact fluid 2004 is used to enable electric field control and global temperature control for the process substrate.

[0125] FIG. 21 illustrates an exemplary backside contact using a vacuum chuck 2101, according to an embodiment of the present disclosure.

[0126] In one embodiment, an electric field is used to modulate the dimensions of the nanopore during the AE2 process. In one embodiment, the substrate comprises a valve metal. In one embodiment, the substrate is part of the anode of an electrochemical cell. In one embodiment, the substrate is connected to the anode using a conductive clamp, a conductive fluid, a conductive wire, and / or a conductive pin.

[0127] In one embodiment, electrodes patterned on the front and back covers are used to create an electric field to control the parameters of the pores in the process substrate. It is noted that patterning of AE2 compatible thin electrode layers on flat substrates is possible. It is further noted that backside illumination can be used to create ohmic contacts to establish a current through the process substrate. An exemplary system for electric field control is shown in FIG.

[0128] In one embodiment, the electrolyte on both sides of the substrate is not the same as the etchant. On the front side of the substrate, the electrolyte is the same as the AE2 etchant. The electrolyte on the back side of the substrate may contain chemicals that provide a highly conductive path between the substrate and the electrode. In one embodiment, the electrode is an anode.

[0129] In one embodiment, the seal between the front side process chamber, the process substrate, and the back side substrate cover is AE2 compatible. In one embodiment, the seal is also CMOS compatible. In one embodiment, the seal is also integrally fabricated in the front side process cover and the back side process cover. A rotating seal (integrally fabricated or otherwise) may be used to seal the rotating assembly.

[0130] In one embodiment, intermittent cleaning of the process chamber with a metal-contaminating cleaning solution such as nitric acid is used to remove metal impurities that may accumulate in the process chamber. In one embodiment, the tool maintenance schedule is divided into frequent intermittent metal cleanings and less frequent maintenance involving complete tool disassembly and cleaning.

[0131] Note that the phase of the etchant can be either gas or liquid. In gas phase AE2, the creation and control of the electric field is achieved using atmospheric pressure plasma.

[0132] In one embodiment, the AE2 tool consists of a spin-spray type system for delivery of etchant to the frontside, a backside vacuum chuck, global (single set point) temperature control of the frontside etchant, localized contact or contactless temperature control of the substrate backside, flow or freeze-based reaction suppression, ex-situ reflection scatterometry, and optional in-situ IR-based transmission scatterometry.

[0133] In another embodiment, the AE2 tool consists of a thick fluid sheet for the front side etchant, a thick fluid sheet for the back side, global (single set point) temperature control of the front side etchant, global (single set point) temperature control of the back side of the substrate, flow based reaction suppression, ex-situ reflectance scatterometry, and diamond-like coating (DLC) based electric field generation. As used herein, "thick fluid sheet" refers to a fluid sheet of a thickness such that the optical transmittance (in the relevant measurement spectrum) of the fluid sheet is 50% or less.

[0134] In another embodiment, the AE2 tool consists of a thick fluid sheet for the front side etchant, a thin fluid sheet on the back side, global (single set point) temperature control of the front side etchant, global (single set point) or local temperature control on the back side of the substrate, flow-based reaction suppression, ex-situ reflection scatterometry, optional in-situ IR-based transmission scatterometry, and diamond-like coating (DLC) based electric field generation. As used herein, a "thin fluid sheet" refers to a fluid sheet of a thickness such that the optical transmittance (in the relevant measurement spectrum) of the fluid sheet is 50% or greater.

[0135] In another embodiment, the AE2 tool consists of a thick fluid sheet for the front side etchant, a backside vacuum chuck, global (single set point) temperature control of the front side etchant, global (single set point) or local temperature control of the backside of the substrate, flow-based reaction suppression, ex-situ reflection scatterometry, and optional in-situ IR-based transmission scatterometry.

[0136] In another embodiment, the AE2 tool consists of a thin fluid sheet for the front side etchant, a thicker fluid sheet on the back side, global (single set point) or local temperature control on the front side, global (single set point) temperature control on the back side of the substrate, flow based reaction suppression, in-situ reflection scatterometry, optional ex-situ reflection scatterometry, and diamond-like coating (DLC) based electric field generation.

[0137] In another embodiment, the AE2 tool consists of a thin fluid sheet for the front side etchant, a thin fluid sheet on the back side, global (single set point) or local temperature control on the front side, global (single set point) or local temperature control on the back side of the substrate, flow-based reaction suppression, in-situ reflection scatterometry, optional in-situ IR-based transmission scatterometry, optional ex-situ reflection scatterometry, and DLC-based electric field generation.

[0138] In another embodiment, the AE2 tool consists of a thin fluid sheet for the front side etchant, a backside vacuum chuck, global (single set point) or local temperature control of the front side, global (single set point) or local temperature control of the backside of the substrate, flow or freeze based reaction suppression, in-situ reflection scatterometry, optional in-situ IR based transmission scatterometry, optional ex-situ reflection scatterometry, and DLC based electric field generation.

[0139] In another embodiment, the AE2 tool consists of a gas phase etchant on the front side, a thick fluid sheet on the back side, global (single set point) or local temperature control on the front side, global (single set point) temperature control on the back side of the substrate, in-situ reflection scatterometry, optional ex-situ reflection scatterometry, optional plasma and DLC based electric field generation.

[0140] In another embodiment, the AE2 tool consists of a gas phase etchant on the front side, a thin fluid sheet on the back side, global (single set point) or local temperature control on the front side, global (single set point) or local temperature control on the back side of the substrate, in-situ reflection scatterometry, optional in-situ IR-based transmission scatterometry, optional ex-situ reflection scatterometry, optional plasma and DLC based electric field generation.

[0141] In another embodiment, the AE2 tool consists of a gas phase etchant on the front side, a vacuum chuck on the back side, global (single set point) or local temperature control on the front side, global (single set point) or local temperature control on the back side of the substrate, in-situ reflection scatterometry, optional in-situ IR-based transmission scatterometry, and optional ex-situ reflection scatterometry.

[0142] In another embodiment, the AE2 tool consists of a variable thickness fluid sheet for the front side etchant. In another embodiment, the AE2 tool consists of a variable thickness fluid sheet for the back side. In one embodiment, the variable thickness fluid sheet design is implemented using deformable front and back cover assemblies, for example using a deformable polymer bellows and / or diaphragm.

[0143] In one embodiment, the tool is used to create high aspect ratio holes in the valve metal, and the valve metal layer with the seed pattern is anodized in a pore forming manner (hard anodization and / or mild anodization). In one embodiment, the parameters of the holes (which may include hole density, hole diameter, hole depth, hole spacing, wall thickness, etc.) are adjusted using one or more actuators. In one embodiment, the parameters of the holes are measured using one or more measurement devices. In one embodiment, the actuators are thermal actuators, electrochemical actuators, flow control devices, and / or concentration control devices. In one embodiment, the measurement devices are spectrometers and / or spectrophotometers. In one embodiment, the measurement devices are reflection-based and / or transmission-based devices.

[0144] The following describes new processes and applications for the atomic precision electrochemical etching (AE2) process previously discussed. In one embodiment, AE2 is used to create any high aspect ratio nanostructure in a variety of substrates including silicon, aluminum oxide, etc. In one embodiment, the substrate material is one or a combination of silicon, silicon-containing materials, silicon oxide, spin-on oxide, silicon carbide, silicon nitride, polycrystalline silicon, amorphous silicon, aluminum oxide, metal, polymer, spin-on polymer, carbon, carbon-containing materials, semi-metal, boron, boron carbide, and boron nitride. In one embodiment, the height of such high aspect ratio nanostructures (multi-layer high aspect ratio nanostructures) is greater than one of 10 μm, 20 μm, 50 μm, 100 μm, 200 μm, and 400 μm. In one embodiment, such high aspect ratio nanostructures (including multi-layer high aspect ratio nanostructures) have feature spacing less than one of 500 nm, 200 nm, 100 nm, 50 nm, 20 nm, 10 nm, and 5 nm. In one embodiment, the final aspect ratio of the multi-layer high aspect ratio nanostructure is greater than one of 10:1, 20:1, 50:1, 100:1, 200:1, 500:1, 1000:1, 2000:1, 5000:1, 10000:1, 50000:1, and 100000:1.

[0145] In one embodiment, AE2 includes methods for creating such nanostructures in silicon (and other substrates) using the CICE process (also known as MACE, MacEtch, and AToMM). AE2 can also be used to create nanostructures in valve metal oxides (valve metals include Al, Mg, Zr, Nb, Sn, Hf, Ta, W, Bi, etc.).

[0146] In one embodiment, the etchant chemistry for creating anodic valve metal oxides (AVOs), of which anodic aluminum oxide (AAO) is a type, includes one or more of sulfuric acid, oxalic acid, selenic acid, tartaric acid, malonic acid, phosphonic acid, phosphoric acid, phosphonoacetic acid, malic acid, and etidronic acid.

[0147] In the following, the fabrication of ultra-high aspect ratio nanowires is discussed.

[0148] In one embodiment, ultra-high aspect ratio nanowires are fabricated. In one embodiment, the nanowires comprise functional materials including boron, boron nitride, boron oxide, lithium, silicon, and the like. An example of such high aspect ratio nanowires is given in Ruhl et al., "A Non-Thermal Laser-Driven Mixed Fuel Nuclear Fusion Reactor Concept," arXiv:2202.03170, 2022, which is incorporated herein by reference in its entirety. Another example of high aspect ratio nanowires, in this case silicon nanowires, is for solid-state battery applications. In one embodiment, the nanowires are less than 500 nm, less than 200 nm, less than 100 nm, less than 50 nm, less than 30 nm, less than 20 nm, or less than 10 nm in diameter. In one embodiment, the nanowires are spaced less than 2 μm, less than 1 μm, less than 800 nm, less than 500 nm, less than 300 nm, less than 200 m, or less than 100 nm apart. In one embodiment, the nanowires have a height of more than 1 μm, more than 2 μm, more than 5 μm, more than 10 μm, more than 20 μm, more than 30 μm, more than 50 μm, more than 70 μm, more than 100 μm, more than 120 μm, more than 150 μm, more than 200 μm, or more than 300 μm. In one embodiment, the nanowires also include an auxiliary material that acts as a sealant (e.g., against chemical damage) for the functional material or that conducts electric charges. Exemplary auxiliary materials include carbon, boron nitride, doped boron nitride, p-type doped boron nitride, polysilicon, doped polysilicon, diamond, doped diamond, boron doped diamond, silicon nitride, silicon carbide, silicon dioxide, polymers, fluoropolymers, titanium nitride, and the like. In one embodiment, the auxiliary material is optional and is treated as part of the functional material.

[0149] In one embodiment, RIE-based etching of the functional material is performed to directly form nanowires, as shown in Figure 22, Figures 23A-C, and Figures 24A-C. Figure 22 is a flowchart of a method 2200 for the formation of nanowires of a functional material, according to an embodiment of the present disclosure. Figures 23A-C show cross-sectional views for the formation of nanowires of a functional material using the steps described in Figure 22, according to an embodiment of the present disclosure. Figures 24A-C show cross-sectional views of the functional material during the process of forming nanowires of the functional material, according to an embodiment of the present disclosure.

[0150] 22 along with Figures 23A-23C and 24A-24C, in step 2201, a functional material 2301 is deposited on a substrate 2302 (e.g., silicon), as shown in Figures 23A-24A. In one embodiment, the functional material 2301 is deposited using chemical vapor deposition.

[0151] In step 2202, a hard mask is deposited on the functional material 2301 and then patterned, such as via descum etching and pattern transfer to the hard mask along with nanoimprint lithography (NIL) or any other patterning technique.

[0152] In step 2203, a plasma or wet etch of the functional material 2301 is performed, as shown in Figures 23B and 24B.

[0153] In step 2204, an optional etch (eg, deep reactive ion etch (DRIE)) of the substrate 2302 is performed, as shown in Figures 23C and 24C.

[0154] In another embodiment, a core-shell approach is utilized, where etching of a silicon nanowire is performed (using MACE or plasma etching) and then the functional material is coated around the silicon core (e.g., using CVD or ALD). As discussed below in connection with Figures 25, 26A-C, and 27A-C, the central core of silicon can either remain embedded in the final functional material nanowire, or alternatively, the core can be selectively etched and subsequently filled with the same or a different functional material.

[0155] Figure 25 is a flowchart of a method 2500 for forming nanowires of a functional material (e.g., boron) according to an embodiment of the present disclosure. Figures 26A-C show various versions of the final structure resulting from utilizing the method of Figure 25 according to an embodiment of the present disclosure. Figures 27A-C show cross-sectional views of the final structures of Figures 26A-C, respectively, according to an embodiment of the present disclosure.

[0156] Referring to FIG. 25, in step 2501, a substrate 2601 is patterned, such as via nanoimprint lithography with optional descum etching.

[0157] In step 2502, etching is performed on the base of the substrate 2601, such as via metal assisted chemical etching (MACE).

[0158] In step 2503 , conformal deposition of a functional material (functional material 1 ) 2602 onto the patterned substrate 2601 is performed, such as via chemical vapor deposition, to form nanostructures 2604 .

[0159] In step 2504, a through etch of the base of substrate 2601 is performed, such as via DRIE.

[0160] In step 2505, optionally, the core of the substrate 2601 is removed, such as by using an etching process that selectively etches the base of the substrate 2601 over the functional material 2602, the etching process being based on KOH, XeF 2 - The etching may be a fluorine based plasma etch, etc., resulting in the final structure shown in FIG. 26A.

[0161] Referring to Figure 26A, the final structure includes a thin layer of base substrate 2601 beneath functional material 2602, with a through etch of the base of substrate 2601 timed to leave a thin layer of base of substrate 2601 beneath functional material 2602. Figure 27A shows a cross-sectional view of the final structure of Figure 26A.

[0162] Figure 26B shows the final structure, which includes a nanostructured core of the base material of substrate 2601 with a coating of functional material 2602. Figure 27B shows a cross-sectional view of the final structure of Figure 26B.

[0163] Referring again to step 2505, in one embodiment, after optionally removing the core, a functional material (functional material 2) 2603 is deposited via CVD, ALD, etc., as shown in Figures 26C and 27C. In one embodiment, the material of the functional material (functional material 2) is the same as the material of the functional material (functional material 1) 2602.

[0164] In one embodiment, the nanowires 2604 of functional material 2601 formed in the resulting structure, as shown in Figures 27A-27C, are electrostatically based nanowires.

[0165] In one embodiment, the functional material nanowires 2604 are formed iteratively, where an (N+1)th layer of nanowires is formed / assembled on an Nth layer of nanowires, where N is a natural number. In one embodiment, N is greater than one of 2, 5, 10, 20, 50, and 100. In one embodiment, the patterning of the substrate material in the (N+1)th layer includes one or more of nanoimprint lithography, photolithography, e-beam lithography, interference lithography, self-aligned nanopatterning techniques, nanosphere lithography, and displacement Talbot lithography. In one embodiment, the etching of the substrate material in the (N+1)th layer includes one or more of MACE, Au MACE, Ru MACE, Pt MACE, gas phase MACE, liquid phase MACE, reactive ion etching, and deep reactive ion etching.

[0166] In one embodiment, high aspect ratio nanowires 2604 in a functional material (e.g., functional material 2602) are formed with lateral support. In one embodiment, the nanopores are filled with a functional material (e.g., functional material 2602) such as boron. In one embodiment, the hard anodization layer is selectively removed, leaving boron nanowires 2604 supported by a lateral continuous layer of aluminum oxide. In one embodiment, the hard anodization layer is selectively removed, leaving boron nanowires 2604 supported by lateral tethers of aluminum oxide.

[0167] Reference is now made to FIG. 28, which is a flowchart of a method 2800 for forming nanowires of a functional material, according to one embodiment of the present disclosure.

[0168] In step 2801, a base substrate is optionally coated with an adhesion promoter (e.g., titanium), followed by a highly conductive electrode material (e.g., gold), and optionally followed by a suitable valve metal (e.g., a metal other than aluminum, such as tungsten).

[0169] In step 2802, aluminum is deposited on top of the structure of step 2801, such as by CVD, ALD, e-beam deposition, electrodeposition, chemical deposition, etc., and / or via bonding of an aluminum substrate (e.g., aluminum foil) to a starting substrate via covalent bonding, anodic bonding, eutectic bonding, etc.

[0170] In step 2803, electropolishing of the aluminum surface is optionally performed, such as using a perchloric acid solution, to improve the surface roughness for the anodization step.

[0171] In step 2804, pattern (eg, using nanoimprint lithography) and optionally perform a descum etch and pattern transfer to the aluminum using an aluminum etch.

[0172] In step 2805, deep pores are created using aluminum anodization, such as by optionally using a highly conductive electrode. In one embodiment, the anodization is a single-stage anodization. In another embodiment, the anodization is a two-stage anodization, where a first anodization creates incomplete pores that are removed using a suitable etchant such as phosphoric acid, followed by a second anodization that utilizes the well-placed scallops created after the first anodization to create well-structured deep pores. Anodization can also be performed in pulses to create hard and mild anodized areas.

[0173] In step 2806, a through etch of the base material is performed, such as via DRIE.

[0174] In step 2807, the titanium and gold and any remaining aluminum and AAO barrier layers from the bottom are removed, such as by using dilute phosphoric acid.

[0175] In step 2808, optionally, the holes in the AAO layer are isotropically enlarged using a suitable dilute etchant (e.g., dilute phosphoric acid). Alternatively and optionally, the holes in the AAO layer are shrunk using a suitable conformal coating of a sacrificial material (e.g., aluminum oxide, silicon dioxide, carbon, etc.) using CVD, ALD, etc.

[0176] When a pulsed anodization technique is used, in one embodiment, the hard anodized AAO is removed using a suitable etchant (e.g., phosphoric acid, HF, fluorine-containing plasma, etc.), followed by deposition of a lateral tether material (e.g., carbon, silicon dioxide, etc.) using a conformal deposition method (e.g., CVD, ALD, etc.) to the extent that the lateral pores are sealed, followed by deposition of a functional material into the nanopores using CVD, ALD, etc., and then optionally reducing the size of the nanostructures and / or the size of the tethers using a suitable etching technique (e.g., atomic layer etching, selective atomic layer etching, plasma etching, etc.).

[0177] When pulsed anodization techniques are used, in another embodiment, the hard anodized AAO is removed using a suitable etchant (e.g., phosphoric acid, HF, fluorine-containing plasma, etc.) leaving continuous lateral tethers of mildly anodized aluminum oxide, followed optionally by reducing the nanostructure size and / or tether size using a suitable etching technique (e.g., atomic layer etching, selective atomic layer etching, plasma etching, etc.).

[0178] If pulsed anodization techniques are not used, in one embodiment, the functional material is deposited into the nanopores using CVD, ALD, etc., and then all aluminum oxide is removed using a suitable etchant (e.g., phosphoric acid) while performing a suitable collapse mitigation technique. Once the aluminum oxide is completely removed, collapse mitigation is performed continuously until the functional material fulfills its intended function. Alternatively, the nanostructure of the functional material is allowed to collapse and restored when necessary using a suitable collapse prevention method (e.g., nanowire charging method).

[0179] Figure 29A shows the final structure using the method of Figure 28 when no pulse anodization technique is utilized, according to an embodiment of the present disclosure. As shown in Figure 29A, Figure 29A highlights the region of interest 2901, as well as showing the remaining aluminum oxide 2902 on the outer edge of the region of interest 2901.

[0180] Figure 29B shows the final structure using the method of Figure 28 when a pulse anodization technique is utilized, according to an embodiment of the present disclosure. As shown in Figure 29B, lateral tethers 2903 are utilized.

[0181] Below, we discuss the management of the collapse of ultra-high aspect ratio nanostructures.

[0182] High aspect ratio nanostructures generally require collapse management methods to ensure that the nanostructures remain freestanding during operation during nanostructure fabrication. Possible collapse modes may include lateral collapse (nanostructures collapse due to adhesion forces between adjacent nanostructures) or downward collapse (nanostructures collapse due to adhesion forces between the nanostructure and the base of the nanostructure). In one embodiment, collapse management (which may include collapse prevention and recovery of collapsed nanostructures) is performed on dry nanostructures (e.g., during dry processing using techniques such as plasma etching, vapor-phase MACE, vapor-liquid-solid growth, etc.). In one embodiment, collapse management (which may include collapse prevention and recovery of collapsed nanostructures) is performed on wet nanostructures (e.g., during wet processing of the nanostructures). In one embodiment, collapse management (which may include collapse prevention and recovery of collapsed nanostructures) is performed in high vacuum (100 milliPascal or less). In one embodiment, the collapse management (which may include collapse prevention as well as recovery of collapsed nanostructures) is performed at low vacuum (100 milliPascal or higher). In one embodiment, the collapse management (which may include collapse prevention as well as recovery of collapsed nanostructures) is performed at atmospheric pressure. In one embodiment, the nanostructures comprise nanowires.

[0183] In one embodiment, nanostructure collapse is mitigated by coating the surface of the nanostructure with a low surface energy coating to reduce adhesion forces (in the case of lateral and downward collapse). Exemplary low surface energy coatings (e.g., surface tension less than 20 mN / m, or less than 15 mN / m, or less than 10 mN / m) include fluoropolymers (C x F y H z , x, y ∈ [1, inf) and z ∈ [0, inf)).

[0184] In one embodiment, nanostructure collapse is mitigated by charging the nanostructure with a charge of the same polarity. In one embodiment, charging is performed using a separate device that connects to the nanostructure, or alternatively, using a suitable integrated device (e.g., a capacitor, an integrated capacitor, an integrated metal-insulator-metal (MIM) capacitor, a battery, or an integrated battery). In one embodiment, charging is performed while fabrication of the nanowire is being performed, and optionally also during use of the nanostructure. In one embodiment, non-conductive nanostructures are coated with a thin conductive coating to improve charge redistribution between nanostructures. Exemplary illustrations for collapse prevention and / or recovery of collapsed nanostructures are discussed below with respect to Figures 30A-B.

[0185] 30A-30B show diagrams for preventing collapse and / or restoring collapsed nanostructures according to certain embodiments of the present disclosure.

[0186] As shown in Figure 30A, Figure 30A shows an optional integrated capacitor 3001 in the AAO. In one embodiment, other optional charge sources include integrated batteries, solid state batteries, and the like.

[0187] Additionally, Figure 30A shows one electrode 3002 of an integrated capacitor 3001 or other integrated charge source. In one embodiment, the electrode 3002 is connected to a functional material nanostructure 3003 and, optionally, to a thin conductive layer that covers the nanostructure 3003. Additionally, Figure 30A shows a functional material 3004 with nanostructures 3003 that have been protected from collapse or, optionally, may have collapsed and need to be restored.

[0188] In one embodiment, the other electrode 3005 of the integrated capacitor 3001 or other integrated charge source is connected to either ground or to a conductive mesh 3009 and / or to a conductive transparent continuous layer.

[0189] In one embodiment, if an external high voltage source 3006 is utilized, the cable or connection connecting the source 3006 to the nanostructured sample 3007 may optionally be removed once the functional material 3004 has served its intended purpose. A new sample may come with a dedicated disposable connector that repeatedly connects to the imaging power source.

[0190] In one embodiment, the external high voltage power supply / high voltage source 3006 may correspond to a capacitor, a supercapacitor, a battery, etc. In one embodiment, one end of the power supply 3006 is connected to the functional material nanostructures 3003 and, optionally, to a thin conductive layer coating the nanostructures 3003.

[0191] In one embodiment, the other end of the power supply 3006 is connected to either ground 3008 or a conductive mesh 3009 and / or to a conductive transparent continuous layer.

[0192] Additionally, Figure 30A shows an optional conductive mesh 3009. In one embodiment, the size of the pores in the mesh 3009 is equal to or smaller than the size of the region of operational interest 3010.

[0193] In one embodiment, the remaining AAO thickness is large enough to prevent electrical breakdown due to the potentially large voltage difference between the top and bottom of the residue layer (see element 3011).

[0194] FIG. 30A also shows a material that is transparent to UV light and electrically conductive (e.g., SrNbO 3 ), an optional thin continuous layer 3012 is shown.

[0195] FIG. 30B shows a cross section of the bottom of nanostructure 3003. As shown in FIG. 30B, in one embodiment, the nanostructure has a material of boron. In one embodiment, a thin conductive layer 3013 (e.g., TiN, doped polysilicon, doped diamond) surrounds nanostructure 3003. In one embodiment, thin conductive layer 3013 and nanostructure 3003 are surrounded by an encapsulation layer 3014 (e.g., SiO 2, carbon, BN). In one embodiment, the sealing layer 3014 corresponds to a low surface energy coating.

[0196] Figure 31 is a flow chart of a method 3100 for forming nanowires of boron (or any other functional material) according to an embodiment of the present disclosure. Figures 32A-32D show cross-sectional views for forming nanowires of boron (or any other functional material) using the steps described in Figure 31 according to an embodiment of the present disclosure.

[0197] 31 in conjunction with Figures 32A-32D, as shown in Figure 32A, boron 3203 is deposited on silicon core 3202 and silicon base 3201. Figure 32B shows a cross section of the deposited boron 3203.

[0198] In step 3102, silicon base 3201 is opened, such as via DRIE, as shown in FIG. 32C (the opened spaces correspond to elements 3204).

[0199] In step 3103, XeF is added to form an open channel 3205, as shown in FIG. 2 Selective etching of the silicon core 3202 is performed, such as by using XeF. Additionally, FIG. 32C shows the targeted laser irradiation area 3206. In one embodiment, such selective etching is performed by using XeF 2 Etching, Fluoropolymer-based Etching (CF 4 , CHF 3 ), gas phase HF, HF, plasma etching, wet etching, vapor phase etching, crystalline etching, KOH etching, DRIE, and RIE.

[0200] In step 3104, boron 3207 is deposited, such as via CVD, into the open channel 3205, as shown in Figures 32C-32D. Further, in one embodiment, boron 3207 is deposited into the open space 3204, as shown in Figures 32C-32D. As a result of such deposition, nanowire 3208 is formed. Further, in one embodiment, nanowire 3208 with boron 3207 is optionally cut off. Additionally, in one embodiment, optional nanowire charging device 3209 is utilized to induce charge on nanowire 3208.

[0201] In one embodiment, the charge induced on the nanostructures (e.g., nanowire 3208) is such that the force resulting from electrostatic repulsion between the nanostructures is sufficient to overcome the adhesive forces tending to collapse the nanostructures or the adhesive forces already holding the collapsed nanostructures together.

[0202] In one embodiment, the induction of charge to the nanostructure (e.g., nanowire 3208) for the purpose of collapse management is performed using an electron beam entering the nanostructure (e.g., nanowire 3208). In another embodiment, an intense light beam (e.g., a more intense laser) is used to strip electrons from the nanostructure. This removal of electrons can be temporary, such that on the timescale it takes for the electrons to flow back and rebalance the charge, the temporarily upright nanostructure fulfills its functional goal. The nanostructure may itself be insulating, or alternatively, may be placed against an insulating holder to hold the charge being transferred (via the methods mentioned previously).

[0203] Optionally, fluorine-based plasma removal of the lateral support may be performed while maintaining electrostatic repulsion between the nanowires.

[0204] If a core-shell approach is utilized (see Figures 26A-C, 27A-C), the central core can be charged to prevent the nanowire from collapsing if it is to be retained in the final functional material nanowire.

[0205] To reduce / remove remaining strain in the nanostructures, an annealing step can be utilized after deposition of the functional material (core-shell approach of Figures 26A-C, 27A-C or AAO-based approach of Figures 28 and 29A-B).

[0206] Applications of the AE2 process are discussed below.

[0207] In one embodiment, the AAO nanopore arrays are utilized to fabricate arrays of charge storage devices, with applications in the fabrication of DRAM, 3D NAND flash, supercapacitors, and batteries.

[0208] Metal-assisted chemical etching (MACE) reliably etches only single crystal silicon, limiting its use to a few front-end semiconductor device layers. The principles of the present disclosure extend the capabilities of MACE to polysilicon, which, when combined with additional process steps, offers the potential to create anodes for dense and flexible batteries. Polysilicon MACE also has potential applications in patterns for metal vias and deep trench capacitors used in semiconductor logic and memory devices, when used with compatible polysilicon deposition methods and adapted CMOS-compatible MACE.

[0209] The principles of this disclosure present MACE wet etching of polysilicon that produces arrays of structures with sub-50 nm resolution and anisotropic properties. Three demonstrated structures are pillars with 6:1 aspect ratio and 50 nm spacing for comparison with the MACE literature, pillars with 30 nm spacing to establish the resolution limits of polysilicon etching, and a diamond pillar array with the potential to fabricate holes spaced only 15 nm apart.

[0210] Metal-assisted chemical etching (MACE) is a wet etching technique that is uniquely suited to etch high-quality, high-resolution (<100 nm, <50 nm, <20 nm), high-aspect ratio (H3) nanostructures in single-crystal silicon. However, for some high-volume, cost-sensitive applications, such as optics for AR / VR, new batteries and capacitors, single-crystal silicon is not the substrate of choice. These applications require parallel processing of many unit products on large substrates to lower the average cost per product. For such applications, roll-to-roll processing is ideally suited. However, single-crystal silicon does not grow easily on rolled substrates. In this context, the ability to perform high-quality MACE on polysilicon (poly-MACE) can be crucial, since roll-to-roll deposition of polysilicon can be routinely performed.

[0211] Besides MACE on roll substrates, poly-MACE may have the potential to realize H3 nanostructures on non-silicon substrates such as glass (especially display-grade glass with applications in the AR / VR field). Poly-MACE may also be used to fabricate polysilicon-based nanostructures on top of existing semiconductor devices, which may have applications in the emerging fields of heterogeneous integration (HI) and advanced packaging.

[0212] MACE for polysilicon is currently in its infancy. The poor quality of polysilicon MACE has been attributed to the presence of grain boundaries in polysilicon, which may increase the tendency of the catalyst to wander uncontrollably during etching. The approach proposed by Kim et al., "Self-Anchored Catalyst Interface Enables Ordered Via Array Formation from Submicrometer to Millimeter Scale for Polycrystalline and Single-Crystalline Silicon," ACS Applied Materials and Interfaces, Vol. 10, No. 10, 2018, pp. 9116-9122, can produce polysilicon vias (with 1 micrometer spacing) down to approximately 400 nm in diameter. However, there appears to be a large amount of tapering in the 400 nm diameter vias, and the method seems unlikely to be successfully extended to high aspect ratio nanostructures below 100 nm.

[0213] The principles of the present disclosure enable high quality, high resolution (sub-100 nm, sub-50 nm, sub-20 nm), high aspect ratio MACE of polysilicon, which is enabled by three process steps: (1) planarization of the deposited polysilicon to a level that enables high resolution patterning, (2) high resolution patterning using nanoimprint lithography (NIL), and (3) high aspect ratio etching of the NIL pattern in polysilicon using the MACE process. The combination of the above three process steps is referred to herein as "poly-MACE."

[0214] In one embodiment, polished <100> One micrometer thick undoped polysilicon deposited on a single single crystal silicon p-type wafer was utilized to demonstrate poly-MACE. The polysilicon was deposited using low pressure chemical vapor deposition (LPCVD) at 620°C, followed by chemical mechanical polishing (CMP) of the film. For comparison purposes, <100> A single crystal MACE sample was also fabricated using a single p-type silicon wafer, and MACE was performed using previously reported techniques utilizing gold as the MACE catalyst. All experiments followed the same general process flow as discussed below with respect to FIG. 33 and FIGS. 34A-34D. FIG. 33 is a flowchart of a method 3300 for fabricating silicon and polysilicon structures using MACE and metal interruption techniques according to an embodiment of the present disclosure. FIGS. 34A-34D show cross-sectional views for fabricating silicon and polysilicon structures using MACE and metal interruption techniques using the steps described in FIG. 33 according to an embodiment of the present disclosure.

[0215] Referring to FIG. 33 along with FIGS. 34A-34D, in step 3301, a nanoimprint resist 3401 is deposited on silicon 3402 (eg, single crystal silicon, polysilicon film on silicon) as shown in FIG. 34A.

[0216] In step 3302, an etch of the residual layer is performed to remove portions of the nanoimprint resist 3401, as shown in Figure 34B.

[0217] In step 3303, metal is deposited on nanoimprint resist 3401. In one embodiment, titanium 3403 is deposited on nanoimprint resist 3401 followed by gold catalyst 3404, as shown in Figure 34C.

[0218] In step 3304, MACE is performed to form silicon and polysilicon structures 3405, as shown in Figure 34D.

[0219] In one embodiment, the wafer is patterned using jet and flash imprint lithography (J-FIL), which is a form of nanoimprint lithography (NIL). In one embodiment, an Imprio-1100 wafer-scale J-FIL tool is utilized for this purpose. In one embodiment, the NIL template is fabricated by Dai Nippon Printing (DNP), a commercial photomask vendor in Japan. In one embodiment, J-FIL is based on a RIE process, producing a residue layer that is removed using oxygen and argon.

[0220] In one embodiment, thin films of titanium 3403 and gold 3404 are deposited using a vacuum-based electron beam evaporator (CHA Industries, Inc). Gold acts as a catalyst for the MACE process. Titanium acts as an adhesion promoter to prevent gold peeling at the beginning of the etch. In one embodiment, titanium 3403 is between 0.5 nm and 2 nm thick, and gold 3404 is between 10 nm and 15 nm thick. In one embodiment, titanium deposition is at a rate of 0.1 Å / s and gold deposition is at a rate of 0.4 Å / s, both approximately 5*10 -6 This is done at a pressure of 1000 torr.

[0221] In one embodiment, the MACE etchant is a mixture of hydrofluoric acid (HF), hydrogen peroxide (H 2 O 2 ), and deionized (DI) water.

[0222] In one embodiment, both single crystal silicon and polysilicon MACEs are prepared using 4HF:1H 2 SO 4 at room temperature on an acid bench located in a class 100 clean room. 2 O 2 :4H 2 0 (by volume) of etchant composition.

[0223] Cross-sectional SEM characterization was performed using a Zeiss Neon 40 scanning electron microscope (SEM), and top-down SEM using a Scios 2HiVac dual beam SEM system. Sample separation of the polysilicon samples included the deposition of 2 nm of gold-palladium alloy using an Emitech Sputter Coater K575X-SEM to improve image fidelity.

[0224] The results of implementing the method of FIG. 33 are discussed below.

[0225] 35A is a SEM (scanning electron microscope) image of a cross section of a polysilicon pillar (e.g., structure 3405) according to an embodiment of the present disclosure (scale bar is 200 nm). FIG 35B is a SEM image of a tilted cross section of a polysilicon pillar (e.g., structure 3405) according to an embodiment of the present disclosure (scale bar is 1 micrometer).

[0226] 35A-35B show 6:1 aspect ratio pillars as created in polysilicon using a process-of-record (PoR) for single crystal silicon modified for polysilicon using NIL-based patterning.

[0227] Reference is now made to Figure 36, which is a flow chart of a method for making a reverse-toned imprint template, according to an embodiment of the present disclosure. Figures 37A-37C show cross-sectional views for making a reverse-toned imprint template using the steps described in Figure 36, according to an embodiment of the present disclosure.

[0228] Referring to FIG. 36 in conjunction with FIGS. 37A-37C, in step 3601, a nano-imprint resist 3701 is deposited on a glass wafer 3702, as shown in FIG. 37A.

[0229] In step 3602, gold 3703 is deposited onto nanoimprint resist 3701 to create an inverse tone template 3704, as shown in Figure 37B. In one embodiment, such deposition is performed via sputtering.

[0230] In step 3603, the inverse tone template 3704 is utilized to create an imprint template 3705 of the inverse tone template 3704 on a substrate 3706 (e.g., single crystal silicon, polysilicon film on silicon) using imprint lithography, as shown in Figure 37C. Polysilicon pillars 3707 are formed, as further shown in Figure 37.

[0231] In one embodiment, the fabrication of 30 nm spaced polysilicon pillars (e.g., polysilicon pillars 3707) utilized a modified imprint step (creating an inverse-tone template 3704) in which the diameter of the pillar resist cap was increased from an initial value of 150 nm to 170 nm. This modification may result in surface defects in the patterned catalyst layer, which results in vertical stripes after MACE as shown in FIG. 38A. This occurred in single crystal silicon as shown in FIG. 38B. Thus, such stripes are an artifact of the modified imprint process and not the polysilicon MACE process. FIG. 38A is an SEM image of a cross section of approximately 170 nm spaced polysilicon pillars (e.g., polysilicon pillars 3707) in accordance with an embodiment of the present disclosure (scale bar of 200 nm). FIG. 38B is an SEM image of a cross section of polysilicon pillars (eg, polysilicon pillars 3707) spaced approximately 30 nm apart after removal of the resist cap according to an embodiment of the present disclosure (scale bar 200 nm).

[0232] The following discusses diamond shaped polysilicon pillars.

[0233] To investigate the resolution limits of polysilicon MACE and to further compare MACE etch quality between polysilicon and silicon, pillars with diamond-shaped cross-sections were fabricated using the method of FIG. 36. It is worth noting that etching diamond-shaped pillars also results in the creation of complementary circular holes (connected using tethers). Thus, being able to etch diamond-shaped pillars has important implications for etching high aspect ratio vias and holes, e.g., for DRAM structures. In general, it is difficult to etch isolated holes using MACE because the isolated catalyst islands are subject to drift. In addition, etchant transport becomes increasingly problematic as the etch depth increases. High aspect ratio holes in single crystal silicon have already been achieved with MACE. However, these are dimensionally constrained. Holes in polysilicon have also already been etched with MACE. However, these exhibit common etch defects such as tapered features and rough sidewalls.

[0234] FIG 39A shows a cross-sectional SEM image of a polysilicon diamond-shaped pillar fabricated using the steps of FIG 36 according to an embodiment of the present disclosure (scale bar 400 nm). FIG 39B shows a top-down SEM image of a polysilicon diamond-shaped pillar fabricated using MACE using the steps of FIG 36 according to an embodiment of the present disclosure (scale bar 500 nm). FIG 39C shows a top-down SEM image of a polysilicon diamond-shaped pillar fabricated using MACE using the steps of FIG 36 according to an embodiment of the present disclosure (scale bar 100 nm).

[0235] In one embodiment, CMP of polysilicon was incorporated to minimize the surface roughness of the deposited film to enable patterning using NIL. Polysilicon films as deposited often have a high surface roughness, up to 580 Å for an 11 μm thick film, which appears to adversely affect the morphology of the NIL resist cap after etching of the residue layer. Defects in the resist cap morphology lead to defects in the catalyst layer, which ultimately lead to vertical sidewall stripes after MACE. CMP can greatly reduce the extent of these defects, but still leaves some amount of sidewall stripes. This effect of CMP on polysilicon etching, where CMP reduces but does not completely remove sidewall stripes, is also seen in reactive ion etching.

[0236] In one embodiment, the principles of the present disclosure utilize commercial grade NIL, which allows for the creation of patterns with long-range order, as well as good development uniformity in the resulting nanostructures.

[0237] In one embodiment, a longer etch was performed to examine the MACE at the polysilicon-silicon interface and to further investigate the poly-MACE. The 150 nm spacing pillars did not maintain structural integrity and were broken off at the interface of the visible materials. However, the 150 nm wide fins were successfully etched. SEM characterization of the resulting polysilicon-silicon stack showed tapered polysilicon profiles, as shown in FIG. 40.

[0238] 40 is a cross-sectional SEM of a fin 4001 etched beyond the polysilicon film interface according to an embodiment of the present disclosure (scale bar of 800 nm). In one embodiment, such a fin 4001 has dimensions of 150 nm (width) by 450 nm (height).

[0239] The tapering does not result from the MACE etch itself, but rather from intrinsic residual stress near the material interface. It is known that the intrinsic stress of polycrystalline thin films is highly dependent on the film deposition conditions. In some cases, the amount of tapering near the interface can be reduced by performing the LPCVD deposition of polysilicon at a higher temperature or by a post-deposition high temperature anneal. For example, a 1100°C anneal has been shown to lower the intrinsic stress of polysilicon films from an intrinsic compressive stress of 350 Mpa to near zero. Note that the LPCVD polysilicon films were deposited at a relatively low temperature of 620°C and were not annealed after deposition.

[0240] Thus, the principles of the present disclosure enable reliable etching of high aspect ratio structures in polysilicon that are unmarred by grain boundaries and do not exhibit spurious porosity (which is achieved through careful tuning of the etch chemistry). Etching is made possible by three techniques: (1) reducing the surface roughness in the as-deposited polysilicon to a level that allows high-resolution patterning, (2) high-resolution patterning using nanoimprint lithography (NIL), and (3) high-aspect ratio etching of NIL patterns in polysilicon using the MACE process.

[0241] In an embodiment, combining the principles of the present disclosure with the high-resolution patterning capabilities of NIL on roll substrates and plasma-based substrate planarization techniques may potentially open new avenues for deploying MACEs in roll-to-roll formats for a variety of high-volume industrial applications requiring high-quality, high-resolution, high-aspect ratio nanostructures, ranging from optical elements for AR / VR to new batteries and capacitors, etc. It is noted that nanoimprint lithography (NIL) may be the only viable, cost-effective method for patterning arbitrary shapes with feature sizes below 50 nm on roll substrates. Comparable optical techniques such as photolithography (including EUV) and interference lithography require high substrate site flatness (λ / NA) for high-resolution imaging on substrates. 2 (approximately 150 nm for 0.33 NA EUV) and the limited field size make large area, high speed patterning impractical. Such high levels of substrate site flatness are not possible on rolled substrates.

[0242] High aspect ratio polysilicon structures are prone to profile defects such as tapering. Such defects are likely to arise from internal residual stresses in the polysilicon during deposition. Normally, high temperature processing removes these internal residual stresses. However, this may not be an option in various applications that are limited to low temperature processing due to the type of roll substrate (e.g., polymer roll substrate) utilized. Thus, stresses can be mitigated using polysilicon deposited at lower temperatures (below 400°C, below 200°C, or below 150°C, or below 100°C). Exemplary options include wire chemical vapor deposition, PECVD (plasma enhanced CVD), and the like. In some cases, deposition of amorphous silicon may be required, and the MACE process can be tailored for etching of amorphous silicon.

[0243] In one embodiment, the principles of the present disclosure may be applied to polycrystalline silicon films deposited on metal films, wafer-scale substrates, or flexible roll-to-roll substrates. In one embodiment, the principles of the present disclosure are applied to polycrystalline silicon films deposited on copper films, single crystal wafer substrates, and polycarbonate roll-to-roll substrates. In one embodiment, the polycrystalline silicon films are planarized by chemical mechanical polishing (CMP) or Inkjet-enabled Adaptive Planarization (IAP) to remove film surface roughness greater than 5 nm RMS. Planarization is followed by deposition of a metal catalyst film and / or imprint lithography.

[0244] In one embodiment, the patterning of the metal catalyst is performed in one of two ways: etching the metal catalyst film or a "metal break" technique. Both means of catalyst patterning result in localized areas where the metal catalyst is in direct contact with the polysilicon film. In one embodiment, MACE of the polysilicon is performed where the metal catalyst is in contact with the material. One means is through patterning of the metal catalyst film that is present underneath the imprint resist. The catalyst film is deposited on the polysilicon film, followed by imprint lithography, followed by etching of the residue layer. Etching of the residue layer exposes areas of the metal catalyst film that are etched with dilute cerium ammonium nitrate or potassium iodide. The remaining imprint resist is removed with a piranha solution, a mixture of sulfuric acid and hydrogen peroxide. Removal of the resist exposes the patterned metal catalyst, which is in contact with the polysilicon film. Another means of metal catalyst patterning is "metal break" where catalyst deposition is performed after lithography and the shape of the metal catalyst matches the imprint resist. After etching the residue layer to create the imprint resist cap, the catalyst metal is deposited through e-beam evaporation. There is a break in the deposited metal catalyst layer that occurs at the location of the exposed polycrystalline silicon and the imprint resist cap, which allows the transport of the etchant to the desired etching location. In an embodiment, the lithography technique mentioned above can be roll-to-roll imprint lithography. In an embodiment, resist coating for the lithography process is performed using one or more of the following methods: inkjet, slot die coating, knife edge coating, etc. In an embodiment, evaporation of optional solvent in the resist is performed to reduce the thickness of the coated resist film. As shown in FIG. 41 and FIG. 42, the variation in thickness of the residue layer due to non-uniform evaporation (after evaporation of the solvent) can be mitigated by monitoring the temperature distribution of the coated layer (e.g., using a thermal imaging camera) and utilizing inverse modeling and thermal actuation methods to compensate for the non-uniform evaporation. FIG. 41 illustrates mitigating disturbances in the residue layer according to an embodiment of the present disclosure.FIG. 42 illustrates an in-situ monitoring and control process according to an embodiment of the present disclosure.

[0245] In one embodiment, the metal catalyst is one or more (mixtures) of gold, platinum, palladium, ruthenium, carbon, chromium, silver, titanium, and the like. In one embodiment, the etchant used to produce anisotropic etching of polycrystalline silicon consists of hydrofluoric acid, hydrogen peroxide, and deionized water. In one embodiment, the composition of the etchant is a 4:1:4 volume ratio of HF to hydrogen peroxide to water. In one embodiment, the above composition may be diluted using water. In one embodiment, this is done to improve control over etching parameters such as etch rate, porosity, and the like. In one embodiment, the composition of the etchant is a 4:1:20 volume ratio of HF to hydrogen peroxide to water.

[0246] As previously discussed, in connection with FIGS. 3A-3F, in one embodiment, high aspect ratio holes are created in valve metal 302. In one embodiment, a seed pattern is first created on the surface of valve metal 302. In one embodiment, the seed pattern is created using a combination of nanoimprint lithography and etching (which can be wet or dry etching). The valve metal 302 is then anodized in a pore-forming manner, and the time of etching determines the depth of the hole. In one embodiment, the hole is tapered. In one embodiment, the taper is continuous. In another embodiment, the taper is stepwise. In one embodiment, the taper is monotonic. In one embodiment, valve metal 302 is aluminum. In one embodiment, a functional material (e.g., functional material 306) is deposited into the high aspect ratio holes after anodization. In one embodiment, the deposition is performed using CVD, PECVD, LPCVD, APCVD, ALD, PVD, electrochemical deposition, or the like.

[0247] It is noted that the tapering is produced by gradually changing the etching conditions (electric field, current, temperature, etchant concentration, etc.) as the etch progresses. It is also noted that the optional functional material for deposition in the high aspect ratio holes can be silicon, polysilicon, silicon nitride, silicon carbide, carbon, diamond, boron nitride, III-V (GaAs, GaN, etc.), metals, metal oxides, lithium, etc., or combinations thereof or materials of which these materials are part.

[0248] In one embodiment, the lithography technique utilized to create the above seed pattern is roll-to-roll imprint lithography. In one embodiment, resist coating for the lithography process is performed using one or more of inkjet, slot die coating, knife edge coating, etc. In one embodiment, optional solvent evaporation in the resist is performed to reduce the thickness of the coated resist film. As discussed in FIG. 41 and FIG. 42, the thickness variation of the residue layer (after the evaporation of the solvent) due to non-uniform evaporation can be mitigated by monitoring the temperature distribution of the coated layer (e.g., using a thermal imaging camera) and utilizing inverse modeling and thermal actuation methods to compensate for the non-uniform evaporation.

[0249] Reference is now made to FIG. 43A, which illustrates an exemplary AE2 process, according to an embodiment of the present disclosure.

[0250] As shown in FIG. 43A, the AE2 process involves the removal of the front side overcoat (see element 4301).

[0251] The AE2 process further includes a triple layer (or optionally double layer) roll of an optional front side protective film, a valve metal film (e.g., aluminum), and a back side protective film (e.g., polycarbonate) (see element 4302). In one embodiment, the thickness of the valve metal film is less than 1 mm, less than 100 μm, less than 50 μm, less than 20 μm, or less than 10 μm. In one embodiment, the thickness of the back side protective film is less than 1 mm, less than 100 μm, less than 50 μm, less than 20 μm, or less than 10 μm. In one embodiment, the back side protective film provides mechanical stability to the valve metal film during the R2R NIL step.

[0252] Additionally, the AE2 process includes the removal of the backside passivation film prior to deposition of the functional material (see element 4303).

[0253] In addition, the AE2 process includes R2R AE2 with gradual and / or stepwise taper in the nanostructures to enable subsequent high aspect ratio deposition steps (see element 4304).

[0254] Additionally, the AE2 process includes R2R deposition of a functional material (e.g., polysilicon, metal, gold, ruthenium, silicon oxide, silicon nitride, silicon carbide, polymer, carbon, diamond, and boron nitride) (see element 4305). An optional encapsulant (e.g., polysilicon, metal, gold, ruthenium, silicon oxide, silicon nitride, silicon carbide, polymer, carbon, diamond, boron nitride, and generally a material resistant to valve metal etchants) may be deposited prior to deposition of the functional material.

[0255] In addition, the AE2 process includes the optional transfer of functional material to the perforated carrier (see element 4306). In one embodiment, the carrier material is copper, polycarbonate, or other polymer, optionally with a coating of nickel, copper, polysilicon, or other substrate suitable for nanowire growth. In one embodiment, the carrier material is resistant to valve metal wet etchants. In one embodiment, the transfer and attachment of functional material to the perforated carrier (shown in FIG. 43B) is performed using one or more of the following techniques: direct bonding, covalent bonding, anodic bonding, and bonding between two surfaces with high density nanowires / nanoforests. For the last part, nanowires / nanoforests need to be grown on the back side of the functional material and on the front side of the perforated carrier.

[0256] Reference is now made to FIG. 43B, which illustrates a perforated carrier 4307 according to an embodiment of the present disclosure.

[0257] As shown in FIG. 43B, the holey carrier 4307 includes a holey carrier membrane 4308, a nanowire / nanoforest interface 4309, and a nanostructured functional material 4310.

[0258] Returning to Figure 43A, the AE process further includes a wet / dry etchant (e.g., KOH) for the valve metal and valve metal oxide (see element 4311). In one embodiment, such a process step is used to remove the valve metal oxide scaffold and any residual valve metal after attachment to an optional carrier material.

[0259] Figure 43A additionally shows a side view of the roller showing the valve metal membrane etched away near the center (see element 4312). In one embodiment, the portions near the edges provide mechanical connection and structural stability to the previously unetched membrane.

[0260] With regard to mitigating collapse in nanostructures, in one embodiment, the nanostructures are comprised of nanopillars. In one embodiment, one or more of the nanostructures have undergone collapse. In one embodiment, one or more of the nanostructures are in a vacuum environment. In one embodiment, an electron beam entering the front, side, or back of the nanostructure is used to induce charge in the nanostructure. The nanostructure will recover when the amount of negative charge on the nanostructure is such that the electrostatic repulsion between like charges exceeds the adhesive forces that keep the nanostructure in the collapsed state. In another embodiment, a laser beam (entering from the front, side, or back) is utilized to strip electrons from the nanostructure so that the nanostructure contains an overall positive charge. In this case, the nanostructure will recover when the amount of positive charge on the nanostructure is such that the electrostatic repulsion between like charges exceeds the adhesive forces that keep the nanostructure in the collapsed state.

[0261] In one embodiment, the restoration method described above may be utilized in parallel with other processes.

[0262] In one embodiment, assuming a process exists for fabrication of nanostructures on a substrate, and a new layer of the substrate may be deposited on top of the existing nanostructures, an iterative process may be performed to create an (N+1)th layer of nanostructures on top of the N layers of nanostructures, where N is a natural number. In one embodiment, the nanostructure fabrication process utilizes one or more of the following methods: nanoimprint lithography, photolithography, e-beam lithography, interference lithography, self-aligned nanopatterning techniques, etching techniques including MACE, reactive ion etching, deep reactive ion etching, deposition techniques (e.g., atomic layer deposition, chemical vapor deposition (CVD), plasma enhanced CVD, sputtering, e-beam deposition, physical deposition techniques, and chemical deposition techniques), and growth techniques such as vapor-liquid-solid (VLS) growth, vapor-solid (VS) growth, etc. In one embodiment, deposition of the new layer of the substrate is performed using one or more of the following methods: bonding (e.g., fusion bonding, direct bonding, hybrid bonding, anodic bonding, covalent bonding, etc.) followed by an optional backgrind or etchback step, or thin film deposition techniques such as CVD, ALD, plasma enhanced CVD, etc. In one embodiment, the substrate is one of the following materials: silicon, silicon-containing materials, silicon oxide, spin-on oxide, silicon carbide, silicon nitride, polycrystalline silicon, amorphous silicon, aluminum oxide, metal, polymer, spin-on polymer, carbon, carbon-containing materials, semi-metals, boron, boron carbide, and boron nitride. In one embodiment, the (N+1)th layer of nanostructures is aligned with respect to the Nth layer of nanostructures using an appropriate alignment technique (such as using embedded moire alignment marks, IR moire alignment marks, offline alignment marks, alignment marks requiring high NA (e.g., greater than 0.3 NA) metrology, and alignment marks requiring low NA (e.g., less than 0.3 NA) metrology).In one embodiment, the alignment (or alternatively, overlay or registration to the base layer) is better than one of 100 nm (mean+3*sigma), 50 nm, 20 nm, 10 nm, 5 nm, 2 nm, and 1 nm.

[0263] In one embodiment, nanoimprint lithography is used to pattern a seed (or catalyst) layer used for the growth of nanostructures using a suitable growth technique, such as VLS and VS growth techniques, where the minimum feature size in the seed (or catalyst) layer is less than one of 500 nm, 200 nm, 100 nm, 50 nm, 20 nm, 10 nm, and 5 nm.

[0264] In one embodiment, during the fabrication of the nanostructures described above, one or more of in-situ metrology, ex-situ metrology, and at-line metrology are performed to control or detect one of nanostructure lateral dimension uniformity (CD uniformity), nanostructure height uniformity, nanostructure yield, and nanostructure collapse. For example, the spatial variation of the etch rate or a surrogate thereof (such as a unique spectral feature corresponding to the height of a given etch feature) is monitored in-situ. For example, the metrology may be accomplished using one or more of spectrophotometric methods, angle-resolved spectrophotometric methods, wavelength-resolved spectrophotometric methods, visible wavelength metrology, IR metrology, thermal mapping, spectroscopy, optical imaging, ultrasonic imaging, interferometry, white light interferometry, and low coherence interferometry. The metrology may be either reflective or transmissive. Furthermore, the metrology may be performed either in real-time (synchronously) or asynchronously. In one embodiment, the metrology is performed on wafer scale (on one of 50 mm, 75 mm, 100 mm, 150 mm, 200 mm, 250 mm, 300 mm, and 450 mm substrates) or roll-to-roll (on one of 50 mm, 100 mm, 150 mm, 200 mm, 300 mm, 400 mm, and 500 mm wide rolls).

[0265] In one embodiment, intermittent tethers are utilized to improve the stability of high aspect ratio nanostructures of functional materials.

[0266] Figure 44 is a flowchart of a method 4400 for creating high aspect ratio nanostructures of functional material with tethers for stability according to an embodiment of the present disclosure. Figures 45A-45E show cross-sectional views for creating high aspect ratio nanostructures of functional material with tethers for stability using the steps described in Figure 44 according to an embodiment of the present disclosure.

[0267] 44 along with FIGS. 45A-45E, in step 4401, a layer of functional material 4501 is deposited on optional etch stop layer 4502 overlying bulk substrate 4503 as shown in FIG. 45A. In one embodiment, functional material 4501 (e.g., boron) is coated onto optional etch stop layer 4502 using CVD, e-beam deposition, spin coating, etc., at one of a thickness of 1 μm or more, 5 μm or more, 10 μm or more, 50 μm or more, 100 μm or more, 200 μm or more, and 400 μm or more. In one embodiment, strain management techniques such as intermittent annealing and deposition are utilized to remove strain remaining during the coating or deposition process.

[0268] In one embodiment, optional stop layer 4502 corresponds to silicon oxide, aluminum oxide, silicon carbide, boron nitride, boron, carbon, or the like.

[0269] In one embodiment, the bulk substrate 4503 corresponds to silicon, a polymer, a metal, or the like.

[0270] In step 4402, a coating of hardmask layer 4504 is deposited over functional material 4501, as shown in Figure 45B.

[0271] In step 4403, hardmask layer 4504 is etched, as shown in Figure 45B.

[0272] In step 4404, patterning is performed (eg, involving nanoimprint lithography and optionally alignment to previous layers), as shown in Figure 45B.

[0273] In step 4405, a descum etch and a hard mask etch are performed along with resist strip, as shown in Figure 45B.

[0274] In step 4406, a deep etch of larger holes in the functional material 4501 is performed using an iterative hybrid process such as deep reactive ion etching (a first anisotropic etch and a second isotropic etch step followed by a sidewall sealing step) as shown in Figure 45B. A top view of the resulting structure is shown in Figure 45C.

[0275] In step 4407, an optional isotropic etch of functional material 4501 is performed to open tethers 4505, as shown in Figure 45D.

[0276] In step 4408, a deep etch from the backside is performed, as shown in Figure 45E.

[0277] In step 4409, an etch of etch stop layer 4502 is performed, such as by using hydrogen fluoride (HF), as shown in Figure 45E.

[0278] In step 4410, hardmask layer 4504 is removed, as shown in Figure 45E.

[0279] Figure 46 is a flowchart of an alternative method 4600 for creating high aspect ratio nanostructures of functional material with tethers for stability, according to an embodiment of the present disclosure. Figures 47A-47G show cross-sectional views for creating high aspect ratio nanostructures of functional material with tethers for stability using the steps described in Figure 46, according to an embodiment of the present disclosure.

[0280] 46 along with Figures 47A-47G, in step 4601, as shown in Figure 47A, a sacrificial layer 4701 for creation of auxiliary nanostructures is deposited on an optional stop layer 4702 (e.g., silicon oxide, aluminum oxide, silicon carbide, boron oxide, boron, carbon, etc.) on a bulk substrate 4703. In one embodiment, the cross section of the auxiliary nanostructures is one of a circle, a rectangle with rounded corners, and a polygon with rounded corners.

[0281] In step 4602, a polymer resist or hard mask 4704 is deposited on the sacrificial layer 4701, as shown in Figure 47B.

[0282] In step 4603, patterning is performed, such as by using nanoimprint lithography, optionally with alignment to the previous layer, as shown in Figure 47B, thereby forming nanowires 4705. A top view of auxiliary nanostructures such as nanowires 4705 is shown in Figure 47C.

[0283] Additionally, FIG. 47C illustrates a polygonal cross-section (e.g., square, hexagon, octagon, etc.) with optionally rounded vertices. The polygonal cross-section reduces the amount of conformal deposition that needs to be performed compared to a nanowire with a circular cross-section. Note that this geometry is very difficult to pattern using photolithography for nanoscale features, but is easy to pattern using NIL. Note also that if e-beam patterning of closely spaced features in the template proves difficult, the features may be patterned using e-beam with larger gaps, which are later filled using a conformal deposition process (e.g., ALD) in the template itself.

[0284] In step 4604, a descum etch is performed, as shown in Figure 47B.

[0285] In step 4605, a deep etch (eg, using MACE, RIE, etc.) of larger nanowires 4705 is performed, as shown in Figure 47B. For example, nanowires 4705 with a diameter of 380 nm and spaced 400 nm apart may be formed.

[0286] In step 4606, as shown in Figure 47D, an optional sacrificial gap fill material 4706 (e.g., oxide, silicon oxide, aluminum oxide, carbon, silicon nitride, silicon carbide, polymer, fluoropolymer, etc.) is deposited to close gaps in the nanostructures. In one embodiment, such deposition is followed by an optional coating of sealant 4708 (see Figure 47E) followed by deposition of functional material. One or more of the following methods may be utilized for the coating: spin-coating of a reflowable polymer (e.g., polymer-derived BN, polyborazylene, polymers based on boron hydride compounds, spin-on glass, spin-on carbon, spin-on oxide, etc.); chemical vapor deposition or conformal coating process (e.g., atomic layer deposition (ALD)) of a functional material (e.g., boron, BN); or a template growth process (e.g., using a VLS / VS process) using an optional sacrificial gap-fill material 4706 as a template for growth (e.g., using a VLS / VS process) and optionally using a MACE catalyst as a catalyst for the growth process (after removing the gap-fill material 4706 from the bottom of the etched nanowires 4705 using a suitable anisotropic etching process).

[0287] In one embodiment, the gap fill material 4706, the encapsulation material 4708, and the functional material 4701 include one or more of silicon, silicon-containing materials, silicon oxide, spin-on oxide, silicon carbide, silicon nitride, polycrystalline silicon, amorphous silicon, aluminum oxide, metals, polymers, spin-on polymers, carbon, carbon-containing materials, semi-metals, boron, boron carbide, boron nitride, polymer-derived BN, polyborazylene, polymers based on boron hydride compounds, spin-on glass, spin-on carbon, spin-on oxide, TiN, diamond, and CVD diamond.

[0288] FIG. 47E shows an optional thin conductive layer 4707 as doped polysilicon or doped BN or doped diamond or TiN.

[0289] In step 4607, as shown in FIG. 47F, the functional material 4701 is planarized, such as by using chemical mechanical planarization, or an etchback of the functional material 4701 is performed, followed by deposition of a next sacrificial layer 4709 for creation of auxiliary nanostructures 4705 (e.g., polysilicon) for the next level of functional material nanostructures 4705.

[0290] In one embodiment, the shape of the template and / or the physical components of the descum etch process may be used to optimize the sidewall slope of the imprint resist posts such that functional material planarization leaves thin lateral tethers 4710, as shown in Figure 47F. Alternatively, during the patterning step, a first lithography and a short first etch (e.g., MACE) are performed, followed by a conformal coating step (e.g., using ALD of a sacrificial material such as aluminum oxide) to widen the diameter of the etched nanostructures, followed by a self-aligned catalyst deposition and deep etch (e.g., using MAC). As a result, lateral tethers 4710 of functional material 4701 are created after the planarization step.

[0291] In step 4608, a determination is made whether N iterations (N is a positive integer) of steps 4603-4607 have been performed. If not, patterning is performed in step 4603.

[0292] However, once N iterations of steps 4603-4607 have been performed, in step 4609, a final backside etch of the substrate material (e.g., bulk substrate 4703) and sacrificial layer (e.g., sacrificial layer 4701) is performed to result in the structure shown in FIG. 47G, which includes multi-level functional material nanowires 4711.

[0293] It should be noted that the process (method 4600) may be used for deposition of any functional material with any optional sealant to prevent oxidation or chemical corrosion of the functional material (e.g., functional material 4701).

[0294] In one embodiment, an oxide scaffold is maintained around the loaded boron until just prior to laser irradiation, such as to keep the fragile boron nanowires stable against vibrations during transport.

[0295] In one embodiment, a voltage / charge is applied to the functional material nanostructures (e.g., nanostructure 4711) during or immediately after fabrication, not necessarily to prevent collapse, but to prevent entanglement during the fabrication step. A high voltage or charge may then be applied to restore any nanostructures that may have collapsed prior to use of the functional material nanostructures (e.g., nanostructure 4711). In one embodiment, the surface of the nanostructures may be treated with a low surface energy material, such as a fluoropolymer, to reduce their tendency to collapse or entangle. In one embodiment, the nanostructures (e.g., nanostructure 4711) may be purposely fabricated oversized to improve mechanical stability, and then isotropically etched down to the correct dimensions required immediately prior to use.

[0296] In one embodiment, as before, first a single layer of functional material nanostructures (e.g., nanostructures 4711) is created using an appropriate method (e.g., growth, direct etching of functional material, etc.), which is then fully encapsulated by coating a sacrificial material (e.g., using spin coating) to stabilize the nanostructures, followed by coating a second layer of functional material and fabricating nanostructures on this second layer (using aligned lithography steps to the first layer), etc. Finally, the sacrificial material can be removed to expose the high aspect ratio nanostructures.

[0297] Referring to FIG. 48, FIG. 48 illustrates a method 4800 for a RIE-based process for the creation of functional material nanostructures, according to an embodiment of the present disclosure.

[0298] In step 4801, a functional material is deposited on a silicon substrate.

[0299] In step 4802, a hard mask is coated with a functional material.

[0300] In step 4803, an adhesion layer is deposited on the hardmask.

[0301] In step 4804, nanoimprint lithography is performed.

[0302] In step 4805, a polymer descum is performed.

[0303] In step 4806, the hard mask is etched.

[0304] In step 4807, a polymer wash is performed.

[0305] In step 4808, the functional material is etched.

[0306] In step 4809, final characterization and process optimization is performed.

[0307] Referring to FIG. 49, FIG. 49 is a flowchart of a method 4900 for creating functional material nanostructures using CVD-based hole filling, according to an embodiment of the present disclosure.

[0308] In step 4901, an adhesion layer is coated onto a silicon-on-insulator or sacrificial material overlying a substrate.

[0309] In step 4902, nanoimprint lithography (or other type of lithography) is performed.

[0310] In step 4903, a polymer descum is performed.

[0311] In step 4904, a deep silicon etch is performed.

[0312] In step 4905, a residue / resist / MACE catalyst clean is performed.

[0313] In step 4906, CVD of the encapsulation material is performed.

[0314] In step 4907, CVD of the functional material is performed.

[0315] In step 4908, the backside of the hard mask is etched.

[0316] In step 4909, backside lithography is performed.

[0317] In step 4910, a backside etch of the silicon-on-insulator or substrate with a sacrificial material is performed.

[0318] In step 4911, final characterization and process optimization is performed.

[0319] Referring to FIG. 50, FIG. 50 is a flowchart of a method 5000 for creating functional material nanostructures using ALD-based hole filling, according to an embodiment of the present disclosure.

[0320] In step 5001, an adhesion layer is coated onto a silicon-on-insulator or sacrificial material overlying a substrate.

[0321] In step 5002, nanoimprint lithography (or other type of lithography) is performed.

[0322] In step 5003, a polymer descum is performed.

[0323] In step 5004, a deep silicon etch is performed.

[0324] In step 5005, a residue / resist / MACE catalyst clean is performed.

[0325] In step 5006, ALD of the encapsulation material is performed.

[0326] In step 5007, ALD of the functional material is performed.

[0327] In step 5008, the backside of the hard mask is etched.

[0328] In step 5009, backside lithography is performed.

[0329] In step 5010, a backside etch of the silicon-on-insulator or substrate with a sacrificial material is performed.

[0330] In step 5011, final characterization and process optimization is performed.

[0331] Referring to FIG. 51, FIG. 51 is a flow chart of a method 5100 for spin-coating a functional material-containing polymer for hole filling, according to an embodiment of the present disclosure.

[0332] In step 5101, an adhesion layer is coated onto a silicon-on-insulator or sacrificial material overlying a substrate.

[0333] In step 5102, nanoimprint lithography (or other type of lithography) is performed.

[0334] In step 5103, a polymer descum is performed.

[0335] In step 5104, a deep silicon etch is performed.

[0336] In step 5105, a residue / resist clean is performed.

[0337] In step 5106, a functional material comprising a polymer is spin coated.

[0338] In step 5107, annealing is performed.

[0339] In step 5108, the backside of the hard mask is etched.

[0340] In step 5109, backside lithography is performed.

[0341] In step 5110, a backside etch of the silicon-on-insulator or substrate with a sacrificial material is performed.

[0342] In step 5111, final characterization and process optimization is performed.

[0343] Referring to FIG. 52, FIG. 52 is a flow chart of a method 5200 for growth of confined / molded VLS / VS functional materials, according to an embodiment of the present disclosure.

[0344] In step 5201, an adhesion layer is coated onto a silicon-on-insulator or sacrificial material overlying a substrate.

[0345] In step 5202, nanoimprint lithography (or other type of lithography) is performed.

[0346] In step 5203, a polymer descum is performed.

[0347] In step 5204, a deep silicon etch using a VLS optimized catalyst is performed.

[0348] In step 5205, a residue / resist clean is performed.

[0349] In step 5206, VLS / VS of the functional material (eg, boron) is performed.

[0350] In step 5207, the backside of the hard mask is etched.

[0351] In step 5208, backside lithography is performed.

[0352] In step 5209, a backside etch of the silicon-on-insulator or substrate with a sacrificial material is performed.

[0353] In step 5210, final characterization and process optimization is performed.

[0354] FIG. 53 is a flowchart of a method 5300 for a multi-layer process according to an embodiment of the present disclosure.

[0355] In step 5301, a thick polymer coating is deposited on a structure.

[0356] In step 5302, layer (N+1) processing is performed using aligned lithography.

[0357] In step 5303, final characterization and process optimization is performed.

[0358] As a result of the above, embodiments of the present disclosure provide tools and processes for utilizing electrochemical etching in creating arbitrary high aspect ratio nanostructures in a variety of substrates such as silicon, aluminum oxide, and the like.

[0359] The description of various embodiments of the present invention is presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used in this specification are selected to best explain the principles of the embodiments, practical applications, or technical improvements beyond those found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein. [Explanation of symbols]

[0360] 301 Mask Layer 302 Valve metals 303 Support material 304 AVO Nanostructure 305 AVO Scaffolding 306 Functional Materials 401 NIL template role 402 Source Substrate Roll 403 R2R NIL 405 R2R Reactive Ion Etching (RIE) / Descum Etching 406 R2R AE2 407 R2R Deposition 408 In-situ Functional Measurement 409 Last Roll 501 Process Chamber 502 Inlet manifold 503 Outlet Manifold 504 Process Wafer 601 Multi-layer front cover 602 Process Wafer 603 Etching products 604 Etchant inlet 605 Etchant outlet 701 Front cover 702 Eccentric Rotating Etchant Spray Arm 703 Etchant inlet 704 Etchant outlet 705 Etchant 706 Process Wafer 801 Process Wafer 802 Sliding Etching Zone 803 Etchant 804 Etchant inlet 805 Etchant outlet 806 Front cover 901 Front cover 902 Process Wafer 903 Counter rotating etchant stirring arm 904 Etchant 905 Etchant outlet 906 Etchant inlet jet 1000 Etchant Flow Assembly 1001 Process Wafer 1002 Front cover 1003 Etchant inlet 1004 Etchant outlet 1005 Mixing chamber 1006 Etchant Pump 1007 Etchant Status Sensor 1009 Precursor Storage Unit 1010 Precursor Status Sensor 1101 Air bubbles 1102 Process wafer 1103 Etchant outlet 1104 Degassing chamber 1105 Etchant inlet 1107 Front cover 1201 Wafer chuck 1202 Process Wafer 1203 TEC 1204 Front cover 1205 Etchant inlet 1206 Etchant outlet 1207 Seal 1301 Wafer Chuck 1302 Process Wafer 1303 TEC 1304 Front cover 1305 Etchant inlet 1306 Etchant outlet 1307 Seal 1308 Vacuum Chamber 1309 Etchant 1401 Wafer Chuck 1402 Process Wafer 1403 Front cover 1404 Etchant inlet 1405 Etchant outlet 1406 Thermoelectric Cooler 1500 in-situ measurement system 1501 Process Board 1502 Focusing optics 1503 Imaging Device 1504 Sapphire front and back covers 1505 Light source 1506 Optical Filter 1507 Backside fluid inlet 1508 Backside fluid outlet 1509 Etchant inlet 1510 Etchant outlet 1511 finite radius 1600 in-situ measurement system 1601 Imaging device assembly 1602 Process wafer 1701 Light Source and DMD Assembly 1702 Backside Fluid 1801 Process Wafer 1802 Front transparent electrode 1803 Back transparent electrode 1804 Backside lighting 1901 Wafer Chuck 1902 Process Wafer 1903 Front cover 1905 Edge Exclusion Zone 1906 Front seal contact 2001 Process Wafer 2002 Wafer Chuck 2003 Chuck Pin 2004 Backside contact fluid 2101 Vacuum chuck 2301 Functional materials 2302 Substrate 2601 Substrate 2602 Functional Materials 2603 Functional Materials 2604 Nanostructure 2901 Area of ​​Interest 2902 Aluminum oxide 2903 Tether 3001 Integrated Capacitor 3002 Electrode 3003 Functional Materials Nanostructures 3004 Functional materials 3005 Electrode 3006 High voltage source 3007 Nanostructure sample 3009 Ground or conductive mesh 3010 Area of ​​Interest 3012 Thin continuous layer 3013 Thin conductive layer 3014 Sealing layer 3201 Silicon base 3202 Silicon Core 3203 Boron 3204 Open Space 3205 Open Channel 3206 Target laser irradiation area 3207 Boron 3208 Nanowires 3209 Nanowire charging device 3401 Nanoimprint resist 3402 Silicon 3403 Titanium 3404 Gold catalyst 3405 Polycrystalline silicon structure 3701 Nanoimprint resist 3702 Glass wafer 3703 Gold 3704 Reverse Tone Template 3705 Imprint Template 3706 Substrate 3707 Polysilicon pillar 4001 Fin 4307 Perforated Carrier 4308 Perforated carrier membrane 4309 Nanowire Interface 4310 Nanostructured Functional Materials 4501 Functional materials 4502 Etch stop layer 4503 Bulk Board 4504 Hard Mask Layer 4505 Tether 4701 Sacrificial Layer 4702 Stop layer 4703 Bulk Substrate 4704 Hard Mask 4705 Nanowires 4706 Sacrificial Gap Fill Material 4707 Thin conductive layer 4708 Sealant coating 4709 Sacrificial Layer 4710 Tether 4711 Nanowires

Claims

1. A method for fabricating a nanostructure with a high aspect ratio in any functional material, comprising: depositing a (N + 1)th layer of a substrate material on top of an existing N-layer nanostructure, where N is a natural number; patterning and etching in the (N + 1)th layer of the substrate material to create auxiliary nanostructures therein; performing conformal coating of a gap filling material, a sealing layer, and a functional material onto the auxiliary nanostructures to create functional material nanostructures in the (N + 1)th layer; and performing a set of selective etching on the substrate material to leave a multi-layer high aspect ratio nanostructure in the functional material.

2. The method according to claim 1, wherein the overall height of the multi-layer high aspect ratio nanostructure is greater than one of 10 μm, 20 μm, 50 μm, 100 μm, 200 μm, and 400 μm.

3. The method according to claim 1, wherein the shape spacing of the multi-layer high aspect ratio nanostructure is less than one of 500 nm, 200 nm, 100 nm, 50 nm, 20 nm, 10 nm, and 5 nm.

4. The method according to claim 1, wherein the final aspect ratio of the multi-layer high aspect ratio nanostructure is greater than one of 10:1, 20:1, 50:1, 100:1, 200:1, 500:1, 1000:1, 2000:1, 5000:1, 10000:1, 50000:1, and 100000:

1.

5. The method according to claim 1, wherein N is greater than one of 2, 5, 10, 20, 50, and 100.

6. The method according to claim 1, wherein the substrate material is one or a combination of silicon, silicon-containing materials, silicon oxide, spin-on oxides, silicon carbide, silicon nitride, polycrystalline silicon, amorphous silicon, aluminum oxide, metals, polymers, spin-on polymers, carbon, carbon-containing materials, semimetals, boron, boron carbide, and boron nitride.

7. The method according to claim 1, wherein the patterning is one of nanoimprint lithography, photolithography, electron beam lithography, interference lithography, self-aligned nanopatterning techniques, nanosphere lithography, and displacement Talbot lithography.

8. The method according to claim 1, wherein the etching is one of MACE, Au MACE, Ru MACE, Pt MACE, vapor-phase MACE, liquid-phase MACE, reactive ion etching, and deep reactive ion etching.

9. The method according to claim 1, wherein the cross-section of the auxiliary nanostructure is one of circular, rounded square, and rounded polygon.

10. The method according to claim 1, wherein the (N + 1)th layer of the substrate material is deposited on the existing N-layer nanostructure using one or more of the methods of fusion bonding, direct bonding, hybrid bonding, anodic bonding, and covalent bonding.

11. The method according to claim 1, wherein the coating of the gap filling material, the encapsulation material, and the functional material is performed using one or more of the methods of spin coating of a reflowable polymer, chemical vapor deposition, and conformal coating process.

12. The method according to claim 1, wherein the gap filling material, the encapsulation material, and the functional material comprise one or more of silicon, silicon-containing material, silicon oxide, spin-on oxide, silicon carbide, silicon nitride, polycrystalline silicon, amorphous silicon, aluminum oxide, metal, polymer, spin-on polymer, carbon, carbon-containing material, semimetal, boron, boron carbide, boron nitride, polymer-derived BN, polyboradiene, polymer based on boron hydride compound, spin-on glass, spin-on carbon, spin-on oxide, TiN, diamond, and CVD diamond.

13. The set of the selective etching includes XeF ２ etching, fluoropolymer-based etching (using CF ４ , CHF ３ ), one or more of vapor HF, HF, plasma etching, wet etching, vapor etching, crystal etching, KOH etching, DRIE, and RIE, the method according to claim 1.

14. The method according to claim 1, wherein the inclination of the sidewall near the end of the auxiliary nanostructure, or alternatively, the step near the end of the auxiliary nanostructure, is used together with a planarization step after the coating of the functional material on the auxiliary nanostructure to create a lateral tether in the functional material.

15. The method according to claim 14, wherein the lateral tether improves the structural stability of the multi-layer high aspect ratio nanostructure.

16. The method according to claim 1, wherein two or more of said deposition, said patterning and etching, said execution of said conformal coating, and said execution of said set of selective etching are performed in a roll-to-roll manner.

17. The method according to claim 1, further comprising the step of controlling or detecting the uniformity of the lateral dimension of the nanostructure, the uniformity of the height of the nanostructure, the yield of the nanostructure, and / or the collapse of the nanostructure, with respect to said multi-layer high aspect ratio nanostructure.

18. The method according to claim 1, wherein said functional material nanostructure in said (N + 1)-th layer is fabricated on top of an existing N layers and aligned with one or more of said existing N layers during said patterning in said (N + 1)-th layer.

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