Array Substrate and Display Device

Abstract

This application belongs to the field of display technology, and an array substrate (000) and a display device are disclosed. The array substrate (000) includes a substrate (100), a pixel electrode layer (200) and a common electrode layer (300) located on the substrate (100), and a plurality of common signal lines (400) located on the substrate (100). The common signal lines (400) are installed insulated from the pixel electrode layer (200) and are electrically connected to the common electrode layer (300). There is an overlapping region between the orthographic projection of the common signal line (400) on the substrate (100) and the orthographic projection of the pixel electrode layer (200) on the substrate (100). The common signal line (400) has a plurality of electrode structures (400a), and different electrode structures (400a) are located in different sub-pixel regions (00a). The plurality of electrode structures (400a) include a wrap electrode (401) that wraps with the common electrode layer (300) and an auxiliary electrode (402) that does not wrap with the common electrode layer (300). In order to install the wrap electrode (401) and the auxiliary electrode (402) on the common electrode line (400) at the same time, the magnitudes of the storage capacitances (Cst) in the sub-pixel regions (00a) where the wrap electrode (401) and the auxiliary electrode (402) are located are substantially the same, and the probability of occurrence of defective phenomena such as screen flickering and jitter on the screen displayed by the display device is reduced.

Description

Technical Field

[0001] This application claims the priority of the Chinese patent application with the application number 202210580442.2 and the application title "Array Substrate and Display Device", which was filed on May 25, 2022, and all of its contents are incorporated herein by reference.

[0002] This application relates to the field of display technology, and particularly to an array substrate and a display device.

Background Art

[0003] Currently, display devices have already become essential electronic products in people's lives. For example, display devices such as smart bracelets, mobile phones, and tablets have greatly improved the convenience of people's lives.

[0004] A display device can include an array substrate and a color filter substrate that are oppositely arranged, and a liquid crystal layer located between the array substrate and the color filter substrate. The array substrate can include a substrate, a common signal line and a common electrode located on the substrate. The common signal line and the common electrode are installed in different layers and are electrically connected through vias. However, at present, the display effect of the display device is poor.

Summary of the Invention

Means for Solving the Problems

[0005] Embodiments of this application provide an array substrate and a display device, which can improve the display effect of the display device. The technical solution is as follows:

[0006] According to one aspect, an array substrate is provided. The array substrate has a plurality of sub-pixel regions. The array substrate includes: a substrate, a pixel electrode layer and a common electrode layer located on the substrate, A plurality of common signal lines located on the substrate, including The common signal lines are installed insulated from the pixel electrode layer and are electrically connected to the common electrode layer. There is an overlapping area between the orthographic projection of the common signal lines on the substrate and the orthographic projection of the pixel electrode layer on the substrate. The common signal lines have a plurality of electrode structures. Different electrode structures are located in different sub-pixel regions. The plurality of electrode structures include a wrap electrode that wraps with the common electrode layer and an auxiliary electrode that does not wrap with the common electrode layer.

[0007] As one option, the orthographic projection of the auxiliary electrode on the substrate and the orthographic projection of the wrap electrode on the substrate are the same in both shape and area.

[0008] As one option, the plurality of sub-pixel regions include at least two-color sub-pixel regions. The plurality of electrode structures correspond one-to-one to a plurality of sub-pixel regions within the same-color sub-pixel regions, and the electrode structures are located within the corresponding sub-pixel regions.

[0009] As one option, within the same-color sub-pixel regions, for any two adjacent sub-pixel regions, the wrap electrode is distributed in one pixel region and the auxiliary electrode is distributed in the other pixel region.

[0010] As one option, the sub-pixel region where the electrode structure is distributed is a blue sub-pixel region.

[0011] As one option, the array substrate has a plurality of vias. The common electrode layer wraps with the wrap electrode through at least one of the vias, and the orthographic projection of the via on the substrate and the orthographic projection of the wrap electrode on the substrate overlap at least partially.

[0012] As one option, a part of the via in the orthographic projection onto the substrate is located within the orthographic projection of the wrap electrode onto the substrate, and another part is located outside the orthographic projection of the wrap electrode onto the substrate.

[0013] As one option, the pixel electrode layer is closer to the substrate than the common electrode layer, the pixel electrode layer includes pixel electrodes located within the sub-pixel region, and the orthographic projection of the pixel electrode onto the substrate does not overlap with the orthographic projection of the electrode structure onto the substrate.

[0014] As one option, the pixel electrode has a stippled structure, and within the same sub-pixel region, the orthographic projection of the electrode structure onto the substrate is located within the orthographic projection of the stippled structure onto the substrate.

[0015] As one option, the distance between the outer boundary of the orthographic projection of the electrode structure onto the substrate within each sub-pixel region and the outer boundary of the orthographic projection of the stippled structure onto the substrate is equal.

[0016] As one option, the array substrate further includes a plurality of data lines, a plurality of gate lines, and a plurality of transistors, and the plurality of transistors correspond one-to-one to the plurality of pixel electrodes. One of the gate lines is electrically connected to the gate of each transistor among the transistors in the same row, the gate line and the common signal line are installed in the same layer and have the same material, and the extending direction of the gate line and the extending direction of the common signal line are parallel. One of the data lines is electrically connected to the first pole of each transistor among the transistors in the same column, and the second pole of the transistor is electrically connected to the corresponding pixel electrode.

[0017] As one option, for any two adjacent transistors among a column of transistors electrically connected to the same data line, one of the transistors is located on one side of the data line, and the other transistor is located on the other side of the data line.

[0018] As one option, the array substrate further includes a first insulating layer located on a side away from the substrate of the plurality of transistors, and a second insulating layer located between the pixel electrode layer and the common electrode layer. The pixel electrode layer is located on a side away from the substrate of the first insulating layer.

[0019] As one option, the common electrode layer has a plurality of slits.

[0020] According to another aspect, a display device is provided, and the device includes a color filter substrate, a liquid crystal layer, and any one of the above array substrates. The array substrate and the color filter substrate are installed opposite to each other, and the liquid crystal layer is located between the array substrate and the color filter substrate.

[0021] The beneficial effects of the technical solutions provided in the embodiments of the present application include at least the following contents:

[0022] The array substrate provided in the embodiment of the present application includes a substrate, a pixel electrode layer located on the substrate, a common electrode layer, and a plurality of common signal lines. On the common electrode line, a wrap electrode that wraps with the common electrode layer and an auxiliary electrode that does not wrap with the common electrode layer are simultaneously installed. In this way, by effectively reducing the number of vias for wrapping the common electrode layer and the common signal lines installed in the array substrate, in the subsequent process of forming an alignment film on the array substrate, it can be ensured that the probability of non-uniform diffusion of the alignment liquid for forming the alignment film is low, and after subsequently integrating this array substrate into a display device, it can be ensured that the probability of occurrence of luminance non-uniformity and the like in the display device is low. Also, in the common electrode line, by simultaneously installing the wrap electrode and the auxiliary electrode, it can be ensured that the size of the storage capacitance in the sub-pixel region where the wrap electrode is located is substantially the same as the size of the storage capacitance in the sub-pixel region where the auxiliary electrode is located. And it can be ensured that the numerical value of △Vp corresponding to the pixel electrode in the sub-pixel region where the wrap electrode is located is substantially the same as the numerical value of △Vp corresponding to the pixel electrode in the sub-pixel region where the auxiliary electrode is located. Therefore, when the array substrate in the present application is integrated into a display device and the display device displays a screen in a column inversion method, the probability of occurrence of defective phenomena such as screen flickering and jitter in the screen displayed by the display device is low, effectively improving the display effect of the display device.

[0023] To more clearly explain the technical solution in the embodiment of the present application, hereinafter, the drawings necessary for the description of the embodiment will be briefly described. However, the drawings in the following description are only some embodiments of the present application, and it is obvious to those skilled in the art that based on these drawings, other drawings can be obtained without creative labor.

Brief Description of the Drawings

[0024]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Embodiments for Carrying Out the Invention

[0025] To make the objectives, technical solutions and advantages of the present application clearer, the embodiments of the present application will be described in more detail below in conjunction with the drawings.

[0026] Referring to FIGS. 1 and 2, FIG. 1 is a plan view of a current general array substrate, and FIG. 2 is a cross-sectional view taken along D-D' of the array substrate shown in FIG. 1. The array substrate 00 can include a substrate 01, a pixel electrode layer 02 and a common electrode layer 03 located on the substrate 01, and a plurality of common signal lines 04 located on the substrate 01. The common signal lines 04 are installed insulated from the pixel electrode layer 02 and are electrically connected to the common electrode layer 03.

[0027] Here, the array substrate 00 has a plurality of sub-pixel regions 0a. For example, the array substrate 00 can further include a plurality of data lines 06 and a plurality of gate lines 07. Any two adjacent data lines 06 and any two adjacent gate lines 07 can surround one sub-pixel region 0a. The pixel electrode layer 02 can include pixel electrodes 021 distributed within each sub-pixel region 0a.

[0028] Since there is an overlapping region between the orthographic projection of the common electrode line 04 on the substrate 01 and the orthographic projection of the pixel electrode 021 on the substrate 01, a portion where the common electrode line 04 and the pixel electrode 021 overlap can form a storage capacitor Cst. The storage capacitor Cst can hold the pixel voltage applied to the pixel electrode 021, enabling the display device in which this array substrate 00 is integrated to continuously display images.

[0029] As shown in FIG. 1, the plurality of sub-pixel regions 0a in the array substrate 00 can include a plurality of red sub-pixel regions R, a plurality of green sub-pixel regions G, and a plurality of blue sub-pixel regions (B1, B2).

[0030] To more clearly understand the structure of the array substrate, refer to FIG. 3, which is a partial enlarged view of the array substrate shown in FIG. 1 at B. The array substrate 00 has a plurality of vias 05. The common signal line 04 has a wrap electrode 041 corresponding to the via 05. The common electrode layer 03 wraps around the wrap electrode 041 of the common signal line 04 through a plurality of vias 05 to realize the electrical connection between the common electrode layer 03 and the common signal line 04. When the number of vias 05 in the array substrate 00 is large, in the process of forming the alignment film on the array substrate 00, the diffusion of the alignment liquid for forming the alignment film becomes non-uniform. Subsequently, after integrating this array substrate 00 into the display device, a bad problem of luminance non-uniformity is likely to occur in the display device, affecting the display effect of the display device. Therefore, it is necessary to reduce the number of vias 05 installed in the array substrate 00. For example, in the array substrate 00, one via 05 can be installed for every six sub-pixel regions.

[0031] In this case, one via 05 can be installed in each blue sub-pixel region B1, and it is also possible that no via 05 is installed in the blue sub-pixel region B2 adjacent to the blue sub-pixel region B1. Also, wrap electrodes 041 are distributed in each blue sub-pixel region B1, and no wrap electrodes 041 are distributed in each blue sub-pixel region B2. Whether the wrap electrode 041 is distributed in the sub-pixel region directly affects the magnitude of the storage capacitance formed between the pixel electrode 021 and the common electrode line 04 in this sub-pixel region. Therefore, the magnitude of the storage capacitance formed between the pixel electrode 021 and the common electrode line 04 in the blue sub-pixel region B1 is different from the magnitude of the storage capacitance formed between the pixel electrode 021 and the common electrode line 04 in the blue sub-pixel region B2.

[0032] Here, the actual potential applied to the pixel electrode 021 in each sub-pixel region 0a in the array substrate 00 is correlated with the magnitude of the storage capacitance in this sub-pixel region 0a. For example, the difference △Vp between the preset potential applied to the pixel electrode 021 and the actual potential can be calculated by the following formula:

[0033]

Equation

[0034] Here, Cgs represents the coupling capacitance formed between the gate line 07 and the data line 06 in the sub-pixel region 0a. Clc represents the liquid crystal capacitance formed by the pixel electrode 021 and the common electrode layer 03 in the sub-pixel region 0a. Cst represents the storage capacitance formed at the overlapping portion of the common electrode line 04 and the pixel electrode 021. Vgh represents the high-level voltage applied to the gate line 07. Vgl represents the low-level voltage applied to the gate line 07.

[0035] Therefore, when the magnitude of the storage capacitance in the blue sub-pixel region B1 is different from the magnitude of the storage capacitance in the blue sub-pixel region B2, the numerical value of △Vp corresponding to the pixel electrode 021 in the blue sub-pixel region B1 is different from the numerical value of △Vp corresponding to the pixel electrode 021 in the blue sub-pixel region B2. For this reason, even if the array substrate 00 applies signals of the same potential (i.e., the pre-set potential is applied) to the pixel electrodes 021 in the two types of blue sub-pixel regions simultaneously, the actual potential applied to the pixel electrode 021 in the blue sub-pixel region B1 is different from the actual potential applied to the pixel electrode 021 in the blue sub-pixel region B2. In this case, when the display device in which this array substrate 00 is integrated adopts the column inversion method to display a blue screen, the blue screen displayed by the display device is likely to have defective phenomena such as screen flickering and jitter.

[0036] For example, referring to FIG. 4, FIG. 4 is a schematic diagram showing the polarity change of the voltage corresponding to each sub-pixel region when the display device adopts the column inversion method for display. In FIG. 4, the first frame screen and the second frame screen respectively show the polarity of the pixel voltage applied to the pixel electrode 021 in each sub-pixel region 0a before column inversion and the polarity of the pixel voltage applied to the pixel electrode 021 in each sub-pixel region 0a after column inversion. Here, the polarities of the pixel voltages applied to the pixel electrode 021 in each sub-pixel region 0a before and after column inversion are opposite.

[0037] Thus, in order to ensure that no defective phenomena such as flickering or jitter occur on the display screen of the display device, it is necessary to ensure that the luminance of each sub-pixel region 0a before and after column inversion is close or the same. Also, when the display device displays a screen, the luminance of the sub-pixel region 0a correlates with the voltage difference formed between the pixel electrode 021 and the common electrode layer 03 within this sub-pixel region 0a. For this reason, when ensuring that the voltage differences formed between the pixel electrode 021 and the common electrode layer 03 within the sub-pixel region 0a before and after column inversion are the same, the degree of defective phenomena such as flickering and jitter that occur when the display device displays a screen can be reduced.

[0038] However, the numerical value of △Vp corresponding to the pixel electrode 021 within the blue sub-pixel region B1 is different from the numerical value of △Vp corresponding to the pixel electrode 021 within the blue sub-pixel region B2, and the pixel electrodes within each sub-pixel region 0a all commonly use one common electrode layer 03. Thus, the display device designs the common voltage Vcom applied to the common electrode layer 03 based on the numerical value of △Vp corresponding to the pixel electrode 021 of one of the blue sub-pixel regions B1 and B2 (taking B1 as an example in the following embodiments). Thereby, it can be ensured that the voltage differences formed between the pixel electrode 021 and the common electrode layer 03 within the sub-pixel region B1 before and after column inversion are the same. However, since the actual potential applied to the pixel electrode 021 within the blue sub-pixel region B1 is different from the actual potential applied to the pixel electrode 021 within the blue sub-pixel region B2, the voltage differences formed between the pixel electrode 021 and the common electrode layer 03 within the sub-pixel region B2 before and after column inversion are different. For this reason, when this display device displays a blue screen, defective phenomena such as screen flickering and jitter are likely to occur on the blue screen displayed by the display device. In particular, when the display device displays a low-tone blue monochrome screen, the occurrence of defective phenomena such as flickering and jitter in the sub-pixels corresponding to the blue sub-pixel region is the most prominent. From this, it can be seen that the display effect of the current display device is inferior.

[0039] Referring to FIGS. 5 and 6, FIG. 5 is a plan view of an array substrate provided in an embodiment of the present application, and FIG. 6 is a cross-sectional view taken along line A-A' of the array substrate shown in FIG. 5. The array substrate 000 has a plurality of sub-pixel regions 00a, and the array substrate 000 includes a substrate 100, a pixel electrode layer 200, a common electrode layer 300, and a plurality of common signal lines 400 located on the substrate 100.

[0040] Exemplarily, the array substrate 000 can further include a plurality of data lines 700 and a plurality of gate lines 800 located on the substrate 100. Here, the plurality of data lines 700 are arranged in parallel, the plurality of gate lines 800 are arranged in parallel, and the extending direction of the data lines 700 intersects with the extending direction of the gate lines 800. In the array substrate 000, any two adjacent data lines 700 and any two adjacent gate lines 800 can surround one sub-pixel region 00a.

[0041] The common signal line 400 in the array substrate 000 is installed insulated from the pixel electrode layer 200 and is electrically connected to the common electrode layer 300.

[0042] There is an overlapping region between the orthographic projection of the common signal line 400 in the array substrate 000 on the substrate 100 and the orthographic projection of the pixel electrode layer 200 on the substrate 100. Here, the pixel electrode layer 200 in the array substrate 000 can include pixel electrodes 201 distributed in each sub-pixel region 00a. As shown in FIG. 6, since there can be an overlapping region between the orthographic projection of the pixel electrode 201 in each sub-pixel region 00a on the substrate 100 and the orthographic projection of the common signal line 400 on the substrate 100, a storage capacitor Cst can be formed in this sub-pixel region 00a at the overlapping portion of the common electrode line 400 and the pixel electrode 201.

[0043] Here, the common signal line 400 has a plurality of electrode structures 400a, and different electrode structures 400a are located within different sub-pixel regions 00a. The plurality of electrode structures 400a includes a wrap electrode 401 that wraps with the common electrode layer 300 and an auxiliary electrode 402 that does not wrap with the common electrode layer 300.

[0044] In an embodiment of the present application, referring to FIG. 7, FIG. 7 is a partial enlarged view of C of the array substrate shown in FIG. 5. Usually, since an insulating layer exists between the conductive layer where the common signal line 400 is located and the common electrode layer 300, it is necessary to install a via V1 in the array substrate 000 so that the common electrode layer 300 can be electrically connected to the wrap electrode 401 of the common signal line 400 through the via V1.

[0045] Referring to FIG. 8, FIG. 8 is a partial enlarged view of D of the array substrate shown in FIG. 5. In the auxiliary electrode 402 of the common signal line 400, in addition to the wrap electrode 401, another auxiliary electrode 402 is further installed, and this auxiliary electrode 402 does not wrap with the common electrode layer 300. Therefore, there is no need to install a via V1 for wrapping the common electrode layer 300 and the common signal line 400 within the sub-pixel region 00a where the auxiliary electrode 402 is distributed. In this way, by effectively reducing the number of vias V1 for wrapping the common electrode layer 300 and the common signal line 400 installed in the array substrate 000, it can be ensured that the probability of uneven diffusion of the alignment liquid for forming the alignment film is low during the subsequent process of forming the alignment film on the array substrate 000, and after subsequently integrating this array substrate 000 into the display device, it can be ensured that the probability of luminance unevenness and the like occurring in the display device is low.

[0046] In addition, in the present application, in the common electrode line 400, by simultaneously providing a wrap electrode 401 that wraps around the common electrode layer 300 and an auxiliary electrode 402 that does not wrap around the common electrode layer 300, it is possible to ensure that the magnitude of the storage capacitance Cst in the sub-pixel region 00a where the wrap electrode 401 is located is almost the same as the magnitude of the storage capacitance Cst in the sub-pixel region 00a where the auxiliary electrode 401 is located. In this way, it can be ensured that the numerical value of ΔVp corresponding to the pixel electrode 201 in the sub-pixel region 00a where the wrap electrode 401 is located is almost the same as the numerical value of ΔVp corresponding to the pixel electrode 201 in the sub-pixel region 00a where the auxiliary electrode 401 is located. Therefore, when the array substrate 000 in the present application is integrated in a display device and the display device displays a screen in a column inversion method, the probability of occurrence of defective phenomena such as screen flickering and jitter in the screen displayed by the display device is low, effectively improving the display effect of the display device.

[0047] As described above, the array substrate provided in the embodiment of the present application includes a substrate, a pixel electrode layer, a common electrode layer, and a plurality of common signal lines located on the substrate. On the common electrode line, a wrap electrode that wraps with the common electrode layer and an auxiliary electrode that does not wrap with the common electrode layer are simultaneously installed. In this way, by effectively reducing the number of vias for wrapping the common electrode layer and the common signal line installed in the array substrate, in the process of subsequently forming an alignment film on the array substrate, it can be ensured that the probability of uneven diffusion of the alignment liquid for forming the alignment film is low, and after subsequently integrating this array substrate into the display device, it can be ensured that the probability of uneven brightness or the like occurring in the display device is low. Further, in the common electrode line, by simultaneously installing the wrap electrode and the auxiliary electrode, it can be ensured that the magnitude of the storage capacitance in the sub-pixel region where the wrap electrode is located is substantially the same as the magnitude of the storage capacitance in the sub-pixel region where the auxiliary electrode is located. And it can be ensured that the numerical value of △Vp corresponding to the pixel electrode in the sub-pixel region where the wrap electrode is located is substantially the same as the numerical value of △Vp corresponding to the pixel electrode in the sub-pixel region where the auxiliary electrode is located. Therefore, when the array substrate in the present application is integrated into the display device and the display device displays the screen in the column inversion method, the probability of occurrence of defective phenomena such as screen flickering and jitter in the screen displayed by the display device is low, effectively improving the display effect of the display device.

[0048] In the present application, as shown in FIG. 5, the shapes and areas of the orthographic projections of each electrode structure 400a on the substrate 100 are all the same. That is, the shape and area of the orthographic projection of the wrap electrode 401 on the common signal line 400 on the substrate 100 are the same as those of the orthographic projection of the wrap electrode 401 on the substrate 100. In this case, it can be ensured that the magnitude of the storage capacitance Cst in the sub-pixel region 00a where the wrap electrode 401 is located is the same as the magnitude of the storage capacitance Cst in the sub-pixel region 00a where the auxiliary electrode 401 is located, thereby further reducing the probability of occurrence of defective phenomena such as screen flickering and jitter in the screen displayed by the display device.

[0049] In the present application, as shown in FIG. 5, the plurality of sub-pixel regions 00a in the array substrate 000 can include at least two-color sub-pixel regions 00a, and the plurality of electrode structures 400a correspond one-to-one to the plurality of sub-pixel regions 00a within the sub-pixel regions 00a of the same color, and each electrode structure 400a can be located within the corresponding sub-pixel region 00a. Exemplarily, the plurality of sub-pixel regions 00a include three-color sub-pixel regions 00a, and each of these three-color sub-pixel regions is a red sub-pixel region R, a green sub-pixel region G, and a blue sub-pixel region (B1, B2).

[0050] Here, the sub-pixel regions where the electrode structures 400a are distributed are sub-pixel regions of the same color. For example, in FIG. 5, the sub-pixel regions where the electrode structures 400a are distributed are blue sub-pixel regions (B1, B2). Since the electrode structures 400a of the common electrode line 400 are usually made of a non-light-transmissive metal material, when the electrode structures 400a are distributed within the sub-pixel regions 00a, the aperture ratio of this sub-pixel region 00a will decrease. In order to improve the protection of the display device against the eyes, usually, it is necessary to reduce the emission intensity of blue light when the display device displays the screen, and the influence of blue light on the display effect of the display device is small. Therefore, when all the electrode structures 400a are distributed within the blue sub-pixel regions (B1, B2), even if the aperture ratio of the blue sub-pixel regions (B1, B2) is small, it will not affect the overall display effect of the display device, and at the same time, it can be ensured that the intensity of the blue light emitted when the display device displays the screen is low, thereby ensuring that this display device has a certain degree of eye protection.

[0051] Exemplarily, as shown in FIG. 5, within the sub-pixel regions 00a of the same color, for any two adjacent sub-pixel regions (B1, B2), a wrap electrode 401 is distributed within one sub-pixel region B1, and an auxiliary electrode 402 is distributed within the other sub-pixel region B2. Exemplarily, in FIG. 5, wrap electrodes 401 are all distributed in each sub-pixel region B1, and auxiliary electrodes 402 are all distributed within each sub-pixel region B2.

[0052] In this case, the wrap electrodes 401 are uniformly distributed within the array substrate 000, the auxiliary electrodes 402 are also uniformly distributed within the array substrate 000, and the vias V1 corresponding to the wrap electrodes 401 in the array substrate 000 are also uniformly distributed within the array substrate 000. In this way, the uniformity of the diffusion of the alignment liquid for forming the alignment film can be further improved, and the defective problem of luminance non-uniformity due to non-uniform diffusion of the alignment liquid can be avoided, thereby improving the display effect of the display device.

[0053] In the present application, the array substrate 000 has a plurality of vias V1, the common electrode layer 300 wraps around the wrap electrode 401 through at least one via V1, and the orthographic projection of the via V1 on the substrate 100 and the orthographic projection of the wrap electrode 401 on the substrate 100 at least partially overlap.

[0054] In a possible embodiment, the orthographic projection of the via V1 on the substrate 100 is located within the orthographic projection of the wrap electrode 401 on the substrate 100.

[0055] In another possible embodiment, referring to FIG. 9, FIG. 9 is a cross-sectional view taken along B-B' of the array substrate shown in FIG. 7. A part of the orthographic projection of the via V1 on the substrate 100 is located within the orthographic projection of the wrap electrode 401 on the substrate 100, and the other part is located outside the orthographic projection of the wrap electrode 401 on the substrate 100. That is, the orthographic projection of the via V1 on the substrate 100 and the orthographic projection of the wrap electrode 401 on the substrate 100 only partially overlap.

[0056] In this case, the depth of the part of the via V1 that overlaps with the wrap electrode 401 is small, and the depth of the part of the via V1 that does not overlap with the wrap electrode 401 is large. That is, the via V1 belongs to a deep and shallow via structure with a deep local region and a shallow local region. This deep and shallow via structure is advantageous for the diffusion of the alignment liquid, and can further improve the uniformity of the diffusion of the alignment liquid for forming the alignment film, avoid the defective problem of luminance non-uniformity due to non-uniform diffusion of the alignment liquid, and improve the display effect of the display device.

[0057] Referring to FIG. 10, FIG. 10 is a cross-sectional view taken along N-N' of the array substrate shown in FIG. 8. Here, since the auxiliary electrode 402 does not wrap with the common electrode layer 300, there is no need to provide a via V1 for wrapping the common electrode layer 300 and the common signal line 400. Thus, the number of vias V1 for wrapping the common electrode layer 300 and the common signal line 400 installed in the array substrate 000 can be effectively reduced.

[0058] Continuing to refer to FIGS. 6 to 8, the pixel electrode layer 200 is closer to the substrate 100 than the common electrode layer 300. The pixel electrode layer 200 in the array substrate 000 includes pixel electrodes 201 located within the sub-pixel region 00a, and the orthographic projection of the pixel electrode 201 onto the substrate 100 does not overlap with the orthographic projection of the electrode structure 400a onto the substrate 100.

[0059] In this case, when the electrode structure 400a is the wrap electrode 401, the wrap electrode 401 needs to be electrically connected to the common electrode 300 after passing through the pixel electrode layer 200. When the orthographic projection of the pixel electrode 201 onto the substrate 100 does not overlap with the orthographic projection of the electrode structure 400a onto the substrate 100, it is possible to avoid short-circuiting with the pixel electrode 201 when the wrap electrode 401 is electrically connected to the common electrode 300.

[0060] In addition, in other possible embodiments, the common electrode layer 300 can also be closer to the substrate 100 than the pixel electrode layer 200. In this case, the common electrode layer 300 can be directly electrically connected to the wrap electrode 401 via the via V1 and does not need to pass through the pixel electrode layer 200. Thus, the orthographic projection of the pixel electrode layer 200 onto the substrate 100 can overlap with the orthographic projection of the electrode structure 400a onto the substrate 100.

[0061] To more clearly understand the structure of the pixel electrode within the sub-pixel region, refer to FIG. 11, which is a schematic diagram of the structure of the array substrate within one sub-pixel region shown in FIG. 5. The pixel electrode 201 in the sub-pixel region 00a has a watermark engraving structure 201a. Within the same sub-pixel region 00a, the orthographic projection of the electrode structure 400a onto the substrate 100 is located within the orthographic projection of the watermark engraving structure 201a onto the substrate 100.

[0062] In this case, when the electrode structure 400a is the wrap electrode 401, the wrap electrode 401 needs to be electrically connected to the common electrode 300 after passing through the pixel electrode layer 200. On the other hand, when the pixel electrode 201 in the pixel electrode layer 200 has the watermark engraving structure 201a, it is possible to avoid short-circuiting with the pixel electrode 201 when the wrap electrode 401 is electrically connected to the common electrode 300.

[0063] Note that within each sub-pixel region 00a, a coupling capacitance is formed between the electrode structure 400a and the pixel electrode 201, and the magnitude of the coupling capacitance correlates with the distance between the outer boundary of the electrode structure 400a and the outer boundary of the pixel electrode 201.

[0064] In the embodiment of the present application, as shown in FIG. 5, the distance between the outer boundary of the orthographic projection of the electrode structure 400a onto the substrate 100 and the outer boundary of the orthographic projection of the watermark engraving structure 201a onto the substrate 100 within each sub-pixel region 00a is equal. In this way, it is possible to ensure that the coupling capacitance formed between the electrode structure 400a and the pixel electrode 201 is close. Also, the magnitude of the storage capacitance correlates with the magnitude of the coupling capacitance, and when the distance between the outer boundary of the orthographic projection of the electrode structure 400a onto the substrate 100 and the outer boundary of the orthographic projection of the watermark engraving structure 201a onto the substrate 100 is equal, since the area of the overlapping portion between the pixel electrode 201 and the common electrode line 400 is also the same, it is possible to ensure that the storage capacitance between the electrode structure 400a and the pixel electrode 201 within each sub-pixel region 00a is the same.

[0065] Continuing to refer to FIG. 11, the array substrate 000 further includes a plurality of transistors 900 located on the substrate 100, and the plurality of transistors 900 correspond one-to-one to the plurality of pixel electrodes 201. To more clearly understand the structure of the array substrate 000, refer to FIG. 12, which is a schematic diagram of the film layer at M-M' of the array substrate shown in FIG. 11. Here, one gate line 800 is electrically connected to the gates 904 of each transistor 900 in the transistors 900 of the same row, and the gate line 800 and the common signal line 400 are installed in the same layer and have the same material. The extending direction of the gate line 800 and the extending direction of the common signal line 400 are parallel. One data line 700 is electrically connected to the first poles 901 of each transistor 900 among the transistors 900 in the same column, and the second poles 902 of the transistors 900 are electrically connected to the corresponding pixel electrodes 201.

[0066] As an option, refer to FIG. 13. FIG. 13 is a partial enlarged view of the array substrate shown in FIG. 11 at E. Here, the first pole 901 is the source of the transistor 900, and the second pole 902 is the drain of the transistor 900. The transistor 900 includes a gate 904, a source 901, a drain 902, and an active layer 903.

[0067] Continuing to refer to FIG. 12, the array substrate 000 further includes a first insulating layer 500 located on the side away from the substrate 100 of the plurality of transistors 900, and a second insulating layer 600 located between the pixel electrode layer 200 and the common electrode layer 300. Here, the pixel electrode layer 200 is located on the side away from the substrate 100 of the first insulating layer 500, and the pixel electrode layer 200 is closer to the substrate 100 than the common electrode layer 300. Here, by installing the second insulating layer 600 between the pixel electrode layer 200 and the common electrode layer 300, a liquid crystal capacitance can be formed in the overlapping portion of the common electrode layer 300 and the pixel electrode layer 200.

[0068] In other possible embodiments, referring to FIG. 14, FIG. 14 is a schematic diagram of another film layer at M-M' of the array substrate shown in FIG. 11. A first insulating layer 500 is not provided between the transistor 900 and the pixel electrode 201, and the second electrode 902 of the transistor 900 directly wraps around the corresponding pixel electrode 201. In this way, the process steps can be reduced and the production cost can be lowered.

[0069] For any two adjacent transistors 900 among a row of transistors 900 electrically connected to the same data line 700, one transistor 900 is located on one side of the data line 700, and the other transistor 900 is located on the other side of the data line 700. Here, the polarities of the pixel voltages applied to the pixel electrodes 201 in each sub-pixel region 00a before and after column inversion are opposite, and the polarities of the pixel voltages applied to the pixel electrodes 201 in any two adjacent sub-pixel regions 00a before and after column inversion are also opposite.

[0070] Referring to FIG. 15, FIG. 15 is a schematic structural diagram of the common electrode layer of the array substrate shown in FIG. 5. The common electrode layer 300 in the array substrate 000 has a plurality of slits 301. In this way, an electric field in a direction parallel to the substrate 100 can be formed between the pixel electrode 201 in each pixel region 00a and the common electrode layer 300 having a plurality of slits 301, and the liquid crystal can be driven to be deflected along a direction parallel to the substrate 100 by this electric field.

[0071] As described above, the array substrate provided in the embodiment of the present application includes a substrate, a pixel electrode layer located on the substrate, a common electrode layer, and a plurality of common signal lines. A wrap electrode that wraps with the common electrode layer and an auxiliary electrode that does not wrap with the common electrode layer are simultaneously provided on the common electrode line. In this way, by effectively reducing the number of vias for wrapping the common electrode layer and the common signal lines installed in the array substrate, in the process of subsequently forming an alignment film on the array substrate, it can be ensured that the probability of non-uniform diffusion of the alignment liquid for forming the alignment film is low, and after subsequently integrating this array substrate into a display device, it can be ensured that the probability of luminance non-uniformity and the like occurring in the display device is low. Further, in the common electrode line, by simultaneously providing the wrap electrode and the auxiliary electrode, it can be ensured that the magnitude of the storage capacitance in the sub-pixel region where the wrap electrode is located is substantially the same as the magnitude of the storage capacitance in the sub-pixel region where the auxiliary electrode is located. And it can be ensured that the numerical value of △Vp corresponding to the pixel electrode in the sub-pixel region where the wrap electrode is located is substantially the same as the numerical value of △Vp corresponding to the pixel electrode in the sub-pixel region where the auxiliary electrode is located. Therefore, when the array substrate in the present application is integrated into a display device and the display device displays a screen in a column inversion method, the probability of occurrence of defective phenomena such as screen flickering and jitter in the screen displayed by the display device is low, effectively improving the display effect of the display device.

[0072] In the embodiment of the present application, a display device is further provided. As shown in FIG. 16, FIG. 16 is a schematic structural diagram of a film layer of the display device provided in the embodiment of the present application. The display device may include a color filter substrate 001, a liquid crystal layer 002, and any one of the above array substrates 000. The array substrate 000 and the color filter substrate 001 are installed opposite to each other, and the liquid crystal layer 002 is located between the array substrate 000 and the color filter substrate 001. In the embodiment of the present application, the display device may be any product or component having a display function, such as a liquid crystal panel, an electronic paper, a mobile phone, a tablet, a television, a display, a notebook computer, a digital photo frame, a navigator, etc.

[0073] Note that in the drawings, for the sake of clarity of the drawings, the dimensions of layers and regions may be exaggerated. And when an element or layer is said to be "on" another element or layer, it can be understood that it may be directly on the other element or there may be an intermediate layer. Also, when an element or layer is said to be "under" another element or layer, it can be understood that it may be directly under the other element or there may be one or more intermediate layers or elements. Further, when a layer or element is said to be "between" two layers or two elements, it can be understood that it may be the only layer between the two layers or two elements, or there may be one or more intermediate layers or elements. In this specification, similar reference numerals denote similar elements.

[0074] In the present application, the terms "first" and "second" are used only for the purpose of explanation and should not be construed as indicating or implying relative importance. The term "plurality" means two or more unless specifically limited.

[0075] The above are only selectable embodiments of the present application and are not used to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made in the spirit and principle of the present application should all be included within the protection scope of the present application.

Explanation of Reference Numerals

[0076] 000 Array substrate 00a Sub-pixel region 100 Substrate 200 Pixel electrode layer 300 Common electrode layer 400 Common signal line 400a Electrode structure 401 Wrap electrode 402 Auxiliary electrode

Claims

1. An array substrate having a plurality of sub-pixel regions, wherein the array substrate comprises a substrate, a pixel electrode layer and a common electrode layer located on the substrate, and a plurality of common signal lines located on the substrate, and the common signal lines are installed insulated from the pixel electrode layer and are electrically connected to the common electrode layer, and there is an overlapping region between the orthographic projection of the common signal lines on the substrate and the orthographic projection of the pixel electrode layer on the substrate, the common signal lines have a plurality of electrode structures, different ones of the electrode structures are located in different sub-pixel regions, and the plurality of electrode structures include a wrap electrode that wraps with the common electrode layer and an auxiliary electrode that does not wrap with the common electrode layer, an array substrate.

2. The orthographic projection of the auxiliary electrode on the substrate and the orthographic projection of the wrap electrode on the substrate are both the same in shape and area, the array substrate according to Claim 1.

3. The plurality of sub-pixel regions include at least two-color sub-pixel regions, the plurality of electrode structures correspond one-to-one to a plurality of sub-pixel regions within the same-color sub-pixel regions, and the electrode structures are located within the corresponding sub-pixel regions, the array substrate according to Claim 1.

4. In the same-color sub-pixel regions, for any two adjacent sub-pixel regions, the wrap electrode is distributed in one of the pixel regions and the auxiliary electrode is distributed in the other pixel region, the array substrate according to Claim 3.

5. The sub-pixel region in which the electrode structure is distributed is a blue sub-pixel region, the array substrate according to Claim 3.

6. The array substrate has a plurality of vias, the common electrode layer wraps with the wrap electrode through at least one of the vias, and the orthographic projection of the via on the substrate and the orthographic projection of the wrap electrode on the substrate overlap at least partially, the array substrate according to Claim 1.

7. A part of the orthographic projection of the via on the substrate is located within the orthographic projection of the wrap electrode on the substrate, and the other part is located outside the orthographic projection of the wrap electrode on the substrate, the array substrate according to Claim 6.

8. The pixel electrode layer is closer to the substrate than the common electrode layer, the pixel electrode layer includes pixel electrodes located within the sub-pixel regions, and the orthographic projection of the pixel electrodes onto the substrate does not overlap with the orthographic projection of the electrode structure onto the substrate. The array substrate according to any one of claims 1 to 5.

9. The pixel electrode has a watermark engraving structure, and within the same sub-pixel region, the orthographic projection of the electrode structure onto the substrate is located within the orthographic projection of the watermark engraving structure onto the substrate. The array substrate according to claim 8.

10. The distance between the outer boundary of the orthographic projection of the electrode structure onto the substrate and the outer boundary of the orthographic projection of the watermark engraving structure onto the substrate within each sub-pixel region is equal. The array substrate according to claim 9.

11. The array substrate further includes a plurality of data lines, a plurality of gate lines, and a plurality of transistors, and the plurality of transistors correspond one-to-one to the plurality of pixel electrodes. One of the gate lines is electrically connected to the gates of each of the transistors among the transistors in the same row, the gate line and the common signal line are installed in the same layer and have the same material, and the extending direction of the gate line and the extending direction of the common signal line are parallel. One of the data lines is electrically connected to the first poles of each of the transistors among the transistors in the same column, and the second poles of the transistors are electrically connected to the corresponding pixel electrodes. The array substrate according to claim 8.

12. For any two adjacent transistors among the transistors in a column electrically connected to the same data line, one of the transistors is located on one side of the data line, and the other transistor is located on the other side of the data line. The array substrate according to claim 11.

13. The array substrate further includes a first insulating layer located on the side of the plurality of transistors away from the substrate, and a second insulating layer located between the pixel electrode layer and the common electrode layer. The pixel electrode layer is located on the side of the first insulating layer away from the substrate. The array substrate according to claim 11.

14. The common electrode layer has a plurality of slits. The array substrate according to any one of claims 9 to 13.

15. A display device comprising a color filter substrate, a liquid crystal layer, and an array substrate according to any one of claims 1 to 14, wherein the array substrate and the color filter substrate are disposed to face each other, and the liquid crystal layer is located between the array substrate and the color filter substrate, a display device.

Images