Direct word line contact, and manufacturing method therefor of 3D memory

Abstract

A memory device having an array region and an extended region adjacent to the array region is described. The array region includes at least two unit cells stacked vertically. The extended region includes a memory stack and a plurality of word line contacts. The memory stack includes alternating layers of at least one conductive layer, a semiconductor layer, and an insulating layer. The plurality of word line contacts extend through the memory stack to at least one conductive layer. Each of the plurality of word line contacts has a height different from the height of an adjacent word line contact. Each of the plurality of word line contacts has a metallization layer on its top surface. A method of forming the memory device is described.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of electronic devices and electronic device manufacturing. More particularly, embodiments of the present disclosure provide three-dimensional (3D) dynamic random access memory cells.

Background Art

[0002] Electronic devices, such as personal computers, workstations, computer servers, mainframes, and other computer-related devices such as printers, scanners, and hard disk drives, use memory devices that provide a significant data storage capacity while consuming low power. There are two main types of random access memory cells, dynamic and static, which are suitable for use in electronic devices. Dynamic random access memory (DRAM) stores a voltage representing one of two binary values, but can be programmed to require periodic reprogramming or "refresh" to maintain this voltage for a period longer than a very short time period. Static random access memory (SRAM) is so called because it does not require periodic refresh.

[0003] DRAM memory circuits are manufactured by replicating millions of identical circuit elements known as DRAM cells on a single semiconductor wafer. Each DRAM cell is an addressable location capable of storing one bit (binary digit) of data. In its most common form, a DRAM cell consists of two circuit components, namely, a field effect transistor (FET) and a capacitor.

[0004] The manufacture of DRAM cells involves the manufacture of transistors, capacitors, and three contacts, namely, one contact to a bit line, one contact to a word line, and one contact to a reference voltage. DRAM manufacturing is an extremely competitive business. Especially in the case of densities greater than 256 megabits, there is a constant pressure to reduce the size of individual cells and increase the memory cell density in order to enable more memory to be packed onto a single memory chip. The limitations to cell size reduction include the passage of both active and passive word lines through the cell, the size of the cell capacitor, and the compatibility of the array device with non-array devices. The formation of a low-resistance contact between the active area and the 3D DRAM bottom electrode is essential for the performance of the device.

[0005] DRAM is composed of hundreds of sub-blocks. For each sub-block, word lines (WLs) and bit lines (BLs) are connected to a control circuit. Multiple cells are stacked in the 3D DRAM. Every word line of each stack should have a contact for connecting the word line to the control circuit in the sub-array. When nWL memory cells are stacked in the 3D DRAM, contacts for nWL are required in each column of the WL. Reduction of the WL contact area is important for reducing the chip area.

[0006] Therefore, in the art, there is a need for memory devices having a reduced chip area and methods of forming such memory devices. SUMMARY OF THE INVENTION

[0007] One or more embodiments of the present disclosure are directed to a memory device. In one or more embodiments, the memory device includes an array region including at least two unit cells stacked vertically, and an extended region adjacent to the array region, the extended region including a memory stack and a plurality of word line contacts, the memory stack including an alternating layer of at least one conductive layer, a semiconductor layer, and an insulating layer, the plurality of word line contacts extending through the memory stack to at least one conductive layer, each of the plurality of word line contacts having a height different from that of an adjacent word line contact, and each of the plurality of word line contacts having a metallization layer on a top surface.

[0008] Additional embodiments of the present disclosure are directed to a method of forming a memory device. In one or more embodiments, the method of forming a memory device includes forming a memory stack on a substrate, the memory stack including an alternating layer of at least one sacrificial layer, an insulating layer, and a semiconductor layer; patterning the memory stack to form a plurality of openings extending through the memory stack, each of the plurality of openings having a depth different from that of an adjacent opening; depositing an etch stop layer and a sacrificial fill layer in each of the plurality of openings; replacing at least one sacrificial layer of a unit cell with at least one conductive layer; removing the sacrificial fill layer in each of the plurality of openings to form a plurality of contact openings; removing a bottom portion of the etch stop layer; and depositing a conductive material in each of the plurality of contact openings to form a plurality of word line contacts, each of the plurality of word line contacts having a height different from that of an adjacent word line contact.

[0009] A further embodiment of the present disclosure is a non-transitory computer-readable medium including instructions that, when executed by a controller of a processing chamber, cause the processing chamber to form a memory stack on a substrate, the memory stack comprising alternating layers of at least one sacrificial layer, an insulating layer, and a semiconductor layer; pattern the memory stack to form a plurality of openings extending through the memory stack, each of the plurality of openings having a depth different from an adjacent opening; deposit an etch stop layer and a sacrificial fill layer in each of the plurality of openings; replace at least one sacrificial layer of a unit cell with at least one conductive layer; remove the sacrificial fill layer in each of the plurality of openings to form a plurality of contact openings; remove a bottom portion of the etch stop layer; and deposit a conductive material in each of the plurality of contact openings to form a plurality of word line contacts, each of the plurality of word line contacts having a height different from a height of an adjacent word line contact.

[0010] As the above-described features of the present disclosure can be understood in detail, a more detailed description of the present disclosure, briefly summarized above, can be made by referring to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the present disclosure may admit other equally effective embodiments, so the accompanying drawings merely show typical embodiments of the present disclosure and should not be regarded as limiting its scope. The embodiments described herein are presented by way of example and not limitation in the figures of the accompanying drawings, in which like reference numerals indicate like elements.

Brief Description of the Drawings

[0011]

Figure 1

Figure 2A

Figure 2B

Figure 2C

Figure 3A

Figure 3B

Figure 3C

Figure 4A

Figure 4B

Figure 4C

Figure 5A

Figure 5B

Figure 5C

Figure 6A

Figure 6B

Figure 6C

Figure 6D

Figure 7A

Figure 7B

Figure 7C

Figure 7D

Figure 8A

Figure 8B

Figure 8C

Figure 8D

Figure 9A

Figure 9B

Figure 9C

Figure 9D

Figure 10A

Figure 10B

Figure 10C

Figure 11A

Figure 11B

Figure 11C

Figure 11D

Figure 12A

Figure 12B

Figure 12C

Figure 12D

Figure 13A

Figure 13B

Figure 13C

Figure 14A

Figure 14B

Figure 15

Figure 16A

Figure 16B

Figure 16C

Figure 17

Figure 18A

Figure 18B

Figure 19A

Figure 19B

Figure 20A

Figure 20B

Figure 21A

Figure 21B

Figure 22A

Figure 22B

Figure 23

DETAILED DESCRIPTION OF THE INVENTION

[0012] Before describing some exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of the structures or process steps described in the following description. The present disclosure can have other embodiments and can be practiced or carried out in various ways.

[0013] In the following description, numerous specific details are set forth in order to provide a thorough understanding of one or more embodiments of the present disclosure. However, it will be apparent to those skilled in the art that one or more embodiments of the present disclosure may be practiced without these specific details. In other instances, semiconductor manufacturing processes, techniques, materials, equipment, etc. are not described in great detail so as to avoid unnecessarily obscuring this description. Those skilled in the art will be able to implement appropriate functions using the included description without undue experimentation.

[0014] Although some exemplary embodiments of the present disclosure are described and shown in the accompanying drawings, such embodiments are merely exemplary and do not limit the present disclosure. It should be understood that the present disclosure is not limited to the specific structures and arrangements illustrated and described, as modifications may be envisioned by those skilled in the art.

[0015] As used in this specification and the appended claims, the terms “precursor,” “reactant,” “reactive gas,” etc. are used interchangeably to refer to any gas species capable of reacting with the substrate surface.

[0016] According to one or more embodiments, the term “on” with respect to a film or layer of a film includes that the film or layer is immediately above a surface, e.g., a substrate surface, and that there is one or more underlying layers between the film or layer and the surface, e.g., the substrate surface. Thus, in one or more embodiments, the phrase “on the substrate surface” is intended to include one or more underlying layers. In other embodiments, the phrase “directly on” refers to a layer or film that contacts a surface, e.g., a substrate surface, without an intervening layer. Thus, the phrase “a layer directly on the substrate surface” refers to a layer that contacts the substrate surface directly without an intervening layer.

[0017] As used herein, "atomic layer deposition" or "cyclic deposition" refers to the sequential exposure of two or more reactive compounds to deposit a layer of material on a substrate surface. The substrate or a portion of the substrate is separately exposed to two or more reactive compounds introduced into the reaction zone of the processing chamber. In a time-domain ALD process, each exposure to a reactive compound is separated by a time delay to allow each compound to adsorb onto and / or react on the substrate surface and then be purged from the processing chamber. These reactive compounds are said to be exposed to the substrate sequentially. In a spatial ALD process, different portions of the substrate surface, or different portions of the material on the substrate surface, are simultaneously exposed to two or more reactive compounds, and thus any given point on the substrate is not substantially simultaneously exposed to more than one reactive compound. As used herein and in the appended claims, the term "substantially" in this context means, as would be understood by one of ordinary skill in the art, that a small portion of the substrate may potentially be simultaneously exposed to multiple reactive gases by diffusion and that such simultaneous exposure is unintended.

[0018] In one aspect of a time-domain ALD process, a first reactive gas (i.e., a first precursor or compound A, e.g., an aluminum precursor) is pulsed into the reaction zone, followed by a first time delay. Next, a second precursor or compound B (e.g., an oxidizing agent) is pulsed into the reaction zone, followed by a second delay. During each time delay, a purge gas, such as argon, is introduced into the processing chamber to purge the reaction zone or otherwise remove residual reactive compounds or reaction by-products from the reaction zone. Alternatively, the purge gas can flow continuously throughout the deposition process such that only the purge gas flows during the time delay between pulses of the reactive compounds. The reactive compounds are alternatively pulsed until the desired film or film thickness is formed on the substrate surface. In any scenario, the ALD process that pulses compound A, the purge gas, compound B, and the purge gas is a cycle. The cycle can start with either compound A or compound B and continue through each sequence of the cycle until a film with a predetermined thickness is achieved.

[0019] In one embodiment of a spatial ALD process, a first reactive gas and a second reactive gas (e.g., nitrogen gas) are supplied to the reaction zone simultaneously but are separated by an inert gas curtain and / or a vacuum curtain. The substrate is moved relative to the gas supply apparatus such that any given point on the substrate is exposed to the first reactive gas and the second reactive gas.

[0020] As used herein, "chemical vapor deposition" refers to a process in which a substrate surface is exposed to a precursor and / or co-reactant simultaneously or substantially simultaneously. As used herein, "substantially simultaneously" refers to either co-flow or cases where there is overlap for most of the exposure of the precursor.

[0021] Plasma enhanced chemical vapor deposition (PECVD) is widely used to deposit thin films due to cost efficiency and film property versatility. In a PECVD process, a hydrocarbon source, such as vapor of a gas-phase hydrocarbon or a liquid-phase hydrocarbon entrained in a carrier gas, is introduced into a PECVD chamber. A plasma-initiated gas, typically helium, is also introduced into the chamber. Then, a plasma is initiated in the chamber to create excited CH radicals. The excited CH radicals chemically bond to the surface of a substrate disposed in the chamber to form a desired film thereon. Embodiments described herein with respect to the PECVD process can be performed using any suitable thin film deposition system. Any apparatus description provided herein is exemplary and should not be construed or interpreted as limiting the scope of the embodiments described herein.

[0022] As used herein, the term “dynamic random access memory” or “DRAM” refers to a memory cell that stores data bits by storing packets of charge (i.e., binary 1) or no charge (i.e., binary 0) on a capacitor. The charge is gated onto the capacitor via an access transistor and detected by turning on the transistor and looking at the voltage perturbation created by dumping the charge packet onto an interconnect line at the transistor output. Thus, a single DRAM cell is made up of one transistor and one capacitor. A DRAM device is formed from an array of DRAM cells.

[0023] Conventionally, DRAM cells have embedded a high work function metal structure in an embedded word line structure. In a DRAM device, bit lines are formed at a metal level above the substrate and word lines are formed at a polysilicon gate level on the surface of the substrate. In an embedded word line (bWL), the word line is embedded below the surface of a semiconductor substrate using metal as a gate electrode.

[0024] In current 3D DRAM devices, a staircase structure is created, and word line contacts are formed on the staircase. However, to prevent a short circuit between the staircase and the word line contacts, the contact holes must have a large critical dimension, which becomes a problem during manufacturing. In one or more embodiments, a memory device is provided, which advantageously has word line contacts of varying heights, where the word line contacts connect a metallization layer to the conductive layer of the unit cell, which forms a reduced chip area and reduces processing difficulties. Thus, the method of one or more embodiments does not require the formation of a staircase structure. In the word line contacts of one or more embodiments, only the short circuit between contacts needs to be considered. Further, the contact structure of one or more embodiments advantageously serves as a support to prevent the collapse of the mold during the gate replacement process.

[0025] In one or more embodiments, metal deposition and other processes can be performed in an isolated environment (e.g., a cluster process tool). Thus, some embodiments of the present disclosure provide an integrated tool system having related process modules for implementing the method.

[0026] FIG. 1 shows a process flow diagram for a method 10 that can include any or all of the processes shown. Further, the order of the individual processes can vary for some portions. The method 10 can start at any of the processes listed without departing from the present disclosure. Referring to FIG. 1, at operation 12, a memory stack is formed. At operation 14, an opening is patterned in the memory stack. At operation 16, an etch stop layer is deposited through the opening. At operation 18, a sacrificial fill layer is deposited on the etch stop layer in the opening. At operation 20, the memory stack is slit patterned. At operation 22, the sacrificial layer of the memory stack is removed and replaced with a conductive layer. At operation 24, the sacrificial fill layer is removed to form contact openings. At operation 26, the slit is filled with an insulating material. At operation 28, the bottom portion of the etch stop layer is removed. At operation 30, a conductive material is deposited in the contact openings to form word line contacts.

[0027] FIGS. 2A-22B show cross-sectional views of a memory device during processing, according to the method of one or more embodiments.

[0028] Referring to FIGS. 2A-2C, a 3D DRAM device 100 includes an array region 101 and an extended region 103 adjacent to the array region 101. The extended region 103 connects memory cells to non-array nodes of the DRAM device. In one or more embodiments, the array region 101 includes at least two unit cells 105 stacked vertically. The unit cell 105 includes a transistor and a cell capacitor. In one or more embodiments, the extended region 103 includes a memory stack 111 and a plurality of word line contacts 136. In one or more embodiments, the memory stack 111 does not have a staircase structure and instead has a plurality of word line contacts 136 with different heights from the height of adjacent contacts.

[0029] Referring to FIGS. 3A - 3C, an initial or starting mold of the extended region 103 is formed in accordance with one or more embodiments of the present disclosure. FIG. 3B is a view along line A of FIG. 2C, and FIG. 3C is a view along line B of FIG. 2C. In some embodiments, the electronic device 103 shown in FIG. 3A is formed in layers on a bare substrate (not shown). In one or more embodiments, the electronic device of FIG. 3A is made from a substrate 102 and a unit stack 110. In one or more embodiments, the unit stack 110 includes an insulating layer 104, at least one sacrificial layer 106, and a semiconductor layer 108. In some embodiments, the unit stack 110 includes an insulating layer 104, a first sacrificial layer 106 on the insulating layer 104, a semiconductor layer 108 on the first sacrificial layer 106, and a second sacrificial layer 106b on the semiconductor layer 108. The repetition of the unit stack 110 stacked vertically on top of each other forms a memory stack 111 on the substrate. The memory stack 111 includes alternating layers of an insulating layer 104, at least one sacrificial layer 106, and a semiconductor layer 108.

[0030] The substrate 102 can be any suitable material known to those skilled in the art. As used herein and in the appended claims, the term "substrate" refers to the surface or a portion of the surface on which a process acts. Also, those skilled in the art will understand that a reference to a substrate can refer to only a portion of the substrate, unless the context clearly indicates otherwise. Further, a reference to a deposition on a substrate can mean both a bare substrate and a substrate on which one or more films or features have been deposited or formed thereon.

[0031] As used herein, "substrate" refers to any substrate or the surface of a material formed on a substrate on which film processing is performed during the manufacturing process. For example, the substrate surface on which processing can be performed can be, depending on the application, materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. The substrate includes, but is not limited to, semiconductor wafers. The substrate can be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to performing film processing directly on the surface of the substrate itself, in the present disclosure, any of the disclosed film processing steps can also be performed on a lower layer formed on the substrate as disclosed in more detail below, and the term "substrate surface" is intended to include such a lower layer as the context indicates. Thus, for example, when a film / layer or a partial film / layer is deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0032] In one or more embodiments, an insulating layer 104 is on the top surface of a substrate 102. The insulating layer 104 can be formed by any suitable technique known to those skilled in the art and can be made of any suitable material. In one or more embodiments, the insulating layer 104 includes silicon oxide (SiO x ).

[0033] In one or more embodiments, a first sacrificial layer 106 is on the insulating layer 104. The first sacrificial layer 106 can include any suitable material known to those skilled in the art. In one or more embodiments, the first sacrificial layer 106 includes silicon nitride (SiN).

[0034] In one or more embodiments, a semiconductor layer 108 can be formed on the first sacrificial layer 106. The semiconductor layer 108 may also be referred to as an active layer or a memory layer.

[0035] As used herein, the terms "active" or "memory layer" refer to a layer of material in which channels, bit lines, word lines, or capacitors can be fabricated. In one or more embodiments, the active layer, or semiconductor layer 108, includes one or more of silicon or doped silicon. In some embodiments, the semiconductor layer 108 may include a semiconductor material that is a doped material, such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In some embodiments, the semiconductor layer 108 may be doped using any suitable process, such as an ion implantation process. As used herein, the term "n-type" refers to a semiconductor layer 108 created by doping with an electron donor element during manufacture. The term n-type is derived from the negative charge of electrons. In an n-type semiconductor material layer, electrons are the majority carriers and holes are the minority carriers. As used herein, the term "p-type" refers to the positive charge of a well (or hole). In contrast to an n-type semiconductor material, a p-type semiconductor material has a hole concentration greater than its electron concentration. In a p-type semiconductor material layer, holes are the majority carriers and electrons are the minority carriers. In one or more embodiments, the dopant is selected from one or more of boron (B), gallium (Ga), phosphorus (P), arsenic (As), other semiconductor dopants, or combinations thereof. In some embodiments, the semiconductor layer 108 includes several different conductive or semiconductor materials.

[0036] The first sacrificial layer 106 and the insulating layer 104 can be formed on the substrate 102 and can be made of any suitable material. In some embodiments, one or more of the first sacrificial layer 106 and the insulating layer 104 can be removed and replaced in a later process. In some embodiments, one or more of the first sacrificial layer 106 and the insulating layer 104 are not removed and remain within the memory device 100. In this case, the term "sacrificial" has an extended meaning to include permanent layers and may also be referred to as a conductive layer. In one or more embodiments, one or more of the first sacrificial layer 106 and the insulating layer 104 include materials that can be selectively removed with respect to the layers of an adjacent memory stack.

[0037] In the illustrated embodiment, the memory stack 111 includes a plurality of alternating sacrificial layers 106, insulating layers 104, and semiconductor layers 108. As shown in FIG. 3A, the memory stack 111 has four sets of alternating sacrificial layers 106, insulating layers 104, and semiconductor layers 108, but those skilled in the art will recognize that this is merely for illustrative purposes. The memory stack 111 can have any number of alternating sacrificial layers 106, insulating layers 104, and semiconductor layers 108. For example, in some embodiments, the memory stack 111 includes 192 pairs of alternating sacrificial layers 106, insulating layers 104, and semiconductor layers 108. In other embodiments, the memory stack 111 includes more than 50 pairs of alternating sacrificial layers 106, insulating layers 104, and semiconductor layers 108, or more than 100 pairs of alternating sacrificial layers 106, insulating layers 104, and semiconductor layers 108, or more than 300 pairs of alternating sacrificial layers 106, insulating layers 104, and semiconductor layers 108.

[0038] In one or more embodiments, successive depositions are used to form a number of active area regions. In one or more embodiments, alternating layers of films, such as oxide-polysilicon, polysilicon-nitride, oxide-nitride, silicon-silicon germanium, oxide-nitride-silicon-nitride are deposited.

[0039] In one or more embodiments, the sacrificial layer 106 independently includes an insulating material. In one or more embodiments, the sacrificial layer 106 includes a nitride material, such as silicon nitride, and the insulating layer 104 includes an oxide material, such as silicon oxide. The sacrificial layer 106 includes a material that is etch-selective with respect to the insulating layer 104 and the semiconductor layer 108 such that the sacrificial layer 106 can be removed without substantially affecting the insulating layer 104 and the semiconductor layer 108. In one or more embodiments, the sacrificial layer 106 includes silicon nitride (SiN). In one or more embodiments, the insulating layer 104 includes silicon oxide (SiO x) is included. In one or more embodiments, the sacrificial layer 106, the insulating layer 104, and the semiconductor layer 108 are deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0040] Individual alternating layers can be formed to any suitable thickness. In some embodiments, the thickness of each sacrificial layer 106 is substantially equal. In one or more embodiments, each sacrificial layer 106 has a sacrificial layer thickness. In some embodiments, the thickness of each insulating layer 104 is substantially equal. The substantially equal thickness used in this regard is within + / - 5% of each other. In some embodiments, a semiconductor layer 108, such as silicon, is formed between the first sacrificial layer 106 and the second sacrificial layer 106b of the unit stack 110. The thickness of the semiconductor layer 108 can be relatively thin compared to the thickness of the sacrificial layer 106 and the insulating layer 104.

[0041] In one or more embodiments, the insulating layer 104 has a thickness in the range of about 0.5 nm to about 30 nm, including about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm. In one or more embodiments, the insulating layer 104 has a thickness in the range of about 0.5 to about 40 nm. In one or more embodiments, the sacrificial layer 106 has a thickness in the range of about 0.5 nm to about 30 nm, including about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm. In one or more embodiments, the sacrificial layer 106 has a thickness in the range of about 0.5 to about 40 nm.

[0042] Referring to FIGS. 4A - 4C, the device is patterned to form insulating openings 109 for insulation between cells.

[0043] Referring to FIGS. 5A - 5C, the insulating opening 109 is filled with an insulating material 109i. The insulating material 109i can be any suitable insulating material known to those skilled in the art. In one or more embodiments, the insulating material 109i is a dielectric material. As used herein, the term "dielectric material" refers to a layer of material that is an electrical insulator and can be polarized in an electric field. In one or more embodiments, the insulating material 109i includes one or more of oxides, carbon - doped oxides, silicon oxide (SiO), porous silicon dioxide (SiO 2 ), silicon nitride (SiN), silicon oxide / nitride, carbides, oxycarbides, nitrides, oxynitrides, oxycarbonitrides, polymers, silicate glasses, fluorosilicate (SiOF) glasses, or organosilicate (SiOCH) glasses. In one or more embodiments, the insulating material 109i includes silicon oxide (SiO x ).

[0044] Referring to FIGS. 6A - 6D, the device 103 is patterned to form an opening 112. In some embodiments, patterning the opening 112 includes etching through the memory stack 111. In one or more embodiments, the semiconductor layer 108 acts as an etch stop. Referring to FIG. 6A, the opening 112 extends through the memory stack 111 and has sidewalls that expose the surfaces of the sacrificial layer 106, the insulating layer 104, and the semiconductor layer 108.

[0045] In one or more embodiments, each of the openings 112 has a depth different from the depth of the adjacent openings 112. In one or more embodiments, the openings 112 have a depth within the range of nLayer×tUnit ranging from 1.5 μm to 50 μm, where nLayer, the number of stacks, is from 50 layers to 500 layers, and tUnit (the thickness of the unit mold) ranges from 30 nm to 100 nm.

[0046] The sacrificial layer 106, the semiconductor layer 108, and the insulating layer 104 have surfaces that are exposed as sidewalls of the opening 112. The bottom of the opening 112 can be formed at any point within the thickness of the semiconductor layer 108. In some embodiments, the opening 112 extends into the semiconductor layer at a thickness within the range of about 10% to about 90% of the thickness of the semiconductor layer 108, or within the range of about 20% to about 80% of the thickness of the semiconductor layer 108, or within the range of about 30% to about 70% of the thickness of the semiconductor layer 108, or within the range of about 40% to about 60% of the thickness of the semiconductor layer 108. In some embodiments, the opening 112 extends into the semiconductor layer 108 at a distance only greater than or equal to 10%, 20%, 30%, 40%, 50%, 60%, 70% or 80% of the thickness of the semiconductor layer 108.

[0047] Referring to FIGS. 7A - 7D, an insulating layer 114 is conformally deposited in each of a plurality of high aspect ratio openings 112. The conformal film used in this way has a thickness near the top of the feature that is within the range of about 80 - 120% of the thickness at the bottom of the feature. The insulating layer 114 can be any suitable material known to those skilled in the art. In one or more embodiments, the insulating layer 114 (or liner) comprises one or more of silicon oxide (SiO x ) and silicon nitride (SiN). In some embodiments, the insulating layer 114 functions as an etch stop layer in a later processing step.

[0048] Referring to FIGS. 8A - 8D, the sacrificial layer 116 is deposited in a plurality of openings 112 adjacent to the insulating layer 114. The sacrificial layer 116 can be any suitable material known to those skilled in the art. In one or more embodiments, the sacrificial layer 116 includes one or more of tungsten (W), silicon germanium (SiGe), germanium (Ge), carbon (C), titanium nitride (TiN), etc. In subsequent processing, the sacrificial layer 116 will be replaced with the conductive material 134 after the formation of the replacement gate. In one or more embodiments, the plurality of openings 112 are filled in a bottom - up gap - filling process that fills the features from the bottom. In other embodiments, the plurality of openings 112 are filled using a conformal process where the features are filled from the bottom and the sides.

[0049] FIGS. 9A - 9D illustrate the operation 20 of method 10, where the device is slit - patterned to form a slit - pattern opening 120 that extends from the top surface of the memory stack 111 to the substrate 102.

[0050] Referring to FIGS. 10A - 10C, the sacrificial layer 106 (i.e., silicon nitride (SiN)) is selectively removed through the slit - patterned opening 120 to form the opening region 118. In one or more embodiments, the sacrificial layer 106, for example, the nitride layer, is removed through the slit - patterned opening 120 using high - temperature phosphorus (HP).

[0051] Referring to FIGS. 11A - 11D, a gate oxide layer 124 is deposited over the insulating layer 104 through an opening 120. The gate oxide layer 124 can include any suitable material known to those skilled in the art. The gate oxide layer 124 can be deposited using one or more deposition techniques known to those skilled in the art. In one or more embodiments, the gate oxide layer 124 is deposited using one of the deposition techniques such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin - on, or other deposition techniques known to those skilled in the art. The illustrated embodiment shows the gate oxide layer 124 as a conformal layer having a uniform shape. However, those skilled in the art will recognize that this is for illustrative purposes only and that the gate oxide layer 124 can be formed isotropically such that the gate oxide layer 124 has a rounded appearance. In some embodiments, the gate oxide layer 124 is selectively deposited as a conformal layer on the surface of the insulating layer 104. In some embodiments, the gate oxide layer 124 is formed by oxidation of the semiconductor surface.

[0052] In one or more embodiments, the gate oxide layer 124 comprises silicon oxide (SiO x ). The term "silicon oxide" can be used to describe the gate oxide layer 124, but those skilled in the art will recognize that the present disclosure is not limited to a particular stoichiometry. For example, both the terms "silicon oxide" and "silicon dioxide" can be used to describe a material having silicon atoms and oxygen atoms in any suitable stoichiometric ratio. The same applies to other materials listed in the present disclosure, such as silicon nitride, silicon oxynitride, tungsten oxide, zirconium oxide, aluminum oxide, hafnium oxide, etc.

[0053] In one or more embodiments, a word line is then formed in the opening 118. The word line includes one or more of the barrier layer 126 and the word line metal 122. The barrier layer 126 can include any suitable barrier layer known to those skilled in the art. In one or more embodiments, the barrier layer 126 includes one or more of titanium nitride (TiN), tantalum nitride (TaN), etc. In one or more embodiments, the word line metal 122 includes a bulk metal including one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh). In one or more embodiments, the word line metal 122 includes tungsten (W). In other embodiments, the word line metal 122 includes ruthenium (Ru).

[0054] Referring to FIGS. 12A - 12D, the slit pattern opening 120 is filled with an insulating material 128. The insulating material 128 can include any suitable material known to those skilled in the art. In one or more embodiments, the insulating material 128 includes silicon oxide (SiO x ). In one or more embodiments, the insulating material 128 is a sacrificial material that is removed in a subsequent process.

[0055] Referring to FIGS. 13A - 13C, the sacrificial layer 116 is removed to form a plurality of contact openings 130. The sacrificial layer 116 can be removed by any suitable technique known to those skilled in the art. In one or more embodiments, the sacrificial layer 116 is removed by one or more of wet etching or dry etching. Each of the plurality of contact openings 130 has a depth different from the depth of the contact opening adjacent to each of the plurality of contact openings 130. Each contact opening 130 extends from the top surface of the device 103 to the semiconductor layer 108. In one or more embodiments, the critical dimension of each of the contact openings 130 is in the range from 100 nm to 2000 nm.

[0056] Referring to FIGS. 14A and 14B, a portion of the insulating layer 114 at the bottom of each of the plurality of contact openings 130 is removed to form a portion 131 of the contact opening 130 without the insulating layer 114. Referring to FIG. 15, in one or more embodiments, the semiconductor layer 108, the gate oxide layer 124, and the conductive layer 122 that are delaying the bottom of the plurality of contact openings 130 are enlarged using a selective removal process (SRP).

[0057] Referring to FIGS. 16A-16C, a barrier layer 133 is conformally deposited in each of the plurality of contact openings 130. The barrier layer 133 can include any suitable material known to those skilled in the art. In one or more embodiments, the barrier layer 133 includes titanium nitride (TiN).

[0058] Referring to FIG. 17, a conductive layer 134 is deposited in the plurality of contact openings 130 to form contacts. In one or more embodiments, the plurality of contact openings 130 are filled in a bottom-up gap filling process that fills the features from the bottom. In other embodiments, the plurality of contact openings 130 are filled using a conformal process in which the features are filled from the bottom and the sides. The conductive layer 134 can include any suitable material known to those skilled in the art. In one or more embodiments, the conductive layer 134 includes tungsten (W).

[0059] Referring to FIGS. 18A and 18B, the insulating material 109i is removed to form the opening 160. The insulating material 109i can be removed by any suitable means known to those skilled in the art.

[0060] Referring to FIGS. 19A-19B, the semiconductor layer 108 is removed and the sacrificial layer 106 is trimmed to form the opening 234. The opening 234 can be enlarged or trimmed to create an enlarged opening 234. The opening 234 can be enlarged by any suitable technique known to those skilled in the art. In some embodiments, the opening 234 is enlarged by a ratio of the thickness of the semiconductor layer 108. In some embodiments, the opening 234 is enlarged by an amount in the range of 10% to 80% of the thickness of the semiconductor layer 108. In some embodiments, the opening 234 is enlarged by an amount in the range of 20% to 75% or in the range of 30% to 60%. In some embodiments, the opening 234 is enlarged using diluted HF (about 1% HF in water) wet etching.

[0061] Referring to FIGS. 20A-20B, in one or more embodiments, the liner at the bottom of the contact is removed.

[0062] Referring to FIGS. 21A-21B, the bit line 238 is formed in the filled slit pattern opening. In one or more embodiments, the bit line 238 can include an optional bit line liner (also referred to as a bit line barrier layer) and bit line metal.

[0063] Any bit line liner can be made from any suitable material deposited by any suitable technique known to those skilled in the art. In one or more embodiments, the bit line liner is deposited on the source / drain region at the inner end of the active material. The bit line liner can be any suitable material, including but not limited to titanium nitride (TiN) or tantalum nitride (TaN). In some embodiments, the optional bit line liner comprises or consists essentially of titanium nitride (TiN). The term "consists essentially of" as used in this context means that the composition of the film is the stated species greater than or equal to about 95%, 98%, 99% or 99.5%. In some embodiments, the optional bit line liner comprises or consists essentially of tantalum nitride (TaN). In some embodiments, the bit line liner is a conformal layer. In some embodiments, the bit line liner is deposited by atomic layer deposition.

[0064] In some embodiments, bit line 238 includes bit line metal. The bit line metal can include any suitable metal known to those skilled in the art. In one or more embodiments, the bit line metal comprises or consists essentially of one or more of tungsten silicide (WSi), tungsten nitride (WN), or tungsten (W). The bit line metal can be deposited by any suitable technique known to those skilled in the art and can be any suitable material. In one or more embodiments, forming bit line 238 further includes forming a bit line metal seed layer (not shown) prior to depositing the bit line metal.

[0065] Referring to FIGS. 22A and 22B, the extended region 103 of the 3D DRAM device connects the memory cells to the non-array nodes of the DRAM device. In one or more embodiments, the extended region 103 comprises a memory stack 111 and a plurality of word line contacts 136. In one or more embodiments, the memory stack 111 does not have a staircase structure. Instead, it has a plurality of word line contacts 136 with heights that are different from the height of adjacent contacts respectively.

[0066] The memory stack 111 comprises alternating layers of at least one conductive layer 122, a semiconductor layer 108, and an insulating layer 104. The plurality of word line contacts 136 extend through the memory stack 111 to at least one conductive layer 122. Each of the plurality of word line contacts 136 has a height different from the height of adjacent word line contacts 136, and each of the plurality of word line contacts 136 has a metallization layer 138 on its top surface.

[0067] In one or more embodiments, each of the word line contacts 136 includes a first region a, a second region b, and a third region c. The second region b is located between the first region a and the third region c. In one or more embodiments, the third region c is larger than the second region b.

[0068] In one or more embodiments, the first region and the third region are connected to one or more of the metallization layer 138 and at least one conductive layer 122. The second region b can be surrounded by a liner 114. In one or more embodiments, the liner 114 is adjacent to at least one conductive layer 122, the insulating layer 104, and the semiconductor layer 108.

[0069] Additional embodiments of the present disclosure are directed to a processing tool 900 for the formation of the described memory devices and methods, as shown in FIG. 23. The cluster tool 900 includes at least one central transfer station 921, 931 having a plurality of sides. Robots 925, 935 are disposed within the central transfer stations 921, 931 and are configured to move the robot blades and wafers to each of the plurality of sides.

[0070] The cluster tool 900 includes a plurality of process chambers 902, 904, 906, 908, 910, 912, 914, 916, and 918, also referred to as process stations, connected to the central transfer station. The various process chambers provide separate processing areas isolated from adjacent process stations. The process chambers can be any suitable chambers, including, but not limited to, a pre-cleaning chamber, a buffer chamber, one or more transfer spaces, a wafer orienter / gas-venting chamber, a cryo cooling chamber, a deposition chamber, an annealing chamber, an etching chamber, a selective etching chamber, etc. The specific arrangement of the process chambers and components can vary depending on the cluster tool and should not be taken as limiting the scope of the present disclosure.

[0071] In the embodiment shown in FIG. 23, a factory interface 950 is connected to the front of the cluster tool 900. The factory interface 950 includes a loading chamber 954 and an unloading chamber 956 on the front surface 951 of the factory interface 950. The loading chamber 954 is shown on the left side and the unloading chamber 956 is shown on the right side, but those skilled in the art will understand that this represents only one possible configuration.

[0072] The sizes and shapes of the loading chamber 954 and the unloading chamber 956 can vary, for example, according to the substrates processed in the cluster tool 900. In the illustrated embodiment, the loading chamber 954 and the unloading chamber 956 are sized to hold a wafer cassette, and a plurality of wafers are placed within the cassette.

[0073] The robot 952 is within the factory interface 950 and can move between the loading chamber 954 and the unloading chamber 956. The robot 952 can transfer wafers from a cassette in the loading chamber 954 through the factory interface 950 to the load lock chamber 960. The robot 952 can transfer wafers from the load lock chamber 962 through the factory interface 950 to a cassette in the unloading chamber 956. As will be understood by those skilled in the art, the factory interface 950 can have two or more robots 952. For example, the factory interface 950 can have a first robot that transfers wafers between the loading chamber 954 and the load lock chamber 960 and a second robot that transfers wafers between the load lock 962 and the unloading chamber 956.

[0074] The illustrated cluster tool 900 has a first section 920 and a second section 930. The first section 920 is connected to the factory interface 950 through load lock chambers 960, 962. The first section 920 includes a first transfer chamber 921 in which at least one robot 925 is disposed. The robot 925 is also referred to as a robot wafer transport mechanism. The first transfer chamber 921 is centrally located with respect to the load lock chambers 960, 962, process chambers 902, 904, 916, 918, and buffer chambers 922, 924. The robot 925 in some embodiments is a multi-arm robot capable of independently moving two or more wafers at a time. In some embodiments, the first transfer chamber 921 includes two or more robot wafer transfer mechanisms. The robot 925 in the first transfer chamber 921 is configured to move wafers between the chambers around the first transfer chamber 921. Individual wafers are transported onto a wafer transport blade located at the distal end of the first robot mechanism.

[0075] After processing the wafers in the first section 920, the wafers can be passed through a pass-through chamber to the second section 930. For example, the chambers 922, 924 can be unidirectional or bidirectional pass-through chambers. The pass-through chambers 922, 924 can be used, for example, to cryo cool the wafers before processing in the second section 930 or to enable wafer cooling or post-processing before moving back to the first section 920.

[0076] System controller 990 communicates with a first robot 925, a second robot 935, a first plurality of processing chambers 902, 904, 916, 918 and a second plurality of processing chambers 906, 908, 910, 912, 914. The system controller 990 can be any suitable component capable of controlling the processing chambers and the robots. For example, the system controller 990 can be a computer including a central processing unit (CPU), a memory, suitable circuitry, and storage.

[0077] The process can generally be stored in the memory of the system controller 990 as a software routine that, when executed by a processor, causes the process chambers to perform the processes of the present disclosure. The software routine can also be stored and / or executed by a second processor (not shown) located remotely from the hardware controlled by the processor. Also, some or all of the methods of the present disclosure can be implemented in hardware. Thus, the process can be implemented in software and executed on a computer system in hardware, for example, as an application specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. The software routine, when executed by a processor, converts a general-purpose computer into a special-purpose computer (controller) that controls the chamber operations such that the process is performed.

[0078] Spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein for ease of description to describe the relationship of one or more other elements or features to a particular element or feature shown in the figures. It will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, an element described as "beneath" or "below" another element or feature will be oriented "above" those other elements or features. Thus, the exemplary term "below" can encompass both an upward and a downward orientation. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0079] In the context of the description of the materials and methods described herein (in particular, in the context of the following claims), the use of the terms "a", "an", and "the", and similar designators, should be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by the context. Recitation of ranges of values herein is merely intended to serve as a shorthand way of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated herein as if it were individually recited herein. All methods described herein can be performed in any suitable order, unless otherwise indicated herein or otherwise clearly contradicted by the context. The use of any and all examples, or exemplary language (e.g., "such as") provided herein is merely intended to better illustrate the materials and methods and does not impose a limitation on the scope unless otherwise claimed. Words in this specification should not be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0080] References throughout this specification to "one embodiment", "certain embodiments", "one or more embodiments", or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, appearances of the phrases "in one or more embodiments", "in certain embodiments", or "in an embodiment" in various places throughout this specification are not necessarily referring to the same embodiment of the present disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0081] The disclosure of this specification has been described with reference to particular embodiments, but those skilled in the art will understand that the described embodiments are merely illustrative of the principles and uses of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatuses of the present disclosure without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure can include modifications and variations that are within the scope of the appended claims and their equivalents.

Claims

1. An array region including at least two unit cells stacked in a vertical direction, and An extended region adjacent to the array region, the extended region including a memory stack and a plurality of word line contacts, the memory stack including an alternating layer of at least one conductive layer, a semiconductor layer, and an insulating layer, the plurality of word line contacts extending through the memory stack to the at least one conductive layer, each of the plurality of word line contacts having a height different from that of an adjacent word line contact, and each of the plurality of word line contacts having a metallization layer on a top surface, the extended region A memory device comprising.

2. The memory device according to claim 1, wherein the plurality of word line contacts connect the metallization layer to the at least one conductive layer.

3. The memory device according to claim 1, wherein each of the plurality of word line contacts includes a first region, a second region, and a third region.

4. The memory device according to claim 3, wherein the first region and the third region are connected to one or more of the metallization layer and the at least one conductive layer.

5. The memory device according to claim 3, wherein the second region is located between the first region and the third region.

6. The memory device according to claim 3, wherein the second region is surrounded by a liner.

7. The memory device according to claim 6, wherein the liner is adjacent to the at least one conductive layer, the insulating layer, and the semiconductor layer.

8. The memory device according to claim 3, wherein the third region is larger than the second region.

9. The memory device according to claim 1, wherein the memory device is a 3D DRAM device.

10. A method of manufacturing a memory device, the method comprising: Forming a memory stack on a substrate, the memory stack including an alternating layer of at least one sacrificial layer, an insulating layer, and a semiconductor layer; and Patterning the memory stack to form a plurality of openings extending through the memory stack, each of the plurality of openings having a depth different from that of an adjacent opening. Depositing an etching stop layer and a sacrificial fill layer in each of the plurality of openings; Replacing the at least one sacrificial layer of the unit cell with at least one conductive layer; Removing the sacrificial fill layer in each of the plurality of openings to form a plurality of contact openings; Removing a bottom portion of the etching stop layer; Depositing a conductive material in each of the plurality of contact openings to form a plurality of word line contacts, wherein each of the plurality of word line contacts has a height different from the height of an adjacent word line contact; A method comprising. **Claim 11** The method according to claim 10, wherein the memory device is a 3D DRAM device. **Claim 12** The method according to claim 10, wherein the at least one sacrificial layer comprises silicon nitride. **Claim 13** The method according to claim 10, wherein the insulating layer comprises one or more of silicon oxide and silicon nitride. **Claim 14** The method according to claim 10, wherein the conductive material of the plurality of word line contacts comprises one or more of titanium nitride (TiN) and tungsten (W). **Claim 15** The method according to claim 10, further comprising slit patterning the device to form at least one slit opening adjacent to the plurality of openings. **Claim 16** The method according to claim 15, wherein the at least one sacrificial layer is removed and replaced through the at least one slit opening to form the at least one conductive layer. **Claim 17** The method according to claim 16, wherein the at least one conductive layer comprises a gate oxide layer comprising a material selected from one or more of titanium nitride (TiN) and tungsten (W). **Claim 18** The method according to claim 16, further comprising filling the slit opening with an insulating material. **Claim 19** The method according to claim 10, wherein the method is performed in a processing tool without breaking vacuum. **Claim 20** A non-transitory computer-readable medium comprising instructions that, when executed by a controller of a processing chamber, cause the processing chamber to Forming a memory stack on a substrate, wherein the memory stack comprises alternating layers of at least one sacrificial layer, an insulating layer, and a semiconductor layer; Patterning the memory stack to form a plurality of openings extending through the memory stack, wherein each of the plurality of openings has a depth different from that of an adjacent opening; Depositing an etch stop layer and a sacrificial fill layer in each of the plurality of openings; Replacing the at least one sacrificial layer with at least one conductive layer; Removing the sacrificial fill layer in each of the plurality of openings to form a plurality of contact openings; Removing a bottom portion of the etch stop layer; Depositing a conductive material in each of the plurality of contact openings to form a plurality of word line contacts, wherein each of the plurality of word line contacts has a height different from that of an adjacent word line contact; A non-transitory computer-readable medium for causing operations to be performed.

Images