Recovery Annealing of Metal Oxide Thin Film Transistors

Abstract

A method of forming a TFT is provided, the method including forming a buffer layer on a substrate. A metal oxide channel layer is formed on the buffer layer and the channel layer is annealed. A gate insulator layer is formed on the channel layer and an ILD is deposited on the gate insulator layer to form a TFT. The TFT is annealed with respect to first annealing conditions to form an annealed TFT. The annealed TFT is shorted or includes a first threshold voltage of about 0 volts or less. The annealed TFT is annealed with respect to second annealing conditions to form a regenerated TFT having a second threshold voltage greater than the first threshold voltage. The second annealing conditions include a temperature of about 150 °C to about 275 °C.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to thin film transistor (TFT) devices for enhancing electrical performance and device stability, and methods for processing such devices.

Background Art

[0002] A thin film transistor (TFT) is formed by depositing thin films of an active semiconductor layer, a dielectric layer, and a metal contact on a support substrate such as glass. In particular, the TFT can be a metal oxide semiconductor field effect transistor (MOSFET).

[0003] Due to its high resolution, low power consumption, and high-speed operation for liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays, thin-film transistors (TFTs) have gained significant interest in display applications. TFTs are embedded in the panels of displays. To control the displayed image by turning the TFTs in the active display panel area on and off, the TFTs in the pixel circuits are supplied with data line voltage signals from source driver integrated circuits (ICs) in the display module and scan line voltage signals from gate driver circuits in the peripheral display panel area of the display panel. By improving the response of the TFTs through higher mobility and / or reducing crosstalk between pixels, image distortion is reduced. Most display products, including LCD or OLED televisions (TVs) and monitors, contain TFTs in the panel. Many of the latest high-resolution and high-quality electronic visual display devices use active matrix-based OLED displays that include a large number of TFTs as components of the pixel circuits. One beneficial aspect of TFT technology is the use of separate TFTs for each pixel on the display. Each TFT functions as a switch or current source within the pixel circuit or gate driver circuit by controlling the voltage and current of the data signal line and gate signal line to enhance the control of the displayed image. The higher on-current from high-mobility TFTs enables fast refresh of the displayed image and better image quality by minimizing distortion of the data signal voltage and gate signal voltage.

[0004] During the manufacture of TFTs for certain devices such as low-temperature polycrystalline oxide (LTPO) displays, the TFTs can be sensitive to the integration process, resulting in insufficient uniformity, extremely high conductivity, or electrical short circuits. Although several techniques are used to enhance device performance, conventional techniques can often only be used for certain integration processes and have other drawbacks.

[0005] Accordingly, there is a need for a method of manufacturing stable TFTs that can be widely applied to a wide range of TFTs with different integration processes. SUMMARY OF THE INVENTION

[0006] In some embodiments, a method of forming a thin film transistor (TFT) is provided. The method includes forming a buffer layer on a substrate. A metal oxide channel layer is formed on the buffer layer. The method includes annealing the metal oxide channel layer after forming the metal oxide channel layer. A gate insulator layer is formed on the metal oxide channel layer. The method includes depositing an interlayer dielectric (ILD) on the gate insulator layer to form a TFT. The method includes annealing the TFT with respect to a first annealing condition to form an annealed TFT. The method includes annealing the annealed TFT with respect to a second annealing condition to form a regenerated TFT having a second threshold voltage greater than a first threshold voltage, and the second annealing condition includes a temperature of about 150 °C to about 275 °C.

[0007] In some embodiments, a method of forming a thin film transistor (TFT) is provided. The method includes forming a buffer layer on a substrate and forming a metal oxide channel layer on the buffer layer. The method includes annealing the metal oxide channel layer at a temperature of about 140 °C to about 240 °C for about 5 minutes to about 30 minutes after forming the metal oxide channel layer. A gate insulator layer is formed on the metal oxide channel layer. The gate insulator layer is annealed. The method includes depositing an interlayer dielectric (ILD) on the gate insulator layer and annealing the TFT with respect to a first annealing condition to form an annealed TFT. The method includes annealing the annealed TFT with respect to a second annealing condition in the presence of air to form a regenerated TFT having a second threshold voltage greater than a first threshold voltage. The second annealing condition includes annealing at a temperature of about 150 °C to about 275 °C.

[0008] In some embodiments, a method for processing a thin film transistor (TFT) is provided. The method includes providing a TFT including a silicon-containing buffer layer, a metal oxide channel layer, a gate insulator layer, and an interlayer dielectric (ILD). The TFT is annealed with respect to first annealing conditions to form an annealed TFT. The annealed TFT is annealed with respect to second annealing conditions to form a regenerated TFT. The second annealing conditions include a temperature of about 150 °C to about 275 °C.

[0009] To better understand the features of the present disclosure listed above, by referring to the embodiments, a more detailed description of the present disclosure briefly outlined above can be obtained, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings only show exemplary embodiments, and thus should not be regarded as limiting the scope, and other equally valid embodiments may be acceptable.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

[0011] For ease of understanding, where possible, the same reference numerals have been used to denote the same elements common to the figures. It is contemplated that elements and features of one embodiment can be beneficially incorporated into other embodiments without further recitation.

[0012] Embodiments of the present disclosure generally provide a TFT device structure having enhanced electrical performance and stability for a display device and a method of forming the TFT structure. In particular, top-gate TFT devices are sensitive to conventional integration processes. Small process variations in operating parameters can significantly increase the non-uniformity of the films deposited on the substrate. Forming low-temperature polycrystalline silicon oxide (LTPO) involves forming an interlayer dielectric and annealing the interlayer dielectric. Annealing the TFT can cause the TFT to electrically short-circuit or increase the conductivity to a value that makes the TFT unusable for its intended application. Conventional methods for addressing and preventing or solving the problem of TFT short-circuiting were specialized for integration, such as changing the film properties in certain individual layers to achieve a uniform and acceptably stable final TFT performance.

[0013] In contrast, the method described herein provides a process for regenerating a short-circuited or highly conductive TFT into a TFT usable for an LTPO product. This regeneration process restores the voltage threshold of the short-circuited or highly conductive TFT independently of the process in which the TFT is integrated. Further, in the process described herein, the entire TFT is processed without adjusting the individual layers. This regeneration process includes annealing the TFT at a temperature of about 275°C or less, such as a temperature of about 200°C to about 250°C, for 30 minutes to 12 hours, such as about 60 minutes to about 120 minutes.

[0014] Gate insulator layer cutting integration FIG. 1 shows a process flow diagram of an exemplary method 100 for forming a thin film transistor according to some embodiments. Method 100 includes, in activity 102, forming a buffer layer on a substrate. As used herein, the term "substrate" includes any suitable material such as a silicon-based substrate, a semiconductor-based substrate, an insulating-based substrate, and a germanium-based substrate. In some embodiments, this substrate includes one or more layers present in an LTPO device. The substrates described herein can include transparent materials such as hard glass or flexible polyimide, or other materials useful for displays. In some embodiments, this buffer layer is an insulating material, for example, silicon nitride (SiN x ), silicon oxide (SiO x ), multilayer silicon nitride / silicon oxide (SiN x / SiO y ), silicon oxynitride (SiON), or other silicon-containing materials, or other insulating materials, or combinations thereof. Any layer deposited herein can be deposited using conventional processes, such as chemical vapor deposition such as plasma chemical vapor deposition.

[0015] Method 100 includes, in activity 104, forming a metal oxide channel layer over a buffer layer, and in activity 106, annealing the metal oxide channel layer after forming the metal oxide channel layer. The metal oxide channel layer can include InGaZnO, InZnO, InSnO, InGaO, InGaSnO, InGaZnSnO, InGaZnON, ZnO, ZnON, ZnSnO, CdSnO, GaSnO, TiSnO, CuAlO, SrCuO, LaCuOS, GaN, InGaN, AlGaN, InGaAlN, or combinations thereof. In some embodiments, the metal oxide channel layer includes a single layer or multiple sub-layers. In some embodiments, the metal oxide channel layer is annealed at a temperature of about 130°C to about 500°C, such as about 140°C to about 400°C, for about 5 minutes to about 60 minutes, such as about 10 minutes to about 20 minutes. In some embodiments, the channel layer is deposited to a thickness of about 300 Å to about 500 Å. In some embodiments, forming the metal oxide channel layer includes flowing a mixed gas at a pressure of about 0.1 Pa to about 0.8 Pa, such as about 0.2 Pa to about 0.5 Pa. The mixed gas includes about 2 vol% to about 80 vol% oxygen gas, such as about 10 vol% to about 50 vol%, such as about 20 vol% to about 40 vol%.

[0016] In activity 108, a gate insulator layer is formed over the metal oxide channel layer. The gate insulator layer can be formed to a thickness of about 1000 Å to about 2000 Å. The gate insulator layer can include an insulating material such as silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof. In some embodiments, the gate insulator layer is formed by co-flowing a silicon-containing gas such as silane and a nitrogen-containing gas such as nitrogen oxide. In some embodiments, for example, for a 680 mm × 880 mm substrate, the silicon-containing gas is flowed at a flow rate of about 100 sccm to about 250 sccm, such as about 150 sccm to about 170 sccm, and the nitrogen-containing gas is flowed at a flow rate of about 5000 sccm to about 15000 sccm, such as about 10000 sccm.

[0017] This method includes, at activity 110, etching a portion of the gate insulator layer. In some embodiments, etching a portion of the gate insulator layer includes forming a gate over an inner portion of the gate insulator layer and exposing an outer portion of the gate insulator layer to a plasma such as a helium-containing plasma. The outer portion of the gate insulator layer is etched to expose portions of the channel layer. Those portions of the channel layer are exposed to this plasma.

[0018] At activity 112, an interlayer dielectric is deposited over the gate insulator layer to form a TFT. This interlayer dielectric can be a single layer of about 3000 Å to about 5000 Å. At activity 114, this TFT is annealed under a first annealing condition to form an annealed TFT. At activity 116, this annealed TFT can be annealed under a second annealing condition to form a regenerated TFT.

[0019] FIG. 2 shows a schematic side cross-sectional view of a thin film transistor in a manufacturing stage according to some embodiments. The TFT of FIG. 2 can be formed using a method of forming a TFT such as method 100. This TFT includes a substrate 202, a buffer layer disposed over substrate 204, e.g., the buffer layer described in activity 102 of method 100, a channel layer 206, e.g., the channel layer described in activity 104 of method 100, a gate insulator layer 208, e.g., the gate insulator layer described in activity 106 of method 100, and a gate electrode 210 disposed over gate insulator layer 208.

[0020] FIG. 3 shows a schematic cross-sectional view of a TFT after etching a portion of the gate insulator layer 208 as described in activity 110 of method 100. A portion of the gate insulator layer 208 is etched, exposing a portion 306 of the channel layer 206. As shown in FIG. 4, an interlayer dielectric 412 is deposited over the gate electrode 210. A portion of the interlayer dielectric 412 is etched to form a connection between the portion 306 of the channel layer and the source and drain electrodes 414A, 414B. In some embodiments, the TFT shown in FIG. 4 is considered a top-gate TFT formed by a gate insulator etch integration process. In some embodiments, the as-deposited TFT includes an as-deposited threshold voltage (Vth) of from about -5V to about 20V, such as from about 0.5V to about 2V, such as from about 1V to about 1.5V. In some embodiments, the as-deposited TFT includes an as-deposited electron mobility (μ) of from about 12 cm 2 / (V·sec) to about 14 cm 2 / (V·sec), and an as-deposited subthreshold slope (SS) of from about 0.1V / decade to about 0.6V / decade, such as from about 0.18V / decade to about 0.25V / decade.

[0021] After depositing the interlayer dielectric 412, the TFT is annealed under the first annealing conditions described in activity 112 of method 100. In some embodiments, the first annealing conditions include a first temperature of about 250° C. or greater, such as from about 260° C. to about 280° C., for a first duration of from about 5 minutes to about 90 minutes, such as from about 20 minutes to about 40 minutes. The first annealing conditions include annealing the TFT in the presence of nitrogen gas. After the first duration, the TFT threshold voltage drops to a threshold voltage lower than the threshold voltage of the as-deposited TFT prior to the first annealing conditions. In some embodiments, after the first duration, the TFT is electrically shorted or the threshold voltage is negative.

[0022] Following the annealing of the TFT under the first annealing conditions, the annealed TFT is transferred to a furnace and heated to the second annealing conditions described in activity 114 of method 100. The second annealing conditions include annealing the annealed TFT at a second temperature lower than the first temperature. In some embodiments, the second annealing conditions include a temperature of about 275 °C or less, such as from about 150 °C to about 260 °C, such as about 250 °C. The second annealing conditions include a second duration of about 30 minutes or more, such as from about 45 minutes to about 12 hours, such as from about 60 minutes to about 180 minutes, such as from about 90 minutes to about 120 minutes. The second annealing conditions include the presence of air, such as the presence of more than 90 volume % air. In some embodiments, the second annealing conditions include a nitrogen-containing gas, an oxygen-containing gas, or a combination thereof. In some embodiments, the second annealing conditions include a vacuum condition. The regenerated TFT includes a threshold voltage greater than the threshold voltage of the annealed TFT, such as a threshold voltage from about -2.5 V to about 1 V, such as from about -1 V to about 0.5 V. In some embodiments, the threshold voltage is about 0, such as within about 0 to about 0.25 V. The regenerated TFT includes an electron mobility substantially the same as the as-deposited electron mobility, such as an electron mobility within about 10% of the as-deposited electron mobility, such as from about 13 cm 2 / (V·s) to about 14 cm 2 / (V·s). The regenerated TFT includes a subthreshold slope substantially the same as the as-deposited subthreshold slope, such as a subthreshold slope within about 10% of the as-deposited subthreshold slope, such as from about 0.1 V / decade to about 0.6 V / decade, such as from about 0.18 V / decade to about 0.25 V / decade.

[0023] Ion implantation integration FIG. 5 shows a process flow diagram of an exemplary method 500 for forming a thin film transistor using an ion implantation integration process, according to some embodiments. Method 500 includes, at activity 502, forming a buffer layer on a substrate. In some embodiments, forming the buffer layer at activity 502 is substantially the same as forming the buffer layer described at activity 102 of method 100.

[0024] Method 500 includes, at activity 504 similar to activity 104 of method 100, forming a metal oxide channel layer on the buffer layer, and at activity 506 similar to activity 106, annealing the metal oxide channel layer after forming the metal oxide channel layer. In some embodiments, this metal oxide channel layer is annealed at a temperature of about 300°C to about 400°C, such as about 300°C to about 350°C, for about 30 minutes to about 90 minutes, such as about 30 minutes to about 60 minutes. In some embodiments, this channel layer is deposited to a thickness of about 300 Å to about 500 Å. In some embodiments, forming the metal oxide channel layer includes flowing a mixed gas at a pressure of about 0.1 Pa to about 0.8 Pa, such as about 0.2 Pa to about 0.5 Pa. The mixed gas includes about 2 vol% to about 80 vol% oxygen gas, such as about 10 vol% to about 50 vol%, such as about 20 vol% to about 40 vol%.

[0025] Form an insulating gate layer over the metal oxide channel layer with an activity 508 similar to the activity 108 of method 100. This insulating gate layer can be formed to a thickness of about 1000 Å to about 2000 Å. This insulating gate layer can include an insulating material such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. In some embodiments, this insulating gate layer is formed by flowing a silicon-containing gas such as silane and a nitrogen-containing gas such as nitrogen oxide together. In some embodiments, for example, for a 680 mm × 880 mm substrate, the silicon-containing gas is flowed at a flow rate of about 100 sccm to about 250 sccm, for example, about 150 sccm to about 170 sccm, and the nitrogen-containing gas is flowed at a flow rate of about 5000 sccm to about 15000 sccm, for example, about 10000 sccm.

[0026] Method 500 includes, in activity 510, implanting ions such as boron ions into the metal oxide channel layer. In some embodiments, after forming a gate electrode over the insulating gate layer, as shown in FIG. 6, the ions pass through the insulating gate layer 608 and are implanted into the metal oxide channel layer 606. In some embodiments, before implantation, the insulating gate layer is annealed at a temperature of about 300 °C to about 360 °C for about 30 minutes to about 90 minutes, for example, about 60 minutes.

[0027] In activity 512, deposit an interlayer dielectric over the insulating gate layer to form a TFT. In some embodiments, an implantation energy of about 20 keV to about 60 keV, for example, about 30 keV to about 40 keV and about 10 14 cm -2 ~ about 10 16 cm -2At an implantation dose of [[ID=]], expose the gate insulator layer to ions. In some embodiments, the interlayer dielectric is a single layer of about 500 Å to about 8000 Å, such as about 3000 Å to about 5000 Å. In some embodiments, the interlayer dielectric is a plurality of layers, such as a first sublayer of about 500 Å to about 3500 Å, such as about 1500 Å to about 3000 Å, a second sublayer of about 500 Å to about 3500 Å, such as about 1500 Å to about 3000 Å, and a third sublayer of about 500 Å to about 3500 Å, such as about 1000 Å to about 1500 Å. In activity 514, anneal this TFT under a first annealing condition to form an annealed TFT. In activity 516, this annealed TFT can be annealed under a second annealing condition to form a regenerated TFT.

[0028] FIG. 6 shows a schematic side cross-sectional view of a thin film transistor in a manufacturing stage according to some embodiments. The TFT of FIG. 6 can be formed using a method of forming a TFT such as method 500. This TFT includes a substrate 202, a buffer layer 204 disposed on the substrate 202, such as the buffer layer 204 described in activity 502 of method 500, a channel layer 206, such as the channel layer described in activity 504 of method 500, a gate insulator layer 608, such as the gate insulator layer described in activity 508 of method 500, and a gate electrode 210 disposed on the gate insulator layer 208. A portion 606 of the channel layer 206 contains ions such as boron ions implanted therein.

[0029] FIG. 7 shows a schematic cross-sectional view of a TFT after the implantation described in method 500. A portion of the gate insulator layer 208 is etched to expose a portion 706 of the channel layer 206. As shown in FIG. 7, an interlayer dielectric 712 is deposited over the gate electrode 210. A portion of the interlayer dielectric 412 is etched to form a connection between the portion 706 of the channel layer and the source and drain electrodes 714A, 714B. In some embodiments, the TFT shown in FIG. 7 is considered a top-gate TFT formed by an implantation integration process. In some embodiments, the as-deposited TFT includes a turn-on voltage of about -5V to about 20V, such as about -2.5V to about 1V, such as about -2.1V to -1V, for an implanted TFT without annealing the gate insulator layer, or about 0.25V to about 0.6V for a TFT formed by annealing the gate insulator layer. In some embodiments, the as-deposited TFT has an electron mobility of about 2.5 cm 2 (V·s) to about 15 cm 2 (V·s), such as about 3.0 cm 2 (V·s) to about 3.5 cm 2 (V·s) or about 12.0 cm 2 (V·s) to about 13.0 cm 2 (V·s). In some embodiments, the as-deposited subthreshold slope (SS) is about 0.1 V / decade to about 0.6 V / decade, such as about 0.15 V / decade to about 0.40 V / decade, such as about 0.18 V / decade to about 0.35 V / decade.

[0030] After depositing the interlayer dielectric 712, the TFT is annealed under the first annealing conditions described in activity 514 of method 500. In some embodiments, for example, for a TFT in which the gate insulator layer has not been annealed, the first annealing conditions include a first temperature of about 250° C. or higher, such as about 300° C. to about 380° C., for a first duration of about 5 minutes to about 90 minutes, such as about 20 minutes to about 40 minutes. The first annealing conditions include annealing the TFT in the presence of nitrogen gas. After the first duration, the threshold voltage of the TFT decreases to a threshold voltage lower than the threshold voltage of the as-deposited TFT. In some embodiments, after the first duration, the threshold voltage is lower than zero, such as about -2V or less, such as about -5V or less, such as about -10V or less. Alternatively, after the first duration, the TFT is electrically shorted.

[0031] Following the annealing of the TFT with the gate insulating layer not annealed under the first annealing condition, transfer the annealed TFT to a furnace and heat it to the second annealing condition described in activity 516 of method 500. The second annealing condition includes annealing the annealed TFT at a second temperature lower than the first temperature in the first annealing condition. In some embodiments, the second annealing condition includes a temperature of about 275 °C or lower, such as from about 225 °C to about 260 °C, such as about 250 °C. The second annealing condition includes a second duration of about 30 minutes or more, such as from about 45 minutes to about 12 hours, such as from about 60 minutes to about 3 hours. In some embodiments, the second annealing condition includes the presence of air, such as the presence of more than 90% by volume of air. In some embodiments, the second annealing condition includes a nitrogen-containing gas, an oxygen-containing gas, or a combination thereof. In some embodiments, the second annealing condition includes a vacuum condition. The regenerated TFT includes a threshold voltage greater than the threshold voltage of the annealed TFT, such as a threshold voltage from about -2.5 V to about 1 V, such as from about -1 V to about 0.5 V. In some embodiments, the threshold voltage is about 0, such as within about 0 to about 0.25 V. The regenerated TFT includes an electron mobility substantially the same as the as-deposited electron mobility, such as an electron mobility within about 10% of the as-deposited electron mobility, such as from about 12 cm 2 (V·s) to about 14 cm 2 (V·s). The regenerated TFT includes a subthreshold slope substantially the same as the as-deposited subthreshold slope, such as a subthreshold slope within about 10% of the as-deposited subthreshold slope, such as a subthreshold slope from about 0.08 V / decade to about 0.25 V / decade.

[0032] In some embodiments, for example, for a TFT with an annealed gate insulator layer, the first annealing condition includes a single temperature of about 300 °C or higher, such as about 320 °C to about 360 °C, for a single duration of about 5 minutes to about 90 minutes, such as about 10 minutes to about 20 minutes. The first annealing condition includes annealing the TFT in the presence of nitrogen gas. After this single duration, the TFT is electrically short-circuited.

[0033] Following the annealing of the TFT under the first annealing condition, the annealed TFT is transferred to a furnace and heated to the second annealing condition described in activity 516 of method 500. The second annealing condition includes annealing the annealed TFT at a third temperature lower than the first temperature, the second temperature, a single temperature, or both. In some embodiments, the second annealing condition includes a temperature of about 275 °C or lower, such as about 225 °C to about 260 °C, such as about 250 °C. The second annealing condition includes a duration of about 30 minutes or longer, such as about 45 minutes to about 12 hours, such as about 1 hour to about 3 hours, such as about 60 minutes to about 90 minutes. In some embodiments, the second annealing condition includes the presence of air, such as the presence of more than 90% by volume of air. In some embodiments, the second annealing condition includes a vacuum condition. The regenerated TFT includes a threshold voltage greater than the threshold voltage of the annealed TFT, such as a threshold voltage of about -2V to about 0.5V, such as about -1V to about 0V. In some embodiments, the threshold voltage is about 0, such as within about 0 to about 0.5V. The regenerated TFT includes an electron mobility substantially the same as the as-deposited electron mobility, such as an electron mobility within about 10% of the as-deposited electron mobility, such as about 13 cm 2 / (V·s) to about 15 cm 2 / (V·s). The regenerated TFT includes a subthreshold slope substantially the same as the as-deposited subthreshold slope, such as a subthreshold slope within about 10% of the as-deposited subthreshold slope, such as a subthreshold slope of about 0.1V / decade to about 0.3V / decade.

Example

[0034] Several samples were formed for each of the integration processes listed in Table 1.

[0035] [Table 1]

[0036] Integrated types B1, B2, and B3 were each formed by depositing a silicon nitride layer on a substrate to a thickness of about 1000 Å. A silicon oxide layer was formed on the silicon nitride layer to a thickness of about 3000 Å. The substrates of integrated types B1 and B2 further included an IGZO channel layer deposited to a thickness of about 400 Å at a pressure of 0.2 Pa. The substrate of integrated type B3 further included an IGZO channel layer deposited at a pressure of about 0.4 Pa. For each of integrated types B1, B2, and B3, depositing the channel layer included exposing the substrate to a mixed gas containing argon, oxygen, or a combination thereof. In some embodiments, one or more target materials were sputtered by oxygen or argon in the mixed gas. In some embodiments, the target materials to be sputtered included indium, gallium, zirconium, and combinations thereof. For integrated types B1 and B2, the mixed gas was made to contain about 20% by volume of oxygen. For integrated type B3, the mixed gas was made to contain about 50% by volume of oxygen. For integrated types B1 and B2, the IGZO channel layer was annealed at about 350 °C for 1 hour. For integrated type B3, the IGZO channel layer was annealed at about 141 °C for 10 minutes. For each of B1, B2, and B3, a gate insulator layer was deposited on the IGZO layer at a temperature of about 270 °C to about 280 °C. The gate insulator layer was deposited to a thickness of about 1500 Å. Depositing the gate insulator included flowing silane and dinitrogen monoxide together. For B3, the gate insulator was annealed at about 330 °C for 1 hour. For integrated types B2 and B3, the samples were subjected to boron ion implantation as described in method 500. For integrated type B1, the samples were formed using the gate insulator cutting integration process described in method 100. The samples formed using integrated types B1 and B2 included an interlayer dielectric having a thickness of 4000 Å. The samples formed using integrated type B3 included three sublayers, namely, a sublayer having a thickness of about 2000 Å (e.g., SiO sublayer), a sublayer having a thickness of 2000 Å (e.g., SiO sublayer), and a sublayer having a thickness of 1000 Å (e.g., SiN sublayer).

[0037]

Table 2

[0038] The values of the threshold voltage, electron mobility, and subthreshold voltage of the substrate formed using integration type B1 before ILD annealing are summarized and shown in Table 2. The substrate formed using integration type B1 after ILD annealing at a temperature of about 300 °C for 15 minutes was short-circuited. Subsequently, the short-circuited TFT was annealed at a lower temperature of about 250 °C for about 1 hour in the presence of air. The TFT was regenerated and had a negative threshold voltage. When the TFT was annealed for an additional 1 hour, the threshold voltage increased to near zero.

[0039] The as-deposited threshold voltage values of the substrate formed using integration type B2 before ILD annealing are summarized and shown in Table 2. Table 2 further summarizes and shows the current and gate voltage values of the sample TFT after ILD annealing at 275 °C for about 30 minutes in the presence of a nitrogen-containing gas. Compared with the sample before annealing, the threshold voltage value shifted to a more negative threshold voltage in the annealed substrate. For the intended purpose of the TFTs, those highly conductive TFTs were not suitable for use. Usually, short-circuited TFTs or highly conductive TFTs are discarded as not suitable for use. Subsequently, those highly conductive TFTs were annealed at a lower temperature of about 250 °C for about 1 hour in the presence of air. As shown in Table 2, it was shown that the threshold voltage was regenerated near zero.

[0040] Table 2 summarizes the threshold voltage values as-deposited before ILD annealing of the substrates formed using the integrated type B3. Table 2 shows a summary of the threshold voltage, electron mobility, and subthreshold voltage. Those TFTs were ILD annealed at 340 °C for about 15 minutes in the presence of a nitrogen-containing gas. The TFTs short-circuited. Then, as shown in Table 2, the short-circuited TFTs were annealed at a lower temperature of about 250 °C for about 1 hour in the presence of air. The TFTs were regenerated and had a threshold voltage near zero.

[0041] As shown by the examples, it has been found that the low-temperature annealing method described herein is effective for various TFTs regardless of how the TFTs are integrated. Further, the annealing method described herein showed a higher threshold voltage uniformity compared to the threshold voltage uniformity of the TFTs before low-temperature annealing, over several samples of TFTs formed using the same process. In particular, the bias temperature stress test performed on the as-deposited TFTs before regeneration showed a greater variation between the TFTs integrated using the same integration process. The same bias temperature stress test can be performed on the regenerated TFTs. The regenerated TFTs processed using any of the methods described herein show less variation and higher stability than the as-deposited TFTs. The stability test can include applying a gate voltage, such as a voltage of about 10 V to about 30 V, to the gate electrode of the TFT. The TFTs can be heated to about 50 °C to about 70 °C for a predetermined duration, for example, about 300 seconds, 600 seconds, 900 seconds, 1800 seconds, or 3600 seconds, and it can be seen whether the TFT transfer curve moves during one or more of those predetermined durations, for example, during each of the durations of 300 seconds, 600 seconds, 900 seconds, 1800 seconds, and 3600 seconds. A small movement indicates stability, and a larger movement indicates lower stability. It is possible to test the TFTs using both negative and positive voltages.

Claims

1. A method of forming a thin film transistor (TFT), comprising: forming a buffer layer on a substrate; forming a metal oxide channel layer on the buffer layer; annealing the metal oxide channel layer after forming the metal oxide channel layer; forming a gate insulator layer on the metal oxide channel layer; depositing an interlayer dielectric (ILD) on the gate insulator layer to form the TFT; annealing the TFT with respect to first annealing conditions to form an annealed TFT, wherein the annealed TFT is short-circuited or includes a first threshold voltage; and annealing the annealed TFT with respect to second annealing conditions to form a regenerated TFT having a second threshold voltage greater than the first threshold voltage, wherein the second annealing conditions include a temperature of about 150°C to about 275°C. A method comprising the above steps.

2. The method according to claim 1, further comprising annealing the gate insulator layer at a temperature of about 200°C to about 350°C for about 60 minutes to about 120 minutes after forming the gate insulator layer.

3. The method according to claim 1, wherein the first annealing conditions include annealing in the presence of a nitrogen-containing gas.

4. The method according to claim 1, wherein forming the metal oxide channel layer includes flowing a mixed gas at a pressure of about 0.1 Pa to about 0.8 Pa, and the mixed gas includes about 2 vol% to about 80 vol% oxygen gas.

5. The method according to claim 1, wherein the metal oxide is selected from indium gallium zinc oxide (IGZO), InGaZnON, ZnO, ZnON, ZnSnO, CdSnO, GaSnO, TiSnO, CuAlO, SrCuO, LaCuOS, GaN, InGaN, AlGaN, InGaAlN, or combinations thereof.

6. The method according to claim 1, wherein the buffer layer includes silicon nitride, silicon oxide, or combinations thereof.

7. The method according to claim 1, wherein the first annealing conditions include annealing the TFT at a temperature of about 250°C or higher for a first duration.

8. The method according to claim 1, wherein the second annealing conditions include annealing for about 30 minutes to about 12 hours.

9. The method according to claim 1, further comprising doping ions into the metal oxide channel layer.

10. A thin film transistor (TFT) comprising: A buffer layer on a substrate; A metal oxide channel layer disposed on the buffer layer; A gate insulator layer disposed on the metal oxide channel layer; An interlayer dielectric (ILD) disposed on the gate insulator layer; The TFT is annealed under a first annealing condition to reduce the threshold voltage of the TFT, and then annealed under a second annealing condition to increase the threshold voltage of the TFT to about 0 V or more. A thin film transistor (TFT).

11. The TFT according to claim 10, wherein the metal oxide channel layer is deposited to a thickness of about 300 Å to about 500 Å.

12. The TFT according to claim 10, further comprising an interlayer dielectric having a first sublayer having a first thickness of about 500 Å to about 3500 Å, a second sublayer having a second thickness of about 500 Å to about 3500 Å, and a third sublayer having a third sublayer having a thickness of about 500 Å to about 3500 Å.

13. The TFT according to claim 10, further comprising an interlayer dielectric having a thickness of about 500 Å to about 8000 Å.

14. The TFT according to claim 10, wherein the first annealing condition includes annealing the TFT at a temperature of about 300 °C or higher for about 5 minutes to about 90 minutes.

15. The TFT according to claim 10, wherein the second condition includes a duration of about 30 minutes to about 12 hours.

16. A method of processing a TFT, comprising: Providing the TFT including a silicon-containing buffer layer, a metal oxide channel layer, a gate insulator layer, and an interlayer dielectric (ILD); Annealing the TFT under a first annealing condition to form an annealed TFT having a first threshold voltage; and Annealing the annealed TFT under a second annealing condition to form a regenerated TFT having a second threshold voltage greater than the first threshold voltage, wherein the second annealing condition includes a temperature of about 150 °C to about 275 °C. A method including.

17. The method according to claim 16, wherein the annealed TFT has a first threshold voltage of about 0 volts or less or is electrically short-circuited.

18. The method according to claim 16, wherein the first annealing condition includes annealing the TFT at a temperature of about 250°C or higher.

19. The method according to claim 16, wherein the second threshold voltage of the regenerated TFT is about 0 V or higher.

20. The method according to claim 16, wherein the electron mobility of the regenerated TFT is equal to or greater than the electron mobility of the TFT before annealing.

Images