Testing device for bonded structures

Abstract

A bonded structure for testing a semiconductor device and a method for testing a semiconductor device are disclosed. The bonded structure may include a test element and one or more semiconductor elements. The test element may include test circuitry. The test element may be bonded to or embedded within the semiconductor device. The test element may be configured to test the semiconductor device. The test element may be configured to test a first semiconductor device to which it is bonded, as well as other semiconductor devices bonded to the first semiconductor device.

Description

[Technical field]

[0001] The technical field relates to self-test devices for bonded structures, and more particularly to self-test elements having self-test circuitry.

[0002] [Citation to Related Applications] This application is a claim of the benefit of U.S. Provisional Patent Application No. 63 / 344,772, filed on March 23, 2022, entitled "TESTING ELEMENTS FOR BONDED STRUCTURES," which is incorporated by reference in its entirety. [Background technology]

[0003] Semiconductor devices, particularly systems on chips (SoCs), are becoming increasingly complex while decreasing in feature size. As SoCs and semiconductor devices become more complex, the importance of testing the functionality of these devices increases. However, providing test circuitry that adequately tests the critical active circuits of a chip without increasing the chip's footprint is a challenge. Thus, improved self-test devices and processes continue to be needed. Summary of the Invention

[0004] In one aspect, a bonded structure is described that includes a first semiconductor device having a first active circuit portion and a test device having test circuit portion, the test device being adhesive-free direct bonded to the first semiconductor device along a bonding interface, the test circuit portion being configured to test functionality of at least a portion of the first active circuit portion of the first semiconductor device.

[0005] In some embodiments, the test element further comprises a memory configured to store the results of the test. In some embodiments, the test element is smaller than the first semiconductor element. A first non-conductive bonding layer of the first semiconductor element is directly bonded to a second non-conductive bonding layer of the test element without an intervening adhesive, and a first contact feature of the first semiconductor element is directly bonded to a second contact feature of the test element without an intervening adhesive. In some embodiments, the test element further comprises a plurality of signal contact pads. In some embodiments, a majority of the plurality of signal contact pads are configured to test at least a portion of the first active circuit portion.

[0006] In another aspect, a bonded structure is described having a first semiconductor device with test circuitry and a second semiconductor device adhesive-free direct bonded to the first semiconductor device along a bonding interface, the second semiconductor device having first active circuitry, the test circuitry configured to test functionality of at least a portion of the first active circuitry of the second semiconductor device.

[0007] In some embodiments, the testing circuitry is further configured to store the results of the functionality of at least a portion of the first active circuitry. In some embodiments, the first non-conductive bonding layer of the first semiconductor element is directly bonded to the second non-conductive bonding layer of the testing element without an intervening adhesive, and the first contact feature of the first semiconductor element is directly bonded to the second contact feature of the second semiconductor element without an intervening adhesive. In some embodiments, the bonded structure further comprises a third semiconductor element having a second active circuitry, the third semiconductor element being directly bonded to the second semiconductor element, and the testing circuitry is configured to test the functionality of at least a portion of the second active circuitry. In some embodiments, the bonded structure further comprises a fourth semiconductor element having a third active circuitry, the fourth semiconductor element being directly bonded to the third semiconductor element.

[0008] In some embodiments, the first semiconductor device further comprises a fourth active circuit portion. In some embodiments, the test circuit portion of the first semiconductor device is configured to test at least a portion of the functionality of the first active circuit portion, the second active circuit portion, the third active circuit portion, and / or the fourth active circuit portion. In some embodiments, the bonded structure further comprises a third semiconductor device having a second active circuit portion, the third semiconductor device being directly bonded to the first semiconductor device, and the test circuit portion is configured to test at least a portion of the functionality of the second active circuit portion. In some embodiments, the first semiconductor device includes a test chip. In some embodiments, the test chip is configured to test only the active circuit portion of one or more other semiconductor devices, and the test chip is free of other active circuit portions. The bonded structure further includes a third semiconductor element having a second active circuit portion and a second bonding layer bonded to the second semiconductor element without adhesive, and the test circuit portion is configured to test functionality of at least a portion of the third active circuit portion.

[0009] In some embodiments, the bonded structure further comprises a fourth semiconductor element having a third bonding layer adhesivelessly bonded to the third active circuitry and the second semiconductor element, and the testing circuitry is configured to test functionality of at least a portion of the third active circuitry. In some embodiments, the testing circuitry is configured to transmit one or more signals to the first active circuitry. In some embodiments, the one or more signals probe one or more portions of the first active circuitry. In some embodiments, the first active circuitry provides a feedback signal, the feedback signal being sent from the first active circuitry to the testing circuitry, and the testing circuitry is configured to analyze the feedback signal and transmit an indication signal to the first device.

[0010] In another aspect, a bonded structure is described, the bonded structure including a wafer (sometimes referred to as a base wafer) including a first active circuit portion and a self-test core, and a first semiconductor device including a second active circuit portion, the semiconductor device being directly bonded to the wafer without an adhesive, the self-test core including test circuit portion configured to test functionality of at least a portion of at least one of the first active circuit portion and the second active circuit portion.

[0011] In some embodiments, the first non-conductive bonding layer of the wafer is directly bonded to the second non-conductive bonding layer of the first semiconductor element without an intervening adhesive, and the first contact feature of the wafer is directly bonded to the second contact feature of the first semiconductor element without an intervening adhesive. In some embodiments, the bonded structure further comprises a third semiconductor element having a third active circuit portion, a third non-conductive bonding layer, and a third contact feature in communication with the third active circuit portion, the third non-conductive bonding layer being directly bonded to the first non-conductive bonding layer of the wafer without an intervening adhesive, and the third contact feature being directly bonded to the first contact feature of the wafer without an intervening adhesive. In some embodiments, the first semiconductor element has a fourth non-conductive bonding layer and a fourth contact feature in communication with the second active circuit portion.

[0012] In some embodiments, the bonded structure further includes a second semiconductor element having a third active circuit portion, a third non-conductive bonding layer, and a third contact feature in communication with the third active circuit portion, wherein the third non-conductive bonding layer of the second semiconductor element and the fourth non-conductive bonding layer of the first semiconductor element are directly bonded to each other without an intervening adhesive, and the third contact feature of the second semiconductor element is directly bonded to the fourth contact feature of the first semiconductor element without an intervening adhesive.

[0013] In some embodiments, the second semiconductor element has a fourth non-conductive bonding layer and a fourth contact feature in communication with the third active circuitry. In some embodiments, the bonded structure further comprises a third semiconductor element having a fourth active circuitry, a sixth non-conductive bonding layer, and a sixth contact feature in communication with the third active circuitry, wherein the sixth non-conductive bonding layer of the third semiconductor element and the fifth non-conductive bonding layer of the second semiconductor element are directly bonded to one another without an intervening adhesive, and the sixth contact feature of the third semiconductor element is directly bonded to the fifth contact feature of the second semiconductor element without an intervening adhesive. In some embodiments, the testing circuitry is configured to test functionality of at least a portion of at least one of the first active circuitry, the second active circuitry, the third active circuitry, and the fourth active circuitry.

[0014] In another aspect, a method of forming a bonded structure is described, the method including providing a first semiconductor element having a test circuit portion and bonding, without an adhesive, the first semiconductor element to a second semiconductor element, the second semiconductor element having a first active circuit portion, the test circuit portion configured to test functionality of the first active circuit portion.

[0015] In some embodiments, the method further includes bonding a third semiconductor device having a second active circuit portion to the first semiconductor device without adhesive. In some embodiments, the method further includes bonding a third semiconductor device having a second active circuit portion to the second semiconductor device. In some embodiments, the method further includes bonding a fourth semiconductor device having a third active circuit portion to the second semiconductor device. In some embodiments, the first semiconductor device includes a test chip.

[0016] In some embodiments, the method further includes bonding at least one semiconductor device having active circuitry to a second semiconductor device, the test circuitry being configured to test at least a portion of the functionality of the at least one semiconductor device.

[0017] In another embodiment, the bonded structure may include a first semiconductor element having a first active circuit portion, a first non-conductive bonding layer of the first semiconductor element at least partially constituting a direct bonding surface of the bonded structure, and one or more traces connected to the first active circuit portion and extending at least partially into the first non-conductive bonding layer, the one or more traces configured to enable electrical communication between the first active circuit portion and the element under test, the one or more traces terminating at or below the direct bonding surface.

[0018] In some embodiments, the bonded structure may further include a first contact feature at least partially embedded within the first non-conductive bonding layer and connected to one or more traces, the first contact feature configured for direct bonding to a corresponding second contact feature of the device under test. In some embodiments, the bonded structure may further include a plurality of contact features at least partially embedded within the first non-conductive bonding layer, the first non-conductive bonding layer and the plurality of contact features cooperating at least in part to define a direct hybrid bondable bonding surface. In some embodiments, the one or more traces terminate at or below the direct bonding surface, and the one or more traces are not connected to a contact pad at the bonding surface of the bonded structure.

[0019] For purposes of summarizing the disclosure and the advantages achieved over the prior art, certain objects and advantages of the disclosure are described herein. Not all such objects or advantages may be achieved in any particular embodiment. Thus, for example, one skilled in the art will recognize that the invention can be embodied or achieved in a manner that achieves or optimizes one advantage or group of advantages taught herein without necessarily achieving other objects or advantages taught or suggested herein.

[0020] All of these embodiments are intended to fall within the scope of the invention disclosed herein. These and other embodiments will become readily apparent to those of ordinary skill in the art from the following detailed description of the preferred embodiments, which proceeds with reference to the accompanying drawings, and the invention is not limited to any particular embodiment disclosed. [Brief description of the drawings]

[0021] [Figure 1A] 1 is a schematic cross-sectional side view of a self-test chip directly bonded to a semiconductor device according to one embodiment. [Figure 1B] 1 is a schematic cross-sectional side view of a self-test chip directly bonded to a semiconductor device according to another embodiment. [Figure 1C] FIG. 2 is a schematic plan view showing a self-test chip bonded to a semiconductor device. [Figure 2A] FIG. 1 is a schematic plan view showing a self-test chip in the form of a wafer bonded to a semiconductor device. [Figure 2B] 1 is a schematic plan view of a semiconductor device having a conventional built-in self-test circuit integrated with a chip in a wafer configuration; [Figure 3A] 1 is a schematic cross-sectional side view of a self-test core embedded within a chip bonded to a semiconductor device; [Figure 3B] 1 is a schematic cross-sectional side view of a self-test core embedded within a chip bonded to a plurality of semiconductor elements laterally spaced from one another on the chip; [Figure 3C] 1 is a schematic cross-sectional side view of a test core embedded within a chip bonded to a plurality of stacked semiconductor devices. [Figure 4] 1 is a simplified diagram illustrating a direct bonded test core configuration compared to a built-in self-test configuration formed in a semiconductor device die, according to various embodiments. [Figure 5A] 1A-1D are schematic diagrams illustrating a process for forming a direct hybrid bonded structure without an intervening adhesive, according to some embodiments. [Figure 5B] 1A-1D are schematic diagrams illustrating a process for forming a direct hybrid bonded structure without an intervening adhesive, according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] Overview The present disclosure can be understood with reference to the following detailed description: It should be noted that, for purposes of clarity of illustration, certain elements in the various figures may not be drawn to scale, may be represented diagrammatically or conceptually, or may otherwise not precisely correspond to certain physical forms of certain embodiments.

[0023] The embodiments relate to a test element for a semiconductor device, such as a system on a chip (SoC). The test element, or self-test core (ST core), of the present disclosure can reduce the area of ​​the semiconductor device used to perform the self-test function. To this end, the self-test core is bonded to an appropriate bonding surface of the semiconductor device, as opposed to being patterned on the area of ​​the chip to be tested. As described herein, the ST core may be provided in a separate chip or chiplet that is directly bonded to a base element, which may include the chip (or wafer) to be tested or a host device to which the chip to be tested is bonded.

[0024] Conventionally, self-test devices (e.g., self-test circuits) are widely used to evaluate and self-test semiconductor devices with as few probe contacts as possible. As semiconductor devices (e.g., chips or integrated circuit devices) become more complex, self-test architectures become more and more important because such architectures enable higher yields in more complex devices. In particular, SoC devices that are difficult to test with external measurement equipment benefit from built-in self-test structures and circuits.

[0025] One method for performing functional testing is built-in self-test (BIST). Traditional BIST methods allocate a portion of the chip's area for self-test circuitry. More complex semiconductor devices also use more complex self-test circuitry. However, complex self-test circuitry takes up a lot of space on the chip, thereby limiting the ability to miniaturize complex semiconductor devices.

[0026] In some devices, self-test circuitry is added in the dicing lane. However, the self-test circuitry is becoming large and complicated, which impairs the engineering efforts to miniaturize the device. Therefore, there is a need for self-test circuitry that provides high functionality (e.g., a self-test circuit portion that tests most of the functionality of the semiconductor device) without occupying a large area of ​​the semiconductor device, for example, in the die.

[0027] Various embodiments disclosed herein may utilize a self-test core that includes testing circuitry. In some embodiments, the self-test core may include a chip and may be bonded to a surface of a semiconductor device. The self-test core may be configured to test some or all of the functionality of the semiconductor device. In some embodiments, the self-test core may be bonded to a first semiconductor device, which is bonded to another semiconductor device. In some embodiments, the self-test core may be configured to test some or all of the functionality of the other bonded semiconductor device.

[0028] In some embodiments, the self-test core may be embedded within the base element. In some embodiments, the embedded self-test core may be configured to test some or all of the functionality of the base element. In some embodiments, the base element may be bonded to another semiconductor device. In some embodiments, the self-test core may be configured to test some or all of the functionality of some or all of the semiconductor elements bonded to the base element. In some embodiments, the base element is a chip, a wafer, or an interposer.

[0029] Another advantage of using the disclosed embodiment of a self-test core or self-test chip is that a low-cost processing node can be used to pattern the test circuitry (e.g., 40 nm processing node) while a high-resolution processing node (e.g., 2 nm processing node) can be used to pattern the active circuitry of the semiconductor device. This change in patterning reduces the cost associated with the test circuitry, so that the test device (e.g., test chiplet) can be patterned with a low-cost technology and the semiconductor die with the advanced active circuitry can be patterned with a high-resolution and costly technology. The use of direct bonding to bond the test device to the semiconductor die allows the separation of the test device (e.g., test chiplet) and the semiconductor device (e.g., active die) so that they can be manufactured using a variety of processing nodes and technologies. The use of direct bonding also enables a cost-effective node strategy by providing fine pitch contacts that result in a large number of input / output ("I / O") pins for testing the chip circuitry. Fine pitch contacts enable the high density test schemes achievable with direct bonding.

[0030] A test element or self-test core (e.g., a chip or chiplet) can be directly bonded (e.g., using a hybrid direct bonding technology, such as DBI® technology, used by Adeia, Inc., San Jose, Calif.) to the bonding surface of a semiconductor element (e.g., a semiconductor chip) that can benefit from self-test. After bonding the self-test core to the element (e.g., a semiconductor chip or integrated device die), the self-test core can test some or all of the functionality of the element.

[0031] Exemplary embodiments of test elements for bonded structures FIG. 1A is a schematic cross-sectional side view of a test chip 102 (e.g., a test core or self-test core) bonded to a semiconductor device 104. In some embodiments, the test chip 102 may include a core substrate 106, test circuitry 108 patterned in a portion of the substrate 106, and a chip bonding layer (e.g., bonding layer 110). The test chip 102 may test active circuitry of one or more other semiconductor devices and may itself be devoid of any other active circuitry. In various embodiments, at least 80% or at least 90% of all circuitry in the test chip 102 constitutes the test circuitry 108. In some embodiments, all of the circuitry provided in the test chip 102 constitutes the test circuitry 108. The test circuitry 108 may include one or both of logic circuitry and / or memory circuitry.

[0032] The bonding layer 110 may include a dielectric layer 111 and a number of conductive contacts 113 at least partially embedded within the dielectric layer 111. Although FIG. 1A shows the chip bonding layer 110 diagrammatically as a single layer, it should be recognized that the layer 110 may include multiple layers or sublayers. In some embodiments, the bonding layer 110 may comprise one or multiple back-end-of-line (BEOL) layers deposited on the core substrate 106. In some embodiments, the semiconductor device 104 may include a device (diagrammatically shown in FIG. 1A as a portion of a substrate on which the active circuitry 109 may be patterned) having an active circuitry 109 patterned within a substrate bonding surface (e.g., the bonding layer may be the dielectric layer 114) with a number of conductive contacts 115 at least partially embedded within a portion of the substrate 112 and / or the dielectric layer 114 (e.g., a circuitry including at least one integrated circuit with one or more transistors). In some embodiments, the substrate 112 of the semiconductor device 104 may include a system-on-chip (SoC) device. In some embodiments, the semiconductor device 104 may include a central processing unit, a memory device, a microcontroller, a microprocessor, an application specific integrated circuit, a graphics processing unit, or any combination thereof. The substrate 112 of the semiconductor device 104 may have a semiconductor device portion including a semiconductor material, such as silicon. For example, the substrate 112 may include monocrystalline silicon or may include polycrystalline silicon. In some embodiments, the semiconductor device 104 may include through vias 138. The through vias 138 may include metal structures that extend at least partially and / or completely through the semiconductor device 104. In some embodiments, the through vias 138 may include a conductive material, such as copper or any other suitable conductive material. In some embodiments, the active circuitry 109 may be connected to a surface of the substrate 112 by input and / or output structures. In some embodiments, the input and / or output structures may be through vias 138, for example.The input and / or output structures may be in electrical communication with the active circuitry 109. In some embodiments, the semiconductor device 104 may have routing circuitry in communication and / or connected to the active circuitry 109. In some embodiments, the input and / or output structures may include routing circuitry. In some embodiments, the electrical contacts 115 may be electrically connected to and / or in communication with one and / or both of the active circuitry 109 and / or the routing circuitry.

[0033] 1A shows the substrate bonding layer 114 in a schematic manner as a single layer, it should be appreciated that the layer 114 can include multiple layers or sublayers (including, for example, BEOL layers as described above). In some embodiments, the test chip 102 can be directly hybrid bonded to the semiconductor device 104. In some embodiments, the chip bonding layer 110 can be directly bonded to the substrate bonding surface 114. In a hybrid bonding configuration, the non-conductive dielectric layers 114, 110 can be directly bonded to each other without adhesive, and the opposing contacts 113, 115 can also be directly bonded to each other without adhesive. In some embodiments, the dielectric layers 111, 114 can be made of an inorganic dielectric compatible with integrated circuit fabrication. For example, the dielectric layers 111, 114 can be a dielectric material, such as silicon nitride, silicon oxynitride, silicon carbonitride, diamond-like carbon, and / or any other suitable dielectric material. In some embodiments, the conductive contacts 113, 115 may comprise any suitable metal, for example, copper.

[0034] In some embodiments, the test chip 102 can test some and / or all of the functionality of the active circuitry 109 of the semiconductor device 104. In some embodiments, the active circuitry 109 can include one or both of logic and / or memory circuitry. For example, in operation, the test chip 102 can transmit one or more signals to the active circuitry 109 (e.g., one or more transistors) via the test chip 102 and the direct bonded conductive contact pads 113, 115 of the semiconductor device 104. Additionally or alternatively, to test the semiconductor device 104, the test chip 102 can communicate with the active circuitry 109 in the semiconductor device 104 via lateral traces and / or vertical interconnects within the chip. The lateral traces can laterally route one or more signals from the active circuitry 109 to the contact pads 113, 115 through the lateral traces. In some embodiments, the non-conductive layer can be one or more back-end-of-line (BEOL) layers. In some embodiments, a non-conductive or dielectric layer 114 may be formed on the trace lines. The transmitted signals may probe portions of the active circuitry (e.g., one or more transistors to be probed or tested), and the tested active circuitry may send a feedback signal that is sent from the semiconductor device 104 via the bonding layer contact pads 113, 115 to the test circuitry 108 of the test chip 102. The feedback signal may be processed by the test circuitry, which may be programmed to determine whether the tested active circuitry of the semiconductor device 104 is functional and / or non-functional. The feedback signal may also be stored or saved by an internal memory of the test chip 102. The test chip 102 may send an indication signal to the semiconductor device 104 and / or an external device (e.g., a package or a system board) that indicates the state of the tested active circuitry (e.g., whether the tested circuitry is functional and / or non-functional). The test chip 102 can store the feedback signals, which can be retrieved by a test engineer or an external test system.

[0035] In some embodiments, the functionality of the semiconductor device 104 may represent the suitability of the semiconductor device 104 for a given purpose and / or the quality of the semiconductor device 104. In some embodiments, the quality of the semiconductor device 104 corresponds to whether the semiconductor device 104 functions as designed. In some embodiments, following testing of the active circuitry 109, the test chip 102 may remain bonded to the semiconductor device 104 and may be housed in an external electronic device. In other embodiments, the test chip 102 may be detached from the semiconductor device 104 before the semiconductor device 104 is packaged and / or housed in an electronic device. For example, the test chip 102 may be detached from the semiconductor device 104 by polishing or may be otherwise detached from the semiconductor device 104. In embodiments in which the test chip 102 is detached from the semiconductor device 104, one or more traces connected to the active circuitry 109 may extend at least partially from the active circuitry 109 into the non-conductive layer 114. One or more traces may terminate at or below the bonding surface of the device 104. In some embodiments, the traces may extend from the active circuitry 109 to one or more test contact features or pads (e.g., pads 115) that were bonded to the test chip 102 prior to dicing. After dicing, the one or more test contact features or pads may be exposed at the hybrid bonding surface and may not be directly bonded to another device. The other pads 115 of the device 104 may be directly bonded to corresponding pads of other devices (e.g., other active dies).

[0036] 1B is a schematic cross-sectional side view of a test chip 102 (e.g., a test core or self-test core) bonded to a semiconductor device 104. In some embodiments, the test chip 102 can include a portion of a substrate 106 and test circuitry 108 patterned in a chip bonding layer (e.g., bonding layer 110).

[0037] The bonding layer 110 may include a dielectric layer 111 and a plurality of conductive contacts 113 at least partially embedded within the dielectric layer 111. Although FIG. 1B illustrates the chip bonding layer 110 generally as a single layer, it should be appreciated that the layer 110 may include multiple layers or sublayers. In some embodiments, the semiconductor device 104 may include a device (e.g., a circuit portion including at least one integrated circuit with at least one transistor) that is patterned within a portion of the substrate 112 and within a substrate bonding surface (e.g., the bonding layer, which may be the dielectric layer 114) with a plurality of conductive contacts 115 at least partially embedded within the dielectric layer 114. Although FIG. 1B illustrates the substrate bonding layer 114 generally as a single layer, it should be appreciated that the layer 114 may include multiple layers or sublayers. In some embodiments, the semiconductor device 104 may include a central processing unit, a memory device, a microcontroller, a microprocessor, an application specific integrated circuit, a graphics processing unit, or any combination thereof. The substrate 112 of the semiconductor device 104 may include silicon. For example, the substrate 112 may include monocrystalline silicon or may include polycrystalline silicon.

[0038] 1A, it should be appreciated that layer 114 may include multiple layers or sublayers. In some embodiments, test chip 102 may be direct hybrid bonded to semiconductor device 104. In some embodiments, chip bonding layer 110 may be direct bonded to substrate bonding surface 114. In a hybrid bonding configuration, non-conductive dielectric layers 114, 110 may be directly bonded to each other without adhesive, and opposing contacts 113, 115 may also be directly bonded to each other without adhesive. In some embodiments, dielectric layers 111, 114 may be comprised of an inorganic dielectric compatible with integrated circuit fabrication. For example, dielectric layers 111, 114 may be a dielectric material, such as silicon nitride, silicon oxynitride, silicon carbonitride, diamond-like carbon, and / or any other suitable dielectric material. In some embodiments, conductive contacts 113, 115 may include any suitable metal, such as copper.

[0039] In some embodiments, a second semiconductor element 116 may be bonded to the substrate bonding surface 114 at a first location by a second device bonding layer 118. The second semiconductor element 116 may have a second semiconductor device 120 having active circuitry 123 (e.g., circuitry including at least one integrated circuit with one or more transistors and / or SoC) patterned in and / or on the second element bonding surface (e.g., the bonding layer, which may be the dielectric layer 118) with a portion of the element 116 and a plurality of conductive contacts 119 at least partially embedded in the dielectric layer 118. Although FIG. 1B illustrates the second bonding layer 118 diagrammatically as a single layer, it should be understood that the layer 118 may include multiple layers or sublayers. In some embodiments, the second semiconductor element 116 may be direct hybrid bonded to the semiconductor element 104. In some embodiments, the second element bonding layer 118 may be direct bonded to the substrate bonding surface 114. In an example hybrid bonding configuration, the non-conductive dielectric layers 114, 118 may be directly bonded to one another without an adhesive, and the opposing contacts 119, 115 may be directly bonded to one another without an adhesive.

[0040] In some embodiments, a third semiconductor element 122 may be bonded to the substrate bonding surface 114 at the second location by a third device bonding layer 124. The third semiconductor element 122 may include a third semiconductor device 126. The third semiconductor element 122 and the second semiconductor element 116 may be attached to a common semiconductor element 104. As shown, the third semiconductor element 122 and the second semiconductor element 116 may be laterally spaced apart on the semiconductor element 104. In some embodiments, the third semiconductor element 122 may include a device implementing active circuitry 125 (e.g., circuitry including at least one integrated circuit with one or more transistors and / or SoC) patterned in a bonding surface (e.g., a bonding layer that may be the dielectric layer 124) with a portion of the element 116 and a plurality of conductive contacts 121 at least partially embedded in the dielectric layer 124 (such circuitry may include one or both of logic and / or memory circuitry). Although FIG. 1B illustrates the third device bonding layer 124 diagrammatically as a single layer, it should be understood that the layer 124 may include multiple layers or sublayers. In some embodiments, the third semiconductor element 124 may be direct hybrid bonded to the semiconductor element 104. In some embodiments, the third element bonding layer 124 may be direct bonded to the substrate bonding surface 114. In an exemplary hybrid bonding configuration, the non-conductive dielectric layers 114, 124 may be directly bonded to one another without an adhesive, and the opposing contacts 121, 115 may be directly bonded to one another without an adhesive.

[0041] In some embodiments, the semiconductor elements 104, 116, and / or 122 may include through vias 138. The through vias 138 may include metal structures that extend at least partially and / or completely through the semiconductor elements. In some embodiments, the through vias 138 may include a conductive material, such as copper or any other suitable conductive material. In some embodiments, the semiconductor element 104 may have routing circuitry in communication with and / or connected to the active circuitry 109. In some embodiments, the input and / or output structures may include routing circuitry. In some embodiments, the electrical contacts 115 may be electrically connected to and / or in communication with one and / or both of the active circuitry 109 and / or the routing circuitry.

[0042] In some embodiments, the test chip 102 can test at least a portion and / or all of the functionality of the semiconductor device 104, at least a portion and / or all of the functionality of the second semiconductor device 116, and at least a portion and / or all of the functionality of the third semiconductor device 122. In some embodiments, the test chip 102 does not need to be directly bonded to the second semiconductor device 116 and / or the third semiconductor device 122 in order to test a portion and / or all of the functionality of the second semiconductor device 116 and / or the third semiconductor device 122. In some embodiments, the functionality of the semiconductor devices 104, 116, and / or 122 can represent the adequacy of the semiconductor device 104 for a given purpose and / or the quality of the semiconductor device 104. In some embodiments, the quality of the semiconductor devices 104, 116, and / or 122 corresponds to whether the semiconductor devices 104, 116, and / or 122 are functioning as designed.

[0043] In some embodiments, more semiconductor elements may be bonded to the semiconductor element 104. The test chip 102 may test some or all of the functionality of these more bonded semiconductor elements in a manner similar to that described above. In some embodiments, the test chip 102 may test some or all of the functionality of any number of semiconductor elements, such as 1, 2, 3, 4, 5, 6, 7, or more. In some embodiments, the test chip 102 may test multiple semiconductor devices sequentially and / or simultaneously.

[0044] In some embodiments, the test chip 102 may include a plurality of contact pads. In some embodiments, the contact pads may include signal pads (e.g., pads for transmitting signals), power pads (e.g., pads connected to a power source and configured to transmit power), and / or ground pads (e.g., pads designed to ground an electronic device). In some embodiments, the signal pads may direct test signals to a portion of the semiconductor element 104 and / or some or all of the functions of the second semiconductor element 116 and / or some or all of the functions of the third semiconductor element 122.

[0045] In some embodiments, the test chip 102 may include a plurality of signal pads. In some embodiments, the plurality of signal pads may be located at the bond interface 130. In some embodiments, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, or at least 99%, or any value between these values, of the signal pads may be capable of testing a portion of the semiconductor device 104 and / or a portion or all of the functionality of the second semiconductor device 116 and / or a portion or all of the functionality of the third semiconductor device 122. In some embodiments, 90% of the signal pads may be capable of testing a portion or all of the functionality of the semiconductor device 112. In some embodiments, 50% of the signal pads may be capable of testing a portion or all of the functionality of the semiconductor device 112.

[0046] 1C is a schematic plan view of a test chip 102 (e.g., a test core or self-test core) in the form of a wafer bonded to the semiconductor device 104 described in FIGS. 1A and 1B. The test core 128a may include test pads 132, and such test core may be positioned on the surface of the semiconductor device 104. The test core 128a and the test circuit portion 108 may be in electrical communication with the test pads 132. The test pads 132 may be in electrical communication with the semiconductor device 104 and the integrated circuit portion 109. The test pads 132 may be disposed within a dicing lane 136, which may then be removed by a dicing process.

[0047] The testing core 128b may include test pads 134, which may be located on the back side (rear surface) of the testing core 128b. The test pads 134 may be in electrical communication with the circuitry under test 108. The test pads 134 may be in electrical communication with the semiconductor device 104 and the integrated circuitry 109. The test pads 132, 134 enable testing of the active circuitry 109 by external probes. In some embodiments, the test pads 132, 134 may transmit an indication signal from the circuitry under test 108 to an external device (e.g., a package or system board or an external operator) that indicates the status of the active circuitry being tested (e.g., whether the circuit being tested is functional and / or non-functional).

[0048] As shown in Figures 2A and 2B, increased device yields can be obtained by using bonded self-test chips 206. Figure 2A is a plan view of an undiced wafer 200 with semiconductor devices 202 and bonded self-test cores or chips 206. In Figure 2A, each semiconductor device 202 may be bonded to a bonded self-test core 206. By bonding the bonded self-test cores 206 to each semiconductor device 208, the total number of semiconductor devices 202 that can be fabricated from the undiced wafer 200 is greater than if test circuitry was patterned into portions of the semiconductor devices 202. In one embodiment, for example, as shown in Figure 2A, the number of semiconductor devices 204 fabricated from the wafer 200 is 42.

[0049] FIG. 2B illustrates that a smaller number of semiconductor devices can be fabricated on a wafer 200 with built-in self-test circuitry according to a conventional self-test method. In FIG. 2B, the undiced wafer 200 is the same size as in FIG. 2A. However, unlike FIG. 2A, in FIG. 2B, the self-test circuitry 208 is built into each semiconductor device 204. The built-in test circuitry 208, which can extend the footprint of the semiconductor device 204, can significantly reduce the number of semiconductor devices 204 that can be fabricated from the undiced wafer 200. Since the built-in self-test circuitry 208 is patterned on the semiconductor device 204, the footprint (e.g., the overall size of the device) of the semiconductor device 204 increases. The increased device size can reduce the number of semiconductor devices 204 that can be fabricated from the wafer 200. However, in FIG. 2A, the self-test circuitry is provided or embodied on the direct-bonded chip 206. By removing the test circuitry from the device footprint, the device footprint can be made smaller, resulting in a larger number of devices per wafer 200. As discussed above, the fine pitch contacts made possible by direct hybrid bonding technology allow a large number of test I / O pads to test the complex active circuitry on the semiconductor device 204.

[0050] As shown in FIG. 2A, the self-test chips may be suitable for undiced or diced wafers (e.g., device dies). In some embodiments, the self-test chips may be suitable for a die-to-wafer format depending on cost, node, yield, and overall economics. In the die-to-wafer format, multiple diced self-test chips or dies may be bonded to a wafer populated with semiconductor devices. In the wafer-to-wafer format, a wafer of test chips may be directly bonded to a wafer of semiconductor devices and then singulated from one another.

[0051] 3A is a schematic cross-sectional side view of a self-test core 302 patterned in a base chip 304. In some embodiments, the self-test core 302 may include a testing circuitry 303. In some embodiments, the self-test core 302 may be patterned in a base chip 304. The base chip 304 may have a substrate bonding surface (e.g., a bonding layer that may be a dielectric layer 306) with a plurality of conductive contacts 307 at least partially embedded in a dielectric layer 306, and a device implementing active circuitry 305 (e.g., circuitry including at least one integrated circuit) patterned in a portion of the base chip 304. The active circuitry 305 may include one or both of memory circuitry and / or logic circuitry. Although FIG. 3A shows the base chip bonding 306 generally as a single layer, it should be recognized that the layer 306 may include multiple layers or multiple sublayers. In some embodiments, the second semiconductor device 313 may have active circuitry 310 (e.g., circuitry including at least one integrated circuit) patterned within a second device front side bonding layer 308 and a portion of the second semiconductor device 313. The second device front side bonding layer 308 may be a dielectric layer 308 with a plurality of conductive contacts 311 at least partially embedded within the dielectric layer 308. The active circuitry 310 may include one or both of logic and / or memory circuitry. Although FIG. 3A illustrates the second device front side bonding layer 308 generally as a single layer, it should be appreciated that the layer 308 may include multiple layers or sublayers. In some embodiments, the base chip bonding layer 306 may be direct bonded to the second device front side bonding layer 308. In an exemplary hybrid bonding configuration, the non-conductive dielectric layers 306, 308 may be directly bonded to one another without an adhesive, and the opposing contacts 311, 307 may be directly bonded to one another without an adhesive.

[0052] In some embodiments, the self-test core 302 can test some or all of the functionality of the base chip 304 and / or the active circuitry 310 of the second semiconductor device. The test paths 300 show that the self-test core 302 can be in electrical communication with the base chip 304 and the second semiconductor device 313. For example, to test the base chip 304, the self-test core 302 can be in communication with the active circuitry 305 in the base chip 304 via lateral traces provided within the chip. Similarly, the test circuitry 303 can send one or more signals to the active circuitry 310 (e.g., one or more transistors) of the second semiconductor device 313 via the directly bonded conductive contact pads 307, 311 of the base chip 304 and the second semiconductor device 313. The sent signals may probe portions of the active circuitry 310 of the second semiconductor device 313 (e.g., one or more transistors that have been probed or are to be tested), and the tested active circuitry may generate a feedback signal that is sent from the second semiconductor device 313 via contact pads 307, 311 of bonding layers 306, 308 to the test circuitry 303 of the self-test core 302. The feedback signal may be processed by the test circuitry 303, which may be programmed to determine whether the tested active circuitry 310 of the second semiconductor device 313 is functional and / or non-functional. The feedback signal may also be stored or saved by an internal memory of the self-test core 302. The self-test core 302 can send an indication of the state of the tested active circuitry (e.g., whether the tested circuitry is functional and / or non-functional) to the base chip 304, the second semiconductor device 313, and / or an external device (e.g., a package or a system board). A test engineer or testing system can access the feedback signals stored within the self-test core, for example, by probing contacts of the self-test core 302.In some embodiments, self-test core 302 can test some or all of the functionality of any number of semiconductor devices, such as 1, 2, 3, 4, 5, 6, 7, or more. In some embodiments, self-test core 302 can test multiple semiconductor devices sequentially and / or simultaneously.

[0053] FIG. 3B is a schematic cross-sectional side view of the self-test core 302 patterned in the base chip 304. In some embodiments, the self-test core 302 may include a testing circuitry 303. As in FIG. 3A, the second semiconductor device 313 may include active circuitry 310 that may be bonded to the base 304 at a first location. In some embodiments, the third device front-side bonding layer 314 and the third semiconductor element device 317 may include active circuitry 316 (e.g., circuitry including at least one integrated circuit) patterned in a portion of the third semiconductor element device 317. The third device front-side bonding layer 314 may be a dielectric layer with a plurality of conductive contacts 315 at least partially embedded therein. The third semiconductor device 317 may be bonded to a die location on the base chip 304. In some embodiments, the active circuitry 316 may include one or both of logic and / or memory circuitry. In some embodiments, the base chip bonding layer 306 is direct bonded to the third device front side bonding layer 314. In an example hybrid bonding configuration, the non-conductive dielectric layers 306, 314 may be directly bonded to one another without adhesive, and the opposing contacts 315, 307 may also be directly bonded to one another without adhesive.

[0054] 3B shows the third device front side bonding layer 314 diagrammatically as a single layer, it should be appreciated that the layer 314 may include multiple layers or sublayers. In some embodiments, the self-test core 302 may test some or all of the functionality of the base chip 304, the second semiconductor device 313, and / or the third semiconductor device 317 in a manner similar to that described in FIG. 3A. The test path 300 shows that the self-test core 302 may be in electrical communication with the base chip 304, the second semiconductor device 313, and the third semiconductor device 317. While FIG. 3B shows that the base chip 304 may be bonded to two separate semiconductor devices 313, 317, it should be appreciated that the base chip 304 may be bonded to more than two semiconductor devices. Similarly, it should be recognized that although only three test paths 300 are shown, the self-test core 302 can test some or all of the functionality of any semiconductor device bonded to the base wafer 304. As a non-limiting example, tens or hundreds of semiconductor devices can be bonded to the base wafer 304 and tested by the self-test core 302 embedded within the base wafer 304.

[0055] 3C is a schematic cross-sectional side view of a testing core 302 patterned into a base chip 304 that can be bonded to other semiconductor devices. In some embodiments, the self-test core 302 can include testing circuitry 303. In some embodiments, the self-test core 302 can be patterned into a base chip 304. The base chip 304 can include a substrate bonding surface (e.g., a bonding layer that can be a dielectric layer 306) with device mounted active circuitry 305 (e.g., circuitry including at least one integrated circuit patterned into a portion of the base chip 304) and conductive contacts 307 at least partially embedded in the dielectric layer 306. In some embodiments, the active circuitry 305 can be one or both of logic and / or memory circuitry. In some embodiments, the second semiconductor device 313 may have active circuitry 310 (e.g., circuitry including at least one integrated circuit, which may be one or both of logic and / or memory circuitry) patterned within a portion of the second semiconductor device 313, a second device front-side bonding layer 308 and a second device back-side bonding layer 312, which may be dielectric layers 308, 312, and a plurality of conductive contacts 311 at least partially embedded within the dielectric layers 308, 312. In some embodiments, the second semiconductor device 310 may have one or more through vias 312, with through vias 324 electrically connecting the second device front-side bonding layer 308 to the second device back-side bonding layer 312. 3C illustrates the second device backside bonding layer 312 and the second device frontside bonding layer 308 generally as a single layer, it should be appreciated that the layers 308, 312 may include multiple layers or sublayers. In some embodiments, the base chip bonding layer 306 may be directly bonded to the second device frontside bonding layer 308. In a hybrid bonding configuration, the non-conductive dielectric layers 306, 308 may be directly bonded to one another without an adhesive, and the opposing contacts 311, 307 may also be directly bonded to one another without an adhesive.Although FIGS. 3A-3C depict the base chip 304 in a schematic manner, it should be recognized that the base chip 304 may be a chip, a wafer, an interposer, and / or a semiconductor device.

[0056] In some embodiments, the third semiconductor device 317 may have active circuitry 316 (e.g., circuitry including at least one integrated circuit) patterned within a portion of the third semiconductor device 317, a third device backside bonding layer 318 that may be dielectric layers 314, 318, and a third device frontside bonding layer 314, and a plurality of conductive contacts 315 at least partially embedded within the dielectric layers 314, 318 that may be direct bonded to the second device backside bonding layer 312. In some embodiments, the active circuitry 316 may be one or both of logic and / or memory circuitry. In a hybrid direct bonding configuration, the non-conductive dielectric layers 312, 314 may be directly bonded to each other without adhesive, and the opposing contacts 311, 315 may be directly bonded to each other without adhesive. In some embodiments, one or more vias 324 may electrically connect the third device front-side bonding layer 314 to the third device back-side bonding layer 318. Although Figure 3C illustrates the third device back-side bonding layer 318 and the third device front-side bonding layer 314 generally as a single layer, it should be recognized that layers 314, 318 may include multiple layers or sublayers.

[0057] In some embodiments, the fourth semiconductor device 322 may have an active circuit portion 316 (e.g., a circuit portion including at least one integrated circuit) patterned within a portion of the fourth semiconductor device 322, a fourth device backside bonding layer 326 that may be a dielectric layer 320, 326, and a fourth device frontside bonding layer 320, and a plurality of conductive contacts 323 at least partially embedded within the dielectric layer 320, 326 that may be direct bonded to the third device backside bonding layer 318. In some embodiments, the active circuit portion 321 may be one or both of logic and / or memory circuit portions. In a hybrid direct bonding configuration, the non-conductive dielectric layers 320, 318 may be directly bonded to each other without adhesive, and the opposing contacts 315, 323 may be directly bonded to each other without adhesive. In some embodiments, one or more vias 324 may electrically connect the fourth device front side bonding layer 320 to the fourth device back side bonding layer 326. Although FIG. 3C shows the fourth device back side bonding layer 326 and the fourth device front side bonding layer 320 generally as a single layer, it should be recognized that the layers 320, 326 may include multiple layers or sublayers. In some embodiments, the self-test core 302 may test some and / or all of the functionality of the base chip 304, the second semiconductor device 310, the third semiconductor device 316, and / or the fourth semiconductor device 322 in a manner similar to that described in FIGS. 1A-2B. The test path 300 shows the self-test core 302 in electrical communication with the base chip 304, the second semiconductor device 310, the third semiconductor device 316, and / or the fourth semiconductor device 322. Although FIG. 3B illustrates bonded structure 328 of four elements, namely, base chip 304, second semiconductor element 313, third semiconductor element 316, and fourth semiconductor element 322, it should be recognized that in some embodiments, bonded structure 328 can include tens and / or hundreds of elements.Similarly, it should be understood that although only four test paths 300 are shown in FIG. 3C , the self-test core 302 can test some or all of the functionality of any semiconductor element in the bonded structure 302. As a non-limiting example, tens and / or hundreds of semiconductor devices can be bonded to the base wafer 304 and tested by the self-test core 302.

[0058] FIG. 4 is a schematic diagram of an example test core configuration compared to an example built-in self-test configuration according to different embodiments. In FIG. 4, the left column 406 shows different embodiments of chips and chip stacks using a self-test core 402 (also referred to herein as a "self-test chip") that can be directly bonded to a semiconductor chip with active circuitry to be tested according to embodiments disclosed herein, which can be one or both of logic and / or memory circuitry. The right column 408 shows a conventional version of a similar chipset with built-in self-test circuitry 404 patterned into the semiconductor chip. The self-test core can be fabricated at a more cost-effective node than traditional built-in test cores. As shown in FIG. 4, the node of the self-test core, i.e., 20 nm, may be of a lower resolution than the equivalent built-in self-test core, i.e., 7 nm, but the cost of the 20 nm node may be significantly lower (e.g., 10%, 20%, 30%, etc.) than that of the built-in test core. The cost of the 20 nm node may be lower because the lower resolution 20 nm node is cheaper to fabricate than the higher resolution 7 nm node, and the 20 nm node does not require any of the footprint of the semiconductor device since the self-test core can be directly bonded to the semiconductor device. Furthermore, the self-test core or chip may scan, test, and / or verify a larger area than the traditional built-in self-test core, because the self-test core or chip may scan and / or test many chips or even the entire system. Additionally, several operations of the built-in self-test core may utilize similar "base" code, allowing for compaction of the test area dedicated to the test nodes and / or reduction in the overall silicon area. For example, FIG. 4 shows that in a traditional built-in self-test system, each die has a portion of the wafer dedicated to the built-in self-test core 404.However, the self-test chip 402 allows a chip (possibly a large chip) to be used to test multiple chips. Because one self-test chip 402 can test multiple chips, the self-test chip 402 may be more efficient and / or reduce overall costs. Furthermore, because the self-test chip 402 does not have to be located within the footprint of the device, the self-test chip 402 may include more algorithms and greater test capacity than the built-in self-test circuitry 404, which may further reduce the complexity of other chips or devices due to possible offboarding of test logic.

[0059] In some embodiments, the bonding layer may include a non-conductive layer (e.g., a dielectric) with the conductive contacts at least partially embedded within the non-conductive layer. In some embodiments, the dielectric layer may be comprised of an inorganic dielectric compatible with integrated circuit fabrication. In some embodiments, the dielectric layer may be a dielectric material, such as silicon nitride, silicon oxynitride, silicon carbonitride, diamond-like carbon, and / or any other suitable dielectric. The conductive contacts may be comprised of any suitable metal, such as copper.

[0060] In some embodiments, the semiconductor device may comprise an integrated circuit device having active circuitry (e.g., circuitry having one or more transistors). In some embodiments, the semiconductor device may comprise a system-on-a-chip (SoC) device. In some embodiments, the semiconductor device may include a central processing unit, a memory device, a microcontroller, a microprocessor, an application specific integrated circuit, a graphics processing unit, or any combination thereof.

[0061] In some embodiments, the semiconductor device may comprise a semiconductor substrate. In some devices, the semiconductor substrate may comprise silicon. In some devices, the semiconductor substrate may comprise single crystal silicon or may comprise polycrystalline silicon. In some embodiments, the semiconductor device may have a through via. In some embodiments, the through via may comprise a metal structure that extends at least partially into the semiconductor device, for example, completely through the semiconductor device. In some embodiments, the through via may comprise a conductive material. In some embodiments, the through via may comprise copper, or any other suitable conductive material.

[0062] In some embodiments, the self-test core may be a self-test chip. In some embodiments, the self-test core may comprise a self-test chip. In some embodiments, the self-test chip may comprise testing circuitry. In some embodiments, the testing circuitry may comprise an integrated circuit. In some embodiments, the testing circuitry may be integrated into a base device. In some embodiments, the self-test core may be configured to test some or all of the semiconductor devices. In some embodiments, the self-test core may be configured to test some or all of the functionality of any number of semiconductor devices, such as 1, 2, 3, 4, 5, 6, 7, 8 or more. In some embodiments, the self-test core may be configured to test multiple devices sequentially and / or simultaneously.

[0063] In some embodiments, the self-test core may be bonded to the semiconductor device without an adhesive. In some embodiments, the self-test core bonded to the semiconductor device may be in electrical communication with one or more integrated circuits within the semiconductor device. In some embodiments, the self-test core may be capable of verifying or testing the functionality of the semiconductor device and / or one or more integrated circuits within the semiconductor device.

[0064] In some embodiments, the self-test core may comprise a chip with integrated circuits. In some embodiments, the self-test core may comprise a chip or an electrical element, or part of a device with routing circuitry. In some embodiments, the routing circuitry may have electrical inputs or electrical outputs. In some embodiments, the routing circuitry may be connected to or in electrical or other communication with the integrated circuitry. In some embodiments, the self-test core may comprise electrical contacts or contact pads. In some embodiments, the electrical contacts or contact pads may be in electrical communication with one or both of the testing circuitry or the integrated circuitry.

[0065] In some embodiments, the self-test core can test some or all of the functionality of the semiconductor device. In some embodiments, the self-test core is configured to provide an output signal. In some embodiments, the output signal correlates to a functionality of the semiconductor element. In some embodiments, the functionality of the semiconductor device is indicative of the validity of the device given a quality objective of the device. In some embodiments, the quality of the device corresponds to whether the device functions as designed.

[0066] In some embodiments, the semiconductor device comprises an integrated circuit disposed within a substrate. In some embodiments, the integrated circuit is connected to a surface of the substrate by input or output structures. In some embodiments, the input or output structures are through vias. In some embodiments, the input or output structures are in electrical communication with the integrated circuit. In some embodiments, the semiconductor device has routing circuitry in communication or connected to an integral integrated circuit portion. In some embodiments, the input or output structures may include routing circuitry. In some embodiments, the semiconductor device may have electrical contacts, such as contact pads. In some embodiments, the electrical contact pads or electrical contacts may be electrically connected or in communication with one or both of the integrated circuit or the routing circuitry.

[0067] Direct bonding method and direct bonded structure Various embodiments disclosed herein relate to direct bonded structures in which two or more elements can be directly bonded together without an intervening adhesive. Figures 5A and 5B show a schematic process of forming a direct hybrid bonded structure without an intervening adhesive according to some embodiments. In Figures 5A and 5B, a bonded structure 500 has two elements 502, 504 that can be directly bonded together at a bond interface 518 without an intervening adhesive. Two or more microelectronic elements 502, 504 (e.g., semiconductor elements, such as integrated device dies, wafers, passive devices, and individual active devices, such as power switches, etc.) can be stacked or bonded together to form the bonded structure 500. A conductive feature 506a (e.g., a contact pad, an exposed end of a via (e.g., TSV), or a through-substrate electrode) of a first element 502 can be electrically connected to a corresponding conductive feature 506b of a second element 504. Any suitable number of elements may be stacked within the bonded structure 500. For example, a third element (not shown) may be stacked on the second element 504, a fourth element (not shown) may be stacked on the third element, etc. Additionally or alternatively, one or more additional elements (not shown) may be stacked laterally adjacent to one another along the first element 502. In some embodiments, the laterally stacked additional elements may be smaller than the second element. In some embodiments, the laterally stacked additional elements may be 1 / 2 the size of the second element.

[0068] In some embodiments, the elements 502, 504 are directly bonded to each other without adhesive. In various embodiments, a non-conductive field region comprising a non-conductive material or dielectric can serve as a first bonding layer 508a of the first element 502 that can be directly bonded to a corresponding non-conductive field region without adhesive, the corresponding non-conductive field region comprising a non-conductive material or dielectric that serves as a second bonding layer 508b of the second element 504. The non-conductive bonding layers 508a, 508b can be provided on the device portions 510a, 510b, e.g., on the front surfaces (front sides) 514a, 514b of the semiconductor (e.g., silicon) portions of the elements 502, 503, respectively. Active devices and / or circuitry can be patterned and / or otherwise provided in or on the device portions 510a, 510b. Active devices and / or circuitry may be provided at or near the front surfaces 514a, 514b of the device portions 510a, 510b and / or at or near the opposite back surfaces 516a, 516b of the device portions 510a, 510b. Bonding layers may be provided on the front and / or back surfaces of the elements. The non-conductive material may be referred to as a non-conductive bonding region or bonding layer 508a of the first element 502. In some embodiments, the non-conductive bonding layer 508a of the first element 502 may be directly bonded to a corresponding non-conductive bonding layer 508b of the second element 504 using dielectric-dielectric bonding techniques. For example, non-conductive or dielectric-dielectric bonds can be formed without adhesives using direct bonding techniques as disclosed in at least U.S. Patent Nos. 9,564,414, 9,391,143, and 10,434,749, which are incorporated by reference in their entirety and for all purposes. It should be appreciated that in various embodiments, the conductive bonding layers 508a and / or 508b can be comprised of a non-conductive material, such as a dielectric, e.g., silicon oxide, or an undoped semiconductor material, e.g., undoped silicon.Dielectric bonding surfaces or materials suitable for direct bonding include, but are not limited to, inorganic dielectrics such as silicon oxide, silicon nitride, or silicon oxynitride, or may include materials containing carbon, such as silicon carbide, silicon oxycarbonitride, low-K dielectrics, SiCOH dielectrics, silicon carbonitride, or diamond-like carbon or diamond surfaces. Such carbon-containing ceramic materials may be considered inorganic despite the carbon content. In some embodiments, the dielectric does not include polymeric materials such as epoxies, resins, or molding materials.

[0069] In some embodiments, the device portions 510a, 510b may have significantly different coefficients of thermal expansion (CTE) constituting a heterogeneous structure. The CTE difference between the device portions 510a, 510b, especially between the semiconductor, typically single crystal portions of the device portions 510a, 510b, may be greater than 5 ppm or 10 ppm. For example, the CTE difference between the device portions 510a, 510b may be in the range of 5 ppm to 100 ppm, 5 ppm to 40 ppm, 10 ppm to 100 ppm, or 10 ppm to 40 ppm. In some embodiments, one of the device portions 510a, 510b may be made of an optoelectronic single crystal material (including perovskite materials) useful in opto-piezoelectric or pyroelectric applications, while the other of the device portions 510a, 510b is made of a more conventional substrate material. For example, one of the device portions 510a and 510b may be made of lithium tantalate (LiTaO 3 ) or lithium niobate (LiNbO 3), and the other one of the device portions 510a, 510b is made of silicon (Si), fused silica, sapphire, or glass. In other embodiments, one of the device portions 510a, 510b is made of a III-V single semiconductor, such as gallium arsenide (GaSa) or gallium nitride (GaN), and the other one of the device portions 510a, 510b is made of a non-III-V single semiconductor, such as silicon (Si), or other material with a similar CTE, such as quartz, fused silica, sapphire, or glass.

[0070] In various embodiments, a direct hybrid bond can be formed without an intervening adhesive. For example, the non-conductive bonding surfaces 512a, 512b can be polished to a high degree of smoothness. For example, chemical mechanical polishing (CMP) can be used to polish the bonding surfaces 512a, 512b. After polishing, the roughness of the bonding surfaces 512a, 512b can be less than 30 rpm. For example, the roughness of the bonding surfaces 512a, 512b can be in the range of about 0.1 rpm to 15 rpm, about 0.5 rpm to 10 rpm, or about 1 rpm to 5 rpm. The bonding surfaces 512a, 512b can be cleaned and exposed to plasma and / or etchants to activate the surfaces 512a, 512b. In some embodiments, the surfaces 512a, 512b can be terminated with species after or during activation (e.g., during a plasma and / or etching process). Without being bound by theory, in some embodiments, the activation process can be performed to break chemical bonds at the bonding surfaces 512a, 512b, and the termination process can provide additional chemical species at the bonding surfaces 512a, 512b that improve the bonding energy during direct bonding. In some embodiments, the activation and termination can be performed in the same step, for example, by plasma exposure to both activate and terminate the bonding surfaces 512a, 512b. In other embodiments, the bonding surfaces 512a, 512b can be terminated in a separate process to provide additional chemical species for direct bonding. In various embodiments, the termination species can include nitrogen. Additionally, in some embodiments, the bonding surfaces 512a, 512b can be exposed to a fluorine-containing plasma. Additionally, in some embodiments, the bonding surfaces 512a, 512b can be exposed to fluorine. For example, there can be one or many regions of increased fluorine concentration at or near the bonding interface 518 between the first element 502 and the second element 504.Thus, in the direct bonded structure 500, the bonding interface 518 between the two non-conductive materials (e.g., bonding layers 508a, 508b) can be an extremely smooth interface with a high nitrogen content and / or fluorine peak at the bonding interface 518. Additional examples of activation and / or termination treatments can be found throughout U.S. Patent Nos. 9,564,414, 9,391,143, and 10,434,749, each of which is incorporated by reference and incorporated herein in its entirety for all purposes. The polished bonding surfaces 512a, 512b can be slightly rough (e.g., about 1 Å rpm to 30 Å rpm, about 3 Å rpm to 20 Å rpm, or even rougher in some cases) after the activation process.

[0071] In various embodiments, the conductive feature 506a of the first element 502 may also be directly bonded to a corresponding conductive feature 506b of the second element 504. For example, hybrid bonding techniques may be used to provide conductor-conductor direct bonds along a bonding interface 518 that includes covalently direct bonded non-conductive-non-conductive (dielectric-dielectric) surfaces that have been pretreated as described above. In various embodiments, conductor-conductor (e.g., conductive feature 506a-conductive feature 506b) direct bonds and dielectric-dielectric hybrid bonds may be formed using direct bonding techniques disclosed in at least U.S. Patent Nos. 9,716,033 and 9,852,988, each of which is incorporated by reference herein in its entirety for all purposes. In the direct hybrid bonding embodiments described herein, the conductive features are provided in a non-conductive bonding layer, and both the conductive and non-conductive features are pretreated for direct bondability, for example, by planarization, activation, and / or end grouping processes described above. Thus, the bonding surface that has been pretreated for direct bondability includes both conductive and non-conductive features.

[0072] For example, the non-conductive (e.g., dielectric) bonding surfaces 512a, 512b (e.g., inorganic dielectric surfaces) may be pretreated as described above and then directly bonded to one another without an intervening adhesive. The conductive contact features (e.g., conductive features 506a, 506b that may be at least partially surrounded by a non-conductive dielectric field region in the bonding layers 508a, 508b) may also be directly bonded to one another without an intervening adhesive. In various embodiments, the conductive contact features 506a, 506b may comprise separate pads at least partially embedded within the non-conductive field regions. In some embodiments, the conductive contact features may comprise exposed contact surfaces of through-substrate vias (e.g., through-silicon vias (TSVs)). In some embodiments, the conductive contact features 506a, 506b may be recessed below the dielectric field region or outer (e.g., upper) surface (non-conductive bonding surface 512a, 512b) of the non-conductive bonding layer 508a, 508b, e.g., by less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, e.g., within a range of 2 nm to 20 nm, or 4 nm to 10 nm. In various embodiments, prior to direct bonding, the recesses of the opposing elements may be sized such that the overall gap between the opposing contact pads is less than 15 nm or less than 10 nm. The non-conductive bonding layers 508a, 508b may be direct bonded together without a contact agent at room temperature in some embodiments, after which the bonded structure 500 may be annealed. Upon annealing, the conductive features 506a, 506b can expand and contact one another, thereby forming metal-metal direct bonds. Beneficially, a high density of conductive features 506a, 506b can be connected to one another across the direct bond interface 518 (e.g., with a small or fine pitch for a regular array) through the use of Direct Bond Interconnect, or DBI®, technology, commercially available from Adeia, Inc. of San Jose, Calif.In some embodiments, the pitch of the conductive features 506a, 506b, e.g., the conductive traces embedded in one of the bonding surfaces of the bonded elements, may be less than 40 microns, less than 10 microns, or even less than 2 microns. For some applications, the ratio of the pitch of the conductive features 506a, 506b to one of the dimensions of the bonding pad (e.g., the diameter) may be less than 20, less than 10, less than 5, or less than 3, and in some cases may be desirably less than 2. In other applications, the width of the conductive traces embedded in one of the bonding surfaces of the bonded elements may be in the range of 0.3 microns to 20 microns, e.g., 0.3 microns to 3 microns. In various embodiments, the conductive features 506a, 506b and / or traces may be made of copper or a copper alloy, although other metals may be suitable. For example, the conductive features disclosed herein, e.g., the conductive features 506a, 506b, may be made of a microcrystalline metal (e.g., microcrystalline copper).

[0073] Thus, in a direct bonding process, the first element 502 can be directly bonded to the second element 504 without an intervening adhesive. In some configurations, the first element 502 can be a singulated element, such as a singulated integrated device die. In other configurations, the first element 502 can be a carrier or substrate (e.g., a wafer) that includes a plurality (e.g., tens, hundreds, or more) of device regions that, when singulated, form a plurality of integrated device dies. Similarly, the second element 504 can be a singulated element, such as a singulated integrated device die. In other configurations, the second element 504 can be a carrier or substrate (e.g., a wafer). The embodiments disclosed herein can be utilized in wafer-to-wafer (W2W), die-to-die (D2D), or die-to-wafer (D2W) bonding techniques. In a wafer-to-wafer (W2W) process, two or more wafers may be directly bonded together (e.g., direct hybrid bonding) and then singulated using a suitable singulation process. After singulation, the side edges of the singulated structure (e.g., the side edges of the two bonded elements) may be substantially flush with one another and may include indicia indicative of the singulation process common to the bonded structures (e.g., saw marks if a saw-based singulation process is used).

[0074] As described herein, the first element 502 and the second element 504 can be directly bonded together without adhesive, which is different from the deposition process and results in a structurally different interface compared to deposition. In one application, the width of the first element 502 in the bonded structure is approximately the same as the width of the second element 504. In some other embodiments, the width of the first element 502 in the bonded structure may be different from the width of the second element 504. Similarly, the width or area of ​​the larger element in the bonded structure may be at least 10% larger than the width or area of ​​the smaller element. Thus, the first and second elements may be comprised of non-deposited elements. Furthermore, unlike deposition layers, the direct bonded structure may include defect areas along the bond interface 518 where nanoscale voids (nanovoids) exist. The nanovoids may form due to activation (e.g., exposure to plasma) of the bonding surfaces 512a, 512b. As discussed above, the bond interface 518 may contain a concentration of materials resulting from the activation and / or final chemical treatment process. For example, in embodiments utilizing nitrogen plasma for activation, a nitrogen peak may form at the bond interface 518. The nitrogen peak may be detectable using secondary ion mass spectrometry (SIMS). In various embodiments, for example, a nitrogen termination treatment (e.g., exposing the bonding layer to a nitrogen-containing plasma) may result in NH 3 , NH 4 , or NH 5 groups replacing OH groups on the hydrolyzed (OH-terminated) surface. 2 Molecules can be used, resulting in a nitrogen-terminated surface. In embodiments utilizing an oxygen plasma for activation, an oxygen peak may form at the bond interface 518. In some embodiments, the bond interface 518 may be comprised of silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. As described herein, the direct bond includes a covalent bond, which is stronger than a van der Waals bond. The bonding layers 508a, 508b may also further include a polished surface that is planarized to a high degree of smoothness.

[0075] In various embodiments, the metal-metal bond between the conductive features 506a, 506b may be bonded such that the metal grains grow into one another across the bonding interface 518. In some embodiments, the metal is or includes copper, which may have grains oriented along the 511 crystal plane to enhance copper diffusion across the bond interface 518. In some embodiments, the conductive features 506a, 506b may include a nanotwin copper grain structure, which may help coalesce the conductive features during annealing. The bonding interface 518 may extend substantially completely to at least a portion of the bonded conductive features 506a, 506b, such that there are substantially no gaps between the non-conductive bonding layers 508a, 508b at or near the bonded conductive features 506a, 506b. In some embodiments, a barrier layer (which may include, for example, copper) may be provided underneath and / or laterally surrounding the conductive features 506a, 506b, however, in other embodiments, there may not be a barrier layer underneath the conductive features 506a, 506b, as described, for example, in U.S. Patent No. 11,195,748, which is incorporated by reference and incorporated herein in its entirety for all purposes.

[0076] Beneficially, the hybrid bonding techniques described herein allow for very fine pitches between adjacent conductive features 506a, 506b and / or small pad sizes. For example, in various embodiments, the pitch p between adjacent conductive features 506a (or 506b) (i.e., the edge-to-edge or center-to-center distance as shown in FIG. 1A) may be in the range of 0.5 to 50 microns, 0.75 to 25 microns, 1 to 25 microns, 1 to 10 microns, or 1 to 5 microns. Furthermore, the larger lateral dimension (e.g., pad diameter) may also be small, e.g., in the range of 0.25 to 30 microns, 0.25 to 5 microns, or 0.5 to 5 microns.

[0077] As described above, the non-conductive bonding layers 508a, 508b may be direct bonded together without adhesive, and then the bonded structure 500 may be annealed. Upon annealing, the conductive features 506a, 506b may expand and contact one another, thereby forming a metal-metal direct bond. In some embodiments, the materials of the conductive features 506a, 506b may diffuse into one another during the annealing process.

[0078] term Unless the context clearly requires otherwise, throughout the specification and claims, the terms "comprise", "comprising", "include", "including" and the like are to be construed in an inclusive sense, i.e., "including, but not limited to", as opposed to an exclusive or exhaustive sense. As used generally herein, the term "coupled" means two or more elements that are either directly connected to each other or connected to each other by one or more intermediate elements. Similarly, as used generally herein, the term "coupled" means two or more elements that are either directly connected to each other or connected to each other by one or more intermediate elements. Additionally, the terms "herein," "above," "below," and words of similar import as used herein refer to the application as a whole and not to any particular portion of the application. Furthermore, as used herein, when a first element is described as "on" or "over" a second element, the first element may be directly located on or over the second element such that the first element and the second element are in direct contact, or the first element may be indirectly located on or over the second element such that one or more elements are interposed between the first element and the second element. Where the context permits, terms in the above Detailed Description using the singular or plural may include the plural or singular, respectively. The term "or" in reference to a list of two or more items includes all of the following interpretations of that term: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0079] Furthermore, conditional terms used in the specification, particularly "can," "could," "might," "may," "eg," "for example," "such as," and the like, unless expressly specified otherwise or understood otherwise within the context in which they are used, are generally intended to imply that certain embodiments include certain features, elements, and / or conditions and that other embodiments do not include certain features, elements, and / or conditions. Thus, such conditional terms are generally not intended to imply that features, elements, and / or conditions are present in any required manner for one or more embodiments.

[0080] Although certain embodiments have been described, these embodiments are provided by way of example only and are not intended to limit the scope of the invention. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms, and furthermore, various omissions, substitutions, and modifications in the form of the methods and systems described herein may be made without departing from the scope of the invention. For example, although blocks are shown in a given arrangement, alternative embodiments may perform substantially the same functions with different components and / or circuit topologies, and some blocks may be deleted, moved, added, divided, combined, and / or modified. Each of these blocks may be embodied in a wide variety of ways. Any suitable combination of elements and acts of the various embodiments described above may be combined to provide further embodiments. The scope of the invention as set forth in the appended claims and equivalents thereto is intended to include such forms or modifications within the scope and spirit of the invention.

[0081] Several exemplary embodiments of test elements for bonded structures and related systems and methods have been disclosed. Although the present disclosure has been described in terms of certain exemplary embodiments and uses, other embodiments and uses, including embodiments and uses that do not provide all of the features and advantages described herein, are also within the scope of the present disclosure. Components, elements, features, acts, or steps may be arranged or performed differently than described, and components, elements, features, acts, or steps may be combined, combined, added, or omitted in various embodiments. All possible combinations and subcombinations of the elements and components described herein are intended to be included in the present disclosure. No single feature or group of features is required or essential.

[0082] Certain features described in this disclosure in the context of separate embodiments may also be embodied in a combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be embodied in multiple embodiments separately or in any suitable subcombination. Furthermore, although features may be described above as acting in certain combinations, one or more features from a claimed combination may in some cases be deleted from the combination and the combination may be claimed as a subcombination or a variation of the subcombination.

[0083] Further, although exemplary embodiments have been described, any embodiment including equivalent elements, any modifications, any omissions, and / or any combinations are also within the scope of the present disclosure. Furthermore, although certain aspects, advantages, and novel features have been described herein, not all such advantages may necessarily be achieved in accordance with any particular embodiment. For example, some embodiments within the scope of the present disclosure may achieve one advantage or a group of advantages as taught herein, but in this case, they do not necessarily have to achieve advantages different from those taught or suggested herein. Furthermore, some embodiments may achieve advantages different from those taught or suggested herein.

[0084] Several embodiments have been described in connection with the accompanying drawings. The figures may or may not be drawn or illustrated to scale, and such scale is not intended to be limiting of the invention, as dimensions and proportions other than those illustrated are contemplated and are within the scope of the disclosed invention. Distances, angles, and the like are merely illustrative and do not necessarily bear precise relationship to the actual dimensions or layout of the devices or arrangements shown. Components may be added, omitted, and / or rearranged. Furthermore, disclosure herein of any particular features, aspects, methods, properties, characteristics, qualities, attributes, elements, etc., associated with various embodiments may be used in all other embodiments described herein. Additionally, any method described herein may be performed using any apparatus provided for performing the recited steps.

[0085] For purposes of summarizing the disclosure, certain aspects, advantages, and features of the present invention have been described herein. Not necessarily all advantages, or any such advantages, will be achieved in accordance with any particular embodiment of the present invention disclosed herein. No aspect of the present disclosure is essential or indispensable. In many embodiments, the apparatus, systems, and methods can be implemented in a manner different from that shown or described herein. For example, various functions provided by the illustrated modules can be combined, rearranged, added, or deleted. In some implementations, additional or different processors or modules can perform some or all of the functions described with reference to the illustrated embodiment. Many specific variations are possible. Any of the features, structures, steps, or processes disclosed herein may be included in any embodiment.

Claims

1. A bonded structure, A first semiconductor element comprising a first active circuit section, The device comprises a test element equipped with a test circuit section, wherein the test element is directly bonded to the first semiconductor element without adhesive along a bonding interface, and the test circuit section is configured to test the function of at least a portion of the first active circuit section of the first semiconductor element by transmitting one or more signals to the first active circuit section during the operation of the bonded structure and receiving feedback signals transmitted from the tested first active circuit section, wherein the one or more signals probe the at least portion of the first active circuit section. The test circuit section processes the feedback signal received during the operation of the bonded structure and determines whether the first active circuit section of the first semiconductor element that was tested is functioning or not.

2. The bonded structure according to claim 1, wherein the test element further comprises a memory configured to store the results of the test.

3. The bonded structure according to claim 1, wherein the test element is smaller than the first semiconductor element.

4. The first non-conductive bonding layer of the first semiconductor element is directly bonded to the second non-conductive bonding layer of the test element without an intervening adhesive. The bonded structure according to claim 1, wherein the first contact feature portion of the first semiconductor element is directly bonded to the second contact feature portion of the test element without an intervening adhesive.

5. The bonded structure according to claim 1, wherein the test element further comprises a plurality of signal contact pads.

6. The bonded structure according to claim 5, wherein the majority of the plurality of signal contact pads are configured to test at least a portion of the first active circuit.

7. A bonded structure, A first semiconductor element equipped with a test circuit section, The first semiconductor element is directly bonded to the second semiconductor element along a bonding interface without adhesive, and the second semiconductor element comprises a first active circuit section. The bonded structure is configured such that the test circuit section is used to test the function of at least a portion of the first active circuit section of the second semiconductor element.

8. The bonded structure according to claim 7, wherein the test circuit is further configured to store the results of the function of at least a portion of the first active circuit.

9. The first non-conductive bonding layer of the first semiconductor element is directly bonded to the second non-conductive bonding layer of the test element without an intervening adhesive. The bonded structure according to claim 7, wherein the first contact feature portion of the first semiconductor element is directly bonded to the second contact feature portion of the second semiconductor element without an intervening adhesive.

10. The bonded structure according to claim 7, further comprising a third semiconductor element having a second active circuit section, wherein the third semiconductor element is directly bonded to the second semiconductor element, and the test circuit section is configured to test the function of at least a portion of the second active circuit section.

11. The bonded structure according to claim 10, further comprising a fourth semiconductor element having a third active circuit portion, wherein the fourth semiconductor element is directly bonded to the third semiconductor element, and the fourth semiconductor element is directly bonded to the third semiconductor element.

12. The bonded structure according to claim 11, wherein the first semiconductor element further comprises a fourth active circuit section.

13. The bonded structure according to claim 12, wherein the test circuit of the first semiconductor element is configured to test at least a portion of the functions of the first active circuit, the second active circuit, the third active circuit, and / or the fourth active circuit.

14. The device further comprises a third semiconductor element having a second active circuit section, the third semiconductor element being directly bonded to the first semiconductor element. The bonded structure according to claim 7, wherein the test circuit is configured to test the function of at least a portion of the second active circuit.

15. The bonded structure according to claim 7, wherein the first semiconductor element is a test chip.

16. The bonded structure according to claim 15, wherein the test chip is configured to test only the active circuit portion of one or more other semiconductor elements, and the test chip does not have any other active circuit portions.

17. The present invention further comprises a second active circuit and a third semiconductor element having a second bonding layer bonded to the second semiconductor element without adhesive. The bonded structure according to claim 16, wherein the test circuit is configured to test the function of at least a portion of the second active circuit.

18. The fourth semiconductor element further comprises a third active circuit and a third bonding layer bonded to the second semiconductor element without adhesive. The bonded structure according to claim 17, wherein the test circuit is configured to test the function of at least a portion of the third active circuit.

19. The bonded structure according to claim 18, wherein the test circuit section is configured to transmit one or more signals to the first active circuit section.

20. The bonded structure according to claim 19, wherein the one or more signals probe one or more portions of the first active circuit section.

21. The first active circuit unit outputs a feedback signal, and the feedback signal is sent from the first active circuit unit to the test circuit unit. The bonded structure according to claim 20, wherein the test circuit section is configured to analyze the feedback signal and transmit an instruction signal to the first device.

22. A bonded structure, A wafer equipped with a first active circuit section and a self-test core, The first semiconductor element comprises a second active circuit section, and the semiconductor element is directly bonded to the wafer without adhesive. The self-testing core is a bonded structure having a test circuit section configured to test the function of at least a portion of at least one of the first active circuit section and the second active circuit section.

23. The first nonconductive bonding layer of the wafer is directly bonded to the second nonconductive bonding layer of the first semiconductor element without an intervening adhesive. The bonded structure according to claim 22, wherein the first contact feature portion of the wafer is directly bonded to the second contact feature portion of the first semiconductor element without an intervening adhesive.

24. The third semiconductor element further comprises a third active circuit portion, a third non-conductive bonding layer, and a third contact feature portion in contact with the third active circuit portion. The third nonconductive bonding layer is directly bonded to the first nonconductive bonding layer of the wafer without an intervening adhesive. The bonded structure according to claim 23, wherein the third contact feature portion is directly bonded to the first contact feature portion of the wafer without adhesive.

25. The bonded structure according to claim 23, wherein the first semiconductor element has a fourth nonconductive bonding layer and a fourth contact feature portion that is in contact with the second active circuit portion.

26. The second semiconductor element further comprises a third active circuit portion, a third non-conductive bonding layer, and a third contact feature portion in contact with the third active circuit portion. The third nonconductive bonding layer of the second semiconductor element and the fourth nonconductive bonding layer of the first semiconductor element are directly bonded to each other without an intervening adhesive. The bonded structure according to claim 25, wherein the third contact feature portion of the second semiconductor element is directly bonded to the fourth contact feature portion of the first semiconductor element without an intervening adhesive.

27. The bonded structure according to claim 26, wherein the second semiconductor element has a fourth nonconductive bonding layer and a fourth contact feature portion that is in contact with the third active circuit portion.

28. The third semiconductor element further comprises a fourth active circuit portion, a sixth non-conductive bonding layer, and a sixth contact feature portion in contact with the third active circuit portion. The sixth nonconductive bonding layer of the third semiconductor element and the fifth nonconductive bonding layer of the second semiconductor element are directly bonded to each other without an intervening adhesive. The bonded structure according to claim 27, wherein the sixth contact feature portion of the third semiconductor element is directly bonded to the fifth contact feature portion of the second semiconductor element without an intervening adhesive.

29. The bonded structure according to claim 28, wherein the test circuit section is configured to test the function of at least a portion of at least one of the first active circuit section, the second active circuit section, the third active circuit section, and the fourth active circuit section.

30. A method for forming a bonded structure, The steps include: preparing a first semiconductor element equipped with a test circuit section; The process includes the step of bonding the first semiconductor element to the second semiconductor element without adhesive, A method wherein the second semiconductor element has a first active circuit section, and the test circuit section is configured to test the function of the first active circuit section.

31. The method according to claim 30, further comprising the step of bonding a third semiconductor element having a second active circuit portion to the first semiconductor element without adhesive.

32. The method according to claim 31, further comprising the step of bonding a third semiconductor element having a second active circuit to the second semiconductor element.

33. The method according to claim 32, further comprising the step of bonding a fourth semiconductor element having a third active circuit to the second semiconductor element.

34. The method according to claim 33, wherein the first semiconductor element comprises a test chip.

35. The method further includes the step of bonding at least one semiconductor element having an active circuit portion to the second semiconductor element, The method according to claim 34, wherein the test circuit is configured to test at least a portion of the function of at least one semiconductor element.

36. A bonded structure, A first semiconductor element comprising a first active circuit section, The first non-conductive bonding layer of the first semiconductor element constitutes at least a portion of the direct bonding surface of the bonded structure, A bonded structure having one or more traces connected to the first active circuit section and extending at least partially into the first nonconductive bonding layer, wherein the one or more traces are configured to enable electrical communication between the first active circuit section and the test element, and the one or more traces terminate at or below the direct bonding surface.

37. The bonded structure according to claim 36, further comprising a first contact feature portion that is at least partially embedded in the first nonconductive bonding layer and connected to one or more traces, wherein the first contact feature portion is configured to directly bond to a corresponding second contact feature portion of the test element.

38. The bonded structure according to claim 36, further comprising a plurality of contact feature portions at least partially embedded in the first nonconductive bonding layer, wherein the first nonconductive bonding layer and the plurality of contact feature portions cooperate to at least partially constitute a bonding surface capable of direct hybrid bonding.

39. The bonded structure according to claim 36, wherein one or more traces are not connected to a contact pad at the bonding surface of the bonded structure.

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