Method and apparatus for information transmission

Abstract

Methods, apparatuses, and systems related to polar adjusted convolution (PAC) coding with variable length are disclosed. In one exemplary aspect, a method for digital communication includes determining, by a first node, an output bit sequence having E bits based on an input bit sequence having K bits. The output bit sequence is determined based on a transformation applied prior to applying a polar transform having a size of N. The transformation is based on at least one set of indices that is a subset of a set of bit indices. The set of bit indices comprises all non-negative integers less than N, and K < N and K < E. The method also includes transmitting, by the first node, a signal including the output bit sequence to a second node.

Description

Technical Field

[0001] This patent document is directed to digital communications.

Background Art

[0002] Mobile communication technology is leading the world towards an increasingly connected and networked society. The rapid growth and technological progress of mobile communications have led to a further demand for capacity and connectivity. Other aspects such as energy consumption, device cost, spectral efficiency, and latency are also important in order to meet the requirements of various communication scenarios. Various techniques, including new ways to provide higher quality of service, longer battery life, and improved performance, are being discussed.

Summary of the Invention

Means for Solving the Problems

[0003] This patent document describes, among other things, techniques related to polar modulation convolutional (PAC) coding with variable length that are disclosed.

[0004] In one exemplary aspect, a method for digital communication includes determining, by a first node, an output bit sequence having E bits based on an input bit sequence having K bits. The output bit sequence is determined based on a transformation applied prior to applying a polar transform having a size of N. The transformation is based on at least one index set that is a subset of a set of bit indices. The set of bit indices comprises all non-negative integers less than N, and K < N and K < E. The method also includes transmitting, by the first node, a signal including the output bit sequence to a second node.

[0005] In another exemplary aspect, a method for digital communication includes receiving, by a second node, a signal including an output bit sequence having E bits from a first node. The method also includes determining, by the second node, an input bit sequence having K bits by decoding the output bit sequence included in the signal. The input bit sequence is determined based on a transformation that is applied after applying an inverse polar transform having a size of N. The transformation is based on at least one index set that is a subset of a set of bit indices. The set of bit indices comprises all non-negative integers less than N, and K < N and K < E.

[0006] In another exemplary aspect, a communication device is disclosed. The device includes a processor configured to perform the method described above.

[0007] In yet another exemplary aspect, a computer program storage medium is disclosed. The computer program storage medium includes code stored thereon. The code, when executed by a processor, causes the processor to perform the method described.

[0008] These and other aspects are described in this document.

Brief Description of the Drawings

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[0034] In the 5th generation (5G) mobile communication standard of the 3rd Generation Partnership Project (3GPP (registered trademark)), a low density parity check (LDPC) code is used for data transmission. However, the LDPC code does not perform as well as the polar code at short payload sizes (also referred to as transport block sizes (TBS)). The LDPC code also has a high error floor (e.g., at a block error rate (BLER) of 0.0001). There is a need for more powerful channel coding to fulfill future ultra-reliable low-latency communication (URLLC).

[0035] The polar adjusted convolutional (PAC) code can achieve the finite length boundary at a moderate decoding complexity. As a result, the PAC code has a code length of N as a polar code, where N = 2 n and n is a positive integer. However, the size of the payload or transport block (TB) in different wireless channel environments is always N = 2 in the time and frequency resources allocated by the base station (BS). nIt does not have the code length of. A rate matching scheme is thus required for applying the PAC code in wireless communication to efficiently transmit the payload. This patent document discloses techniques that can be implemented in various embodiments to enable variable lengths of PAC coding to adapt to different payload sizes in wireless communication for improving efficiency.

[0036] The headings of the following sections are used in this document only to improve readability and do not limit the scope of the disclosed embodiments and techniques within each section to that section only. A certain feature is described using an example of a 5G wireless protocol. However, the applicability of the disclosed techniques is not limited to only 5G wireless systems.

[0037] (Notation)

[0038] GF(2) represents a Galois field of size 2 with two elements, "0" and "1".

[0039] br(i) represents a bit reversal function.

[0040] floor(x) represents the largest integer less than or equal to x.

[0041] min(x,y) represents the minimum value between x and y, that is, [Number] is.

[0042] mod(x,y) represents the remainder when x is divided by y. For example, mod(5,3)=2 and mod(3,5)=3.

[0043] X i,j represents the element at the i-th row and j-th column of the matrix X, and boldface capital letters are used to represent matrices.

[0044] [x 0 ,x 1, ···, x Y-1 represents a column (or vector) of length Y containing the elements x 0 , x 1 , ···, x Y-1 .

[0045] {x 0 , x 1 , ···, x Y-1} represents a set with Y distinct elements x 0 , x 1 , ···, x Y-1 , and for any i ≠ j, x i ≠ x j .

[0046] <x 0 , x 1 , ···, x Y-1 > represents an ordered set with Y distinct elements x 0 , x 1 , ···, x Y-1 , and for any i ≠ j, x i ≠ x j . If X = <x 0 , x 1 , ···, x Y-1 >, then X(i) represents the i-th element x i in the ordered set X.

[0047] For the set X, |X| represents the set size (the number of elements in the set X).

[0048] Z N = {0, 1, ···, N - 2, N - 1} represents an integer set containing all non - negative integers less than N.

[0049] A matrix with Yr rows and Yc columns is called a Yr × Yc matrix.

[0050] The upper - triangular matrix X with Yr rows and Yc columns has an element X i,jis 0 for any j < i, where i is a non - negative integer smaller than Yr, j is a non - negative integer smaller than Yc, and Yr and Yc are positive integers.

[0051] Indices for columns, vectors, or matrices start from zero.

[0052] Additional notations are listed in Table 1 below.

Table 1 - 1

Table 1 - 2

[0053] In the 3GPP (registered trademark) 5G standard, polar codes are used in control channel transmission. Figure 1 illustrates an exemplary schematic diagram of 5G polar coding with rate matching. Let Q be represented as a set of data - bit indices of size K, |Q| = K, and Q is a subset of the set of integers Z N ={0, 1, ···, N - 2, N - 1}. Then, for the output bit sequence e = [e (N) , e 0 , ···, e 1 , e E-2 , e E-1 of 5G polar coding with the polar matrix G 0 , c 1 , ···, c K-2 , c K-1 of the input bit sequence c = [c

[0054] Operation 110: Addition of frozen bits. The addition operation 110 of frozen bits combines N - K zero bits with the input bit sequence c and, according to the data - bit index set Q, forms a polar - transform input sequence u = [u 0 , u 1 , ···, u N-2 , u N-1is formed. The polar transform input sequence u is determined by the input bit sequence c, the data bit index set Q, and the polar matrix size N as follows. [Number]

[0055] Operation 120: Polar transform. The polar transform operation 120 converts a first length-N bit sequence into a second length-N bit sequence by multiplying a first length-N bit sequence by a polar matrix G (N) on GF(2). The length-N polar transform output bit sequence d = [d 0 , d 1 , ···, d N-2 , d N-1 is determined by the polar transform input sequence u and the polar matrix G (N) as d = u · G (N) on GF(2).

[0056] Operation 130: Rate matching. The rate matching operation of polar coding in 5G involves two operations, namely, sub-block interleaving and bit selection.

[0057] (1) Sub-block interleaving: The interleaving output bit sequence d' = [d' 0 , d' 1 , ···, d' N-2 , d' N-1 is determined by the sub-block interleaver pattern π of length 32, the polar transform output bit sequence d, and the polar matrix size N as follows. [Number]

[0058] Here, π = [π 0 , π 1 , π 2 , π 3 , π 4 , π 5 , π 6 , π7 , π 8 , π 9 , π 10 , π 11 , π 12 , π 13 , π 14 , π 15 , π 16 , π 17 , π 18 , π 19 , π 20 , π 21 , π 22 , π 23 , π 24 , π 25 , π 26 , π 27 , π 28 , π 29 , π 30 , π 31 = [0, 1, 2, 4, 3, 5, 6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24, 25, 26, 28, 27, 29, 30, 31] and J = [J 0 , J 1 , ···, J N-2 , J N-1 is an interleaver pattern of length N determined by the sub-block interleaver pattern π and the polar matrix size N. The interleaver pattern J is a permutation of the integer sequence [0, 1, 2, ···, N - 2, N - 1].

[0059] (2) Bit Selection: There are three types of bit selection named repetition, puncturing, and shortening. Using the interleaved output bit sequence d’, the length K of the input bit sequence, the length E of the output bit sequence, and the polar matrix size N, the output bit sequence e is determined as follows.

[0060] A. Repetition: For E ≥ N,

[0061] e k = d’ mod(k,N) , k = 0, 1, 2, ···, E - 2, E - 1.

[0062] B: Puncturing: For E < N and K / E ≤ 7 / 16,

[0063] e k = d’ N-E+k , where k = 0, 1, 2, ···, E - 2, E - 1.

[0064] C. Truncation: For E < N and K / E > 7 / 16,

[0065] e k = d’ k , where k = 0, 1, 2, ···, E - 2, E - 1.

[0066] Rate matching can alternatively be described as follows. Let R = <R(0), R(1), ···, R(N r - 2), R(N r - 1)> be represented as an ordered rate - matching index set of size N r = min(E, N). The ordered rate - matching index set R is a subset of the set of integers Z N . Then, using the polar - transformed output bit sequence d, the ordered rate - matching index set R, the length E of the output bit sequence, and the polar - matrix size N, the output bit sequence e is determined as e k = d R(mod(k,N)) , where k = 0, 1, 2, ···, E - 2, E - 1. Here, for bit selection with iteration, the ordered rate - matching index set R = <J 0 , J 1 , ···, J N-2 , J N-1 >. For bit selection with puncturing, the ordered rate - matching index set R = <J N-E , J N-E+1 , J N-E+2 , ···, J N-2 , J N-1 >. For bit selection with truncation, the ordered rate - matching index set R = <J 0 , J 1 , ···, J E-2 , J E-1 >. J = [J 0,J 1 ,···,J N-2 ,J N-1 is an interleaver pattern of length N determined in the sub-block interleaving operation.

[0067] (PAC coding)

[0068] The PAC code is a class of pre-transformed polar codes. Specifically, the PAC code is a polar code that uses convolutional transformation. FIG. 2 illustrates an exemplary schematic diagram of PAC coding. Let Q be represented as a set of data bit indices of size K, |Q| = K, and Q is a subset of the set of integers Z N ={0, 1, ···, N - 2, N - 1}. Then, the output bit sequence e = [e (N) , e 0 , ···, e 1 , e E-2 , e E-1 from the input bit sequence c = [c 0 , c 1 , ···, c K-2 , c K-1 by the polar matrix G includes the following operations, where K is the length of the input bit sequence, E is the length of the output bit sequence, K < N, K < E, and K and E are positive integers.

[0069] Operation 210: Rate profiling. The rate profiling 210 shown in FIG. 2 is the same operation as the addition operation of frozen bits in 5G polar coding. The rate profiling operation combines N - K zero bits with the input bit sequence c and forms a rate profiling output sequence v = [v 0 , v 1 , ···, v N-2 , v N-1 of length N according to the data bit index set Q. Specifically, the rate profiling output bit sequence v is determined by the input bit sequence c, the data bit index set Q, and the polar matrix size N as follows.

Number

[0070] Operation 220: Convolution conversion. The convolution conversion 220 shown in FIG. 2 is a convolution input bit sequence and a generator polynomial g(D) = g 0 +g 1 ·D + ··· + g m-1 ·D m-1 +g m ·D m defining a length-(m + 1) generator bit sequence g = [g 0 , g 1 , ···, g m-1 , g m is an operation that converts a convolution input bit sequence of length N into a convolution output bit sequence of length N by performing convolution. Here, m is the memory length of the convolution conversion, or equivalently, the generator polynomial degree of the generator polynomial g(D). D is a dummy variable representing delay in a digital circuit. FIG. 3 illustrates an example of convolution conversion with the generator polynomial g(D). Specifically, the convolution conversion output bit sequence u = [u 0 , u 1 , ···, u N-2 , u N-1 is determined by the rate profiling output bit sequence v, the generator polynomial g(D) (or equivalently, the generator bit sequence g), and the polar matrix size N as follows.

Equation

[0071] Operation 230: Polar conversion. The polar conversion 230 as shown in FIG. 2 is the same as that in 5G polar coding. The polar conversion output bit sequence d = [d 0 , d 1 , ···, d N-2 , d N-1 is d = u · G (N) according to the convolution conversion output bit sequence u and the polar matrix G (N)is determined as, and the vector-matrix multiplication is over GF(2).

[0072] (Combination of rate profiling and convolutional transformation for precoding)

[0073] The combination of rate profiling and convolutional transformation is precoding for PAC code, specifically, convolutional precoding. The precoding input bit sequence is the input bit sequence c = [c 0 , c 1 , ···, c K-2 , c K-1 of length K, and the precoding output bit sequence is the convolutional transformation output bit sequence u = [u 0 , u 1 , ···, u N-2 , u N-1 of length N. A state bit sequence t = [t 0 , t 1 , t 2 , ···, t m-1 , t m of length m + 1 is defined. The precoding output bit sequence u corresponds to the precoding input sequence c, a data bit index set Q of size K, a generator polynomial g(D) = g 0 + g 1 ·D + ··· + g m-1 ·D m-1 + g m ·D m on GF(2), a generator bit sequence g = [g 0 , g 1 , ···, g m-1 , g m of length -(m + 1), and is determined by the polar matrix size N.

Number

[0074] (Explanation of vector-matrix multiplication for rate profiling of PAC coding)

[0075] The rate profiling operation in PAC coding can be described as a vector-matrix multiplication over GF(2). Specifically, the rate profiling output bit sequence v is determined by v = c·F with the input bit sequence c, where F is a rate profiling matrix with K rows and N columns defined by a data bit index set Q of size K with the following properties.

[0076] (1) The rate profiling matrix F contains all K rows in the N×N identity matrix, and the row indices belong to the data bit index set Q.

[0077] (2) For any i and j such that 0 ≦ j < i < N, F i,j = 0, and F i,j is the element at the i-th row and j-th column of the rate profiling matrix F.

[0078] For example, for K = 4, N = 8, and Q = {3, 5, 6, 7}, the rate profiling matrix F is a matrix with 4 rows and 8 columns as follows.

Number

[0079] (Explanation of vector-matrix multiplication for the convolutional transformation of PAC coding)

[0080] Similar to rate profiling, the convolutional transformation in PAC coding can be described as a vector-matrix multiplication over GF(2). Specifically, the convolutional transformation output bit sequence u of length N is determined by u = v·C with the convolutional transformation input bit sequence of length N (the rate profiling output bit sequence v of length N), where C is a convolutional transformation matrix with N rows and N columns, which is a generator polynomial g(D) = g 0 + g 1 ·D + ··· + g m-1 ·D m-1 + g m ·D m(or, equivalently, a generator bit string g of length -(m+1) = [g 0 ,g 1 ,···,g m-1 ,g m ]) and the polar matrix size N. The convolution transformation matrix C is defined as

number

number

[0081] For example, N=8 and generator bit string g=[g 0 ,g 1 ,g 2 ,g 3 ]=[1,0,1,1] and generator polynomial g(D)=g with memory length m=3 0 +g 1 D+g 2 D 2 +g 3 D 3 =1+D 2 +D 3 For, the 8×8 convolution transform matrix C is:

number

[0082] (Explanation of Vector-Matrix Multiplication for Precoding in PAC Coding)

[0083] Using the rate profiling matrix F and the convolutional transformation matrix F, the precoding of PAC coding is u = c·W = c·F·C, where u is the precoding output bit sequence of length N, the input bit sequence c is the precoding input bit sequence of length K, and the matrix multiplication and vector-matrix multiplication are over GF(2). W = F·C is the precoding matrix of PAC coding. The precoding matrix W is an upper triangular matrix with K rows and N columns, and the element W i,j at the i-th row and j-th column of the precoding matrix W is 0 for any j < i where i and j are non-negative integers smaller than N.

[0084] Using the above rate profiling matrix F and convolutional transformation matrix C, the precoding matrix W of PAC coding = F·C is as follows.

Equation

[0085] Referring back to FIG. 1, using the disclosed technique, the output bit sequence e is determined by the first node by at least one of the following: the data index set Q, the rate profiling frozen bit sequence f, the rate profiling matrix F with K rows and N columns, the generator bit sequence g = [g 0 , g 1 , ···, g m over GF(2), the generator polynomial g(D) = g 0 + g 1 ·D + ··· + g m-1 ·D m-1 + g m ·D m , the recursive feedback bit sequence q = [q 0 , q 1 , ···, q m over GF(2), the recursive feedback polynomial q(D) = q 0 + q 1 ·D + ··· + q m ·Dm , a state bit sequence t of length m + 1 = [t 0 , t 1 , ···, t m-1 , t m , a pre - transformation matrix T with N rows and N columns, a precoding matrix W with K rows and N columns, a precoding input index set P I , a precoding output index set P O , a precoding frozen bit sequence h, a polar matrix G with N rows and N columns (N) , or an ordered rate - matching index set R = <R(0), R(1), ···, R(N r - 2), R(N r - 1)>. Here, m is the memory length related to one of the following: generator bit sequence g, generator polynomial g(D), recursive feedback bit sequence q, recursive feedback polynomial q(D), state bit sequence t, N r is the size of the ordered rate - matching index set, N r is equal to the minimum of N and E, N r = min(N, E), and Q, P I , P O , and R are subsets of the first integer set Z N = {0, 1, 2, ···, N - 2, N - 1}. The first integer set Z N = {0, 1, 2, ···, N - 2, N - 1} contains all non - negative integers less than N.

[0086] Details about the above - mentioned sets, sequences, matrices, and / or polynomials are further discussed below.

[0087] (Data index set Q): The data index set Q is the first integer set Z Nis a subset of, and the number of elements in the data index set Q is equal to the length K of the input bit string (the data index set Q has K elements. That is, the data index set size is K). The elements in the data index set Q are non - negative integers smaller than the polar matrix size N. In a first specific example where N = 8 and K = 4, the data index set is Q = {3, 5, 6, 7}. In a second specific example where N = 32 and K = 25, the data index set is Q = {5, 9, 6, 17, 10, 18, 12, 20, 24, 7, 11, 19, 13, 14, 21, 26, 25, 22, 28, 15, 23, 31, 27, 29, 30}.

[0088] (Rate profiling frozen bit string f): In some embodiments, the rate profiling frozen bit string f can be any bit string of length N - K. In a specific example where N = 8 and K = 3, the rate profiling frozen bit string is f = [1, 1, 0, 0, 1]. In another specific example where N = 8 and K = 3, the rate profiling frozen bit string is f = [0, 0, 0, 0, 0]. In a third specific example where N = 32 and K = 25, the rate profiling frozen bit string f is a bit string of all zeros with length N - K = 32 - 25 = 7. In some embodiments, the rate profiling frozen bit string f can be any bit string of length N. In a specific example where N = 8, the rate profiling frozen bit string is f = [0, 0, 0, 1, 1, 1, 0, 1]. In another specific example where N = 8, the rate profiling frozen bit string is f = [0, 0, 0, 0, 0, 0, 0, 0]. In a third specific example where N = 32, the rate profiling frozen bit string f is a bit string of all zeros with length N = 32.

[0089] (Rate profiling matrix F): The rate profiling matrix F is an upper - triangular matrix with K rows and N columns having the following properties.

[0090] (1) For any integers i and j such that 0 ≤ j < i < K, F i,j = 0, and F i,jis the element at the i-th row and j-th column of the rate profiling matrix F.

[0091] (2) The rate profiling matrix F includes N - K columns all of which are zero.

[0092] (3) The rate profiling matrix F includes K columns each with only one non-zero element "1", and the K columns each with only one non-zero element "1" form an identity matrix with K rows and K columns.

[0093] In a specific example where K = 4 rows and N = 8 columns, the rate profiling matrix F is as follows.

Number

[0094] The 0-th, 1-st, 2-nd, and 4-th columns are all zero columns, and the 3-rd, 5-th, 6-th, and 7-th columns have only one non-zero element "1",

Number

[0095] (Generator bit sequence g): The generator bit sequence g = [g 0 , g 1 , ···, g m can be any binary sequence of length m + 1, where m is called the memory length. In a specific example where the memory length m = 6, the generator bit sequence is g = [g 0 , g 1 , g 2 , g 3 , g 4 , g 5 , g 6 = [1, 0, 1, 1, 0, 1, 1]. In another specific example where the memory length m = 3, the generator bit sequence is g = [g 0 , g 1 , g 2 , g3 =[1, 1, 0, 1].

[0096] (Generator polynomial g(D)): The generator polynomial g(D) = g 0 + g 1 · D + ··· + g m-1 · D m-1 + g m · D m can be any binary polynomial over GF(2), and m is the degree of the generator polynomial. In a specific example where the memory length m = 6, the generator polynomial is g(D) = g 0 + g 1 · D + g 2 · D 2 + g 3 · D 3 + g 4 · D 4 + g 5 · D 5 + g 6 · D 6 = 1 + 0· D + 1· D 2 + 1· D 3 + 0· D 4 + 1· D 5 + 1· D 6 = 1 + D 2 + D 3 + D 5 + D 6 is. In another specific example where the memory length m = 3, the generator polynomial is g(D) = g 0 + g 1 · D + g 2 · D 2 + g 3 · D 3 = 1 + 1· D + 0· D 2 + 1· D 3 = 1 + D + D 3 is.

[0097] (Recursive feedback bit sequence q): The recursive feedback bit sequence q = [q 0 , q 1 , ···, q m is a binary sequence of length m + 1, where [q 1 , ···, q m is any binary sequence of length m, and q 0= 1, where m is the memory length. In a specific example where the memory length m = 3, the recursive feedback bit sequence is q = [q 0 , q 1 , q 2 , q 3 , q 4 , q 5 , q 6 = [1, 0, 1, 0, 1, 1, 1]. In another specific example where the memory length m = 3, the recursive feedback bit sequence is q = [q 0 , q 1 , q 2 , q 3 = [1, 0, 1, 1].

[0098] (Recursive feedback polynomial q(D)): The recursive feedback polynomial q(D) = q 0 + q 1 · D + ··· + q m-1 · D m-1 + q m · D m is a binary polynomial where the zero - degree coefficient q 0 is 1 and the other coefficients q 1 , ···, q m are arbitrary binary values over GF(2), and m is the memory length. In a specific example where the memory length m = 6, the recursive feedback polynomial is q(D) = q 0 + q 1 · D + q 2 · D 2 + q 3 · D 3 + q 4 · D 4 + q 5 · D 5 + q 6 · D 6 = 1 + 0· D + 1· D 2 + 0· D 3 + 1· D 4 + 1· D 5 + 1· D 6 = 1 + D 2 + D 4 + D 5 + D 6 is. In another specific example where the memory length m = 3, the recursive feedback polynomial is q(D) = q 0 + q1 ·D + q 2 ·D 2 + q 3 ·D 3 = 1 + 0·D + 1·D 2 + 1·D 3 = 1 + D 2 + D 3 is as follows.

[0099] (State bit sequence t): The state bit sequence t is for storing the convolutional state.

[0100] (Pre - transformation matrix T): The pre - transformation matrix T is a binary upper triangular matrix with N rows and N columns, and for any integers i and j such that 0 ≤ j < i < N, T i,j = 0, where T i,j is the element in the i - th row and j - th column of the pre - transformation matrix T.

[0101] (Row characteristics of the pre - transformation matrix T): In some embodiments, the pre - transformation matrix T has N - N r rows all of whose elements are zero, and N r is the size of an ordered set of rate - matching indices. In some embodiments, for a row index i not belonging to the ordered set of rate - matching indices R, all elements in the i - th row of the pre - transformation matrix T are zero. In some embodiments, the pre - transformation matrix T has N - 1 - Q max rows all of whose elements are zero, and Q max is the element having the maximum value in the data index set Q, [Number] is as follows. In some embodiments, the pre - transformation matrix T has all elements in the last N - 1 - Q max rows being zero, and Q max is the element having the maximum value in the data index set Q, [Number] is. In some embodiments, the pre - transformation matrix T has all elements in the i - th row equal to zero for i greater than Q max and Q max is the element having the maximum value in the data index set Q,

Number

Number

Number

Number

[0102] (Column characteristics of the pre - transformation matrix T): In some embodiments, the pre - transformation matrix T has N - N r columns all of whose elements are zero, and N ris the size of an ordered rate matching subscript set. In some embodiments, for a column subscript j that does not belong to the ordered rate matching subscript set R, all elements in the j-th column of the pre-transformation matrix T are zero. In some embodiments, the pre-transformation matrix T has N - 1 - Q max columns all of whose elements are zero, and Q max is the element having the maximum value in the data subscript set Q,

Number

Number

Number

Number

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Number

[0103] (Preliminary coding matrix W): The preliminary coding matrix W has K rows and N columns with the following properties: For any integers i and j such that 0 ≦ j < i < K, W i,j = 0, and W i,j is a binary upper triangular matrix, where is the element in the i - th row and j - th column of the preliminary coding matrix W.

[0104] In some embodiments, the preliminary coding matrix W has at least N - N r columns with all elements being zero, where N r is the set size of the ordered rate - matching index set R. For column indices j not belonging to the ordered rate - matching index set R in some embodiments, all elements in the j - th column of the preliminary coding matrix W are zero.

[0105] In some embodiments, the preliminary coding matrix W has N - 1 - R max columns with all elements being zero, where R max is the element having the maximum value in the data index set R

Number

Number

[0106] (Ordered rate-matching index set R): The ordered rate-matching index set R is an arbitrary subset of the first integer set Z r having N N elements, where N r =min(N, E), and the elements in the ordered rate-matching index set R are non-negative integers smaller than the size N of the polar matrix. The first specific example of the ordered rate-matching index set R is when the size N r =N, and R contains all the elements in the first integer set Z N , i.e., R = <R(0), R(1), R(2), ···, R(N r -2), R(N r -1)> = <0, 1, 2, ···, N-2, N-1>. The second specific example of the ordered rate-matching index set R is when the size N r =E, and R contains all non-negative integers smaller than E, i.e., R = <R(0), R(1), R(2), ···, R(N r -2), R(N r -1)> = <0, 1, 2, ···, E-2, E-1>. The third specific example of the ordered rate-matching index set R is when the size N r =E, and R contains all integers smaller than N and greater than N-E-1, i.e., R = <R(0), R(1), R(2), ···, R(N r -2), R(N r -1)> = <N-E, N-E+1, N-E+2, ···, N-2, N-1>. Let J = [J 0 , J 1 , ···, J N-2 , J N-1 be the sub-block interleaver pattern π = [π 0 , π 1 , π 2 , π 3 , π 4 , π 5 , π 6 , π 7 , π 8 , π 9, π 10 , π 11 , π 12 , π 13 , π 14 , π 15 , π 16 , π 17 , π 18 , π 19 , π 20 , π 21 , π 22 , π 23 , π 24 , π 25 , π 26 , π 27 , π 28 , π 29 , π 30 , π 31 = [0, 1, 2, 4, 3, 5, 6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24, 25, 26, 28, 27, 29, 30, 31] and the interleaver pattern of length N determined by the polar matrix size N. Here, J = [J 0 , J 1 , ···, J N-2 , J N-1 is an interleaver pattern that is a permutation of the integer sequence [0, 1, 2, ···, N - 2, N - 1], and a specific example of J is defined as follows.

Number

[0107] The fourth specific example of the ordered rate matching index set R is that the size N r = N, and R contains all elements in the first integer set Z N . R = <R(0), R(1), R(2), ···, R(N r - 2), R(N r - 1)> = <J 0 , J 1 , ···, J N-2 , J N-1 >, and J i is the interleaver pattern J = [J 0 , J 1 , ···, J N-2,J N-1 is the i-th element in. The fifth specific example of the ordered rate matching index set R has size N r =E, and R contains all elements in the interleaver pattern J with indices smaller than E. R = <R(0), R(1), R(2), ···, R(N r -2), R(N r -1)> = <J 0 ,J 1 , ···, J E-2 ,J E-1 >, where J i is the i-th element in the interleaver pattern J = [J 0 ,J 1 , ···, J N-2 ,J N-1 . The sixth specific example of the ordered rate matching index set R has size N r =E, and R contains all elements in the interleaver pattern J with indices greater than N - E - 1 and smaller than N. R = <R(0), R(1), R(2), ···, R(N r -2), R(N r -1)> = <J N-E ,J N-E+1 ,J N-E+2 , ···, J N-2 ,J N-1 >, where J i is the i-th element in the interleaver pattern J = [J 0 ,J 1 , ···, J N-2 ,J N-1 .

[0108] (Preamcoding input set P I ): The pre-coding input index set P I can be any subset of the first integer set Z N . The pre-coding input set P I can be used in the pre-conversion operation of pre-coding to enable variable length in order to improve the transmission efficiency of the payload.

[0109] Pre-coding input index set PI The first specific example of N is P which is equal to the first set of integers Z I . The pre-coding input index set P I 's second specific example is that P I consists of all non-negative integers where P max is less than or equal to Q, and P I = Q max + 1 elements, {0, 1, 2, ···, Q max - 1, Q max}, where Q max is the element with the maximum value in the data index set Q,

Number

Number

[0110] (Pre-coding output set P O ): The pre-coding output index set P O can be any subset of the first set of integers Z N . The pre-coding output index set P O can be used in the pre-conversion operation of pre-coding to enable variable length in order to improve the transmission efficiency of the payload.

[0111] Preamble output subscript set P O The first specific example of N is P equal to the first integer set Z O . The preamble output subscript set P O The second specific example of is P O where P consists of all non-negative integers less than or equal to Q max , and P O = Q max +1 elements, {0, 1, 2, ···, Q max -1, Q max}, where Q max is the element with the maximum value in the data subscript set Q,

Number

Number

[0112] (Preamble frozen bit sequence h): In some embodiments, the preamble frozen bit sequence h can be any bit sequence of length N - N PO , where N PO is the size of the preamble output subscript set P O , and N is the polar matrix size. In a specific example where N = 8 and N PO = 5, the preamble frozen bit sequence is of length N - N POh = [1, 0, 1] where 8 - 5 = 3. N = 32 and N PO In another specific example where N = 5, the pre - coding frozen bit sequence h is a sequence of all zeros with length N - N PO = 32 - 5 = 27.

[0113] In some embodiments, the pre - coding frozen bit sequence h can be any bit sequence of length N, where N is the polar matrix size. In a specific example where N = 8, the pre - coding frozen bit sequence is h = [0, 0, 0, 0, 0, 1, 0, 1] of length N = 8. In another specific example where N = 32, the pre - coding frozen bit sequence h is a sequence of all zeros of length N = 32.

[0114] (Polar matrix G (N) ): The polar matrix G with N rows and N columns (N) is one of the following:

Number

Number

Number

Number

Number

[0115] FIGS. 5A-5C illustrate examples of polar coding according to one or more embodiments of the present technology. In some embodiments, precoding includes obtaining a precoding input bit sequence and determining a precoding output bit sequence u = [u 0 , u 1 , ···, u N-1 , where the precoding input bit sequence is an input bit sequence c of length K, and the precoding output bit sequence u is of length equal to the polar matrix size N. In some embodiments, as shown in FIGS. 5A-5C, an output bit sequence e = [e 0 , e 1 , ···, e E-1 is determined by setting an input bit sequence c of length K as the precoding input bit sequence and determining a precoding output bit sequence u of length N using at least one of the following: a data index set Q, a rate profiling frozen bit sequence f, a rate profiling matrix F with K rows and N columns, a generator bit sequence g = [g 0 , g 1 , ···, gm , a generator polynomial g(D) = g over GF(2) 0 + g 1 · D + ··· + g m-1 · D m-1 + g m · D m , a recursive feedback bit sequence q = [q 0 , q 1 , ···, q m , a recursive feedback polynomial q(D) = q over GF(2) 0 + q 1 · D + ··· + q m · D m , a pre - transformation matrix T with N rows and N columns, a precoding matrix W with K rows and N columns, a precoding input index set P I , a precoding output index set P O , a precoding frozen bit sequence h.

[0116] (Characteristics of the precoding output bit sequence u)

[0117] In some embodiments, the i - th bit u i in the precoding output sequence u is determined by a subset of elements in the precoding input bit sequence c with indices in the set of non - negative integers {0, 1, 2, ···, i - 1, i} that are less than or equal to i.

[0118] In some embodiments, the i - th bit u i in the precoding output sequence u is a linear combination over GF(2) of the elements c 0 , c 1 , c 2 , ···, c i-1 , c i in the precoding input bit sequence c.

[0119] In some embodiments, the i - th output bit u iis a subsequence of the precoding input sequence c with indices in the set {0, 1, 2, , NE(i)-2, NE(i)-1} and a rate profile frozen bit sequence f = [f 0 ,f 1 , ,f N-K-1 , i}∩Q, and the rate profile freezing bit sequence f can be any binary sequence of length N K. In some embodiments, the rate profile freezing bit sequence f is a sequence of all zeros of length N K.

[0120] In some embodiments, the precoding output index set P O For i that does not belong to, the i-th output bit u in the precoding output sequence u of length N i is of length NN PO Precoding frozen bit string

number

[0121] In some embodiments, the precoding output index set P O For i that does not belong to, the i-th output bit u in the precoding output sequence u of length N i is set to bit 0.

[0122] In some embodiments, the i-th bit u in the precoding output sequence u i is determined by both the subset of elements in the precoding input bit sequence c with indices in the set of integers {0, 1, 2,..., i-1, i} and the subset of elements in the precoding output bit sequence u with indices in the set of integers {0, 1, 2,..., i-2, i-1}.

[0123] In some embodiments, the i-th bit u in the pre-coding output sequence u i is a linear combination over GF(2) of the elements c 0 , c 1 , c 2 , ···, c i-1 , c i in the pre-coding input bit sequence c and the elements u 0 , u 1 , u 2 , ···, u i-2 , u i-1 in the pre-coding output bit sequence u

[0124] In some embodiments, the pre-coding output bits in the pre-coding output bit sequence u are determined by both (1) the current pre-coding input bit and the preceding pre-coding input bits in the pre-coding input bit sequence c and (2) the current pre-coding output bit and the preceding pre-coding output bits in the pre-coding output bit sequence u

[0125] (Pre-coding using the pre-coding matrix W)

[0126] In some embodiments, the pre-coding input sequence c has a length K. The pre-coding output bit sequence u has a length N. The pre-coding output bit sequence u is determined as u = c · W by performing a vector-matrix multiplication on the pre-coding input bit sequence c and a pre-coding matrix W with K rows and N columns. The pre-coding input sequence c of length K is an input bit sequence of length K, and the vector-matrix multiplication is performed over GF(2)

[0127] (Pre-coding using the pre-coding matrix W and the pre-coding frozen bit sequence h)

[0128] In some embodiments, a pre-coding output bit sequence u of length N is determined as u = c·W + h by performing a vector-matrix multiplication on a pre-coding input bit sequence c and a pre-coding matrix W with K rows and N columns, and adding a pre-coding frozen bit sequence h of length N. The pre-coding input sequence c of length K is an input bit sequence of length K. Both the vector-matrix multiplication and the vector-vector addition are performed over GF(2).

[0129] (Pre-coding Using a Rate Profiling Matrix F and a Pre-Transformation Matrix T)

[0130] In some embodiments, a pre-coding output sequence u of length N is determined as u = c·F·T by multiplying a pre-coding input sequence c by both a rate profiling matrix F with K rows and N columns and a pre-transformation matrix T with N rows and N columns. The pre-coding input sequence c is an input bit sequence c of length K, N is a polar matrix size, and the matrix multiplication and the vector-matrix multiplication are performed over GF(2).

[0131] In some embodiments, a pre-coding output sequence u of length N is determined as u = (c·F + f)·T by multiplying a pre-coding input sequence c by a rate profiling matrix F over GF(2), adding a rate profiling frozen bit sequence f of length N over GF(2), and multiplying by a pre-transformation matrix T over GF(2), using a rate profiling matrix F with K rows and N columns, a rate profiling frozen bit sequence f of length N, and a pre-transformation matrix T with N rows and N columns. The pre-coding input sequence c is an input bit sequence c of length K. N is a polar matrix size. The matrix multiplication, the vector-matrix multiplication, and the vector-vector addition are performed over GF(2).

[0132] In some embodiments, a precoding output sequence u of length N is determined as u = c·F·T + h over GF(2) by multiplying a rate profiling matrix F with K rows and N columns, a pre - transformation matrix T with N rows and N columns, and adding a precoding frozen - bit sequence h of length N to a precoding input sequence c over GF(2), multiplying the pre - transformation matrix T over GF(2), and multiplying the rate profiling matrix F over GF(2). The precoding input sequence c is an input bit sequence c of length K. N is a polar matrix size. Matrix multiplication, vector - matrix multiplication, and vector - vector addition are performed over GF(2).

[0133] In some embodiments, a precoding output sequence u of length N is determined as u=(c·F + f)·T + h over GF(2) by multiplying a rate profiling matrix F with K rows and N columns, adding a rate profiling frozen - bit sequence f of length N over GF(2), multiplying a pre - transformation matrix T with N rows and N columns, and adding a precoding frozen - bit sequence h of length N over GF(2) to a precoding input sequence c over GF(2), multiplying the pre - transformation matrix T over GF(2), and multiplying the rate profiling matrix F over GF(2). The precoding input sequence c is an input bit sequence c of length K. N is a polar matrix size. Matrix multiplication, vector - matrix multiplication, and vector - vector addition are performed over GF(2).

[0134] (Q, f, g or g(D), P I and P O (precoding determined by h, t)

[0135] In some embodiments, precoding determines a precoding output bit sequence u of length N using at least one of the following: a data index set Q, a rate profiling frozen - bit sequence f, a generator bit sequence g = [g 0 ,g1 , ···, g m , the generator polynomial g(D) = g 0 + g 1 · D + ··· + g m-1 · D m-1 + g m · D m , the pre - coding input index set P I , the pre - coding output index set P O , the pre - coding frozen bit sequence h, or the state bit sequence t = [t 0 , t 1 , ···, t m-1 , t m . The rate - profiling frozen bit sequence f has length N - K, the pre - coding frozen bit sequence h has length N - N PO , and N PO is the size of the pre - coding output index set P O .

[0136] Table 2 shows the exemplary algorithms 1A - 1L which are exemplary implementations related to pre - coding. In the exemplary algorithms 1A - 1L, the state bit sequence t = [t 0 , t 1 , ···, t m-1 , t m is initialized to all zeros. When the index i belongs to the data index set Q, the bit t 0 , t 1 , ···, t m-1 , t m in the state bit sequence t = [t 0 is set to the bit in the pre - coding input bit sequence c. When the index i belongs to the pre - coding output index set P O , the i - th bit u i of the pre - coding output bit sequence u is determined by the generator bit sequence g = [g 0 , g 1 , ···, g m and the state bit sequence t = [t 0 , t 1 , ···, t m-1 , t m , [Number] is. When the subscript i belongs to the pre - coding output subscript set P O in, the i - th bit u i of the pre - coding output bit sequence u is the generator polynomial g(D)=g 0 +g 1 ·D+···+g m-1 ·D m-1 +g m ·D m (for example, as shown in Figure 3) and the state bit sequence t = [t 0 ,t 1 ,···,t m-1 ,t m is determined by [Number] is. [Table 2 - 1] [Table 2 - 2] [Table 2 - 3]

[0137] In some embodiments, when the subscript i does not belong to the data subscript set Q, the bit t 0 ,t 1 ,···,t m-1 ,t m in the state bit sequence t 0 is set to 0, for example, as in Algorithms 1A, 1B, 1C, 1G, 1H, and 1I. In some examples, when the subscript i does not belong to the data subscript set Q, the bit t 0 ,t 1 ,···,t m-1 ,t m in the state bit sequence t 0It is set to the bits in the rate profiling frozen bit sequence f, as shown in, for example, algorithms 1D, 1E, 1F, 1J, 1K, and 1L.

[0138] In some embodiments, if the subscript i does not belong to the pre-coding output subscript set P O the i-th bit u of the pre-coding output bit sequence u i is set to 0, as shown in, for example, algorithms 1A, 1D, 1G, and 1J.

[0139] In some embodiments, if the subscript i does not belong to the pre-coding output subscript set P O the i-th bit u of the pre-coding output bit sequence u i is set to t in the state bit sequence t = [t 0 , t 1 , ···, t m-1 , t m , as shown in, for example, algorithms 1B, 1E, 1H, and 1K. 0 is set to t.

[0140] In some examples, if the subscript i does not belong to the pre-coding output subscript set P O the i-th bit u of the pre-coding output bit sequence u i is set to the bits in the pre-coding frozen bit sequence h, as shown in algorithms 1C, 1F, 1I, and 1L. The pre-coding frozen bit sequence h has a length of N - N PO where N PO is the size of the pre-coding output subscript set P O .

[0141] In some examples, if the subscript i belongs to the pre-coding input subscript set P I a right shift is performed on the state bit sequence t = [t 0 , t 1 , ···, t m-1 , t m as follows.

Number

[0142] In some examples, for all indices i, the right shift is performed on the state bit sequence t = [t 0 , t 1 , ···, t m-1 , t m . [Number]

[0143] The state bit sequence t = [t 0 , t 1 , ···, t m-1 , t m of length m + 1 is for storing the convolutional state. g j can be either an element in the generator bit sequence g or a coefficient in the generator polynomial g(D), as shown in, for example, Figure 3.

[0144] (Q, f, q or q(D), P I , and P O , h, t - determined precoding)

[0145] In some embodiments, the precoding uses at least one of the following to determine a precoding output bit sequence u of length N: data index set Q, rate profiling frozen bit sequence f, recursive feedback bit sequence q = [q 0 , q 1 , ···, q m , recursive feedback polynomial q(D) = q 0 + q 1 · D + ··· + q m · D m , precoding input index set P I , precoding output index set P O , precoding frozen bit sequence h, or state bit sequence t = [t 0 , t 1, ···, t m-1 , t m . The rate profiling frozen bit sequence f has a length of N - K. The pre-coding frozen bit sequence h has a length of N - N PO and N PO is the size of the pre-coding output index set P O .

[0146] Table 3 shows the exemplary algorithm 2A - 2L which is an exemplary implementation regarding pre-coding. In the exemplary algorithm 2A - 2L, the state bit sequence t = [t 0 , t 1 , ···, t m-1 , t m is initialized to all zeros. When the index i belongs to the data index set Q, the bit t 0 in the state bit sequence t = [t 1 , ···, t m-1 , t m is set to the bit in the pre-coding input bit sequence c. When the index i belongs to the pre-coding output index set P 0 , the i-th bit u O of the pre-coding output bit sequence u is determined by the recursive feedback bit sequence q = [q i , q 0 , ···, q 1 , ···, q m and the state bit sequence t = [t 0 , t 1 , ···, t m-1 , t m .

Number

Number

Number

Table 3-1

Table 3-2

Table 3-3

[0147] In some embodiments, when the subscript i does not belong to the data subscript set Q, the bit t 0 in the state bit sequence t = [t 1 , ···, t m-1 , t m is t 0is set to 0, for example, as in Algorithms 2A, 2B, 2C, 2G, 2H, and 2I.

[0148] In some embodiments, if the subscript i does not belong to the data subscript set Q, the bit t 0 ,t 1 , ···, t m-1 ,t m in the state bit sequence t 0 is set to the bit in the rate profiling freeze bit sequence f, for example, as in Algorithms 2D, 2E, 2F, 2J, 2K, and 2L.

[0149] In some embodiments, if the subscript i does not belong to the precoding output subscript set P O , the i-th bit u i of the precoding output bit sequence u is set to 0, for example, as in Algorithms 2A, 2D, 2G, and 2J.

[0150] In some embodiments, if the subscript i does not belong to the precoding output subscript set P O , the i-th bit u i of the precoding output bit sequence u is set to t 0 ,t 1 , ···, t m-1 ,t m in the state bit sequence t=[t 0 , for example, as in Algorithms 2B, 2E, 2H, and 2K.

[0151] In some embodiments, if the subscript i does not belong to the precoding output subscript set P O , the i-th bit u i of the precoding output bit sequence u is set to the bit in the precoding freeze bit sequence h, for example, as in Algorithms 2C, 2F, 2I, and 2L. The precoding freeze bit sequence h has a length of N - N PO , where N PO is the precoding output subscript set P Ois the size of.

[0152] In some examples, when the subscript i belongs to the pre - coding input subscript set P I a right shift is performed on the state bit sequence t = [t 0 , t 1 , ···, t m-1 , t m as follows.

Number

[0153] In some examples, for all subscripts i, a right shift is performed on the state bit sequence t = [t 0 , t 1 , ···, t m-1 , t m as follows.

Number

[0154] t = [t 0 , t 1 , ···, t m-1 , t m is a state bit sequence of length m + 1 for storing the convolutional state. q j can be either an element in the recursive feedback bit sequence q or a coefficient in the recursive feedback polynomial q(D).

[0155] (Pre - coding determined by (Q, f, g or g(D), q or q(D), P I , and P O , h, t))

[0156] In some embodiments, the pre - coding uses at least one of the following to determine a pre - coding output bit sequence u of length N: data subscript set Q, rate - profiling frozen bit sequence f, generator bit sequence g = [g 0 , g 1 , ···, gm , the generator polynomial g(D) = g 0 + g 1 · D + ··· + g m · D m , the recursive feedback bit sequence q = [q 0 , q 1 , ···, q m , the recursive feedback polynomial q(D) = q 0 + q 1 · D + ··· + q m · D m , the pre - coding input index set P I , the pre - coding output index set P O , the pre - coding frozen bit sequence h, or the state bit sequence t = [t 0 , t 1 , ···, t m-1 , t m . The rate - profiling frozen bit sequence f has length N - K. The pre - coding frozen bit sequence h has length N - N PO , where N PO is the size of the pre - coding output index set P O .

[0157] Table 4 shows the exemplary algorithm 3A - 3L which is an exemplary implementation regarding pre - coding. In the exemplary algorithm 3A - 3L, the state bit sequence t = [t 0 , t 1 , ···, t m-1 , t m is initialized to all zeros. When the index i belongs to the data index set Q, the bit t 0 in the state bit sequence t = [t 1 , ···, t m-1 , t m is set to the bit in the pre - coding input bit sequence c. When the index i belongs to the pre - coding output index set P 0 , the i - th bit u O of the pre - coding output bit sequence u is the generator bit sequence g = [g i , g 0 , ···, g 1 , ···, g m(or a generator polynomial g(D) = g 0 + g 1 · D + ··· + g m · D m )、a recursive feedback bit sequence q = [q 0 , q 1 , ···, q m (or a recursive feedback polynomial q(D) = q 0 + q 1 · D + ··· + q m · D m ), and a state bit sequence t = [t 0 , t 1 , ···, t m-1 , t m . FIG. 7 illustrates another example of a recursive convolutional transform according to one or more embodiments of the present technology. The recursive convolutional transform is determined by a generator bit sequence g = [g 0 , g 1 , ···, g m and / or a recursive feedback bit sequence q = [q 0 , q 1 , ···, q m , or a generator polynomial g(D) = g 0 + g 1 · D + ··· + g m-1 · D m-1 + g m · D m and / or a recursive feedback polynomial q(D) = q 0 + q 1 · D + ··· + q m · D m , where q 0 = 1. The determination is based on a recursive feedback bit sequence q = [q 0 , q 1 , ···, q m (or a recursive feedback polynomial q(D) = q 0 + q 1 · D + ··· + q m · D m ) and a state bit sequence t = [t 0 , t 1 , ···, t m-1 , tm Based on [], the sum bit s is

Number

Number

Table 4-1

Table 4-2

Table 4-3

[0158] In some embodiments, when the subscript i does not belong to the data subscript set Q, for the state bit sequence t = [t 0 , t 1 , ···, t m-1 , t m , the bit t 0Is set to 0, for example, as in Algorithms 3A, 3B, 3C, 3G, 3H, and 3I. In some embodiments, if the subscript i does not belong to the data subscript set Q, the bit t 0 ,t 1 ,···,t m-1 ,t m in the state bit sequence t 0 Is set to the bit in the rate profiling freeze bit sequence f, for example, as in Algorithms 3D, 3E, 3F, 3J, 3K, and 3L. In some embodiments, if the subscript i does not belong to the pre-coding output subscript set P O , the i-th bit u i of the pre-coding output bit sequence u is set to 0, for example, as in Algorithms 3A, 3D, 3G, and 3J. In some embodiments, if the subscript i does not belong to the pre-coding output subscript set P O , the i-th bit u i of the pre-coding output bit sequence u is set to t 0 ,t 1 ,···,t m-1 ,t m in the state bit sequence t=[t 0 , for example, as in Algorithms 3B, 3E, 3H, and 3K.

[0159] In some embodiments, if the subscript i does not belong to the pre-coding output subscript set P O , the i-th bit u i of the pre-coding output bit sequence u is set to the bit in the pre-coding freeze bit sequence h, for example, as in Algorithms 3C, 3F, 3I, and 3L. The pre-coding freeze bit sequence h has a length of N - N PO , where N PO is the size of the pre-coding output subscript set P O . In some examples, if the subscript i belongs to the pre-coding input subscript set P I , a right shift is performed on the state bit sequence t=[t0 , t 1 , ···, t m-1 , t m is performed on

Number

[0160] In some examples, for all subscripts i, the right shift is, for example, as in algorithms 3G, 3H, 3I, 3J, 3K, and 3L, as follows, on the state bit sequence t = [t 0 , t 1 , ···, t m-1 , t m .

Number

[0161] t = [t 0 , t 1 , ···, t m-1 , t m is a state bit sequence of length m + 1 for storing the convolutional state. g j can be either an element in the generator bit sequence g or a coefficient in the generator polynomial g(D). q j can be either an element in the recursive feedback bit sequence q or a coefficient in the recursive feedback polynomial q(D).

[0162] In some embodiments, pre - coding includes rate profiling and pre - transformation. Rate profiling includes obtaining, by a first node, a rate profiling input bit sequence and determining, by the first node, a rate profiling output bit sequence v = [v 0 , v 1 , ···, v N-1 . Pre - transformation includes obtaining, by the first node, a pre - transformation input bit sequence and determining, by the first node, a pre - transformation output bit sequence.

[0163] Figures 8A - 8C illustrate an example of polar coding with pre - conversion and rate - matching according to one or more embodiments of the present technology. The rate - profiling input bit sequence is the input bit sequence c of length K. The rate - profiling output bit sequence v has a length equal to the polar matrix size N. The pre - conversion input bit sequence is the rate - profiling output bit sequence v of length N. The pre - conversion output bit sequence is the pre - coding output bit sequence u of length N.

[0164] (Rate - profiling): Rate - profiling includes obtaining, by a first node, the rate - profiling input bit sequence, and determining, by the first node, the rate - profiling output bit sequence v = [v 0 , v 1 , ···, v N-1 . As shown in Figures 8A - 8C, the rate - profiling input bit sequence is the input bit sequence c of length K. The rate - profiling output bit sequence v has a length equal to the polar matrix size N.

[0165] (Pre - conversion): Pre - conversion includes obtaining, by a first node, the pre - conversion input bit sequence, and determining, by the first node, the pre - conversion output bit sequence u = [u 0 , u 1 , ···, u N-1 . As shown in Figures 8A - 8C, the pre - conversion input bit sequence is the rate - profiling output bit sequence v of length N. The pre - conversion output bit sequence u has a length equal to the polar matrix size N.

[0166] (Parameters related to rate - profiling): Rate - profiling determines, by a first node, the rate - profiling output bit sequence v corresponding to the rate - profiling input bit sequence c using at least one of the following: the data index set Q, the rate - profiling matrix F with K rows and N columns, or the rate - profiling frozen bit sequence f.

[0167] In some embodiments, the rate profiling output bit sequence v is a multiplexing of the rate profiling input bit sequence c and the rate profiling freeze bit sequence f. The rate profiling freeze bit sequence f has a length of N - K, where N is the polar matrix size and K is the rate profiling input bit sequence length. A first specific example with N = 8 and K = 3 has a rate profiling input bit sequence c = [c 0 , c 1 , c 2 and a rate profiling freeze bit sequence f = [f 0 , f 1 , f 2 , f 3 , f 4 , and the rate profiling output bit sequence v = [v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 = [f 0 , f 1 , f 2 , f 3 , f 4 , c 0 , c 1 , c 2 . A second specific example with N = 16 and K = 4 has a rate profiling input bit sequence c = [c 0 , c 1 , c 2 , c 3 and a rate profiling freeze bit sequence f = [f 0 , f 1 , f 2 , f 3 , f 4 , f 5 , f 6 , f 7 , f 8 , f 9 , f 10 , f 11 , and the rate profiling output bit sequence v = [v 0 , v 1 , v 2 , v 3 , v4 , v 5 , v 6 , v 7 , v 8 , v 9 , v 10 , v 11 , v 12 , v 13 , v 14 , v 15 = [f 0 , f 1 , f 2 , f 3 , f 4 , f 5 , f 6 , f 7 , f 8 , f 9 , f 10 , c 0 , f 11 , c 1 , c 2 , c 3 is. The third specific example is given in Algorithm 4A of Table 5.

[0168] In some embodiments, for the index i belonging to the data index set Q, the bit v in the rate profiling output bit sequence v i is the bit in the rate profiling input bit sequence c. In the first specific example where N = 8, K = 3, and the data index set Q = {5, 6, 7}, the rate profiling input bit sequence c = [c 0 , c 1 , c 2 , and the bits with indices belonging to the data index set Q = {5, 6, 7} in the rate profiling output bit sequence v = [v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 are v 5 , v 6 , v 7 is, v 5 = c 0 , v 6= c 1 , and v 7 = c2 is set as. In a second specific example where N = 16, K = 4, and data index set Q = {11, 13, 14, 15}, the rate profiling input bit sequence c = [c 0 , c 1 , c 2 , c 3 . And the rate profiling output bit sequence v = [v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 , v 8 , v 9 , v 10 , v 11 , v 12 , v 13 , v 14 , v 15 . For the bits v 11 , v 13 , v 14 , v 15 belonging to the data index set Q = {11, 13, 14, 15} in the rate profiling output bit sequence v, they are set as v 11 = c 0 , v 13 = c 1 , v 14 = c 2 , and v 15 = c 3 . The third specific example is given in Algorithm 4A in Table 5. The fourth specific example is given in Algorithm 4B in Table 5.

[0169] In some embodiments, for an index i not belonging to the data index set Q, the bit v i in the rate profiling output bit sequence v is a bit in the rate profiling freeze bit sequence f. In a first specific example where N = 8, K = 3, and Q = {5, 6, 7}, the rate profiling freeze bit sequence f = [f 0 , f 1 , f 2 , f 3 , f 4 . And the rate profiling output bit sequence v = [v0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 The bits v with indices not belonging to the data index set Q = {5, 6, 7} in 0 , v 1 , v 2 , v 3 , v 4 is, v 0 = f 0 , v 1 = f 1 , v 2 = f 2 , v 3 = f 3 , and v 4 = f 4 are set as. In a second specific example where N = 16, K = 4, and Q = {11, 13, 14, 15}, the rate profiling freeze bit sequence f = [f 0 , f 1 , f 2 , f 3 , f 4 , f 5 , f 6 , f 7 , f 8 , f 9 , f 10 , f 11 , and the rate profiling output bit sequence v = [v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 , v 8 , v 9 , v 10 , v 11 , v 12 , v 13 , v 14 , v 15 The bits v with indices not belonging to the data index set Q = {11, 13, 14, 15} in 0 , v 1 , v 2 , v 3 , v4 , v 5 , v 6 , v 7 , v 8 , v 9 , v 10 , v 12 is v 0 = f 0 , v 1= f 1 , v 2 = f 2 , v 3 = f 3 , v 4 = f 4 , v 5 = f 5 , v 6 = f 6 , v 7 = f 7 , v 8 = f 8 , v 9 = f 9 , v 10 = f 10 , and v 12 = f 11 is set as. The third specific example is given in Algorithm 4A of Table 5.

[0170] In some embodiments, the rate profiling output bit sequence v is a multiplexing of the rate profiling input bit sequence c and a sequence of all zeros of length N - K, where N is the size of the parity matrix and K is the length of the rate profiling input bit sequence. A first specific example where N = 8 and K = 3 has a rate profiling input bit sequence c = [c 0 , c 1 , c 2 and a sequence of all zeros of length N - K = 8 - 3 = 5, and the rate profiling output bit sequence v = [v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 = [0, 0, 0, 0, 0, c 0 , c 1 , c 2is as follows. A second specific example with N = 16 and K = 4 has a rate profiling input bit sequence c = [c 0 , c 1 , c 2 , c 3 and a sequence of all zeros of length N - K = 16 - 4 = 12, and the rate profiling output bit sequence v = [v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 , v 8 , v 9 , v 10 , v 11 , v 12 , v 13 , v 14 , v 15 = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, c 0 , 0, c 1 , c 2 , c 3 . A third specific example is given in Algorithm 4B of Table 5.

[0171] In some embodiments, for an index i not belonging to the data index set Q, the bit v i in the rate profiling output bit sequence v is equal to 0. In a first specific example with N = 8, K = 3, and Q = {5, 6, 7}, the bits v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 of the rate profiling output bit sequence v with indices not belonging to the data index set Q = {5, 6, 7} are v 0 , v 1 , v 2 , v 3 , v 4 such that v 0 = 0, v 1= = 0, v 2 = 0, v 3 = 0, and v 4is set to 0. In a second specific example where N = 16, K = 4, and Q = {11, 13, 14, 15}, the rate profiling output bit sequence v = [v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 , v 8 , v 9 , v 10 , v 11 , v 12 , v 13 , v 14 , v 15 has bits v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 , v 8 , v 9 , v 10 , v 12 that do not belong to the data index set Q = {11, 13, 14, 15} are set to v 0 = 0, v 1= 0, v 2 = 0, v 3 = 0, v 4 = 0, v 5 = 0, v 6 = 0, v 7 = 0, v 8 = 0, v 9 = 0, v 10 = 0, and v 12 = 0. The third specific example is given in Algorithm 4B of Table 5.

Table 5

[0172] In some embodiments, the rate profiling output sequence v of length N is the multiplication of the rate profiling input bit sequence c and a rate profiling matrix F with K rows and N columns, such that v = c·F. The rate profiling input bit sequence is the input sequence c of length K, and the vector-matrix multiplication is over GF(2). In a specific example where K = 4 rows and N = 8 columns, the rate profiling matrix

Number

[0173] In some embodiments, the rate profiling output sequence v of length N is determined as v = c·F + f by the addition of the rate profiling frozen bit sequence f and the multiplication of the rate profiling input bit sequence c and a rate profiling matrix F with K rows and N columns. The rate profiling input bit sequence is the input sequence c of length K, the vector-matrix multiplication is over GF(2), the vector-vector addition is over GF(2), and the rate profiling frozen bit sequence f is of length N. In a specific example where K = 4 rows and N = 8 columns, the rate profiling matrix

Number

[0174] (Parameters for determining pre - transformation): The pre - transformation determines, by the first node, the pre - transformation output bit sequence u corresponding to the pre - transformation input bit sequence v using at least one of the following: the generator bit sequence g = [g 0 , g 1 , ···, g m over GF(2), the generator polynomial g(D) = g 0 + g 1 ·D + ··· + g m-1 ·D m-1 + g m ·D m over GF(2), the recursive feedback bit sequence q = [q 0 , q 1 , ···, q m over GF(2), the recursive feedback polynomial q(D) = q 0 + q 1 ·D + ··· + q m ·D m over GF(2), the state bit sequence t = [t 0 , t 1 , ···, t m-1 , t m of length m + 1, the pre - transformation matrix T with N rows and N columns, the pre - coding input index set P I , the pre - coding output index set P O , or the pre - coding frozen bit sequence h.

[0175] (Pre - transformation determined by the pre - transformation matrix T)

[0176] In some embodiments, the pre - transformation output sequence u of length N is the multiplication of the pre - transformation input bit sequence and the pre - transformation matrix T with N rows and N columns, such that u = v·T. The pre - transformation input bit sequence is the rate - profiling output sequence v of length N, the pre - transformation output sequence u of length N is the pre - coding output bit sequence, and the vector - matrix multiplication is over GF(2).

[0177] (Pre - transformation determined by the pre - transformation matrix T and the pre - coding frozen bit sequence h)

[0178] In some embodiments, the pre - transformation output sequence u of length N is determined as u = v·T+h by the addition of the pre - coding frozen bit sequence h and the multiplication of the pre - transformation input bit sequence v and the pre - transformation matrix T with N rows and N columns. The pre - transformation input bit sequence is the rate - profiling output bit sequence v of length N, the vector - matrix multiplication is over GF(2), the vector - vector addition is over GF(2), and the length of the pre - coding frozen bit sequence h is equal to the polar matrix size N.

[0179] (g or g(D), t, P I , P O , h - determined pre - transformation)

[0180] In some embodiments, the pre - transformation uses at least one of the following to determine the pre - transformation output bit sequence u of length N: the generator bit sequence g = [g 0 , g 1 , ···, g m , the generator polynomial g(D)=g 0 +g 1 ·D+···+g m-1 ·D m-1 +g m ·D m 、the pre - coding input index set P I 、the pre - coding output index set P O, or the pre-coding frozen bit sequence h. The pre-coding frozen bit sequence h has a length of N - N PO and N PO is the size of the pre-coding output index set P O . Table 6 shows exemplary algorithms 5A - 5G for an exemplary implementation related to pre-conversion.

Table 6

[0181] In some embodiments, when the index i belongs to the pre-coding output index set P O , the bit (u i ) associated with the index i of the pre-conversion output bit sequence u is determined by at least one of the following: the generator bit sequence g = [g 0 , g 1 , ···, g m , the generator polynomial g(D) = g 0 + g 1 ·D + ··· + g m ·D m , and L bits in the pre-conversion input bit sequence v = [v 0 , v 1 , ···, v N-1 (the indices are the L maximum values in the first intersection set M 1 ). The first intersection set M 1 is the intersection set of the set with non-negative integers less than or equal to i ({0, 1, ···, i - 1, i}) and the pre-coding input index set P I . L = min(|M 1 |, min(i + 1, m + 1)), and |M 1 | is the number of elements in the first intersection set M 1 .

[0182] N = 16, i = 3, m = 6, generator polynomial g(D) = g 0 + g 1 ·D + g 2 ·D 2 + g 3 ·D 3 + g 4 ·D4 +g 5 ·D 5 +g 6 ·D 6 、 the pre - coding output sub - script set P O ={0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10}, and the pre - coding input sub - script set P I ={0, 2, 3, 5, 7, 8, 10} is the first specific example as follows.

[0183] (1) The first intersection set M 1 is M 1 ={0, 1, 2, 3} ∩ P I ={0, 1, 2, 3} ∩ {0, 2, 3, 5, 7, 8, 10} = {0, 2, 3}, and

[0184] (2) L = min(|M 1 |, min(i + 1, m + 1)) = min(3, min(3 + 1, 6 + 1)) = 3, and

[0185] (3) The pre - transformation input bit sequence v = [v 1 , v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 , v 8 , v 9 , v 10 , v 11 , v 12 , v 13 , v 14 , v 15 with L = 3 maximum values at the sub - script of the first intersection set M 3 is v 2 , v 0 , and v

[0186] (4) Finally, the bit of the pre - transformation output bit sequence u with sub - script i = 3 is u i = mod(g 0 ·v 3 + g 1 ·v 2 + g2 ·v 0 , 2).

[0187] N = 16, i = 9, m = 3, generator sequence g = [g 0 , g 1 , g 2 , g 3 , pre - coding output index set P O = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10}, and pre - coding input index set P I = {0, 2, 3, 5, 7, 8, 10} is the second specific example as follows.

[0188] (1) The first intersection set M 1 is such that M 1 = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9} ∩ P I = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9} ∩ {0, 2, 3, 5, 7, 8, 10} = {0, 2, 3, 5, 7, 8}, and

[0189] (2) L = min(|M 1 |, min(i + 1, m + 1)) = min(6, min(9 + 1, 3 + 1)) = 4, and

[0190] (3) The pre - transformation input bit sequence v = [v 1 = {0, 2, 3, 5, 7, 8} where the L = 4 maximum values are 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 , v 8 , v 9 , v 10 , v 11 , v 12 , v 13 , v 14 , v 15 has L = 4 bits which are v 8 , v 7 , v 5 , v 3 .

[0191] (4) Finally, the bit at index i = 9 of the pre-conversion output bit sequence u is u 9 = mod(g 0 ·v 8 + g 1 ·v 7 + g 2 ·v 5 + g 3 ·v 3 , 2).

[0192] In some embodiments, when the index i belongs to the pre-coding output index set P O , the bit (u i ) associated with index i of the pre-conversion output bit sequence u is determined by at least one of the following: the generator bit sequence g = [g 0 , g 1 , ···, g m , the generator polynomial g(D) = g 0 + g 1 ·D + ··· + g m ·D m , and / or the L maximum values in the set ({0, 1, ···, i - 1, i}) of non-negative integers with indices less than or equal to i, where L = min(i + 1, m + 1), in the pre-conversion input bit sequence v = [v 0 , v 1 , ···, v N-1 , the L bits v i , v i-1 , ···, v i-L+1 .

[0193] For i = 3, m = 6, the pre-coding output index set P O = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10}, and the generator polynomial g(D) = g 0 + g 1 ·D + g 2 ·D 2 + g 3 ·D 3 + g 4 ·D 4 + g 5 ·D 5 + g 6 ·D 6The first specific example is as follows.

[0194] (1) The set with non - negative integers where i = 3 or less is {0, 1, 2, 3},

[0195] (2) L = min(i + 1, m + 1) = min(3 + 1, 6 + 1) = 4,

[0196] (3) The L = 4 pre - transformation input bit - string v = [v 0 , v 1 , ···, v N-1 where the sub - scripts are the L = 4 maximum values in the set {0, 1, 2, 3} has the L = 4 bits v 3 , v 2 , v 1 , and v 0 ,

[0197] (4) Finally, the i - th bit u i is u i = mod(g 0 ·v 3 + g 1 ·v 2 + g 2 ·v 1 + g 3 ·v 0 , 2).

[0198] For N = 16, i = 9, m = 3, pre - coding output sub - script set P O = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10}, and generator sequence g = [g 0 , g 1 , g 2 , g 3 , the second specific example is as follows.

[0199] (1) The set with non - negative integers where i = 9 or less is {0, 1, 2, 3, 4, 5, 6, 7, 8, 9},

[0200] (2) L = min(i + 1, m + 1) = min(9 + 1, 3 + 1) = 4,

[0201] (3) The L = 4 bits in the pre - transformation input bit sequence v = [v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 , v 8 , v 9 , v 10 , v 11 , v 12 , v 13 , v 14 , v 15 where the subscripts are the L = 4 maximum values in the set {0, 1, 2, 3, 4, 5, 6, 7, 8, 9} are v 9 , v 8 , v 7 , v 6 . And

[0202] (4) Finally, the bit of the pre - transformation output bit sequence u with subscript i = 9 is u 9 = mod(g 0 ·v 9 + g 1 ·v 8 + g 2 ·v 7 + g 3 ·v 6 , 2).

[0203] In some embodiments, for any subscript i, the bit (u i ) of the pre - transformation output bit sequence u with subscript i is determined by at least one of the following: the generator bit sequence g = [g 0 , g 1 , ···, g m , the generator polynomial g(D) = g 0 + g 1 ·D + ··· + g m ·D m , and / or the L bits in the pre - transformation input bit sequence v = [v 1 , v 0 , ···, v 1 , ···, v N-1 where the subscripts are the L maximum values in the first intersection set M where the subscripts are the L maximum values in the first intersection set M1 is the intersection set of the set ({0, 1, ···, i - 1, i}) with non - negative integers less than or equal to i and the pre - coding input index set P I and L = min(|M 1 |, min(i + 1, m + 1)), where |M 1 | is the number of elements in the first intersection set M 1 .

[0204] N = 16, i = 2, m = 6, generator polynomial g(D)=g 0 +g 1 ·D + g 2 ·D 2 +g 3 ·D 3 +g 4 ·D 4 +g 5 ·D 5 +g 6 ·D 6 , and the first specific example where the pre - coding input index set P I ={0, 2, 3, 5, 7, 8, 10} is as follows.

[0205] (1) The first intersection set M 1 is M 1 ={0, 1, 2} ∩ P I ={0, 1, 2} ∩ {0, 2, 3, 5, 7, 8, 10} = {0, 2},

[0206] (2) L = min(|M 1 |, min(i + 1, m + 1)) = min(2, min(3 + 1, 6 + 1)) = 2,

[0207] (3) The pre - transform input bit sequence v = [v 1 ={0, 2} with L = 2 maximum values at the indices in the first intersection set M 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 , v 8 , v 9 , v 10 , v11 , v 12 , v 13 , v 14 , v 15 The two bits at L = 2 in are v 2 and v 0 and are

[0208] (4) Finally, the bit with index i = 2 of the pre-converted output bit sequence u is u 2 = mod(g 0 · v 2 + g 1 · v 0 , 2).

[0209] N = 16, i = 9, m = 3, generator sequence g = [g 0 , g 1 , g 2 , g 3 , and the pre-coding input index set P I = {0, 2, 5, 7, 8, 10} is the second specific example as follows.

[0210] (1) The first intersection set M 1 is M 1 = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9} ∩ P I = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9} ∩ {0, 2, 5, 7, 8, 10} = {0, 2, 5, 7, 8}, and

[0211] (2) L = min(|M 1 |, min(i + 1, m + 1)) = min(5, min(9 + 1, 3 + 1)) = 4,

[0212] (3) The pre-conversion input bit sequence v = [v 1 in which the indices are the four maximum values in the first intersection set M 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 , v 8 , v 9 , v 10 , v11 , v 12 , v 13 , v 14 , v 15 The four bits with L = 4 in ] are v 8 , v 7 , v 5 , v 2 , and

[0213] (4) Finally, the bit with subscript i = 9 of the pre-conversion output bit sequence u is u 9 = mod(g 0 · v 8 + g 1 · v 7 + g 2 · v 5 + g 3 · v 2 , 2).

[0214] In some examples, when the subscript i does not belong to the pre-conversion output subscript set P O , the bit (u i ) with subscript i of the pre-conversion output bit sequence u is set to 0, as in Algorithms 5A and 5D, for example. In some examples, when the subscript i does not belong to the pre-conversion output subscript set P O , the bit (u i ) with subscript i of the pre-conversion output bit sequence u is set to the i-th bit v i of the pre-conversion input bit sequence v, as in Algorithms 5B and 5E, for example. In some examples, when the subscript i does not belong to the pre-conversion output subscript set P O , the bit (u i ) with subscript i of the pre-conversion output bit sequence u is set to the bit in the pre-coding frozen bit sequence h. The pre-coding frozen bit sequence h has a length of N - N PO , where N PO is the size of the pre-coding output subscript set P O .

[0215] In Algorithms 5A - 5G, N is the polar matrix size, m is the memory length, and v iis the bit with subscript i in the pre-conversion input bit sequence, u i is the bit with subscript i in the pre-conversion output bit sequence, g k is the bit with subscript k in the generator sequence g = [g 0 , g 1 , ···, g m or the coefficient of the term with degree k in the generator polynomial g(D) = g 0 + g 1 · D + ··· + g m-1 · D m-1 + g m · D m on GF(2).

[0216] (determined by q or q(D), t, P I , P O , h for the pre-conversion)

[0217] In some embodiments, the pre-conversion uses at least one of the following to determine a pre-conversion output bit sequence u of length N: a recursive feedback bit sequence q = [q 0 , q 1 , ···, q m , a recursive feedback polynomial q(D) = q 0 + q 1 · D + ··· + q m-1 · D m-1 + q m · D m , a pre-coding input index set P I , a pre-coding output index set P O , or a pre-coding frozen bit sequence h. The pre-coding frozen bit sequence h is of length N - N PO , where N PO is the size of the pre-coding output index set P O . Table 7 shows exemplary algorithms 6A - 6G that are exemplary implementations related to the pre-conversion.

Table 7-1

Table 7-2

[0218] In some embodiments, when the subscript i belongs to the pre-conversion output subscript set P O the bit (u i ) with subscript i of the pre-conversion output bit sequence u is determined by at least one of the following: the recursive feedback bit sequence q = [q 0 , q 1 , ···, q m , the recursive feedback polynomial q(D) = q 0 + q 1 · D + ··· + q m · D m on GF(2), the i-th bit v 0 in the pre-conversion input bit sequence v = [v 1 , v N-1 , and / or the L bits in the pre-conversion output bit sequence u = [u i , u 2 , ···, u 0 , u 1 , ···, u N-1 that are the L maximum values in the second intersection set M 2 . The second intersection set M I is the intersection set of the set ({0, 1, ···, i - 2, i - 1}) with non-negative integers smaller than i and the pre-conversion output subscript set P 2 , and L = min(|M 2 |, min(i, m)), where |M 2 | is the number of elements in the second intersection set M 0 = 1, the recursive feedback polynomial q(D) = q 0 + q 1 · D + q 2 · D 2 + q 3 · D 3 + q 4 · D 4 + q 5 · D 5 + q 6 · D 6 , the pre-coding output subscript set PO ={0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10}, and the pre-coding input subscript set P I A first specific example where ={0, 2, 3, 5, 7, 8, 10} is as follows.

[0219] (1) The second intersection set M 2 is M 2 ={0, 1, 2} ∩ P I ={0, 1, 2} ∩ {0, 2, 3, 5, 7, 8, 10} = {0, 2}, and

[0220] (2) L = min(|M 2 |, min(i, m)) = min(2, min(3, 6)) = 2, and

[0221] (3) The pre-conversion input bit sequence v = [v 2 , v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 , v 8 , v 9 , v 10 , v 11 , v 12 , v 13 , v 14 , v 15 with the L = 2 bits in M being v 2 and v 0 , and

[0222] (4) Finally, since the bit with subscript i = 3 in the pre-conversion output bit sequence u has q 0 = 1, then u 3 = mod(q 0 ·v 3 + q 1 ·u 2 + q 2 ·u 0 , 2) = mod(v 3 + q 1 ·u 2 + q 2 ·u0 , 2).

[0223] N = 16, i = 9, m = 3, q 0 = 1 is the recursive feedback sequence q = [q 0 , q 1 , q 2 , q 3 , the pre - coding output index set P O = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10}, and the pre - coding input index set P I = {0, 2, 3, 5, 7, 8, 10} is the second specific example as follows.

[0224] (1) The second intersection set M 2 is M 2 = {0, 1, 2, 3, 4, 5, 6, 7, 8} ∩ P I = {0, 1, 2, 3, 4, 5, 6, 7, 8} ∩ {0, 2, 3, 5, 7, 8, 10} = {0, 2, 3, 5, 7, 8}, and

[0225] (2) L = min(|M 2 |, min(i, m)) = min(6, min(9, 3)) = 3, and

[0226] (3) The pre - transformation input bit sequence v = [v 2 = {0, 2, 3, 5, 7, 8} where the L = 3 maximum values are 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 , v 8 , v 9 , v 10 , v 11 , v 12 , v 13 , v 14 , v 15 . The L = 3 bits in it are v 8 , v 7 , and v 5 , and

[0227] (4) Finally, the bit with index i = 9 in the pre-conversion output bit sequence u is q 0 = 1, so u 9 = mod(q 0 ·v 9 + q 1 ·u 8 + q 2 ·u 7 + g 3 ·u 5 , 2) = mod(v 9 + q 1 ·u 8 + q 2 ·u 7 + g 3 ·u 5 , 2).

[0228] In some embodiments, if the index i belongs to the pre-coding output index set P O , the bit (u i ) associated with the index i of the pre-conversion output bit sequence u is determined by at least one of the following: the recursive feedback bit sequence q = [q 0 , q 1 , ···, q m , the recursive feedback polynomial q(D) = q 0 + q 1 · D + ··· + q m · D m over GF(2), the bit (v 0 ) associated with the index i in the pre-conversion input bit sequence v = [v 1 , v N-1 , ···, v i , and / or the L bits u 0 , u 1 , ···, u N-1 in the pre-conversion output bit sequence u = [u i-1 , u i-2 , ···, u i-L that are the L largest values in the set {0, 1, ···, i - 2, i - 1} associated with non-negative integers smaller than i. L = min(i, m) (as shown in Algorithms 6D, 6E, and 6F, for example).

[0229] N = 16, i = 3, m = 6, pre - coding output index set P O = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10}, and the recursive feedback polynomial q(D) = q 0 + q 1 ·D + q 2 ·D 2 + q 3 ·D 3 + q 4 ·D 4 + q 5 ·D 5 + q 6 ·D 6 The first specific example is as follows.

[0230] (1) The set with non - negative integers smaller than i = 3 is {0, 1, 2}, and

[0231] (2) L = min(i, m) = min(3, 6) = 3, and

[0232] (3) The L = 3 bits in the pre - transformation output bit sequence u = [u 0 , u 1 , ···, u N-1 whose indices are the L = 3 maximum values in the set {0, 1, 2} are u 2 , u 1 , and u 0 , and

[0233] (4) Finally, the bit with index i = 3 in the pre - transformation output bit sequence u is u i = mod(q 0 ·v 3 + q 1 ·u 2 + q 2 ·u 1 + q 3 ·u 0 , 2).

[0234] N = 16, i = 9, m = 3, q 0 = 1 for the recursive feedback q = [q 0 , q 1 , q 2 , q 3 , and the pre - coding output index set PO A second specific example where it is {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10} is as follows.

[0235] (1) The set with non - negative integers less than i = 9 is {0, 1, 2, 3, 4, 5, 6, 7, 8},

[0236] (2) L = min(i, m)=min(9, 3)=3,

[0237] (3) The pre - transformation output bit sequence u = [u 0 , u 1 , u 2 , u 3 , u 4 , u 5 , u 6 , u 7 , u 8 , u 9 , u 10 , u 11 , u 12 , u 13 , u 14 , u 15 where the L = 3 bits are the bits of u 8 , u 7 , and u 6 ,

[0238] (4) Finally, since the bit with subscript i = 9 of the pre - transformation output bit sequence u is q 0 = 1, u i = mod(q 0 ·v 9 +q 1 ·u 8 +q 2 ·u 7 +q 3 ·u 6 , 2)=mod(v 9 +q 1 ·u 8 +q 2 ·u 7 +q 3 ·u 6 , 2).

[0239] In some embodiments, for any index i, the bit (u i ) with index i of the pre-conversion output bit sequence u is determined by at least one of the following: the recursive feedback bit sequence q = [q 0 , q 1 , ···, q m , the recursive feedback polynomial q(D) = q 0 + q 1 ·D + ··· + q m ·D m over GF(2), the i-th bit v 0 in the pre-conversion input bit sequence v = [v 1 , v N-1 , and / or the L bits in the pre-conversion output bit sequence u = [u i , u 2 , ···, u 0 , u 1 , ···, u N-1 that are the L largest values in the second intersection set M 2 . The second intersection set M I is the intersection set of the set ({0, 1, ···, i - 2, i - 1}) with non-negative integers smaller than i and the pre-coding output index set P 2 , and L = min(|M 2 |, min(i, m)), where |M 2 | is the number of elements in the second intersection set M

[0240] (as shown in Algorithm 6G, for example). 0 = 1, a first specific example where the recursive feedback polynomial q(D) = q 0 + q 1 ·D + q 2 ·D 2 + q 3 ·D 3 + q 4 ·D 4 + q 5 ·D 5 + q 6 ·D 6 , and the pre-coding input index set P I = {0, 2, 3, 5, 7, 8, 10} is as follows.

[0241] (1) The second intersection set M 2 is M 2 = {0, 1, 2} ∩ P I = {0, 1, 2} ∩ {0, 2, 3, 5, 7, 8, 10} = {0, 2}, and

[0242] (2) L = min(|M 2 |, min(i, m)) = min(2, min(3, 6)) = 2, and

[0243] (3) The pre-conversion output bit sequence u = [u 2 , u 0 , u 1 , u 2 , u 3 , u 4 , u 5 , u 6 , u 7 , u 8 , u 9 , u 10 , u 11 , u 12 , u 13 , u 14 , u 15 with L = 2 maximum values in the second intersection set M 2 and u 0 are, and

[0244] (4) Finally, since the bit with subscript i = 3 in the pre-conversion output bit sequence u is q 0 = 1, u 3 = mod(q 0 · v 3 + q 1 · u 2 + q 2 · u 0 , 2) = mod(v 3 + q 1 · u 2 + q 2 · u 0 , 2).

[0245] N = 16, i = 9, m = 3, q 0 = 1 for the recursive feedback sequence q = [q0 , q 1 , q 2 , q 3 , and the pre-coding input index set P I A second specific example where = {0, 2, 3, 5, 7, 8, 10} is as follows.

[0246] (1) The second intersection set M 2 is M 2 = {0, 1, 2, 3, 4, 5, 6, 7, 8} ∩ P I = {0, 1, 2, 3, 4, 5, 6, 7, 8} ∩ {0, 2, 3, 5, 7, 8, 10} = {0, 2, 3, 5, 7, 8}, and

[0247] (2) L = min(|M 2 |, min(i, m)) = min(6, min(9, 3)) = 3, and

[0248] (3) The pre-conversion output bit sequence u = [u 2 = {0, 2, 3, 5, 7, 8} where the L = 3 maximum values in 0 , u 1 , u 2 , u 3 , u 4 , u 5 , u 6 , u 7 , u 8 , u 9 , u 10 , u 11 , u 12 , u 13 , u 14 , u 15 The L = 3 bits in are u 8 , u 7 , and u 5 , and

[0249] (4) Finally, since the bit where the index i = 9 of the pre-conversion output bit sequence u is q 0 = 1, u 9 = mod(q 0 · v 9 + q 1 · u 8 + q 2 · u 7+q 3 ·u 5 ,2)=mod(v 9 +q 1 ·u 8 +q 2 ·u 7 +q 3 ·u 5 ,2).

[0250] In some embodiments, if the subscript i does not belong to the pre-coding output subscript set P O , the bit (u i ) associated with the subscript i of the pre-conversion output bit sequence u is set to 0 (e.g., as in Algorithms 6A and 6D). In some embodiments, if the subscript i does not belong to the pre-conversion output subscript set P O , the bit (u i ) associated with the subscript i of the pre-conversion output bit sequence u is set to the i-th bit v i of the pre-conversion input bit sequence v (e.g., as in Algorithms 6B and 6E). In some embodiments, if the subscript i does not belong to the pre-conversion output subscript set P O , the bit (u i ) associated with the subscript i of the pre-conversion output bit sequence u is set to the bit in the pre-coding frozen bit sequence h (e.g., as in Algorithms 6C and 6F). The pre-coding frozen bit sequence h has a length of N - N PO , where N PO is the size of the pre-coding output subscript set P O .

[0251] In exemplary Algorithms 6A - 6G, N is the polar matrix size, m is the memory length, v i is the bit associated with the subscript i in the pre-conversion input bit sequence, u i is the bit associated with the subscript i in the pre-conversion output bit sequence, q k is the bit associated with the subscript k in the recursive feedback sequence q = [q 0 , q 1 , ···, q m or the recursive feedback polynomial q(D) = q over GF(2)0 +q 1 ·D + ··· + q m-1 ·D m-1 +q m ·D m is the coefficient of the term with degree k in

[0252] (g or g(D), q or q(D), t, P I , P O , h-determined pre-transformation)

[0253] In some embodiments, the pre-transformation uses at least one of the following to determine a pre-coding output bit sequence u of length N: generator bit sequence g = [g 0 , g 1 , ···, g m , generator polynomial g(D) = g 0 + g 1 ·D + ··· + g m-1 ·D m-1 + g m ·D m , recursive feedback bit sequence q = [q 0 , q 1 , ···, q m , recursive feedback polynomial q(D) = q 0 + q 1 ·D + ··· + q m-1 ·D m-1 + q m ·D m , pre-coding input index set P I , pre-coding output index set P O , pre-coding frozen bit sequence h, or state bit sequence t of length m + 1 = [t 0 , t 1 , ···, t m-1 , t m . The pre-coding frozen bit sequence h is of length N - N PO , and N PO is the size of the pre-coding output index set P O . Examples of implementations related to the pre-transformation can be found in Algorithms 7A - 7G of Table 8.

[0254] In some embodiments, when the subscript i belongs to the pre - coding output subscript set P O , the bit (u i ) with subscript i of the pre - transformed output bit sequence u is related to the bit (v i ) with subscript i of the pre - transformed input bit sequence v, the generator bit sequence g = [g 0 , g 1 , ···, g m , the generator polynomial g(D)=g 0 +g 1 ·D + ··· + g m ·D m , the recursive feedback bit sequence q = [q 0 , q 1 , ···, q m , the recursive feedback polynomial q(D)=q 0 +q 1 ·D + ··· + q m ·D m , and / or the state bit sequence t = [t 0 , t 1 , ···, t m-1 , t m . The pre - transformation can be implemented using the exemplary implementations given in Algorithms 7A - 7G of Table 8. The pre - transformation is such that the first node sets the bit with subscript 0 in the state bit sequence t to be the bit (v i ) with subscript i of the pre - coding input bit sequence v, i.e., t 0 =v i , and the first node, by the recursive feedback bit sequence q = [q 0 , q 1 , ···, q m (or the recursive feedback polynomial q(D)=q 0 +q 1 ·D + ··· + q m ·D m ) and the updated state bit sequence t = [t 0 , t 1 , ···, t m-1 , t m , determines the sum bit s [Number] determined as, and by the first node, setting the bit with subscript 0 in the state bit string t to the sum bit s, i.e., t 0 = s, and by the first node, the generator bit string g = [g 0 , g 1 , ···, g m (or the generator polynomial g(D) = g 0 + g 1 · D + ··· + g m · D m ) and the updated state bit string t = [t 0 , t 1 , ···, t m-1 , t m , determining the bit (u i ) with subscript i of the pre-coding output bit string u as [Number] determined as, and can include.

[0255] Table 8 shows exemplary algorithms 7A - 7G which are exemplary implementations related to pre-conversion. [Table 8 - 1] [Table 8 - 2]

[0256] In some embodiments, if the subscript i does not belong to the pre-coding output subscript set P O , the bit (u i ) with subscript i of the pre-conversion output bit string u is set to 0, for example, as in algorithms 7A and 7D. In some embodiments, if the subscript i does not belong to the pre-coding output subscript set P O , the bit (u i) is set to the bit (v i ) with index i of the pre-conversion input bit sequence v, for example, as in algorithms 7B and 7E. In some embodiments, if the index i does not belong to the pre-coding output index set P O , the bit (u i ) with index i of the pre-conversion output bit sequence u is set to the bit in the pre-coding frozen bit sequence h, for example, as in algorithms 7C and 7F. The pre-coding frozen bit sequence h has a length of N - N PO , where N PO is the size of the pre-coding output index set P O . In some embodiments, if the index i belongs to the pre-coding input index set P I , a right shift is performed on the state bit sequence t = [t 0 , t 1 , ···, t m-1 , t m , and the bit (t 0 ) with index 0 in the state bit sequence t is set to 0 as follows, for example, as in algorithms 7A, 7B, 7C, and 7G.

Number

[0257] In some embodiments, for any index i, a right shift is performed on the state bit sequence t = [t 0 , t 1 , ···, t m-1 , t m , and the bit (t 0 ) with index 0 in the state bit sequence t is set to 0 as follows, for example, as in algorithms 7D, 7E, and 7F.

Number

[0258] In algorithms 7A - 7G, N is the polar matrix size, m is the memory length, and v iis the bit with subscript i in the pre-conversion input bit sequence, u i is the bit with subscript i in the pre-conversion output bit sequence, q k is the recursive feedback sequence q = [q 0 , q 1 , ···, q m the bit with subscript k or the coefficient of the term with degree k in the recursive feedback polynomial q(D) = q 0 + q 1 · D + ··· + q m-1 · D m-1 + q m · D m in GF(2), and g k is the generator sequence g = [g 0 , g 1 , ···, g m the bit with subscript k or the coefficient of the term with degree k in the generator polynomial g(D) = g 0 + g 1 · D + ··· + g m-1 · D m-1 + g m · D m in GF(2).

[0259] (Polar conversion): The polar conversion includes obtaining a polar conversion input bit sequence by a first node and determining a polar conversion output bit sequence d = [d 0 , d 1 , ···, d N-1 by the first node. Both the polar conversion input bit sequence and the polar conversion output bit sequence d have a length equal to the polar matrix size N. The polar conversion output bit sequence d is determined by multiplying the polar conversion input bit sequence u by a polar matrix G (N) with N rows and N columns, i.e., d = u · G (N) , and the vector-matrix multiplication is performed over GF(2). In some embodiments, the polar conversion input bit sequence is a pre-coding output bit sequence u = [u 0 , u 1 , ···, u N-1. In some embodiments, the polar conversion input bit sequence, as shown in FIGS. 8A-8C, is a pre-conversion output bit sequence u = [u 0 , u 1 , ···, u N-1 of length N.

[0260] (Rate matching): Rate matching includes obtaining a rate matching input bit sequence by a first node and determining a rate matching output bit sequence by the first node. The rate matching input bit sequence is a polar conversion output bit sequence d = [d 0 , d 1 , ···, d N-1 of length N. The rate matching output bit sequence is an output bit sequence e = [e 0 , e 1 , ···, e E-1 of length E. N is the polar matrix size. Specific examples of rate matching are shown in FIGS. 5A and 8A.

[0261] In some embodiments, rate matching uses an ordered rate matching index set R = <R(0), R(1), ···, R(N r -2), R(N r -1)> to determine, by a first node, a rate matching output bit sequence d corresponding to the rate matching input bit sequence e, where N r is the size of the ordered rate matching index set, N r is equal to the minimum value between N and E, N r = min(N, E), N is the polar matrix size, and E is the length of the rate matching output bit sequence or the length of the output bit sequence e. The first specific example is e k = d R(mod(k,N)) , for k = 0, 1, 2, ···, E - 2, E - 1. The second specific example is e k = d R(k) , for k = 0, 1, 2, ···, E - 2, E - 1.

[0262] The third specific example is as follows.

Number

[0263] The fourth specific example is as follows.

Number

[0264] (Interleaving)

[0265] In some embodiments, rate matching includes interleaving. Interleaving includes obtaining an interleaving input bit sequence by a first node and determining an interleaving output bit sequence d’ = [d’ 0 , d’ 1 , ···, d’ N-1 by the first node. N is the polar matrix size. The interleaving input bit sequence is a polar transform output bit sequence d = [d 0 , d 1 , ···, d N-1 of length N. The interleaving output bit sequence d’ = [d’ 0 , d’ 1 , ···, d’ N-1 is of length N.

[0266] In some embodiments, interleaving corresponds to an interleaving output bit sequence d’ = [d’ 0 , J 1 , ···, J N-2 , J N-1 of length N by an interleaver pattern J = [J 0 , d’ 1 , ···, d’ N-1 .

Number

[0267] Interleaver pattern J=[J 0 ,J 1 ,···,J N-2 ,J N-1 A first specific example of is determined as follows:

number

[0268] π=[π 0 ,π 1 ,π 2 ,π 3 ,π 4 ,π 5 ,π 6 ,π 7 ,π 8 ,π 9 ,π 10 ,π 11 ,π 12 ,π 13 ,π 14 ,π 15 ,π 16 ,π 17 ,π 18 ,π 19 ,π 20 ,π 21 ,π 22 ,π 23 ,π 24 ,π 25 ,π 26 ,π 27 ,π 28 ,π 29 ,π 30 ,π 31=[0, 1, 2, 4, 3, 5, 6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24, 25, 26, 28, 27, 29, 30, 31] is a sub-block interleaver pattern, and N is the polar matrix size.

[0269] The interleaver pattern J = [J 0 , J 1 , ···, J N-2 , J N-1 The second specific example of is that the relationship between the subscript i and the i-th element J in the interleaver pattern J i and is the following quadratic form, that is,

Equation

Table 9

[0270] (Bit selection)

[0271] In some embodiments, rate matching includes bit selection. Bit selection includes obtaining a bit selection input bit sequence by a first node and determining a bit selection output bit sequence by the first node. The bit selection output bit sequence is an output bit sequence e = [e 0 , e 1 , ···, e E-1 of length E. In some embodiments, the bit selection input bit sequence is a polar transform output bit sequence d of length N, where N is the polar matrix size. Specific examples are shown in FIGS. 5B and 8B.

[0272] The first specific example is that the bit selection is such that the bit selection output bit sequence e = [e 0 , e 1 , ···, e E-1be the first E bits in the bit selection input bit sequence d = [d 0 , d 1 , ···, d N , so that e k = d k , where k = 0, 1, 2, ···, E - 2, E - 1. E is less than or equal to N.

[0273] The second specific example is that the bit selection is such that the bit selection output bit sequence e = [e 0 , e 1 , ···, e E-1 is the last E bits in the bit selection input bit sequence d = [d 0 , d 1 , ···, d N , so that e k = d N-E+k , where k = 0, 1, 2, ···, E - 2, E - 1. E is less than or equal to N.

[0274] The third specific example is that the bit selection is such that the bit selection output bit sequence e = [e 0 , e 1 , ···, e E-1 is the repetition of the bits in the bit selection input bit sequence d = [d 0 , d 1 , ···, d N , so that e k = d mod(k,N) , where k = 0, 1, 2, ···, E - 2, E - 1. E is greater than or equal to N.

[0275] In some embodiments, the bit selection input bit sequence is an interleaving output bit sequence d' of length N, where N is the polar matrix size. Examples are shown in FIGS. 5C and 8C.

[0276] The first specific example is that the bit selection is such that the bit selection output bit sequence e = [e 0 , e 1 , ···, e E-1 is the interleaving output bit sequence d' = [d' 0 , d' 1 , ···, d'N-1 such that e is the first E bits in k = d’ k , determined as k = 0, 1, 2, ···, E - 2, E - 1. E is less than or equal to N.

[0277] A second specific example is that the bit selection is such that the bit selection output bit sequence e = [e 0 , e 1 , ···, e E-1 is interleaved with the interleaving output bit sequence d’ = [d’ 0 , d’ 1 , ···, d’ N-1 such that e is the last E bits in k = d’ N-E+k , determined as k = 0, 1, 2, ···, E - 2, E - 1. E is less than or equal to N.

[0278] A third specific example is that the bit selection is such that the bit selection output bit sequence e = [e 0 , e 1 , ···, e E-1 is the repetition of bits in the interleaving output bit sequence d’ = [d’ 0 , d’ 1 , ···, d’ N-1 such that e k = d’ mod(k,N) , determined as k = 0, 1, 2, ···, E - 2, E - 1. E is greater than or equal to N.

[0279] (Second interleaving after rate matching)

[0280] In some embodiments, the output sequence e = [e 0 , e 1 , ···, e E-1 is further interleaved with the second output bit sequence f = [f 0 , f 1 , ···, f E-1 , and E is the length of the output sequence e.

[0281] (Modulation after rate matching or second interleaving)

[0282] In some embodiments, the output sequence e = [e 0 , e 1 , ···, e E-1 is further modulated into the first output symbol sequence x = [x 0 , x 1 , ···, x E / Qm-1 using one of the following modulation schemes: π / 2 binary phase shift keying (π / 2-BPSK), binary phase shift keying (BPSK), quadrature phase shift keying (QPSK), quadrature amplitude modulation (QAM), phase shift keying (PSK), amplitude shift keying (ASK), or amplitude phase shift keying (APSK). Q m is the modulation order.

[0283] In some embodiments, the second output bit sequence f = [f 0 , f 1 , ···, f E-1 is further modulated into the first output symbol sequence x = [x 0 , x 1 , ···, x E / Qm-1 using one of the following modulation schemes: π / 2 binary phase shift keying (π / 2-BPSK), binary phase shift keying (BPSK), quadrature phase shift keying (QPSK), quadrature amplitude modulation (QAM), phase shift keying (PSK), amplitude shift keying (ASK), or amplitude phase shift keying (APSK). Q m is the modulation order.

[0284] (input bit sequence c with CRC bits)

[0285] In some embodiments, the input bit sequence c is a cyclic generator polynomial g'(D) = g' with coefficients over GF(2) Lcrc · D Lcrc + g' Lcrc-1 · D Lcrc-1 + ··· + g' 2 · D 2 + g' 1 · D + g' 0It includes Lcrc cyclic redundancy check (CRC) bits determined thereby and K - Lcrc payload bits.

[0286] In some embodiments, the input bit sequence c is determined by the first node by adding Lcrc cyclic redundancy check (CRC) bits to a payload sequence of length K - Lcrc, and the Lcrc CRC bits are determined by a cyclic generator polynomial g’(D)=g’ Lcrc ·D Lcrc +g’ Lcrc-1 ·D Lcrc-1 +···+g’ 2 ·D 2 +g’ 1 ·D+g’ 0 with coefficients over GF(2).

[0287] Some additional examples of the disclosed coding schemes are described below.

[0288] (Example 1)

[0289] In Example 1, the first node obtains an input bit sequence c of length K = 24, c = [c 0 ,c 1 ,c 2 ,c 3 ,c 4 ,c 5 ,c 6 ,c 7 ,c 8 ,c 9 ,c 10 ,c 11 ,c 12 ,c 13 ,c 14 ,c 15 ,c 16 ,c 17 ,c 18 ,c 19 ,c 20 ,c 21 ,c 22 ,c 23 . As shown in Figure 5A, the first node has an output bit sequence e of length E = 28, e = [e 0 ,e 1 ,e 2 ,e3 , e 4 , e 5 , e 6 , e 7 , e 8 , e 9 , e 10 , e 11 , e 12 , e 13 , e 14 , e 15 , e 16 , e 17 , e 18 , e 19 , e 20 , e 21 , e 22 , e 23 , e 24 , e 25 , e 26 , e 27 is determined by performing the following.

[0290] (1) Perform precoding using an input bit sequence c of length K = 24 as a precoding input bit sequence, perform a vector-matrix multiplication on the input bit sequence c and a precoding matrix W with K = 24 rows and N = 32 columns, and then perform a vector addition on a precoding frozen bit sequence h of length N = 32, so that the precoding output bit sequence u of length N = 32 is u = c·W + h, where u = [u 0 , u 1 , u 2 , u 3 , u 4 , u 5 , u 6 , u 7 , u 8 , u 9 , u 10 , u 11 , u 12 , u 13 , u 14 , u 15 , u 16 , u 17 , u 18 , u 19 , u 20 , u 21 , u 22 , u 23 , u 24 , u25 , u 26 , u 27 , u 28 , u 29 , u 30 , u 31 is obtained. The precoding matrix W is

Number

[0291] (2) Polar matrix G of size N = 32 (32) = B (32) · P (32) is used to perform polar transformation using the precoding output bit sequence u as the polar transformation input bit sequence, and d = u·G (32) is used to obtain the polar transformation output bit sequence d = [d 0 , d 1 , d 2 , d 3 , d 4 , d 5 , d 6 , d 7 , d 8 , d 9 , d 10 , d 11 , d 12 , d 13 , d 14 , d 15 , d 16 , d 17 , d 18 , d 19 , d 20 , d 21 , d 22 , d 23 , d 24 , d 25 , d 26 , d 27 , d 28 , d 29 , d 30 , d 31 is obtained, and the matrix operation is over GF(2),

Number

Number

[0292] (3) Perform rate matching using the polar conversion output bit sequence d = [d 0 , d 1 , d 2 , d 3 , d 4 , d 5 , d 6 , d 7 , d 8 , d 9 , d 10 , d 11 , d 12 , d 13 , d 14 , d 15 , d 16 , d 17 , d 18 , d 19 , d 20 , d 21 , d 22 , d 23 , d 24 , d 25 , d 26 , d 27 , d 28 , d 29 , d 30 , d 31 with lengths N = 32 as the rate matching input bit sequence, and for i = 0, 1, 2, ···, 26, 27,

Number

[0293] After rate matching, the first node transmits a signal including the output bit sequence e to the second node.

[0294] (Example 2)

[0295] In Example 2, the second node receives the output bit sequence e of length E = 28 transmitted by the first node, e = [e0 , e 1 , e 2 , e 3 , e 4 , e 5 , e 6 , e 7 , e 8 , e 9 , e 10 , e 11 , e 12 , e 13 , e 14 , e 15 , e 16 , e 17 , e 18 , e 19 , e 20 , e 21 , e 22 , e 23 , e 24 , e 25 , e 26 , e 27 to receive a signal containing. The second node determines an estimated bit sequence of length K = 24 of the input bit sequence c = [c 0 , c 1 , c 2 , c 3 , c 4 , c 5 , c 6 , c 7 , c 8 , c 9 , c 10 , c 11 , c 12 , c 13 , c 14 , c 15 , c 16 , c 17 , c 18 , c 19 , c 20 , c 21 , c 22 , c 23 . As shown in Figure 5B, the output bit sequence e is determined by the first node as follows.

[0296] (1) Using the following, perform precoding using the input bit sequence c of length K = 24 as the precoding input bit sequence, and the precoding output bit sequence u of length N = 32 is u = [u0 , u 1 , u 2 , u 3 , u 4 , u 5 , u 6 , u 7 , u 8 , u 9 , u 10 , u 11 , u 12 , u 13 , u 14 , u 15 , u 16 , u 17 , u 18 , u 19 , u 20 , u 21 , u 22 , u 23 , u 24 , u 25 , u 26 , u 27 , u 28 , u 29 , u 30 , u 31 is obtained.

[0297] The data bit index set Q = {9, 6, 17, 10, 18, 12, 20, 24, 7, 11, 19, 13, 14, 21, 26, 25, 22, 28, 15, 23, 31, 27, 29, 30},

[0298] The generator polynomial g(D) over GF(2) = g 0 + g 1 · D + ··· + g m · D m = 1 + D + D 3 , or equivalently, the generator bit sequence g = [g 0 , g 1 , g 2 , g 3 = [1, 1, 0, 1],

[0299] Q max = 31 is the element with the maximum value in the data bit index set Q, and the pre - coding input index set P I = {0, 1, 2, ···, Q max - 1, Qmax} = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31}, and,

[0300] The pre - coding output index set P with all elements from the ordered rate - matching index set R = <R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), R(24), R(25), R(26), R(27)> = <0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27> O = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27}. The pre - coding is as follows (see also Algorithm 1A in Table 2, for example).

Number

[0301] (2) Polar matrix G of size N = 32 (32) = P (32) Using this, perform polar transformation with the pre - coding output bit sequence u as the polar transformation input bit sequence, and d = u·G (32) to obtain the polar transformation output bit sequence d of length N = 32 as d = [d 0 , d 1 , d 2 , d 3 , d 4 , d 5 , d 6 , d 7 , d 8 , d 9 , d 10 , d 11 , d 12 , d13 , d 14 , d 15 , d 16 , d 17 , d 18 , d 19 , d 20 , d 21 , d 22 , d 23 , d 24 , d 25 , d 26 , d 27 , d 28 , d 29 , d 30 , d 31 is obtained, and the matrix operation is over GF(2), [Number] and [Number] is.

[0302] (3) As the rate matching input bit sequence, a polar conversion output bit sequence u = [u 0 , u 1 , u 2 , u 3 , u 4 , u 5 , u 6 , u 7 , u 8 , u 9 , u 10 , u 11 , u 12 , u 13 , u 14 , u 15 , u 16 , u 17 , u 18 , u 19 , u 20 , u 21 , u 22 , u 23 , u 24 , u 25 , u 26 , u 27 , u 28 , u 29 , u 30 , u31 perform bit selection using [], and for i = 0, 1, 2, ···, 26, 27, e i = d R(i) to obtain a rate - matching output bit sequence (which is also the output bit sequence) e = [e 0 , e 1 , e 2 , e 3 , e 4 , e 5 , e 6 , e 7 , e 8 , e 9 , e 10 , e 11 , e 12 , e 13 , e 14 , e 15 , e 16 , e 17 , e 18 , e 19 , e 20 , e 21 , e 22 , e 23 , e 24 , e 25 , e 26 , e 27 with a length of E = 28. The bit selection follows an ordered rate - matching index set R = <R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), R(24), R(25), R(26), R(27)> = <0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27>, where all elements are non - negative integers less than the output bit sequence length E = 28.

[0303] (Example 3)

[0304] In Example 3, the first node has an input bit sequence c = [c 0 , c 1 , c 2 , c3 , c 4 , c 5 , c 6 , c 7 , c 8 , c 9 , c 10 , c 11 , c 12 , c 13 , c 14 , c 15 , c 16 , c 17 , c 18 , c 19 , c 20 , c 21 , c 22 , c 23 is obtained. As shown in FIG. 5C, the first node has an output bit string e = [e 0 , e 1 , e 2 , e 3 , e 4 , e 5 , e 6 , e 7 , e 8 , e 9 , e 10 , e 11 , e 12 , e 13 , e 14 , e 15 , e 16 , e 17 , e 18 , e 19 , e 20 , e 21 , e 22 , e 23 , e 24 , e 25 , e 26 , e 27 of length E = 28. To determine

[0305] (1) Using the following, pre - coding is performed using an input bit string c of length K = 24 as the pre - coding input bit string, and a pre - coding output bit string u = [u 0 , u 1 , u 2 , u 3 , u 4 , u 5, u 6 , u 7 , u 8 , u 9 , u 10 , u 11 , u 12 , u 13 , u 14 , u 15 , u 16 , u 17 , u 18 , u 19 , u 20 , u 21 , u 22 , u 23 , u 24 , u 25 , u 26 , u 27 , u 28 , u 29 , u 30 , u 31 is obtained.

[0306] K = 24-element data bit index set Q = {9, 6, 17, 10, 18, 12, 20, 24, 7, 11, 19, 13, 14, 21, 26, 25, 22, 28, 15, 23, 31, 27, 29, 30},

[0307] All elements are 0, length N - K = 32 - 24 = 8 rate profiling frozen bit sequence f,

[0308] Recursive feedback polynomial q(D) = q on GF(2) 0 + q 1 · D + ··· + q m · D m = 1 + D 2 + D 3 , or equivalently, recursive feedback bit sequence q = [q 0 , q 1 , q 2 , q 3 = [1, 0, 1, 1],

[0309] The pre-coding input index set P with all elements from the ordered rate matching index set R = <R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), R(24), R(25), R(26), R(27)> = <0, 1, 2, 4, 3, 5, 6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24, 25, 26, 28> I = {0, 1, 2, 4, 3, 5, 6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24, 25, 26, 28}, and

[0310] The pre-coding output index set P, all elements of which are non-negative integers less than or equal to the maximum value R max = 28 in the ordered rate matching index set R O = {0, 1, 2, ···, R max - 1, R max}= {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28}.

[0311] The pre-coding is as follows (see also Algorithm 2E in Table 3, for example).

Number

[0312] (2) Polar matrix of size N = 32

Number

[0313] (3) The polar transform output bit sequence d of length N = 32 is d = [d 0 , d 1 , ···, d N-1 = [d 0 , d 1 , d 2 , d 3 , d 4 , d 5 , d 6 , d 7 , d 8 , d 9 , d 10 , d 11 , d 12 , d 13 , d 14 , d15 , d 16 , d 17 , d 18 , d 19 , d 20 , d 21 , d 22 , d 23 , d 24 , d 25 , d 26 , d 27 , d 28 , d 29 , d 30 , d 31 interleaving is performed on the interleaving input sequence that is, for i = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, [Number] as the interleaving output bit sequence d’ = [d’ 0 , d’ 1 , ···, d’ N-1 = [d’ 0 , d’ 1 , d’ 2 , d’ 3 , d’ 4 , d’ 5 , d’ 6 , d’ 7 , d’ 8 , d’ 9 , d’ 10 , d’ 11 , d’ 12 , d’ 13 , d’ 14 , d’ 15 , d’ 16 , d’ 17 , d’ 18 , d’ 19 , d’ 20 , d’ 21 , d’ 22 , d’ 23 , d’ 24 , d’ 25 , d’ 26 , d’ 27 , d’ 28 , d’29 , d' 30 , d' 31 is determined (the i-th bit of the interleaved output bit sequence d' is equal to the J i -th bit of the interleaved input bit sequence d). J = [J 0 , J 1 , ···, J N-2 , J N-1 = [J 0 , J 1 , J 2 , J 3 , J 4 , J 5 , J 6 , J 7 , J 8 , J 9 , J 10 , J 11 , J 12 , J 13 , J 14 , J 15 , J 16 , J 17 , J 18 , J 19 , J 20 , J 21 , J 22 , J 23 , J 24 , J 25 , J 26 , J 27 , J 28 , J 29 , J 30 , J 31 is the sub-block interleaver pattern π = [π 0 , π 1 , π 2 , π 3 , π 4 , π 5 , π 6 , π 7 , π 8 , π 9 , π 10 , π 11 , π 12 , π 13 , π 14 , π 15 , π 16 , π 17 , π 18 , π 19 , π20 , π 21 , π 22 , π 23 , π 24 , π 25 , π 26 , π 27 , π 28 , π 29 , π 30 , π 31 = [0, 1, 2, 4, 3, 5, 6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24, 25, 26, 28, 27, 29, 30, 31] is the interleaving pattern determined according to

Number

[0314] (4) Bit selection is performed using the interleaving output bit sequence d’ = [d’ 0 , d’ 1 , d’ 2 , d’ 3 , d’ 4 , d’ 5 , d’ 6 , d’ 7 , d’ 8 , d’ 9 , d’ 10 , d’ 11 , d’ 12 , d’ 13 , d’ 14 , d’ 15 , d’ 16 , d’ 17 , d’ 18 , d’ 19 , d’ 20 , d’ 21 , d’ 22 , d’ 23 , d’ 24 , d’ 25 , d’ 26 , d’ 27 , d’ 28 , d’ 29 , d’ 30 , d’ 31 , and for i = 0, 1, 2, ···, 26, 27, e i=d’ i (for i = 0, 1, 2, ···, 26, 27, [Number] ) obtain the rate matching output bit sequence (also the output bit sequence) e = [e 0 , e 1 , e 2 , e 3 , e 4 , e 5 , e 6 , e 7 , e 8 , e 9 , e 10 , e 11 , e 12 , e 13 , e 14 , e 15 , e 16 , e 17 , e 18 , e 19 , e 20 , e 21 , e 22 , e 23 , e 24 , e 25 , e 26 , e 27 with a length of E = 28. The bit selection is such that all elements are elements in the interleaver pattern, and the subscripts are in the ordered rate matching subscript set R = <R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), R(24), R(25), R(26), R(27)> = <J 0 , J 1 , J 2 , J 3 , J 4 , J 5 , J 6 , J 7 , J 8 , J 9 , J 10 , J 11 , J12 , J 13 , J 14 , J 15 , J 16 , J 17 , J 18 , J 19 , J 20 , J 21 , J 22 , J 23 , J 24 , J 25 , J 26 , J 27 > follows.

[0315] After bit selection, the first node transmits a signal including the output bit sequence e to the second node.

[0316] (Example 4)

[0317] In Example 4, the first node obtains an input bit sequence c = [c 0 , c 1 , c 2 , c 3 , c 4 , c 5 , c 6 , c 7 , c 8 , c 9 , c 10 , c 11 of length K = 12. As shown in FIG. 8A, the first node has an output bit sequence e = [e 0 , e 1 , e 2 , e 3 , e 4 , e 5 , e 6 , e 7 , e 8 , e 9 , e 10 , e 11 , e 12 , e 13 , e 14 , e 15 , e 16 , e 17 , e 18 , e 19 , e 20 , e 21 , e 22, e 23 , e 24 , e 25 , e 26 , e 27 To determine [], the following is performed.

[0318] (1) Using the following, perform rate profiling with an input bit sequence c of length K = 12 as the rate profiling input bit sequence, and obtain a rate profiling output bit sequence v = [v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 , v 8 , v 9 , v 10 , v 11 , v 12 , v 13 , v 14 , v 15 , v 16 , v 17 , v 18 , v 19 , v 20 , v 21 , v 22 , v 23 , v 24 , v 25 , v 26 , v 27 , v 28 , v 29 , v 30 , v 31 of length N = 32.

[0319] A data bit index set Q = {14, 21, 26, 25, 22, 28, 15, 23, 31, 27, 29, 30} with K = 12 elements, and

[0320] a rate profiling frozen bit sequence f = [f 0 , f 1 , f 2 , f 3 , f 4 , f 5 , f 6 , f7 , f 8 , f 9 , f 10 , f 11 , f 12 , f 13 , f 14 , f 15 , f 16 , f 17 , f 18 , f 19 = [0, 0, 1, 1, 0, 0, 0, 1, 1, 1, 0, 1, 1, 0, 0, 0, 1, 0, 1, 0].

[0321] The rate profiling output bit sequence v is obtained by setting the bits in the rate profiling output bit sequence v with indices belonging to the data bit index set Q to be the bits in the input bit sequence c, while the other bits in the rate profiling output bit sequence v are set to the bits in the rate profiling freeze bit sequence f.

Number

[0322] (2) Using the following, perform pre - conversion using the rate profiling output bit sequence v as the pre - conversion input bit sequence, and obtain a pre - conversion output bit sequence u = [u 0 , u 1 , u 2 , u 3 , u 4 , u 5 , u 6 , u 7 , u 8 , u 9 , u 10 , u 11 , u 12 , u 13 , u 14 , u 15 , u 16 , u 17 , u 18 , u 19 , u 20 , u 21 , u 22 , u 23 , u 24, u 25 , u 26 , u 27 , u 28 , u 29 , u 30 , u 31 is determined.

[0323] The recursive feedback polynomial q(D) = q 0 + q 1 · D + ··· + q m · D m = 1 + D 2 + D 3 , or equivalently, the recursive feedback bit sequence q = [q 0 , q 1 , q 2 , q 3 = [1, 0, 1, 1],

[0324] The state bit sequence t = [t 0 , t 1 , ···, t m-1 , t m = [t 0 , t 1 , t 2 , t 3 ,

[0325] All elements are non - negative integers less than or equal to the maximum value Q max = 31 in the data bit index set Q = {14, 21, 26, 25, 22, 28, 15, 23, 31, 27, 29, 30}, and the pre - coding output index set P O = {0, 1, 2, ···, Q max - 1, Q max} = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31}, and,

[0326] N PO = 32 is the size of the pre - coding output index set P O and the length N - N POAn empty precoding frozen bit sequence h = [] where 32 - 32 = 0.

[0327] The pre - transformed output bit sequence u is determined as follows (see also Algorithm 7F in Table 8, for example).

Number

[0328] (3) A polar matrix of size N = 32

Number

Number

Number

[0329] (4) Perform rate matching using the polar transform output bit sequence d = [d 0 , d 1 , d 2 , d 3 , d 4 , d 5 , d 6 , d 7 , d 8 , d 9 , d 10 , d 11 , d 12 , d 13 , d 14 , d 15 , d 16 , d 17 , d 18 , d 19 , d 20 , d 21 , d 22 , d 23 , d 24 , d 25 , d 26 , d 27 , d 28 , d 29 , d 30 , d 31 of length N = 32 as the rate matching input bit sequence, and for i = 0, 1, 2, ···, 26, 27, e i = d R(N-E+i) and according to the ordered rate matching index set with R, the rate matching output bit sequence (which is also the output bit sequence) e = [e 0 , e 1 , e 2 , e 3 , e 4 , e 5 , e 6 , e 7 , e 8 , e 9 , e 10 , e 11 , e12 , e 13 , e 14 , e 15 , e 16 , e 17 , e 18 , e 19 , e 20 , e 21 , e 22 , e 23 , e 24 , e 25 , e 26 , e 27 is obtained. The ordered set of rate matching indices R = <R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), R(24), R(25), R(26), R(27)> = <J 0 , J 1 , J 2 , J 3 , J 4 , J 5 , J 6 , J 7 , J 8 , J 9 , J 10 , J 11 , J 12 , J 13 , J 14 , J 15 , J 16 , J 17 , J 18 , J 19 , J 20 , J 21 , J 22 , J 23 , J 24 , J 25 , J 26 , J 27 > and

Number

[0330] After rate matching, the first node transmits a signal including the output bit sequence e to the second node.

[0331] (Example 5)

[0332] In Example 5, the first node obtains an input bit sequence c = [c 0 , c 1 , c 2 , c 3 , c 4 , c 5 , c 6 , c 7 , c 8 , c 9 , c 10 , c 11 of length K = 12. As shown in Figure 8B, the first node has an output bit sequence e = [e 0 , e1 , e 2 , e 3 , e 4 , e 5 , e 6 , e 7 , e 8 , e 9 , e 10 , e 11 , e 12 , e 13 , e 14 , e 15 , e 16 , e 17 , e 18 , e 19 , e 20 , e 21 , e 22 , e 23 , e 24 , e 25 , e 26 , e 27 To determine [], perform the following.

[0333] (1) Use the following to perform rate profiling using an input bit sequence c of length K = 12 as the rate profiling input bit sequence, and obtain a rate profiling output bit sequence v = [v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 , v 8 , v 9 , v 10 , v 11 , v 12 , v 13 , v 14 , v 15 , v 16 , v 17 , v 18 , v 19 , v 20 , v 21 , v 22 , v 23 , v 24 , v 25 , v 26 , v 27 , v 28 , v 29 , v30 , v 31 is obtained.

[0334] The data bit index set Q = {14, 21, 26, 25, 22, 28, 15, 23, 31, 27, 29, 30} with K = 12 elements,

[0335] The rate profiling frozen bit sequence f = [f 0 , f 1 , f 2 , f 3 , f 4 , f 5 , f 6 , f 7 , f 8 , f 9 , f 10 , f 11 , f 12 , f 13 , f 14 , f 15 , f 16 , f 17 , f 18 , f 19 , f 20 , f 21 , f 22 , f 23 , f 24 , f 25 , f 26 , f 27 , f 28 , f 29 , f 30 , f 31 = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0].

[0336] The rate profiling output bit sequence v is obtained by setting the bits in the rate profiling output bit sequence v with indices belonging to the data bit index set Q to be the modulo-2 of the bits in the input bit sequence c and the bits in the rate profiling freeze bit sequence f, and setting the bits in the rate profiling output bit sequence v with indices not belonging to the data bit index set Q to be the bits in the rate profiling freeze bit sequence f. [Number]

[0337] (2) Using the following, perform pre-conversion using the rate profiling output bit sequence v as the pre-conversion input bit sequence, and determine the pre-conversion output bit sequence u = [u 0 , u 1 , u 2 , u 3 , u 4 , u 5 , u 6 , u 7 , u 8 , u 9 , u 10 , u 11 , u 12 , u 13 , u 14 , u 15 , u 16 , u 17 , u 18 , u 19 , u 20 , u 21 , u 22 , u 23 , u 24 , u 25 , u 26 , u 27 , u 28 , u 29 , u 30 , u 31 of length N = 32.

[0338] The generator polynomial g(D) over GF(2) = g 0 + g 1 · D + ··· + g m-1·D m-1 +g m ·D m =1+D+D 3 、or, equivalently, a generator bit sequence g = [g 0 , g 1 , ···, g m = [1, 1, 0, 1] on GF(2) with a memory length m = 3,

[0339] A recursive feedback polynomial q(D) = q 0 +q 1 ·D + ··· + q m ·D m =1+D 2 +D 3 、or, equivalently, a recursive feedback bit sequence q = [q 0 , q 1 , ···, q m = [1, 0, 1, 1] on GF(2) with a memory length m = 3,

[0340] A state bit sequence t = [t 0 , t 1 , ···, t m-1 , t m of length m + 1 = 3 + 1 = 4,

[0341] The pre - coding input index set P I ={N - E, N - E + 1, N - E + 2, ···, N - 2, N - 1> = <4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31},

[0342] The pre - coding input index set P O =P I , and,

[0343] N PO =28 is the size of the pre - coding input index set P O and a pre - coding frozen bit sequence h = [h PO =32 - 28 = 4 of length N - N 0 , h 1 , h 2 , h3 =[1,0,0,1].

[0344] The pre-conversion output bit sequence u is determined as follows. [Number]

[0345] (3) Polar matrix of size N = 32 [Number] Using the polar matrix of size N = 32, perform polar conversion using the pre-conversion output bit sequence u as the polar conversion input bit sequence, and d = u·G (32) to obtain the polar conversion output bit sequence d = [d 0 , d 1 , d 2 , d 3 , d 4 , d 5 , d 6 , d 7 , d 8 , d 9 , d 10 , d 11 , d 12 , d 13 , d 14 , d 15 , d 16 , d 17 , d 18 , d 19 , d 20 , d 21 , d 22 , d 23 , d 24 , d 25 , d 26 , d 27 , d 28 , d 29 , d 30 , d 31 , and the matrix operation is over GF(2), [Number] and [Number] is the fifth Kronecker power of the matrix P (2) , and B (32) is a bit-reversal permutation matrix with N = 32 rows and N = 32 columns.

[0346] (4) Bit selection is performed using the polar conversion output bit sequence d = [d 0 , d 1 , d 2 , d 3 , d 4 , d 5 , d 6 , d 7 , d 8 , d 9 , d 10 , d 11 , d 12 , d 13 , d 14 , d 15 , d 16 , d 17 , d 18 , d 19 , d 20 , d 21 , d 22 , d 23 , d 24 , d 25 , d 26 , d 27 , d 28 , d 29 , d 30 , d 31 of length N = 32, and the output bit sequence e = [e i = d N-E+i is obtained for i = 0, 1, 2, ···, 26, 27 as the output bit sequence e of length E = 28, where 0 , e 1 , e 2 , e 3 , e 4 , e 5 , e 6 , e 7 , e 8 , e 9 , e 10 , e 11 , e 12 , e 13 , e 14 , e 15 , e 16 , e17 , e 18 , e 19 , e 20 , e 21 , e 22 , e 23 , e 24 , e 25 , e 26 , e 27 is obtained. The corresponding ordered set of rate-matching indices R = <R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), R(24), R(25), R(26), R(27)> = <N - E, N - E + 1, N - E + 2, ···, N - 2, N - 1> = <4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31>.

[0347] After bit selection, the first node transmits a signal including the output bit sequence e to the second node.

[0348] (Example 6)

[0349] In Example 6, the first node has an input bit sequence c = [c 0 , c 1 , c 2 , c 3 , c 4 , c 5 , c 6 , c 7 , c 8 , c 9 , c 10 , c 11 of length K = 12. As shown in Figure 8C, the first node has an output bit sequence e = [e 0 , e 1 , e 2 , e 3 , e 4 , e 5 , e 6 , e 7 , e8 , e 9 , e 10 , e 11 , e 12 , e 13 , e 14 , e 15 , e 16 , e 17 , e 18 , e 19 , e 20 , e 21 , e 22 , e 23 , e 24 , e 25 , e 26 , e 27 To determine [], the following is performed.

[0350] (1) Perform rate profiling using an input bit sequence c of length K = 12 as the rate profiling input bit sequence, and perform vector-matrix multiplication and vector addition on the rate profiling matrix F with K = 12 rows and N = 32 columns and the rate profiling frozen bit sequence f over GF(2), so that v = c·F + f and the rate profiling output bit sequence v of length N = 32 is [v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 , v 8 , v 9 , v 10 , v 11 , v 12 , v 13 , v 14 , v 15 , v 16 , v 17 , v 18 , v 19 , v 20 , v 21 , v 22 , v 23 , v 24 , v 25 , v 26 , v 27 , v 28 , v 29 , v30 , v 31 is obtained.

[0351] The rate profiling matrix F is as follows.

Number

[0352] The rate profiling frozen bit sequence is f = [f 0 , f 1 , f 2 , f 3 , f 4 , f 5 , f 6 , f 7 , f 8 , f 9 , f 10 , f 11 , f 12 , f 13 , f 14 , f 15 , f 16 , f 17 , f 18 , f 19 , f 20 , f 21 , f 22 , f 23 , f 24 , f 25 , f 26 , f 27 , f 28 , f 29 , f 30 , f 31 = [0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 1, 1, 1, 0, 0, 0, 1, 0, 1, 1, 1, 0, 0, 0, 1].

[0353] (2) Perform pre - transformation using the rate profiling output bit sequence v as the pre - transformation input bit sequence, and a pre - transformation matrix T with N = 32 rows and N = 32 columns over GF(2), and a precoding frozen bit sequence h = [h 0 , h 1 , h 2 , h 3 , h 4 , h5 , h 6 , h 7 , h 8 , h 9 , h 10 , h 11 , h 12 , h 13 , h 14 , h 15 , h 16 , h 17 , h 18 , h 19 , h 20 , h 21 , h 22 , h 23 , h 24 , h 25 , h 26 , h 27 , h 28 , h 29 , h 30 , h 31 = [0, 1, 1, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1], by performing vector-matrix multiplication and vector addition, we get u = v·T + h, where u = [u 0 , u 1 , u 2 , u 3 , u 4 , u 5 , u 6 , u 7 , u 8 , u 9 , u 10 , u 11 , u 12 , u 13 , u 14 , u 15 , u 16 , u 17 , u 18 , u 19 , u 20 , u 21 , u 22 , u 23 , u 24 , u 25 , u 26 , u 27 , u 28 , u 29 , u 30 , u31 Determine

[0354] The pre - transformation matrix T is as follows.

Number

[0355] (3) Polar matrix of size N = 32

Number

Number

Number

[0356] (4) Using the interleaving input sequence of length N = 32, d = [d 0 , d 1 , ···, d N-1 = [d 0 , d 1 , d 2 , d 3 , d 4 , d 5 , d 6 , d 7 , d 8 , d 9 , d 10 , d 11 , d 12 , d 13 , d 14 , d 15 , d 16 , d 17 , d 18 , d 19 , d 20 , d 21 , d 22 , d 23 , d 24 , d 25 , d 26 , d 27 , d 28 , d 29 , d 30 , d 31 , perform interleaving as follows: For i = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,

Number

Number

[0357] (5) Perform bit selection using the interleaving output bit sequence d’ of length N = 32 as the bit selection input bit sequence. For i = 0, 1, 2, ···, 26, 27, e i = d’ N-E+i and the output bit sequence e = [e 0 , e 1 , e 2 , e 3 , e 4 , e 5 , e 6 , e7 , e 8 , e 9 , e 10 , e 11 , e 12 , e 13 , e 14 , e 15 , e 16 , e 17 , e 18 , e 19 , e 20 , e 21 , e 22 , e 23 , e 24 , e 25 , e 26 , e 27 is obtained.

[0358] After bit selection, the first node transmits a signal including the output bit sequence e to the second node.

[0359] (Example 7)

[0360] In Example 7, the first node obtains an input bit sequence c = [c 0 , c 1 , c 2 , ···, c K-2 , c K-1 . The input sequence c includes Lcrc cyclic redundancy check (CRC) bits determined by the cyclic generator polynomial g’(D) = g’ Lcrc ·D Lcrc + g’ Lcrc-1 ·D Lcrc-1 + ··· + g’ 2 ·D 2 + g’ 1 ·D + g’ 0 with coefficients over GF(2), and K - Lcrc payload bits. As shown in Figure 8C, the first node uses a parity matrix of size N to perform the following to determine an output bit sequence e = [e 0 , e 1 , ···, e E-2 , e E-1 of length E.

[0361] (1) Perform rate profiling using an input bit sequence c of length K as the rate profiling input bit sequence, and according to the data bit index set Q, obtain a rate profiling output bit sequence v = [v 0 , v 1 , ···, v N-2 , v N-1 of length N. The data bit index set Q is a subset of K elements of the first integer set Z N = {0, 1, 2, ···, N - 2, N - 1}, and the first integer set Z N contains all non - negative integers smaller than N. The rate profiling output bit sequence v is obtained as follows: That is, the bits in the rate profiling output bit sequence v with indices belonging to the data bit index set Q are set to the bits in the input bit sequence c, while the bits in the rate profiling output bit sequence v with indices not belonging to the data bit index set Q are set to 0.

Number

[0362] (2) Perform pre - transformation using the rate profiling output bit sequence v as the pre - transformation input bit sequence, and determine a pre - transformation output bit sequence u = [u 0 , u 1 , ···, u N-2 , u N-1 of length N.

[0363] A generator polynomial g(D) = g 0 + g 1 ·D + ··· + g m ·D m over GF(2), or equivalently, a generator bit sequence g = [g 0 , g 1 , ···, g m with memory length m,

[0364] A pre - coding input index set P max whose all elements are non - negative integers less than or equal to value Q I = {0, 1, 2, ···, Qmax -1, Q max , and,

[0365] all elements are the value Q max The pre-coding output index set P, which is a non-negative integer as follows O = {0, 1, 2, ···, Q max -1, Q max}. Q max is the maximum value in the data bit index set Q,

Number

[0366] Next, the pre-transform output bit sequence u is determined as follows (see also Algorithm 5A for example). When the index i does not belong to the pre-coding output index set P O , the i-th bit u i in the pre-transform output bit sequence u is set to 0.

Number

[0367] (3) Using the polar matrix

Number

Number

Number

[0368] (4) Using the polar conversion output bit sequence d = [d 0 , d 1 , ···, d N-2 , d N-1 of length N as the interleaving input sequence, perform interleaving according to the following sub-block interleaver pattern π = [π 0 , π 1 , π 2 , π 3 , π 4 , π 5 , π 6 , π 7 , π 8 , π 9 , π 10 , π 11 , π 12 , π 13 , π 14 , π 15 , π 16 , π 17 , π 18 , π 19 , π 20 , π 21 , π 22 , π 23 , π 24 , π 25 , π 26 , π 27 , π 28 , π 29 , π 30 , π 31 = [0, 1, 2, 4, 3, 5, 6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24, 25, 26, 28, 27, 29, 30, 31] to obtain an interleaving output bit sequence d’ = [d’ 0 , d’ 1 , ···, d’ N-2 , d’ N-1 of length N.

Number

[0369] For \(i = 0, 1, \cdots, N - 2, N - 1\), the \(i\)-th bit of the interleaved output bit sequence \(d'\) is equal to the \(J\) i -th bit of the interleaved input bit sequence \(d\). \(J = [J\) 0 , \(J\) 1 , \(\cdots\), \(J\) N-2 , \(J\) N-1 is an interleaving pattern of length \(N\) determined by the sub-block interleaver pattern \(\pi\) and the polar matrix size \(N\). The interleaving pattern \(J = [J\) 0 , \(J\) 1 , \(\cdots\), \(J\) N-2 , \(J\) N-1 is a permutation of the integer sequence \([0, 1, 2, \cdots, N - 2, N - 1]\).

[0370] (5) Bit selection is performed using the interleaved output bit sequence \(d'\) of length \(N\) as the bit selection input bit sequence, and \(e\) k = \(d'\) k , and an output bit sequence \(e\) of length \(E\) is obtained with \(k = 0, 1, 2, \cdots, E - 2, E - 1\). The output bit sequence \(e\) comprises bits in the interleaved output bit sequence \(d'\) with subscripts less than \(E\).

[0371] After bit selection, the first node transmits a signal including the output bit sequence \(e\) to the second node.

[0372] (Example 8)

[0373] In Example 8, the first node obtains an input bit sequence \(c = [c\) 0 , \(c\) 1 , \(c\) 2 , \(\cdots\), \(c\) K-2 , \(c\) K-1 of length \(K\). The input sequence \(c\) has a cyclic generator polynomial \(g'(D)=g'\) Lcrc \(\cdot D\) Lcrc + \(g'\) Lcrc-1 \(\cdot D\) Lcrc-1 + \(\cdots\) + \(g'\) 2 \(\cdot D\) 2 + \(g'\) 1 \(\cdot D\) + \(g'\) 0It includes Lcrc cyclic redundancy check (CRC) bits determined by 0 , e 1 , ···, e E-2 , e E-1 and performs the following to determine the output bit sequence e = [e

[0374] (1) Perform rate profiling using the input bit sequence c of length K as the rate profiling input bit sequence, and according to the data bit index set Q, obtain the rate profiling output bit sequence v = [v 0 , v 1 , ···, v N-2 , v N-1 . The data bit index set Q is a subset of K elements of the first integer set Z N = {0, 1, 2, ···, N - 2, N - 1}, and the first integer set Z N includes all non - negative integers smaller than N. The rate profiling output bit sequence v is obtained as follows: The bits in the rate profiling output bit sequence v with indices belonging to the data bit index set Q are set to the bits in the input bit sequence c, while the bits in the rate profiling output bit sequence v with indices not belonging to the data bit index set Q are set to 0.

Number

[0375] (2) Perform pre - transformation using the rate profiling output bit sequence v as the pre - transformation input bit sequence using the following, and determine the pre - transformation output bit sequence u = [u 0 , u 1 , ···, u N-2 , u N-1 of length N.

[0376] The generator polynomial g(D) = g 0 + g 1 ·D + ··· + gm ·D m or, equivalently, a generator bit sequence g = [g 0 , g 1 , ···, g m with memory length m

[0377] precoding input index set P I , and

[0378] precoding output index set P O .

[0379] The pre-conversion output bit sequence u is determined as follows (see also Algorithm 5B for example). When the index i does not belong to the precoding output index set P O , the i-th bit u i in the pre-conversion output bit sequence u is set to the i-th bit v i in the pre-conversion input bit sequence v

Number

[0380] (3) Using a polar matrix of size N

Number

Number

Number

[0381] (4) Using the polar conversion output bit sequence d = [d 0 , d 1 , ···, d N-2 , d N-1 of length N as the rate matching input sequence, perform rate matching for i = 0, 1, 2, ···, E - 2, E - 1, and set e i = d R(i) . According to the ordered rate matching index set R = <R(0), R(1), ···, R(E - 2), R(E - 1)> of length E, obtain the output bit sequence e of length E. The i-th bit e i in the output bit sequence e is set to the R(i)-th bit d R(i) in the polar conversion output bit sequence d. For i = 0, 1, 2, ···, E - 2, E - 1, R(i) in the ordered rate matching index set R is determined according to the interleaver pattern J = [J 0 , J 1 , ···, J N-2 , J N-1 of length N. The interleaver pattern J, which is a permutation of the integer sequence [0, 1, 2, ···, N - 2, N - 1], is the sub-block interleaver pattern π = [π 0 , π 1 , π 2 , π 3 , π 4 , π 5 , π 6 , π 7 , π 8 , π 9 , π 10 , π 11 , π 12 , π 13 , π 14 , π 15 , π 16 , π 17 , π 18 , π 19 , π 20 , π 21 , π 22 , π 23 , π 24 , π 25 , π 26 , π 27 , π 28, π 29 , π 30 , π 31 = [0, 1, 2, 4, 3, 5, 6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24, 25, 26, 28, 27, 29, 30, 31] is determined by

Number

[0382] After rate matching, the first node uses quadrature phase shift keying (QPSK) modulation to modulate the output bit sequence e into the first output symbol sequence x = [x 0 , x 1 , ···, x E / Qm-1 , and transmits the signal including the first output symbol sequence x to the second node. Qm = 2 is the modulation order of QPSK.

[0383] The pre-coding input index set P in the above process I , the pre-coding output index set P O , and an exemplary setting regarding the ordered rate matching index set R are as follows.

[0384] Exemplary setting 8-1: R = <R(0), R(1), ···, R(E - 2), R(E - 1)> = <J 0 , J 1 , ···, J E-2 , J E-1 , P I = {0, 1, 2, ···, Q max - 1, Q max}, P O = {0, 1, 2, ···, Q max - 1, Q max},

[0385] Exemplary setting 8-2: R = <R(0), R(1), ···, R(E - 2), R(E - 1)> = <J 0 , J 1 , ···, J E-2 , J E-1 , P I={0, 1, 2, ···, Q max -1, Q max}, P O ={R(0), R(1), R(2), ···, R(E - 1)}、

[0386] Exemplary setting 8 - 3: R = <R(0), R(1), ···, R(E - 2), R(E - 1)> = <J 0 , J 1 , ···, J E-2 , J E-1 >, P I ={R(0), R(1), R(2), ···, R(E - 1)}, P O ={0, 1, 2, ···, Q max -1, Q max}、

[0387] Exemplary setting 8 - 4: R = <R(0), R(1), ···, R(E - 2), R(E - 1)> = <J 0 , J 1 , ···, J E-2 , J E-1 >, P I ={R(0), R(1), R(2), ···, R(E - 1)}, P O ={R(0), R(1), ···, R(E - 2), R(E - 1)}、

[0388] Exemplary setting 8 - 5: R = <R(0), R(1), ···, R(E - 2), R(E - 1)> = <J N-E , J N-E+1 , ···, J N-2 , J N-1 >, P I ={0, 1, 2, ···, Q max -1, Q max}、P O ={0, 1, 2, ···, Q max -1, Q max}、

[0389] Exemplary setting 8 - 6: R = <R(0), R(1), ···, R(E - 2), R(E - 1)> = <J N-E , J N-E+1 , ···, J N-2 , J N-1 >, P I={0, 1, 2, ···, Q max -1, Q max}, P O ={R(0), R(1), R(2), ···, R(E - 1)}、

[0390] Exemplary Setting 8 - 7: R = <R(0), R(1), ···, R(E - 2), R(E - 1)> = <J N-E , J N-E+1 , ···, J N-2 , J N-1 >, P I ={R(0), R(1), R(2), ···, R(E - 1)}, P O ={0, 1, 2, ···, Q max -1, Q max},

[0391] Exemplary Setting 8 - 8: R = <R(0), R(1), ···, R(E - 2), R(E - 1)> = <J N-E , J N-E+1 , ···, J N-2 , J N-1 >, P I ={R(0), R(1), R(2), ···, R(E - 1)}, P O ={R(0), R(1), ···, R(E - 2), R(E - 1)}。

[0392] Here, {0, 1, 2, ···, Q max -1, Q max} represents a set containing all elements that are non - negative integers less than or equal to the value Q max , and the value Q max is the maximum value in the data bit index set Q, [Number] and R(0), R(1), ···, R(E - 2), R(E - 1) are E different elements in the ordered rate - matching index set R = <R(0), R(1), ···, R(E - 2), R(E - 1)> of size E.

[0393] FIG. 9 illustrates an exemplary block error rate (BLER) curve for an exemplary setting 8-1 with parameters in Table 10 compared to a 5G polar code having the same input bit string length K and the same output bit string length E using QPSK modulation for an additive white Gaussian noise (AWGN) channel. It can be shown that the disclosed new scheme (solid line) functions better than the 5G polar code (dashed line).

Table 10-1

Table 10-2

[0394] FIG. 10 illustrates an exemplary BLER curve for an exemplary setting 8-2 with parameters in Table 11 compared to a 5G polar code having the same input bit string length K and the same output bit string length E using QPSK modulation for an AWGN channel. It can be shown that the disclosed new scheme (solid line) functions better than the 5G polar code (dashed line).

Table 11

[0395] FIG. 11 illustrates an exemplary BLER curve for an exemplary setting 8-3 with parameters in Table 12 compared to a 5G polar code having the same input bit string length K and the same output bit string length E using QPSK modulation for an AWGN channel. It can be shown that the disclosed new scheme (solid line) functions better than the 5G polar code (dashed line).

Table 12-1

Table 12-2

[0396] FIG. 12 illustrates an exemplary BLER curve for an exemplary setting 8-4 with parameters in Table 13 compared to a 5G polar code having the same input bit sequence length K and the same output bit sequence length E using QPSK modulation for an AWGN channel. It can be shown that the disclosed new scheme (solid line) functions better than the 5G polar code (dashed line). [Table 13-1] [Table 13-2]

[0397] FIG. 13 illustrates an exemplary BLER curve for an exemplary setting 8-5 with parameters in Table 14 compared to a 5G polar code having the same input bit sequence length K and the same output bit sequence length E using QPSK modulation for an AWGN channel. It can be shown that the disclosed new scheme (solid line) functions better than the 5G polar code (dashed line). [Table 14]

[0398] FIG. 14 gives a specific exemplary BLER curve for an exemplary setting 8-6 with parameters in Table 15 compared to a 5G polar code with the same input bit sequence length K and the same output bit sequence length E using QPSK modulation for an AWGN channel. It can be shown that the disclosed new scheme (solid line) functions better than the 5G polar code (dashed line). [Table 15-1] [Table 15-2]

[0399] FIG. 15 illustrates an exemplary BLER curve for an exemplary setting 8-7 with parameters in Table 16 compared to a 5G polar code having the same input bit sequence length K and the same output bit sequence length E using QPSK modulation for an AWGN channel. It can be shown that the disclosed new scheme (solid line) functions better than the 5G polar code (dashed line).

Table 16-1

Table 16-2

[0400] FIG. 16 illustrates an exemplary BLER curve for an exemplary setting 8-8 with parameters in Table 17 compared to a 5G polar code having the same input bit sequence length K and the same output bit sequence length E using QPSK modulation for an AWGN channel. It can be shown that the disclosed new scheme (solid line) functions better than the 5G polar code (dashed line).

Table 17-1

Table 17-2

[0401] Note that FIGS. 13-16 are the same because, regardless of whether P is {0, 1, 2, ···, Q I} or {R(0), R(1), R(2), ···, R(E-1)}, and / or whether P max is {0, 1, 2, ···, Q O} or {R(0), R(1), R(2), ···, R(E-1)}, the convolutional output is made the same due to making the convolutional output the same. max} or {R(0), R(1), R(2), ···, R(E-1)}, it is noted that they are the same.

[0402] Figure 17 is a flowchart representation of a method for digital communication according to one or more embodiments of the present technology. Method 1700 includes, in operation 1710, determining, by a first node, an output bit sequence having E bits based on an input bit sequence having K bits. The output bit sequence is determined based on a transformation applied prior to applying a polar transformation having a size of N. The transformation (e.g., pre-transformation) is based on at least one index set (e.g., P I and / or P O ) which is a subset of a set of bit indices. The set of bit indices comprises all non-negative integers less than N, where K < N and K < E. Method 1700 includes, in operation 1720, transmitting, by the first node, a signal including the output bit sequence to a second node.

[0403] Figure 18 is a flowchart representation of a method for digital communication according to one or more embodiments of the present technology. Method 1800 includes, in operation 1810, receiving, by a second node, a signal including an output bit sequence having E bits from a first node. Method 1800 includes, in operation 1820, determining, by the second node, an input bit sequence having K bits by decoding the output bit sequence included in the signal. The input bit sequence is determined based on a transformation applied after applying an inverse polar transformation having a size of N. The transformation (e.g., pre-transformation) is based on at least one index set which is a subset of a set of bit indices. The set of bit indices comprises all non-negative integers less than N, where K < N and K < E. In some embodiments, the at least one index set comprises an input index set and / or an output index set.

[0404] In some embodiments, the at least one index set comprises all non-negative integers that are max less than Q, and Q maxis an element having the maximum value in the first index set Q having K elements, where Q is a subset of the set of bit indices comprising all non-negative integers less than N. For example, Q is a data bit index set,

Number

[0405] In some embodiments, at least one index set is the same as the ordered rate matching index set R = <R(0), R(1), ···, R(Nr - 2), R(Nr - 1)>, where Nr = min(E, N).

[0406] In some embodiments, at least one index set comprises all non-negative integers that are max less than or equal to R, where max R is an element having the maximum value in the ordered rate matching index set R,

Number

[0407] In some embodiments, the output bit sequence consists of bits in the output bit sequence of the polar transform, and the indices are those in the ordered rate matching index set R = <R(0), R(1), ···, R(Nr - 2), R(Nr - 1)>. The output bit sequence of the polar transform has a length N, where Nr = min(E, N). For example, K = 4, N = 8, E = 6, R = <R(0), R(1), R(2), R(3), R(4), R(5)> = <0, 1, 3, 4, 7, 5>, and the polar transform output bit sequence d = [d 0 , d 1 , d 2 , d 3 , d 4 , d 5 , d 6 , d 7 . The output bit sequence e = [e 0 , e 1 , e 2 , e 3 , e4 , e 5 =[d R(0) , d R(1) , d R(2) , d R(3) , d R(4) , d R(5) =[d 0 , d 1 , d 3 , d 4 , d 7 , d 5 is.

[0408] In some embodiments, the output bit string is determined based on an intermediate bit string (e.g., string u), and the i-th bit of the intermediate bit string is set to a predetermined value in response to the index i not being in at least one index set. The predetermined value comprises 0, a value in the state bit string, or a value in the frozen bit string.

[0409] In some embodiments, the output bit string is determined based on an intermediate bit string (e.g., string u), and the i-th bit of the intermediate bit string is set to the i-th bit of the rate profile output bit string in response to the index i not being in at least one index set. The rate profile output bit string has a length N.

[0410] In some embodiments, the j-th bit of the intermediate bit string (e.g., string u) is determined by a convolutional bit string or a convolutional polynomial in response to the index j being in at least one index set. In some embodiments, the convolutional bit string comprises a generator bit string g = [g 0 , g 1 , ···, g m or a recursive feedback bit string q = [q 0 , q 1 , ···, q m . In some embodiments, the convolutional polynomial is a generator polynomial g(D) = g 0 + g 1 ·D + ··· + g m-1 ·D m-1 + g m ·Dm or a recursive feedback polynomial q(D)=q 0 +q 1 ·D+···+q m-1 ·D m-1 +q m ·D m is provided.

[0411] In some embodiments, a state bit sequence t = [t 0 , t 1 , ···, t m-1 , t m configured to store a convolutional state is shifted in response to an index i being in at least one index set. In some embodiments, an input bit sequence is represented as c, and an output bit sequence is determined based on an intermediate bit sequence (e.g., sequence u), and the i-th bit in the intermediate bit sequence is based on a linear combination of elements c 0 , c 1 , c 2 , ···, c i-1 , c i in c.

[0412] In some embodiments, an output bit sequence is determined based on an intermediate bit sequence (e.g., sequence u), and the i-th bit in the intermediate bit sequence is determined by a partial sequence of the input bit sequence and a rate profile frozen bit sequence f = [f 0 , f 1 , ···, f N-K-1 that is a binary sequence of length N - K. In some embodiments, an output bit sequence is determined based on an intermediate bit sequence (e.g., sequence u). The i-th bit in the intermediate bit sequence is based on a linear combination of bits in a rate profile output bit sequence whose index is in at least one index set (e.g., the intersection of an input index set and a bit index set) and is less than or equal to i, and the rate profile output bit sequence has a length of N. For example, if P I ={3, 4, 6, 7}, the 0-th bit in the intermediate bit sequence is the empty set {} = {0} ∩ P IDetermined by, the first bit in the intermediate bit string is the empty set {} = {0, 1} ∩ P I Determined by, the second bit in the intermediate bit string is the empty set {} = {0, 1, 2} ∩ P I Determined by, the third bit in the intermediate bit string is the set {3} = {0, 1, 2, 3} ∩ P I Determined by, the fourth bit in the intermediate bit string is the set {3, 4} = {0, 1, 2, 3, 4} ∩ P I Determined by, the fifth bit in the intermediate bit string is the set {3, 4} = {0, 1, 2, 3, 4, 5} ∩ P I Determined by, the sixth bit in the intermediate bit string is the set {3, 4, 6} = {0, 1, 2, 3, 4, 5, 6} ∩ P I Determined by, the seventh bit in the intermediate bit string is the set {3, 4, 6, 7} = {0, 1, 2, 3, 4, 5, 6, 7} ∩ P I Is determined by.

[0413] In some embodiments, the input bit string is represented as c. The output bit string is determined based on the intermediate bit string (e.g., the string u). The i-th bit in the intermediate bit string is an element c in c 0 , c 1 , c 2 , ···, c M-2 , c M-1 Is determined based on the linear combination of. M represents the number of elements shared by a first index set Q that is a subset of the set of bit indices and a second index set {0, 1, 2, ···, i - 1, i} that includes all non-negative integers less than or equal to i. For example, for Q = {3, 5, 7} and i = 1, Q ∩ {0, 1, 2, ···, i - 1, i} = {} and M = 0; for Q = {3, 5, 7} and i = 3, Q ∩ {0, 1, 2, ···, i - 1, i} = {3} and M = 1; for Q = {3, 5, 7} and i = 4, Q ∩ {0, 1, 2, ···, i - 1, i} = {3} and M = 1; for Q = {3, 5, 7} and i = 5, we have Q ∩ {0, 1, 2, ···, i - 1, i} = {3, 5} and M = 2. The i-th bit in the intermediate bit string is an element v in v0 , v 1 , v 2 , ···, v i Based on the linear combination of, v having N bits is the input of the transformation. For example, for K = 3 and N = 8, c = [c 0 , c 1 , c 2 , Q = {3, 5, 7}, v = [v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 = [0, 0, 0, c 0 , 0, c 1 , 0, c 2 . v 3 , v 5、 v 7 are respectively set to c 0 , c 1 , c 2 , while the other bits in v are all set to 0. The 0th bit in the intermediate bit sequence is based on the linear combination of the element v 0 (without the element in c). The 1st bit in the intermediate bit sequence is based on the linear combination of the elements v 0 , v 1 (without the element in c). The 2nd bit in the intermediate bit sequence is based on the linear combination of the elements v 0 , v 1 , v 2 (without the element in c). The 3rd bit in the intermediate bit sequence is based on the linear combination of the elements v 0 , v 1 , v 2 , v 3 (or the linear combination of the element c 0 ). The 4th bit in the intermediate bit sequence is based on the linear combination of the elements v 0 , v 1 , v 2 , v 3 , v 4 (also, the linear combination of the element c 0 ). The 5th bit in the intermediate bit sequence is based on the linear combination of the elements v 0 , v 1 , v 2, v 3 , v 4 , v 5 is based on a linear combination of (or elements c 0、 c 1 ). The sixth bit in the intermediate bit string is based on a linear combination of elements v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 (or elements c 0、 c 1 ). The seventh bit in the intermediate bit string is based on a linear combination of elements v 0 , v 1 , v 2 , v 3 , v 4 , v 5 , v 6 , v 7 (or elements c 0、 c 1 , c 2 ).

[0414] Those skilled in the art will understand that the disclosed techniques can be applied prior to polar transformation in channel coding to improve transmission efficiency. For example, in some embodiments, a method for wireless communication includes applying a pre-transformation operation prior to polar coding such that, as a result of the pre-transformation operation (e.g., based on rate profiling to account for different payload sizes), a subset of bits having a length not equal to the polar coding length N is coded to provide a variable code length that is adaptive according to the payload size. As described in this patent document, the pre-transformation operation can include index-based shuffling. Various possible pre-transformation techniques are described with reference to FIGS. 5A-C, FIGS. 8A-C, Algorithms 1A-1L, Algorithms 2A-2L, Algorithms 3A-3L, Algorithms 4A-4B, Algorithms 5A-5G, Algorithms 6A-6G, and Algorithms 7A-7G. Other pre-transformation operations can include index remapping using a look-up table or a state machine. Illustrated in FIGS. 17-18 and described above, the methods are specific examples of the disclosed techniques. The disclosed techniques also include other approaches that are mathematically equivalent to the methods illustrated in FIGS. 17-18, the algorithms (Algorithms 1A-1L, Algorithms 2A-2L, Algorithms 3A-3L, Algorithms 4A-4B, Algorithms 5A-5G, Algorithms 6A-6G, and Algorithms 7A-7G), and / or the examples described above (e.g., Examples 1-8).

[0415] FIG. 19 shows an example of a wireless communication system 1900 to which techniques according to one or more embodiments of the present technology may be applied. The wireless communication system 1900 can include one or more base stations (BSs) 1905a, 1905b, one or more wireless devices (or UEs) 1910a, 1910b, 1910c, 1910d, and a core network 1925. The base stations 1905a, 1905b can provide wireless services to user devices 1910a, 1910b, 1910c, and 1910d within one or more wireless sectors. In some implementations, the base stations 1905a, 1905b include directional antennas for generating two or more directional beams to provide a wireless communication coverage area within different sectors. The core network 1925 can communicate with one or more base stations 1905a, 1905b. The core network 1925 provides connectivity with other wireless communication systems and wired communication systems. The core network can include one or more service subscription databases for storing information related to subscribed user devices 1910a, 1910b, 1910c, and 1910d. The first base station 1905a can provide wireless services based on a first radio access technology, while the second base station 1905b can provide wireless services based on a second radio access technology. The base stations 1905a and 1905b can be located at the same location or separately installed on-site according to the deployment scenario. The user devices 1910a, 1910b, 1910c, and 1910d can support multiple different radio access technologies. The techniques and embodiments described in this document can be implemented by the base stations of the wireless devices described in this document.

[0416] FIG. 20 is a block diagram representation of a portion of a wireless station to which techniques according to one or more embodiments of the present technology may be applied. A wireless station 2005, such as a network node, base station, or wireless device (or user device, i.e., UE), can include a processor electronic device 2010, such as a microprocessor, that implements one or more of the wireless techniques presented in this document. The wireless station 2005 can include a transceiver electronic device 2015 for transmitting and / or receiving wireless signals via one or more communication interfaces, such as an antenna 2020. The wireless station 2005 can include other communication interfaces for transmitting and receiving data. The wireless station 2005 can include one or more memories (not explicitly shown) configured to store information such as data and / or instructions. In some implementations, the processor electronic device 2010 can include at least a portion of the transceiver electronic device 2015. In some embodiments, at least some of the disclosed techniques, modules, or functions are implemented using the wireless station 2005. In some embodiments, the wireless station 2005 can be configured to implement the methods described herein.

[0417] The disclosed, and other embodiments, modules, and functional operations described in this specification can be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. The disclosed, and other embodiments can be implemented as one or more computer program products, i.e., as one or more modules of computer program instructions encoded on a computer-readable medium for execution by, or to control the operation of, a data processing apparatus. The computer-readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, a composition that generates a machine-readable propagated signal, or a combination of one or more of them. The term "data processing apparatus" includes, by way of example, all apparatus, devices, and machines for processing data, including programmable processors, computers, or multiple processors or computers. The apparatus can include, in addition to hardware, code that creates an execution environment for the computer program, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them. A propagated signal is an artificially generated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal generated to encode information for transmission to a suitable receiver device.

[0418] A computer program (also known as a program, software, software application, script, or code) can be described in any form of programming language, including compiler-type or interpreter-type languages, and can be deployed in any form, including as a stand-alone program or as modules, components, subroutines, or other units suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. The program can be stored within a part of a file that holds other programs or data (such as one or more scripts stored within a markup language document), within a single file dedicated to the program, or within multiple cooperating files (such as files that store one or more modules, subprograms, or portions of code). A computer program can be deployed to be executed on one computer, or on a single location, or distributed across multiple computers located at one or more locations and interconnected by a communication network.

[0419] The processes and logical flows described in this book can be implemented by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logical flows can also be implemented by, or the apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit). A processor suitable for the execution of a computer program includes, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. In general, a processor will receive instructions and data from a read only memory or a random access memory or both. The essential elements of a computer are a processor for performing instructions and one or more memory devices for storing instructions and data. In general, a computer will also include, or be operatively coupled to receive data from, or transfer data to, or both, one or more mass storage devices (e.g., magnetic, magneto optical disks, or optical disks) for storing data. However, a computer need not have such devices. Computer readable media suitable for storing computer program instructions and data include all forms of nonvolatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto optical disks; and CD ROM and DVD-ROM disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

[0420] This patent document contains many details, but these should be construed as descriptions of features that may be specific to particular embodiments of a particular invention rather than as limitations on the scope of any invention or claimed subject matter. Certain features described in this patent document in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. Further, although a feature may be described above as operating in a certain combination and may even be claimed initially as such, one or more features from the claimed combination may in some cases be excluded from the combination, and the claimed combination may be directed to a sub-combination or a variation of a sub-combination.

[0421] Similarly, although operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in a sequential order to achieve desirable results, or that all illustrated operations be performed. Further, the separation of various system components in the embodiments described in this patent document should not be understood as requiring such separation in all embodiments.

[0422] Only some implementations and examples are described, and other implementations, enhancements, and variations can also be made based on what is described and illustrated in this patent document.

Claims

Claim 1 A method for digital communication, the method comprising: determining, by a first node, an output bit sequence having E bits based on an input bit sequence having K bits, wherein the output bit sequence is determined based on a transformation applied prior to applying a polar transformation having a size of N, the transformation being based on at least one index set that is a subset of a set of bit indices, the set of bit indices comprising all non-negative integers less than N, with K < N and K < E; transmitting, by the first node, a signal including the output bit sequence to a second node; A method comprising the above steps. Claim 2 A method for digital communication, the method comprising: receiving, by a second node, a signal including an output bit sequence having E bits from a first node; determining, by the second node, an input bit sequence having K bits by decoding the output bit sequence included in the signal; wherein the input bit sequence is determined based on a transformation applied after applying an inverse polar transformation having a size of N, the transformation being based on at least one index set that is a subset of a set of bit indices, the set of bit indices comprising all non-negative integers less than N, with K < N and K < E. A method. Claim 3 The at least one index set is Q ｍａｘ comprises all non-negative integers that are as follows, Q ｍａｘ is an element having the maximum value in the first index set Q having K elements, and Q is a subset of the set of bit indices comprising all non-negative integers less than N 【Number 90】 The method according to claim 1 or 2. Claim 4 The method according to claim 1 or 2, wherein the at least one index set is the same as an ordered rate matching index set R = <R(0), R(1),..., R(Nr - 2), R(Nr - 1)>, and Nr = min(E, N). Claim 5 The at least one index set is R ｍａｘ comprises all non-negative integers that are as follows, R ｍａｘ is an element having the maximum value in the ordered rate matching index set R, 【Number 91】 The method according to claim 1 or 2. Claim 6 The method according to claim 4 or 5, wherein the output bit sequence consists of bits in the output bit sequence of the polar transformation whose indices are in an ordered rate matching index set R = <R(0), R(1),..., R(Nr - 2), R(Nr - 1)>, the output bit sequence of the polar transformation having a length of N, and Nr = min(E, N). Claim 7 The method according to claim 1 or 2, wherein the output bit sequence is determined based on an intermediate bit sequence, and the i-th bit of the intermediate bit sequence is set to a predetermined value in response to the index i not being in the at least one index set. Claim 8 The method according to claim 7, wherein the predetermined value comprises 0, a value in the state bit sequence, or a value in the frozen bit sequence.

9. The output bit sequence is determined based on an intermediate bit sequence, and the i-th bit of the intermediate bit sequence is set to the i-th bit of a rate profile output bit sequence in response to the subscript i not being in the at least one subscript set, and the rate profile output bit sequence has a length N, according to the method of claim 1 or 2.

10. The j-th bit of the intermediate bit sequence is determined by a convolutional bit sequence or a convolutional polynomial in response to the subscript j being in the at least one subscript set, according to the method of claim 1 or 2.

11. The convolutional bit sequence includes a generator bit sequence g = [g ０ , g １ , ···, g ｍ or a recursive feedback bit sequence q = [q ０ , q １ , ···, q ｍ , and the method according to claim 10.

12. The convolutional polynomial is a generator polynomial g(D) = g ０ + g １ · D + ··· + g ｍ－１ · D ｍ－１ + g ｍ · D ｍ or a recursive feedback polynomial q(D) = q ０ + q １ · D + ··· + q ｍ－１ · D ｍ－１ + q ｍ · D ｍ The method according to claim 10, comprising the same.

13. The state bit string t = [t ０ , t １ , ···, t ｍ－１ , t ｍ , which is configured to store the convolution state, is shifted in response to the subscript i being in the at least one subscript set, according to the method of claim 1 or 2.

14. The input bit string is represented as c, the output bit string is determined based on an intermediate bit string, and the i-th bit in the intermediate bit string is a linear combination of elements c ０ , c １ , c ２ , ···, c ｉ－１ , c ｉ in c, and is determined based on the linear combination, according to the method of claim 1 or 2.

15. The output bit sequence is determined based on the intermediate bit sequence, and the i-th bit in the intermediate bit sequence is a subsequence of the input bit sequence and a rate profile frozen bit sequence f = [f ０ , f １ , ···, f Ｎ－Ｋ－１ of length N - K, the method according to claim 1 or 2.

16. The output bit sequence is determined based on an intermediate bit sequence, and the i-th bit in the intermediate bit sequence is determined based on a linear combination of bits in a rate profile output bit sequence where the subscript is in the at least one subscript set and is less than or equal to i, and the rate profile output bit sequence has a length N, according to the method of claim 1 or 2.

17. The input bit string is represented as c, the output bit string is determined based on an intermediate bit string, and the i-th bit in the intermediate bit string is an element c in c ０ , c １ , c ２ , ···, c Ｍ－２ , c Ｍ－１ determined based on a linear combination of, where M is the number of elements shared by a first index set Q which is a subset of the set of the bit indices and a second index set {0, 1, 2, ···, i - 1, i} comprising all non-negative integers less than or equal to i, the method according to claim 1 or 2.

18. The method according to any one of claims 1 - 17, wherein the at least one subscript set comprises an input subscript set and / or an output subscript set.

19. A communication device comprising a processor configured to implement the method according to any one or more of claims 1 - 18.

20. A computer program product storing code, wherein when the code is executed by a processor, the processor is caused to implement the method according to any one or more of claims 1 - 18.

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