Battery Management System and Monitoring Device

Abstract

A monitoring device is provided. The monitoring device comprises one or more circuits operable to obtain measurements of one or more pins of a battery system, the one or more circuits comprising at least one circuit for monitoring current, the at least one circuit comprising at least one differential amplifier, at least one other circuit for amplifying a variance, comprising one voltage reference electrically connected to a first input of the differential amplifier, at least one output electrically connected to a second input of the differential amplifier, and at least one transconductance means comprising at least one input electrically connected to an output of the differential amplifier, at least one current source electrically connected to at least one output of the at least one transconductance means, and an output electrically connected to at least one output of the at least one transconductance means.

Description

Technical Field

[0001] The present disclosure relates to the fields of battery technology and energy cells. More specifically, the present disclosure relates to battery management systems and monitoring devices for monitoring a battery cell or a group of battery cells, and adjustment systems for use with such monitoring devices.

Background Art

[0002] Battery systems comprising a plurality of battery cells are used in a wide range of modern power applications. For example, they are used to supply power to electric vehicles and in commercial applications such as industrial power applications, transportation, and power supply for up-to-date electronic devices. Considering the relatively high power demand of such applications, battery systems often comprise a plurality of battery cells connected together to achieve the required power output. The battery cells can be connected together to form battery packs, and the battery system can include one or more battery packs.

[0003] It is common to connect a battery system to a battery management system configured to ensure that the battery system operates within its safe operating range. The safe operating area is generally defined as the voltage, temperature, and current conditions under which the battery system is expected to operate without self-damage.

[0004] To achieve this, typically each battery cell of a battery system is monitored using a cell monitoring device. The function of the cell monitoring device is to measure signals from the battery cell being monitored, such as cell terminal voltage, cell current, cell temperature, cell pressure, etc., and then use these signals to determine whether the cell is in a safe state. In some systems, the measurements obtained by the cell monitoring device are collated and sent to a battery management system, which processes the measurements to determine the current state of the monitored cell. Alternatively, the measurements can be collated and processed within the individual cell monitoring device and reported to the battery management system, as a result of which the battery management system can maintain an overview of the current state of the battery system. Summary of the Invention

[0005] The present disclosure provides a monitoring device operable to report sensor measurement data of a battery system. The monitoring device includes one or more circuits operable to acquire measurements of one or more pins of the battery system, and the one or more circuits include at least one circuit for monitoring current. The at least one circuit for monitoring current includes at least one differential amplifier and at least one other circuit for amplifying a variance, including one voltage reference electrically connected to a first input of the differential amplifier, wherein the differential amplifier further includes a second input and an output, the at least one other circuit, at least one output electrically connected to the second input of the differential amplifier, and at least one transconductance means including at least one input electrically connected to the output of the differential amplifier, wherein the second input of the differential amplifier and at least one output of the at least one transconductance means are electrically connected to one or more pins of the battery system, the at least one transconductance means, at least one current source electrically connected to at least one output of the at least one transconductance means, and an output electrically connected to at least one output of the at least one transconductance means. The at least one circuit for monitoring current is operable to detect a break or absence of an electrical connection of a sensor connected to one or more pins by monitoring a current required to cause a variance in the voltage of the one or more pins.

[0006] Aspects of the present disclosure provide an adjustment system for providing an adjusted voltage during power-on reset to a cell monitoring device (CMD) of a battery system. The battery system includes at least one pack, each pack includes a plurality of battery cells, and each battery cell is monitored via its respective CMD. The adjustment system includes a bandgap reference unit configured to generate a bandgap reference voltage (VBG) based on a supply voltage (VDD), and further configured to generate a first enabling signal when the bandgap reference voltage stabilizes and reaches a level appropriate for the operational safety of the CMD core circuit. The system further includes a voltage regulator unit configured to receive the bandgap reference voltage (VBG) and the first enabling signal from the bandgap reference unit, and upon receiving the first enabling signal, the voltage adjustment unit is further configured to generate an adjusted voltage (D VDD ) for powering the CMD core circuit, and the adjusted voltage (D VDD ) is generated based on a comparison with the bandgap reference voltage (VBG). The system additionally includes a power-on reset comparator configured to receive the bandgap reference voltage (VBG) from the bandgap reference unit and the adjusted voltage (D VDD ) from the voltage regulator. The power-on reset comparator is further configured to provide a second enabling signal to the CMD core circuit when the value of the adjusted voltage is greater than the value of the bandgap reference voltage (VBG), and the second enabling signal enables the CMD core circuit to access the adjusted voltage (D VDD ).

[0007] Another aspect of the present disclosure provides a method in an adjustment system for providing a voltage adjusted during power-on reset to a cell monitoring device (CMD) of a battery system. The battery system includes at least one pack, each pack includes a plurality of battery cells, and each battery cell is monitored via its respective CMD. The method includes generating a bandgap reference voltage (VBG) based on a supply voltage (VDD) via a bandgap reference unit (BG), and further generating a first activation signal when the bandgap reference voltage (VBG) stabilizes and reaches a level appropriate for the operational safety of the CMD core circuit 305. The method further includes receiving the bandgap reference voltage (VBG) and the first activation signal from the bandgap reference unit via a voltage regulator unit 301. Upon receiving the first activation signal, the method further includes generating an adjusted voltage (D VDD ) to supply power to the core circuit of the CMD via the voltage regulator unit, and the adjusted voltage (D VDD ) is generated based on a comparison with the bandgap reference voltage (VBG). The method also includes receiving the bandgap reference voltage (VBG) from the bandgap reference unit via a power-on reset comparator, and receiving the adjusted voltage (D VDD ) from the voltage regulator. Additionally, the method includes providing a second activation signal to the CMD core circuit via the power-on reset comparator when the value of the adjusted voltage (D VDD ) is greater than the value of the bandgap reference voltage (VBG), and the second activation signal enables the CMD core circuit to access the adjusted voltage (D VDD ).

[0008] A further aspect of the present disclosure provides a monitoring device, a monitoring system, a controller, and an adjustment system for use in a system as described above, and methods related thereto.

[0009] The foregoing will be described in more detail by the following more detailed description of exemplary embodiments, as shown in the accompanying drawings which refer to the same parts throughout different figures with different reference characters. The drawings are not necessarily to scale, and instead, emphasis is placed on showing exemplary embodiments.

Brief Description of the Drawings

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[0011] Here, reference is made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings, and like numerals in different drawings represent the same or similar elements unless otherwise represented. The embodiments described in the following description of the exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of systems, devices, and methods consistent with aspects of the present invention as recited in the appended claims.

[0012] Overview of Battery Management System Architecture FIG. 1 is an explanatory diagram of an exemplary wired battery management system architecture in which a plurality of cell monitoring devices 10-1... 10-N are connected to a communication controller 15 via a wired harness 12. In the exemplary architecture of FIG. 1, the wired harness 12 connects the cell monitoring devices 10-1... 10-N to the communication controller 15 in the form of a star network centered on the communication controller 15. The communication controller 15 is also connected to a battery management unit 20.

[0013] In the exemplary system of FIG. 1, each cell monitoring device 10-1... 10-N is configured to monitor one or more battery cells 22-1... 22-N and obtain measurements of physical properties associated with the one or more cells 22-1... 22-N, such as voltage, current, temperature, pressure, strain, force, etc., and / or derived measurements such as state of charge (SoC). Next, these measurements (which may include derived measurements in some examples) are transmitted from each cell monitoring device 10-1... 10-N to the communication controller 15 via the wired harness 12.

[0014] The communication controller 15 may be configured to aggregate all messages from the cell monitoring devices 10-1... 10-N and then pass those messages to the battery management unit 20. Alternatively, the communication controller 15 may be configured to pass individual messages directly to the battery management unit 20, which then proceeds to process the received measurements to determine the current state of the battery system.

[0015] In many cases, the communication controller 15 is a hardware device separate from the battery management unit 20. Alternatively, the communication controller 15 and the battery management unit 20 may be integrated into a single hardware device, with the communication controller 15 responsive to adjusting the reception of data via the wired harness 12 and the battery management unit 20 responsive to analyzing and processing the data.

[0016] One drawback of the wired battery management system architecture shown in FIG. 1 is that in such an architecture, the communication controller 15 and the wired harness 12 are configured to receive measurement values from a predefined number of cell monitoring devices 10-1...10-N. This makes it difficult to expand the system. The reason is that the addition of additional cell monitoring devices 10-1...10-N usually requires the addition of extra circuitry and connections to the communication controller 15 to connect to the additional cell monitoring devices, as well as modification of the wire harness 12.

[0017] FIG. 2 shows an alternative approach to the wired battery management system architecture of FIG. 1. In contrast to the wired battery management system architecture of FIG. 1 in which the wired harness 12 connects the cell monitoring devices 10-1...10-N to the communication controller 15 in the form of a star network, in the exemplary architecture of FIG. 2, the cell monitoring devices 10-1...10-N are wired by wiring 25 in the form of a daisy chain network in which consecutive cell monitoring devices 10-1...10-N are connected in series.

[0018] The operation of the wired battery management system architecture in FIG. 2 is quite similar to that of the star network in FIG. 1, except that instead of each cell monitoring device 10-1...10-N communicating directly with the communication controller 15, messages are relayed back and forth through the cell monitoring devices 10-1...10-N by up and down daisy-chain wiring 25. This means that the operation of each cell monitoring device 10-1...10-N is no longer the same. The reason is that the cell monitoring device 10-N directly connected to the communication controller 15 needs to relay messages from all other cell monitoring devices 10-1...10-N-1, while the cell monitoring device 10-1 at the end of the daisy chain has no message relay demand. The latency of the message (the time it takes to move from the source cell monitoring device to the communication controller 15) varies depending on the cell monitoring device and increases as the number of cells / cell monitoring devices increases. In some embodiments, the daisy-chain wiring 25 can be formed into a loop terminated at both ends by the communication controller 15. In this case, the latency can vary among the cell monitoring devices 10-1...10-N depending on the direction around the loop in which the message travels. This varying latency is a drawback of the daisy-chain wired battery network.

[0019] FIG. 3 shows a variant of the battery management system architecture of FIG. 1, where instead of using the wired harness 12, communication is done wirelessly via a wireless network. For that purpose, each cell monitoring device 10-1...10-N has an antenna 30, similar to the communication controller 15. The wireless network can use long-range antennas or short-range coupling.

[0020] The wireless battery management system architecture of FIG. 3 provides the advantages of a wired star network (all cell monitoring devices 10-1...10-N are identical, there is a certain latency, etc.). In addition, as the number of cell monitoring devices 10-1...10-N changes, neither the communication controller 15 nor any of the wire harnesses 12 need to be changed. However, wireless communication is generally less reliable than a wired network because the wireless channels and external wireless energy sources that cause interference with communication are unpredictable.

[0021] Structure of the Communication Controller and Cell Monitoring Device Here, the structures of the communication controller 15 and the cell monitoring devices 10-1...10-N of the system of FIG. 3 will be described in more detail with reference to FIGS. 4 and 5.

[0022] Referring first to FIG. 4, in one embodiment, the cell monitoring device 10 of the battery management system of FIG. 3 may include one or more sensors 31, 32, 33. In FIG. 4, three sensors are shown, namely a voltage sensor 31, a current sensor 32, and a temperature sensor 33. It will be appreciated that in other embodiments, more or fewer sensors or different sensors may be included in the cell monitoring device 10.

[0023] In this embodiment, the sensors 31, 32, 33 are connected to an analog-to-digital converter (ADC) 37 via an analog multiplexer 35, and the ADC 37 is also connected to a processor 39. In an alternative embodiment, the analog multiplexer 35 may be omitted, and instead, multiple ADCs 37 may be provided, and each of the sensors may be directly connected to the processor 39 via its own dedicated ADC 37. However, it will be appreciated that providing the analog multiplexer 35 makes it possible to avoid duplication of the ADC 37.

[0024] Also, the processor 39 is also connected to a memory 40, which can be a non-volatile random access memory (NVRAM) or a read-only memory (ROM) that stores a program including processing instructions for processing digital signals representing sensor measurement values received from the ADC 37. Alternatively, the memory 40 can include a static random access memory (SRAM), thereby enabling the storage and subsequent modification of the program. Such embodiments can facilitate the creation and debugging of programs for storage in the cell monitoring device 10 during the development of the battery management system.

[0025] In addition, the processor 39 is also connected to the antenna 30 via the wireless block 45. A clock 47 is provided within the cell monitoring device 10 to regulate the timing of sensor measurements and other processes performed by the cell monitoring device 10. In some embodiments, the clock 47 can take the form of an oscillator.

[0026] In use, the sensors 31, 32, 33 measure one or more battery cells 22 (only one battery cell 22 is shown in FIG. 4, but typically in multiple embodiments, the monitoring device 10 can be configured to obtain measurement values from a plurality of battery cells, a plurality of battery cells, for example, from a group of 12 or more). The analog measurement values from the sensors 31, 32, 33 are passed to the ADC 37 via the analog multiplexer 35, and the ADC 37 transmits the digitized measurement values to the processor 39. Next, the processor 39 executes a program stored in the memory 40 that converts the received digital signal into measurement values with physical meanings such as volts, amperes, and kelvins, and packages the data so that it can be transmitted. In multiple embodiments, the packaged digital measurement values can be held in an internal register within the processor 39 before transmission. Periodically, when the wireless block 45 becomes active, the stored packaged measurement values stored internally in the register within the processor 39 are wirelessly transmitted via the antenna 30 to the communication controller 15.

[0027] The structure of the communication controller 15 is similar to that of the cell monitoring device 10 in that the communication controller 15 also includes an antenna 30, a radio block 45, a processor 39, a memory 40, and a clock 48. However, instead of storing a program for adjusting the capture, packaging, and transmission of sensor measurements from sensors 31, 32, 33, the memory 40 of the communication controller 15 stores a program for causing the processor 39 of the communication controller 15 to transfer measurement data to the battery management unit 20 for adjustment. The processor 39 of the communication controller 15 can, in some embodiments, detect errors in the transmission, reception, and / or packaging of sensor measurements before transferring the measurement data to the battery management unit 20. Such processing can include checking for error detection or error correction codes included in transmissions received via the antenna 30. Additionally, the communication controller 15 also provides a communication path for control messages transmitted from the battery management unit 20 via the antenna 30 and a wireless communication link to the cell monitoring devices 10-1...10-N. The communication controller 15 can, in some embodiments, generate control messages and transmit them to the cell monitoring devices 10-1...10-N via the antenna 30.

[0028] The architectures of the cell monitoring device 10 and the communication controller 15 shown in FIG. 4 may be satisfactory for low-risk applications, but since the illustrated architectures have many points of low reliability, such architectures are not suitable for high-risk applications.

[0029] As an example, a fault in ADC37 may not be detected. Alternatively, a fault in a software program may not be detected. “Degenerate” faults can occur in many places and values that should change are not updated. If the output value of ADC37 is not updated, the system may not notice that the value is not changing. On the other hand, a cell may exceed its voltage and cause a hazard. The processor software may not be able to update the value sent to the radio block 45, so the communication controller 15 receives what appears to be a safe value but is actually inaccurate.

[0030] Taking these problems into consideration, in many applications, an alternative architecture as shown in FIG. 5 may be used.

[0031] Compared to the architecture of FIG. 4, in the alternative architecture of FIG. 5, the diagnostic source block 50 is included in the cell monitoring device 10 configured to apply a known signal to the analog multiplexer 35. Next, if a known value, or a predicted value based on a known value, is not seen by the processor or communication controller 15 of the monitoring device 10 thereafter, that value may be an indicator that something has gone wrong and a fault will be detected.

[0032] Furthermore, the architecture of FIG. 5 replaces the ADC37 with a multiplexer 51 connected to two ADCs 37-1 and 37-2. It is unlikely that both ADCs 37-1 and 37-2 will exhibit the same fault simultaneously. Therefore, the outputs from ADCs 37-1 and 37-2 can be compared, and if they do not substantially match (i.e., if the acquired ADC conversions substantially match), a fault flag can be set. Usually, in such a situation, if there is a discrepancy in the results of ADCs 37-1 and 37-2, it is only possible to determine that there is a fault in one of ADCs 37-1 and 37-2, but it is not determined which one has the fault. However, in some embodiments, it may be possible to identify which of ADCs 37-1 and 37-2 has an error in combination with a diagnostic source (e.g., a known value or a predicted value based on a known value from the diagnostic source block 50). A further potential advantage of the presence of two ADCs 37-1 and 37-2 is that the outputs of ADCs 37-1 and 37-2 that substantially match (i.e., the acquired values do not exceed the threshold and do not mismatch) can be averaged to obtain an average value of the digitized sensor signal. This reduces the influence of noise in the measurement and conversion process, thereby increasing the accuracy of the analog-to-digital conversion of the measured analog signal. In some embodiments, this may be more preferable than simply discarding the measured signal from a single ADC.

[0033] In addition to replacing the single ADC37 with the pair of ADC37-1, 37-2 and multiplexer 51, in the architecture of FIG. 5, the processors 39 of the monitoring device 10 and the communication controller 15 are replaced by a dual-core lockstep processor 52. The dual-core lockstep processor 52, sometimes called a safety processor, is a processor that includes two (or more) processor cores, each core executing the same software program, but one core being delayed compared to the other core. In addition to this delay, the two cores are executed in lockstep. This allows the outputs of the cores to be compared (taking into account the delay). Since the cores execute the same program on the same data, the results should exactly match. Therefore, if one of the software programs is damaged in one of the cores and the results do not match, a failure can be detected.

[0034] These modifications to the architecture of FIG. 4 improve the ability to confirm that no errors occur during the conversion and transmission of sensor measurements from sensors 31, 32, 33 in the cell monitoring device 10 to the battery management unit 20. However, the reliability of the data received by the battery management unit 20 can be further improved by restricting the processing performed by the dual-core lockstep processor 52.

[0035] More specifically, the applicant recognizes that software processing of data within the communication path between the acquisition of analog measurement values by sensors 31, 32, 33 in the cell monitoring devices 10-1...10-N and the reception of data collected by the battery management unit 20 is a significant potential cause of errors within the battery management system. Hardwired data processing, such as that performed by multiplexer 35 and ADCs 37-1, 37-2, is essentially deterministic. For example, as explained above, the results of hardwired data processing are predictable within an acceptable range, so it is possible to detect malfunctions or errors. However, software processing, especially when it depends on factors external to the processor, may not be detected (for example, such external factors can lead to a wide range of results, so in many cases, in fact, they result in a result from several possibilities that are not predictable until the processing is actually performed). Examples of such external factors include any processing based on interrupts, where the interrupt changes the expected processing by stopping a particular process while a secondary process is being performed. Additionally, actions that depend on non-deterministic external memory access (as opposed to storing values in the processor's registers) can result in non-deterministic errors because the stack can be used when a stack overflow error can occur at an unexpected time. Conversely, when the processing is deterministic and does not include steps such as interrupts and external memory access, the processing can be expected to be executed and completed within a set period, and the variation in the time taken to execute and complete the program would be expected to be relatively small. This would not be the case if the program included interrupt steps. Since such interrupts cause a suspension of processing for an unknown period and at an unknown timing at which such interrupts are triggered, the time taken to execute and complete the program becomes uncertain and cannot be known in advance.

[0036] It may be possible to analyze software in order to "prove" that no errors occur, but such analysis is difficult, time-consuming, and costly. The applicant recognizes that many of the potential reliability degradations in the software processing in the data path between the set of sensors 31, 32, 33 and the battery management unit 20 can be reduced by applying some of the major principles in the construction of the programs executed by the processors 39, 52.

[0037] First, as a principle, the processing of the measurement values from the set of sensors 31, 32, 33 should be limited to converting the sensor measurement values into meaningful digital data (for example, converting the sensor measurement values into digital codes with physical meanings such as volts, amperes, Kelvin, etc.) and packaging such data so that it can be transmitted to the battery management unit 20 for analysis (including the generation and checking of any error detection or error correction codes within the data for transmission). Other processing, such as the generation of histogram data indicating that the time cells 22-1...22-N remain in a specific state, which is not important but potentially useful, should be performed via a separate processing path using a separate processor that has no role in the processing, packaging, and transmission of the sensor measurement data.

[0038] Second, the program executed as part of this data transmission path should be designed to avoid the use of any interrupts, external memory access steps that require storing or accessing data in non-deterministic memory, or the use of a stack. This latter principle can be achieved when the program within the data transmission path is configured to store data in the internal registers of the processor 39 instead of utilizing external memory storage during the process of processing and transmitting sensor data from the sensors 31, 32, 33 to the battery management unit 20. In this case, the scope of the program executed by the processors 39, 52 is such that it necessarily executes and completes within a time scale smaller than the time scale at which sensor measurements are acquired and reported to the battery management unit 20.

[0039] This latter criterion can be achieved when sensor measurements are sampled according to a predetermined schedule and reported to the battery management unit 20. Due to the processing capabilities and clock speeds of any of the processors 39, 52 within the data transmission path between the sensors 31, 32, 33 and the battery management unit 20, any program executed by such processors 39, 52 within the data path will execute and complete within a time scale shorter than the time scale at which data is sampled and reported.

[0040] Thus, as an example, when cell measurements are sampled and reported at a frequency in hertz, processors 39, 52 have a processing speed on the order of megahertz, and the programs executed by processors 39, 52 need to be programs that necessarily execute and complete within a number of clock cycles less than the ratio of the sampling frequency to the processing speed of processors 39, 52. This means that the processing capabilities of processors 39, 52 are not fully utilized, but this ensures that whenever each program executed by processors 39, 52 is complete and the packaged data is needed, it is available for transmission. This, along with the absence of interrupts, use of external memory access, or use of a stack, causes processors 39, 52 to operate as deterministic state machines, and thus the reliability of the processing by processors 39, 52 becomes comparable to that of the other hardwired connection components of cell monitors 10-1...10-N and communication controller 15.

[0041] In some examples, processors 39, 52 may be provided (e.g., designed or manufactured) for the system, provided that at least one or all of the following functions, namely interrupts, external memory access, and / or use of a stack, are excluded. Alternatively, processors 39, 52 may be provided for a system with the above functions, but those functions are disabled. In yet other alternative embodiments, processors 39, 52 are provided for the system with the above functions, but any program executed therein is designed to avoid using any of those functions.

[0042] Furthermore, operations performed by processors 39, 52 within the communication path between ADC37 or ADC37-1, 37-2 and battery management unit 20 are such that the processing is limited to the conversion of the output of the ADC to data and the packaging of such data, including the creation and addition of error check codes or error correction codes such that data representing sensor measurements is not stored or modified. Preferably, the processing is limited to processing according to a single instruction set corresponding to this task. This should help ensure that the operations of processors 39, 52 are the same each time the process is performed.

[0043] Detection of disconnection or incorrect connection using a circuit for current monitoring The following description relates to an exemplary circuit of the present disclosure comprising at least one circuit for monitoring current (e.g., injection current), the at least one circuit being operable to detect a disconnection or fault in a signal communication path, which can occur, for example, due to a pin defect. Detection of this disconnection or fault can take the form of detecting or identifying an open circuit. For example, this open circuit can occur when the connection between a pin, or between a cell monitoring device (CMD) and a sensor external to the CMD is broken, and a voltage is applied to the pin in this open circuit state. Detection of the disconnection or fault can take the form of detecting or identifying, for example, a short circuit between two adjacent pins of the CMD. Such a circuit for monitoring current can be configured to perform either an open circuit detection (OCD) or a short circuit detection (SCD) process as described below. For example, any one or more of circuits 118 of FIG. 6, circuits 118a, 118b of FIG. 7, and circuit 418 of FIG. 8 can form part of an open circuit detection circuit (OCD).

[0044] Conventional systems Conventional systems for detecting an open circuit or short circuit operate by varying the current and observing the change in voltage. Such systems take longer to determine an open circuit or short circuit than systems that use a circuit for monitoring current as described herein (e.g., shown in FIGS. 6-8). For example, such time can be approximately 10 times different under similar conditions where all other variables are equal. The exemplary embodiments related to OCD and / or SCD described herein provide at least a significant time savings when detecting an open circuit or short circuit that may be an indication of the presence of a break or misconnection.

[0045] Open Circuit Detection (OCD) According to Some Exemplary Embodiments In some examples, an open circuit in the connection between a sensor connected to pin 116 (such as sensors 31, 32, 33, etc. of the exemplary battery management system of FIGS. 1-5) and analog multiplexer 35 can be identified by observing the current that needs to be injected into the connection to force or drive the connection to a defined voltage. In normal operation, due to the impedance of sensors 31, 32, 33 being too low, there is not enough current and the connection voltage cannot be forced to change significantly. For example, if an open circuit occurs due to a pin defect, the connection shows a high impedance and the connection voltage can be moved or changed by injecting current into that connection.

[0046] Thus, such a circuit for monitoring the injected current can be used at the electrical connection pins of sensors 31, 32, 33, which need to have normal impedance values within the range of operating impedance, and identify a break or error in the connection by observing how the voltage on the electrical connection pin behaves in a specific way in response to an abnormal injected current or in response to an expected response to a misconnection, thereby detecting a break or error in the connection.

[0047] In some examples, when such a disconnection or misconnection is detected, this detection is reported to the device or controller using the same process or method as the method of communicating measurement data from sensors 31, 32, 33, for example, to the cell monitoring devices 10, 10-1...10-N, diagnostic source block 50, communication controller 15, and / or battery management unit 20 of the battery management system as described herein or shown in FIGS. 1-5. In some examples, data representing the output signal from a circuit for monitoring current is reported to the device or controller using the same process or method as the method of communicating measurement data from sensors 31, 32, 33, for example, to the cell monitoring devices 10, 10-1...10-N, diagnostic source block 50, communication controller 15, and / or battery management unit 20 of the battery management system as described herein or shown in FIGS. 1-5, such that the device or controller can process the received data to determine whether a disconnection or misconnection has been detected. According to some examples, it is understood that an application specific integrated circuit (ASIC) is implemented in the circuit for monitoring current.

[0048] FIGS. 6-8, and the schematic circuits shown in those figures, provide examples of circuits for monitoring such operable current. In some examples, such a circuit for monitoring the injected current can be part of one or more components (e.g., components of a connected status sensor, or a circuit operable to obtain measurements of one or more pins of a battery system), which components are arranged to have one or more electrical connections with another component. For example, as another component, any component of the exemplary battery management system of FIGS. 1-5 such as exemplary cell monitoring devices 10-1, 10-2,..., 10-N, communication controller 15, battery management unit 20, one or more sensors 31, 32, 33, ADCs 37, 37-1, 37-2, and / or multiplexers 35, 51 can be mentioned.

[0049] Figure 6 shows at least one circuit 118 for monitoring an injection current according to some examples described herein. In some examples, circuit 118 can be a component of circuits or cell monitoring devices 10, 10-1...10-N and can be operative to send, communicate, and / or report its output, such as open detection, fault detection, or measurements of a connected status sensor, to a controller (e.g., communication controller 15 or battery management unit 20) of a battery system (not shown).

[0050] Such a circuit comprising at least one circuit for monitoring the current described herein can be operative to obtain measurements (e.g., voltage measurements) of one or more pins 116 of a battery system. In some examples, sensors 31, 32, 33 (not shown) of the exemplary battery management system of FIGS. 1-5 can comprise one or more internal circuits for obtaining voltage measurements of one or more pins 116 and / or can include connections to external circuits and measurement points of a battery system (not shown) via device pins 116. In some examples, sensors 31, 32, 33 (not shown) are external sensors electrically connectable to one or more circuits for obtaining voltage measurements of one or more pins 116 via one or more pins 116. One or more pins 116 can be connectable to one or more circuits 118, 118a, 118b, 418 via a multiplexer 35 as in the examples shown in FIGS. 6-8, such that one or more electrical connections with one or more selected pins can be established by one or more circuits 118, 118a, 118b, 418.

[0051] One or more circuits shown in FIGS. 6 and 7 include at least one circuit 118, 118a, 118b for monitoring current and may include at least one other circuit 117 for amplifying dispersion. The circuit itself may include at least one differential amplifier 112 and one voltage reference 219 (or a reference voltage source for providing a reference voltage Vref) electrically connected to a first input 120 of the differential amplifier 112, and the differential amplifier 112 also includes a second input 121 and an output 122.

[0052] At least one circuit 118, 118a, 118b (e.g., a circuit for OCD) may also include at least one transconductance means 213a, 213b, and the transconductance means 213a, 213b may include at least one output 227a electrically connected to a second input 121 of the differential amplifier 112 and one input 228a, 228b electrically connected to the output 122 of the differential amplifier 112. The transconductance means 213a, 213b may be arranged in the circuit 118 to monitor the injection current, thereby converting the voltage of the transconductance means 228a, 228b into the current of the outputs 227a, 227b.

[0053] The second input 121 of the differential amplifier 112 and at least one output 227a of at least one transconductance means may also be configured to be electrically connected to one or more pins 116 of the battery system, for example, via a multiplexer 35. One or more pins 116 may provide an electrical connection to a module or cell of the battery system and / or may provide an electrical connection to an external measurement point (not shown), for example, to one or more sensors 31, 32, 33. The analog multiplexer 35 may be operable to select at least one of the one or more pins 116 and electrically connect only the selected pin to at least one output 227a of at least one transconductance means.

[0054] At least one circuit 118 for monitoring current may also comprise at least one current source 214 electrically connected to at least one output 227b of at least one of the at least one transconductance means. Such a current source 214 serves to provide a reference current.

[0055] At least one circuit 118 may also include an output 125 electrically connected to at least one output 227b of at least one of the at least one transconductance means. At least one circuit 118 for monitoring current may then be operable to detect disconnection or absence of an electrical connection of a sensor connected to one or more pins 116 by monitoring the current required to cause a voltage variation at one pin 116.

[0056] FIG. 6 shows a specific example in which at least one transconductance means comprises at least one pair of transistors 213a, 213b. In the example shown in FIG. 6, the at least one pair of transistors 213a, 213b includes a pair of field effect transistors, such as a first field effect transistor 213a and a second field effect transistor 213b, each having a source terminal 226a, 226b, a drain terminal 227a, 227b (functioning as an output of the transconductance means), and a gate terminal 228a, 228b (functioning as an input of the transconductance means). The first field effect transistor 213a and the second field effect transistor 213b are arranged in parallel such that their respective gate terminals 228a, 228b are electrically connected to each other and their respective source terminals 226a, 226b are electrically connected to each other.

[0057] The output 122 of the differential amplifier 112 is electrically connected to the gate terminals 228a, 228b of the pair of field effect transistors 213a, 213b. The drain terminal 227a of the first field effect transistor 213a is electrically connected to the second input 121 of the differential amplifier 112.

[0058] In the example shown in FIG. 6, at least one current source 214 is electrically connected to the drain terminal 227b of the second field effect transistor 213b. In the examples shown in FIGS. 6 and 7, at least one current source 214, 214a, 214b comprises a variable current source. In other examples, it will be understood that a constant current source or any other type of current source may be used instead, provided that a reference current can be provided to a field effect transistor of a transconductance means such as, for example, the second field effect transistor 213b.

[0059] Circuits 118, 118a, 118b for monitoring current further comprise at least one output amplifier 229 disposed at the outputs 125, 125a, 125b of the circuits 118, 118a, 118b for monitoring current, and the at least one output amplifier 229 may be implemented as at least one inverter 229.

[0060] In the examples shown in FIGS. 6 and 7, the voltage reference Vref is provided by two resistors 219 arranged in series. Such two resistors 219 may function as a voltage divider that sets the reference voltage as a defined ratio of the supply voltage.

[0061] In some examples, the pair of field effect transistors 213a, 213b may include at least one pair of p-channel field effect transistors or n-channel field effect transistors, also known as PMOS (p-channel metal oxide semiconductor) or NMOS (n-type metal oxide semiconductor) transistors, respectively.

[0062] An exemplary operation of circuit 118 when it functions as part of the OCD circuit is as follows. In FIG. 6, the transconductance means are shown as NMOS transistors 213a, 213b. The reference voltage Vref is set to a relatively low value compared to the normal operating range, for example, about 10% of the power supply voltage. The multiplexer 35 connects the drain terminal 227a to an external sensor (e.g., sensors 31, 32, 33) via pin 116. Next, the amplifier 112 attempts to force or control the gate terminals 228a, 228b such that the voltage at the second input 121 is the same as Vref, thereby effectively trying to pull down the voltage of pin 116 (a "pull-down test"). If the connection is operating correctly, for example, if the signal is transmitted through the connection without interruption or disconnection, even if so, the voltage of pin 116 does not change significantly (in other words, only small fluctuations in voltage can be observed during monitoring). Thus, the current in the NMOS transistors 213a, 213b reaches its maximum. The maximum current is configured to be higher than the reference current from the current source 214. This means that the input to one or more amplifiers 229 (functioning as an inverter chain) is pulled low, and thus the output signal at output 125 is set low. This indicates that there is no fault or disconnection in the electrical connection from the open circuit.

[0063] However, if there is an open circuit at pin 116, there is little injection current required to move the voltage of pin 116. The current in the NMOS transistor 213b becomes low because not much current is required in the NMOS transistor 213a to move the voltage at the input 121 of the amplifier 112, and the input to one or more amplifiers 229 (functioning as an inverter chain) is pulled high by a larger reference current from the current source 214. The output signal at output 125 is set high, indicating a fault or disconnection in the open circuit.

[0064] However, when the voltage of pin 116 is typically very small, e.g., near or at zero volts, attempting to pull the voltage lower as described above will fail because the result of the pull-down test cannot be a reliable indication for detecting an open circuit. Thus, an open circuit cannot be distinguished from a properly operating connection. To test for an open circuit in such a scenario, instead, it is necessary to pull the voltage of pin 116 high ("pull-up test"). This is similar to circuit 118, but requires a second circuit that is differently configured to supply current instead of sinking current. An example of such a second circuit is circuit 118b shown in FIG. 7, which is described below.

[0065] FIG. 7 shows a further example, in which one or more circuits operable to obtain measurement values of one or more pins include a first circuit 118a for monitoring current and a second circuit 118b for monitoring current. The first circuit 118a is identical to the circuit 118 of FIG. 6. For example, the reference voltage Vref of the first circuit 118a can be set to a relatively low value, e.g., about 10% of the power supply voltage, compared to the normal operating range. The second circuit 118b operates similarly, but there are the following differences. As the difference, it means that instead of the pull-down test performed by the first circuit 118a, the second circuit 118b performs a pull-up test. The reference voltage Vref of the second circuit 118b can be set to a higher value, e.g., about 90% of the power supply voltage. The transconductance means is implemented as a PMOS transistor, and the PMOS transistor supplies current to pin 116 and the input to the amplifier. The connection between the current sink 214b (which can be equivalent to the current source 214a of the first circuit 118a, but here behaves as a sink instead of a source) and the PMOS transistor is forced low in the presence of an open circuit. There is only one amplifier that functions as an inverter, and as a result, the signal at output 125b goes high for an open circuit.

[0066] One or more of the circuits of FIG. 7 cannot perform both a pull-up test and a pull-down test simultaneously on the same pin. Thus, at any given time, only one of the first circuit 118a and the second circuit 118b is electrically connected to the same pin by the multiplexer 35. When performing a pull-up test and a pull-down test on the same pin, FIG. 7 shows the outputs 125a and 125b both directly connected to the logic AND element 126 via separate inputs, but note that the logic AND element 126 receives signals from the outputs 125a and 125b at different times, and thus, the AND operation is performed on inputs that introduce a time delay between them. Next, this may require latching the inputs to the logic AND element 126, or the AND operation may be performed by a device with memory, such as a processor.

[0067] To fully detect an open circuit from the voltage of a pin, it is necessary to perform both a pull-down test and a pull-up test on that pin. Typically, these two tests are performed when the operation of one or more circuits does not interfere with other functions of the battery system, for example, obtaining sensor measurements from one or more external sensors (sensors 31, 32, 33, etc.) connected to pin 116. In some examples, one or more of the controllers described herein may schedule or synchronize such pull-down tests and pull-up tests, such that the tests are not performed when the pin 116 is being used to convey signals or data for other functions of the battery system.

[0068] It is understood that an open circuit can be detected using other methods of operating one or more of the circuits of FIG. 7. For example, multiplexer 35 can be controlled such that at a particular instant, first circuit 118a performs its pull-down test at a first pin and second circuit 118b performs its pull-up test at a second pin different from the first pin, the output signals at outputs 125a, 125b are stored in memory, and at another instant, first circuit 118a performs its pull-down test at the second pin and second circuit 118b performs its pull-up test at the first pin, and the output signals at outputs 125a, 125b and the output signals stored from past instants are used as inputs to logic AND element 126 to detect an open circuit. It is understood that still other modified methods of detecting an open circuit can be implemented using one or more of the circuits of FIG. 7.

[0069] In the example shown in FIG. 7, first circuit 118a for measuring current and second circuit 118b for measuring current include a pair of n-type field effect transistors and a pair of p-channel field effect transistors. However, it is understood that other types of transconductance means can be used in first circuit 118a and second circuit 118b depending on the operations (e.g., pull-up test or pull-down test) that circuits 118a, 118b are designed to perform.

[0070] FIG. 8 shows an example of one or more circuits 418 different from the example provided in FIG. 7. The differences include that a first circuit for monitoring a current (for pulling the voltage of pin 116 high) and a second circuit for monitoring a current (for pulling the voltage of pin 116 low) share the same circuit 417 to amplify the dispersion. In this example, the first variable current source 214a is electrically connected to the drain terminal of the second field effect transistor 213b, and the second variable current source 214b is electrically connected to the drain terminal of the fourth field effect transistor 413b. The switches 417a, 417b, 417c, 417d are configured to operate one or more circuits 418 to perform either pull-up or pull-down. In the exemplary circuit for monitoring the current shown in FIG. 8, the drain terminal of the third field effect transistor 413a is electrically connected to the second input 121 of the differential amplifier 112. The output 122 of the differential amplifier 112 is electrically connected to the gate terminals of the third field effect transistor 413a and the fourth field effect transistor 413b when the switch 417c is closed. The output 122 of the differential amplifier 112 is electrically connected to the gate terminals of the first field effect transistor 213a and the second field effect transistor 213b when the switch 417b is closed. Thus, when the first switch 417a and the second switch 417b are closed, one or more circuits 418 pull down the voltage of pin 116. When the third switch 417c and the fourth switch 417d are closed, one or more circuits 418 pull up the voltage of pin 116. In some examples, a controller may be provided to control the opening and closing of the switches 417a, 417b, 417c, 417d to set one or more circuits 418 to either pull-up or pull-down.

[0071] Short Circuit Detection (SCD) According to Some Exemplary Embodiments In some examples, the open - circuit detection process (e.g., pull - up test or pull - down test) as described above is performed on a first pin, and at the same time, the voltage is measured at a second pin different from the first pin. Since the open - circuit detection process is performed on the first pin, by comparing the measurements at the second pin, the presence of a short - circuit between the first pin and the second pin can be determined. As the voltage of the first pin becomes either pulled - up or pulled - down, if the measured voltage value at the second pin also changes, this indicates that there may be a short - circuit between these pins.

[0072] Alternative examples of transconductance means The transconductance means of the circuits in FIGS. 6 - 8 includes at least one transistor. In some examples, such at least one transistor includes at least one field - effect transistor and / or at least one bipolar transistor. Such at least one field - effect transistor may include at least one n - type transistor and / or at least one p - type transistor.

[0073] Influence of impedance on a circuit for monitoring current When the exemplary circuit for monitoring current described above is connected to a high impedance (e.g., a pin of a pressure sensor), the open - circuit detection function of the circuit may be less useful than the short - circuit detection function. Alternatively, when such a circuit for monitoring current is electrically connected to a low impedance (such as a current shunt or a pin of a cell voltage), the short - circuit detection function of the circuit may be less useful than the open - circuit detection function of the circuit.

[0074] Methods for enabling detection of open - circuits or short - circuits according to some exemplary embodiments In some examples of a method for enabling detection of an open circuit or a short circuit, at least one circuit for monitoring current in components of the battery system described herein is provided, the circuit for monitoring current is operable to provide an output signal for detecting an open circuit or a short circuit, and then this can be used to detect an interruption or failure in a signal communication path of the battery system. Such an interruption or failure can occur, for example, due to a pin defect. For example, the at least one circuit can be any of circuits 118, 118a, 118b, 418 of FIGS. 6-8.

[0075] The method includes providing a first element to establish an electrical connection between one voltage reference and a first input of a differential amplifier of at least one other circuit for amplifying the variance, the differential amplifier further including a second input and an output; providing a second element to establish an electrical connection between the second input of the differential amplifier and at least one output of at least one transconductance means; providing a third element to establish an electrical connection between at least one input of at least one transconductance means and the output of the differential amplifier, wherein the second input of the differential amplifier and at least one output of at least one transconductance means are configured to be electrically connected to one or more pins of a battery system; providing a fourth element to establish an electrical connection between at least one current source and at least one output of at least one transconductance means; and providing a fifth element to establish an electrical connection between an output of at least one circuit for monitoring current and at least one output of at least one transconductance means. In some examples, the first element, the second element, the third element, the fourth element, and the fifth element are provided on a semiconductor material and / or within an integrated circuit (IC) chip. In some examples, at least a portion of the first element, the second element, the third element, the fourth element, and the fifth element are provided on a printed circuit board (PCB) or a printed wiring board (PWB). Preferably, the first element, the second element, the third element, the fourth element, and the fifth element comprise conductive components with exposed surfaces for establishing electrical connections.

[0076] In some examples, the method may further include providing at least one circuit for monitoring the current of the monitoring device described herein, the monitoring device being operable to report sensor measurements of the battery system, the monitoring device comprising one or more circuits operable to obtain measurements of one or more pins of the battery system, and the one or more circuits comprising at least one circuit for monitoring current.

[0077] In some other examples, the method may further include establishing an electrical connection using a first element, a second element, a third element, a fourth element, and a fifth element (e.g., by physically connecting by soldering or by controlling one or more switches to establish an electrical contact), whereby at least one circuit for monitoring current is operable to generate an output signal for detecting an open circuit or a short circuit, and then using the output signal to monitor the current required to cause a voltage fluctuation of one or more pins, so as to be operable to detect a break or absence of an electrical connection of a sensor connected to one or more pins of the battery system. For example, the output signal may indicate a break or absence of an electrical connection of a sensor connected to one or more pins.

[0078] Power-on reset Circuits for application-specific integrated circuits (ASICs) are typically designed using a library of standard components. For example, rather than an ASIC designer having to design a flip-flop circuit, the ASIC manufacturer provides a pre-verified design of the flip-flop for all designers to use. There are many such components, and they are combined into a standard component library. Next, the selection of these standard components is combined by the ASIC designer into the core circuit to perform any function that the ASIC needs to perform, such as acting as a processor. For example, the core circuit can be designed or configured to perform some or all of the functions or functionality described herein as being performed by a circuit, device, or processor. In some examples, one or more components of the systems or devices described herein are implemented using an ASIC.

[0079] The standard library is specified to operate within a clearly defined voltage range. For example, the library can be defined to operate within a voltage range of 1.10V to 1.30V. Within this range, it is guaranteed that the library components will operate as defined. Outside of this range, operation is not guaranteed. For example, if the voltage is too low, the operation of the component may be too slow, or an exemplary flip-flop may not hold its state. If the voltage is too high, the switching of the component may be too fast, resulting in timing problems, or the aging of the component may be too fast.

[0080] The circuit needs to operate properly, or at least in a predictable manner, especially in safety-critical systems such as systems that require functional safety. It is useful to always put the circuit in a known state rather than in an unknown state and thus potentially an unsafe state. When the core circuit is operating correctly, the circuit power supply needs to supply the supply voltage within the specified range. To provide certainty or at least predictability, if the voltage is outside the specified range, the core circuit can be forced into a known "reset" state, in which it is known not to operate but is safe.

[0081] The most common situation in which this occurs is when the core circuit is powered on. The circuit starts from zero supply voltage. As the voltage increases, it is initially quite low, and the circuit needs to stay in the reset state. Eventually, the voltage comes within the specified range, and the circuit may be able to release the reset state and start normal operation.

[0082] The function of forcing the reset state is performed by a reset circuit. The reset circuit, often called a power-on reset or POR circuit, sends a signal to the core circuit. When asserted, this signal causes the core circuit to enter the reset state. When not asserted, the core circuit can release the reset state in a defined manner. A typical reset circuit measures the supply voltage and when it reaches a sufficiently high level, the reset signal is not asserted.

[0083] Normally, the power is applied very quickly, for example usually in a time much shorter than 1 second. The ASIC may have specifications regarding the amount of time required for the power supply voltage to rise quickly, for example, it may specify that the supply voltage needs to reach the specified range in less than 1 ms.

[0084] Some circuits, such as clock generators or oscillators, etc., start operating as soon as the voltage becomes sufficiently high. The clock generator also needs to be operational before the core circuit can operate correctly. The clock generator requires a certain amount of time, for example 10 ms, to stabilize. There may be other circuits that also take a similar amount of time to become fully operational and stable.

[0085] For this reason, the POR circuit typically introduces a time delay before the reset signal is deasserted, which is longer than the time it takes for the slowest circuit to stabilize. In the above case, for example, this time delay can be set to 50 ms, giving sufficient time for the clock generator to stabilize into proper operation. Thus, the core circuit can exit the reset state only when the supply voltage is within the specified range and remains within that range for a (predetermined) period longer than a certain duration.

[0086] In some examples, an ASIC type can be implemented in the cell monitoring device (CMD) described herein. Such a CMD includes a core circuit built from standard library components and performs a safety function that requires the core circuit to always be in a known state. The CMD attached to the battery cell is powered by the battery cell. If the CMD is attached to the cell when its voltage is lower than the minimum specified voltage, the core circuit of the CMD is held in the reset state and remains in that state until the cell voltage rises high enough to provide a supply voltage within the specified range for the CMD power supply.

[0087] Unlike more typical applications where the power is switched on, in the case of a CMD attached to a cell, the power is always connected and remains on almost permanently until the cell runs out of power, so the supply power may change very slowly. The cell voltage usually rises only when the cell is being charged.

[0088] As one special case, consider when the CMD is attached to the cell during manufacturing. First, the cell is at zero volts. Next, the cell undergoes a "formation charge" and is charged at a certain rate that enables the necessary electrochemical process to occur within the cell. The formation charge can take several hours or even days.

[0089] Therefore, instead of increasing in 1 ms or even 1 s increments, the supply voltage increases over several hours. This very slow rise causes problems with normal POR circuits because the circuit cannot implement a time delay (of any practical length) to ensure that all circuits are within the specified range and can become operational before the POR time delay expires.

[0090] Accordingly, some of the exemplary embodiments presented herein are directed to an adjustment system that provides a power-on reset to a CMD core circuit (e.g., the core circuits of the cell monitoring devices 10, 10-1...10-N described herein) in a defined state in an efficient manner, thereby eliminating the need for a time delay at POR. FIG. 9 shows an exemplary electronic adjustment system for adjusting the voltage supplied to the core logic of a CMD 305 within a battery system during a power-on reset (POR). The system includes a voltage adjustment unit 301, a bandgap reference unit (BG), and a power-on reset comparator 303.

[0091] During operation, the CMD can function when the voltage level supplied to the CMD core circuit 305 is in the range of, for example, 1.1 to 1.3 volts. The power supply 307 can be configured to supply a voltage (VDD) to the adjustment system during a power-on reset within the range of 0 to 5 volts. The electronic control system generates an adjustment voltage (D VDD ) based on a bandgap voltage (VBG) reference provided by the bandgap reference unit (BG) and enables the core circuit of the CMD 305 when the adjustment voltage reaches a threshold value, providing functionality in a safe manner (e.g., 1.1 v to 1.3 v).

[0092] First, the voltage (VDD) supplied by the power supply 307 activates the bandgap reference unit (BG). The bandgap reference unit (BG) is configured to enable the voltage adjustment unit 301 by providing an activation signal (VBG_ok) to the voltage adjustment unit 301. The bandgap reference unit (BG) is further configured to supply a stable bandgap voltage reference (VBG) to the voltage adjustment unit 301 and the power-on reset comparator 303. When enabled by the bandgap reference unit (BG), the voltage adjustment unit 301 is configured to generate an adjusted voltage (D VDD ) based on a comparison of the bandgap reference voltage (VBG). The voltage adjustment unit 301 is further configured to provide the adjusted voltage (D VDD ) to the power-on reset comparator 303. The power-on reset comparator enables CMD305 to receive the adjusted voltage (D VDD ) via the power supply line 304.

[0093] In some examples, the bandgap reference unit (BG) is a temperature-independent voltage reference circuit that generates a fixed voltage and a constant voltage regardless of variations caused by the power supply, temperature changes, or circuit load. An exemplary configuration of the bandgap adjustment unit (BG) is provided in FIG. 10. The bandgap reference unit (BG) includes a first comparator 401 and a second comparator 403, and the second comparator 403 is configured to enable the operation of the first comparator 401.

[0094] The supply voltage (VDD) is provided as an input to the second comparator 403. The second comparator 403 is further configured to receive a base-emitter voltage (VBE) reference as an input. The base-emitter voltage (VBE) reference voltage generator can be used in the form of a bipolar device that is used as a reference for the second comparator 403. According to a part of the exemplary embodiment, before being provided to the second comparator 403, the supply voltage (VDD) can be input to a divided reference to ensure that the magnitude of the voltage evaluated by the second comparator 403 is within the operating range of the second comparator 403.

[0095] The second comparator 403 can be used to detect the timing when the supply voltage (VDD) is greater than the VBE reference voltage. When the supply voltage reaches a level greater than the VBE reference voltage, the second comparator 403 transmits an enable signal (EN) to the first comparator 401, thereby enabling the operation of the first comparator 401. When the supply voltage reaches a level greater than the VBE reference voltage, a true logic signal is also transmitted to the AND logic element 405.

[0096] The first comparator 401 is configured to receive the supply voltage (VDD) and the generated bandgap voltage reference (VBG) as inputs. It should be recognized that the divided supply voltage (VDD) can also be input to the first comparator 401 to ensure that the magnitude of the voltage evaluated by the second comparator 403 is within the operating range of the second comparator 403. When receiving the enable signal (EN) from the second comparator 403, the first comparator 401 can compare the supply voltage (VDD) with the bandgap voltage (VBG) reference. When the supply voltage (VDD) reaches a level exceeding the bandgap voltage (VBG) reference, the first comparator 401 transmits a true logic signal to the logical AND element 405.

[0097] Under typical process and temperature conditions, a first comparator 401 with a bandgap voltage (VBG) reference and a supply voltage (VDD) as inputs may be sufficient to indicate the timing at which the bandgap approaches the steady-state output voltage. For example, assuming a value below 1V for minimum VDD operation, when the bandgap voltage (VBG) reference exceeds 1.0V, the enable signal (VBG_ok) flags, thereby indicating that the supply voltage (VDD) is guaranteed to exceed 1.0V.

[0098] As a problem with this solution, when the supply voltage (VDD) rises in non-ideal conditions (high / low temperature, slow / fast silicon), the bandgap voltage (VBG) reference can exceed this threshold, and then, as the supply voltage (VDD) rises, it may return to 0V. Under these conditions, the enable signal (VBG_ok) flags from high to low (potentially) for multiple VDD voltages, which can cause startup problems in subsequent circuits.

[0099] To address such problems, a second comparator 403 is used between the supply voltage (VDD) and the base-emitter voltage (VBE) reference. This circuit part is intended to indicate the timing at which the supply voltage (VDD) exceeds the minimum voltage. This voltage threshold is chosen to be the minimum value of the supply voltage (VDD) that guarantees that the bandgap voltage (VBG) reference does not return to 0V. This can be found from process-voltage-temperature (PVT) simulations. In other words, to raise the supply voltage (VDD), this circuit part indicates the timing at which the bandgap stabilizes at power-on. The base-emitter voltage (VBE) reference can be configured to be equal to the determined minimum threshold voltage, and it should be recognized that this guarantees that the bandgap voltage (VBG) does not return to 0V.

[0100] When this supply voltage (VDD) threshold voltage (e.g., base-emitter voltage (VBE) reference) is reached, the first comparator 401 that subsequently detects whether a (stable) bandgap has actually started up is enabled using the second comparator 403. According to some exemplary embodiments, it is useful to use the second comparator 403 in addition to the first comparator 401. The reason is, for example, that the first comparator 401 can fail suddenly to raise the high-speed VDD, resulting in an incorrect VBG_ok signal. To stop this behavior, a small delay can be added between the power-on of the first comparator 401 and the time when VBG_ok becomes active. The amount of delay required can be characterized by simulation of the entire PVT of the high-speed VDD rise. Such delays can be on the order of nanoseconds.

[0101] The logic AND element 405 receives two true logic signals as inputs when the supply voltage is detected by the first comparator 401 and the second comparator 403 to be greater than the bandgap voltage (VBG) reference and the base-emitter voltage (VBE) reference, respectively. When both inputs to the logic AND element 405 are true signals, the element 405 is configured to send an enabling signal (VBG_ok) to the voltage regulator 301, thereby enabling the operation of the regulator 301.

[0102] The voltage regulator is configured to generate a fixed output voltage of a preset magnitude that remains constant regardless of changes in its input voltage or load conditions. The voltage regulator 301 uses the bandgap voltage (VBG) reference as a baseline or comparison to generate an adjusted voltage (D VDD ). According to some exemplary embodiments, the voltage regulation unit 301 can be a low dropout (LDO) regulator or any other voltage regulator capable of generating an output voltage that is adjusted to a preset magnitude.

[0103] Adjusted voltage (D VDD) is provided to the supply rail 304 used by the core circuit of CMD305 and is further supplied to the POR comparator 303. When the value of the regulated voltage (D VDD ) is greater than the value of the bandgap voltage (VBG) reference, the POR comparator 303 provides a further enabling signal (POR) to the core circuit of CMD305. The enabling signal POR warns the core circuit of CMD305 that the rising supply voltage (VDD) has reached the level of operational safety. Thereafter, the core circuit of CMD305 uses the regulated voltage (D VDD ) from the supply rail 304 as a power supply, for example, for its operation.

[0104] The description of the exemplary embodiments provided herein is presented for purposes of illustration. This description is not intended to be exhaustive or to limit the exemplary embodiments to the precise form disclosed, and modifications and variations are possible in light of the above teachings or may be acquired from practice of various alternatives of the provided embodiments. The principles and properties of various exemplary embodiments are described and, by their practical application, enable one skilled in the art to utilize the exemplary embodiments in various manners and with various modifications as are suited to the particular use contemplated. Examples have been selected and described herein to enable the features of the embodiments described herein to be combined in all possible combinations of methods, apparatus, modules, systems, and computer program products. It should be recognized that the exemplary embodiments presented herein may be practiced in any arbitrary combination with each other.

[0105] Note that the word "comprising" does not necessarily exclude the existence of other elements or steps besides those listed, and the words "a" or "an" preceding an element do not exclude the existence of a plurality of such elements. Further, note that any reference signs do not limit the scope of the claims, that exemplary embodiments can be implemented at least in part by both hardware and software, and that some "means", "units", or "devices" can be represented by the same item of hardware.

[0106] The various exemplary embodiments described herein are described in the general context of method steps or processes, which, in one aspect, can be implemented by a computer program product embodied on a computer-readable medium that includes computer-executable instructions such as program code executed by a computer in a network environment. The computer-readable medium can include removable storage devices and non-removable storage devices, which include, but are not limited to, read-only memory (ROM), random access memory (RAM), compact disc (CD), digital versatile disc (DVD), flash memory, etc. Generally, program modules can include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The computer-executable instructions, associated data structures, and program modules represent examples of program code for executing the steps of the methods disclosed herein. A particular sequence of such executable instructions or associated data structures represents an example of corresponding acts for implementing the functions described in such steps or processes.

[0107] It should be understood that the processors 39, 52 described herein may be implemented using at least one processing unit (or at least one core) and one or more internal registers. It should also be understood that the processors 39, 52 described herein may be implemented using circuitry configured to perform the operations described herein.

[0108] Various embodiments are described herein with reference to systems, methods, processes, devices, or computer-readable media. It is not intended that one disclosure be all disclosures. For example, the disclosure of a computer-readable media described herein also constitutes the disclosure of a method implemented using that computer-readable media, as well as the disclosure of a system and device for implementing those methods using, for example, at least one processor or circuitry configured to implement those methods. The form of this disclosure is for ease of explanation only, and it should be understood that one or more aspects of one embodiment herein may be combined with one or more aspects of other embodiments herein within the scope intended by this disclosure.

[0109] In the drawings and the specification, exemplary embodiments are disclosed. However, many changes and modifications can be made to these embodiments. Therefore, although specific terms are employed, they are used in a general and descriptive sense only and not for purposes of limitation, and the scope of the plurality of embodiments is defined by the following claims.

Claims

1. A monitoring device capable of reporting sensor readings of a battery system, The system comprises one or more circuits that are capable of taking measurements of one or more pins of a battery system, and the one or more circuits are It comprises at least one circuit for monitoring current, and the at least one circuit is A circuit for amplifying dispersion, comprising at least one differential amplifier and one voltage reference electrically connected to a first input of the differential amplifier, wherein the differential amplifier further comprises a second input and output, A transconductance means comprising at least one output electrically connected to the second input of the differential amplifier, and at least one input electrically connected to the output of the differential amplifier, The second input of the differential amplifier and at least one output of the at least one transconductance means are electrically connected to one or more pins of the battery system, At least one current source electrically connected to at least one output of at least one of the at least one transconductance means, The output comprises at least one output of the at least one transconductance means and an output electrically connected thereto, A monitoring device wherein the at least one circuit for monitoring current is operable to detect an interruption or absence of electrical connection of a sensor connected to one or more pins by monitoring the current required to cause a voltage fluctuation at one or more pins.

2. The monitoring device according to claim 1, wherein the at least one transconductance means comprises at least one transistor.

3. The monitoring device according to claim 2, wherein the at least one transistor includes at least one pair of p-channel field-effect transistors or n-type field-effect transistors.

4. The monitoring device according to claim 3, wherein the at least one pair of p-channel field-effect transistors or n-type field-effect transistors comprises a first field-effect transistor and a second field-effect transistor, each having a source terminal, a drain terminal, and a gate terminal, and the first field-effect transistor and the second field-effect transistor are arranged in parallel such that their respective gate terminals are electrically connected to each other and their respective source terminals are electrically connected to each other.

5. The monitoring device according to claim 4, wherein the output of the differential amplifier is electrically connected to the gate terminal of the pair of field-effect transistors.

6. The monitoring device according to claim 5, wherein the drain terminal of the first field-effect transistor is electrically connected to the second input of the differential amplifier.

7. The monitoring device according to claim 6, wherein the at least one current source is electrically connected to the drain terminal of the second field-effect transistor.

8. The monitoring device according to claim 1, wherein the at least one current source includes a variable current source.

9. The monitoring device according to claim 1, wherein the at least one circuit for monitoring current comprises a first circuit for monitoring current and a second circuit for monitoring current, the first circuit for monitoring current comprises a p-channel field-effect transistor and the second circuit for measuring current comprises an n-type field-effect transistor.

10. The monitoring device according to claim 1, wherein the at least one circuit for monitoring current further comprises at least one output amplifier located at the output of the circuit.

11. The monitoring device according to claim 1, wherein the at least one circuit for monitoring current is electrically connected to one or more pins of the battery system via a multiplexer.

12. The monitoring device according to claim 1, wherein the current source provides a reference current.

13. The monitoring device according to claim 1, wherein the one or more circuits operable to acquire measurements of one or more pins of a battery system comprises at least a first circuit operable to detect an open circuit at a first pin and a second circuit operable to identify a voltage fluctuation at a second pin, and the monitoring device is operable to detect a short circuit when the voltage fluctuation at the second pin is identified.

14. A tuning system for providing a voltage adjusted during power-on reset to a cell monitoring device (CMD) core circuit (305) of a battery system, wherein the battery system comprises at least one pack, each pack comprising a plurality of battery cells, each battery cell comprising a plurality of battery cells, each monitored via a CMD, and the tuning system, A bandgap reference unit (BG) is configured to generate a bandgap reference voltage (VBG) based on a supply voltage (VDD), and further configured to generate a first enable signal (VBG_ok) when the bandgap reference voltage (VBG) is stable and at a level appropriate for the operational safety of the CMD core circuit (305), A voltage regulator unit (301) is configured to receive the bandgap reference voltage (VBG) and the first activation signal (VBG_ok) from the bandgap reference unit (BG), wherein upon receiving the first activation signal, the voltage regulator unit (301) further supplies power to the CMD core circuit (305) by adjusting the voltage (D ＶＤＤ ) is configured to generate the adjusted voltage (D ＶＤＤ ) is generated based on a comparison of the bandgap reference voltage (VBG), and comprises a voltage regulator unit (301), The bandgap reference voltage (VBG) is received from the bandgap reference unit (BG), and the adjusted voltage (D ＶＤＤ A power-on reset comparator (303) configured to receive the adjusted voltage (D) from the voltage regulator unit (301), wherein the power-on reset comparator (303) further comprises the adjusted voltage (D) ＶＤＤ When the value of ) becomes greater than the value of the bandgap reference voltage (VBG), a second activation signal (POR) is provided to the CMD core circuit 305, and the second activation signal (POR) is provided to the CMD core circuit when the adjusted voltage (D ＶＤＤ A power-on reset comparator (303) enables access to the following: An adjustment system equipped with this system.

15. The aforementioned bandgap reference unit (BG) is A first comparator (401) configured to receive the supply voltage (VDD) and the generated bandgap reference voltage (VBG) as inputs, The system includes a second comparator (403) configured to receive the aforementioned supply voltage (VDD) and base-emitter voltage (VBE) references as inputs, The second comparator (403) is configured to enable the operation of the first comparator (401) and provide true logic to the logic AND element (405) when the second comparator detects that the supply voltage (VDD) is greater than the base-emitter voltage (VBE) reference. The first comparator (401), when enabled via the second comparator (403), is configured to transmit true logic to the logic AND element (405) when the first comparator detects that the supply voltage (VDD) is greater than the bandgap reference voltage (VBG). The adjustment system according to claim 14, wherein the logic AND element (405) is configured to provide the first enable signal (VBG_ok) to the voltage regulator unit (301) and the generated bandgap reference voltage (VBG) to the power-on reset comparator (303) when both inputs to the logic AND element are true.

16. A method in a tuning system for providing a voltage adjusted during power-on reset to a cell monitoring device (CMD) core circuit (305) of a battery system, wherein the battery system comprises at least one pack, each pack comprising a plurality of battery cells, each battery cell comprising a plurality of battery cells, each monitored via its respective CMD, and the method is A bandgap reference voltage (VBG) is generated based on the supply voltage (VDD) via a bandgap reference unit (BG), and further, when the bandgap reference voltage (VBG) stabilizes and reaches a level appropriate for the operational safety of the CMD core circuit (305), a first enable signal (VBG_ok) is generated. The bandgap reference voltage (VBG) and the first activation signal (VBG_ok) are received from the bandgap reference unit (BG) via the voltage regulator unit (301), Upon receiving the first activation signal, the voltage regulator unit (301) supplies power to the CMD core circuit (305) by adjusting the voltage (D ＶＤＤ ) to generate the adjusted voltage (D ＶＤＤ ) is generated based on the comparison of the bandgap reference voltage (VBG), and the generation is, The bandgap reference voltage (VBG) is received from the bandgap reference unit (BG) via the power-on reset comparator (303), and the adjusted voltage (D ＶＤＤ ) is received from the voltage regulator unit (301), Via the power-on reset comparator, when the value of the adjusted voltage (D ＶＤＤ ) becomes greater than the value of the bandgap reference voltage (VBG), a second activation signal (POR) is provided to the CMD core circuit (305), and the second activation signal (POR) enables the CMD core circuit to access the adjusted voltage (D ＶＤＤ ), the providing and Methods that include...

17. The first comparator (401) receives the supply voltage (VDD) and the generated bandgap reference voltage (VBG) as inputs, The second comparator (403) receives the supply voltage (VDD) and base-emitter voltage (VBE) references as inputs, When the second comparator detects that the supply voltage (VDD) is greater than the base-emitter voltage (VBE) reference, the operation of the first comparator (401) is enabled via the second comparator (403), providing true logic to the logic AND element (405). When enabled, if the first comparator detects that the supply voltage (VDD) is greater than the bandgap reference voltage (VBG), it transmits true logic to the logic AND element (405) via the second comparator (403). The logic AND element (405) provides the first enable signal (VBG_ok) to the voltage regulator unit (301) when both inputs to the logic AND element are true, and provides the generated bandgap reference voltage (VBG) to the power-on reset comparator (303), The method according to claim 16, further comprising:

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