OLED Anode Structure Containing Amorphous Transparent Conductive Oxide
By incorporating an amorphous protective barrier in the OLED anode structure, the challenges of etchant interaction with metal layers in OLED manufacturing are addressed, leading to improved device performance and efficiency through reduced light absorption.
Patent Information
- Application Number
- JP2024570727
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2022-05-31
- Filing Date
- 2023-05-25
- Publication Date
- 2025-06-12
AI Technical Summary
Existing OLED manufacturing processes face challenges with etchant selectivity, where etchants can interact with underlying layers, affecting device performance. Current solutions, such as increasing the thickness of metal oxide materials, lead to light absorption and reduced efficiency.
The implementation of an amorphous protective barrier between the metal layer and the second metal oxide material in the OLED anode structure. This barrier, composed of an amorphous material like indium zinc oxide, suppresses etchant interaction with the metal layer, allowing for thinner metal oxide layers that minimize light absorption.
The amorphous protective barrier effectively prevents etchant interaction with the metal layer, maintaining device performance while allowing for thinner metal oxide layers that enhance light transmittance and reduce light absorption, thus improving the overall efficiency of the OLED device.
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Figure 2025518232000001_ABST
Abstract
Description
Technical Field
[0001] Cross - Reference to Related Applications This application claims priority to U.S. Patent Application No. 17 / 828,360, filed May 31, 2022, entitled "OLED ANODE STRUCTURES INCLUDING AMORPHOUS TRANSPARENT CONDUCTING OXIDES AND OLED PROCESSING METHOD COMPRISING THE SAME", the entire content of which is incorporated herein by reference.
[0002] This technology relates to deposition processes, structures, and systems. More particularly, this technology relates to a method for manufacturing an organic light - emitting diode (OLED) anode structure that is resistant to etchants.
Background Art
[0003] Input devices, including display devices, can be used in various electronic systems. An organic light - emitting diode (OLED) is a light - emitting diode (LED) that is a film of an organic compound in which an emissive electroluminescent layer emits light in response to an electric current. An OLED device is classified as a bottom - emission device when the emitted light passes through a transparent or semi - transparent lower electrode and a substrate on which the panel is fabricated. A top - emission device is classified based on whether the light emitted from the OLED device exits through a lid added after the device is manufactured. OLEDs are used to fabricate display devices for many electronic devices. Electronic device manufacturers are miniaturizing display devices while providing higher resolutions.
Summary of the Invention
Problems to be Solved by the Invention
[0004] The patterning of OLED pixels can include deposition and subsequent selective removal of dielectric layers (e.g., organic and inorganic materials) and metal layers. To perform the selective removal operation, a dry etchant and / or a wet etchant can be brought into contact with the structure during formation. However, the etchant may not be completely selective to the material to be removed, may interact unnecessarily with underlying layers, and may ultimately affect the performance of the final device. Accordingly, improved systems and methods that can be used to manufacture high-quality devices and structures are needed. These and other needs are addressed by the present technology.
Means for Solving the Problems
[0005] Embodiments of the present technology include an OLED device. The device can include a substrate. The device can include an anode. The anode can include a first portion of a first metal oxide material covering the substrate. The anode can include a metal material covering the first portion of the first metal oxide material. The metal material can be silver or can include silver. The anode can include a protective barrier covering the metal material (i.e., above the metal material). The protective barrier can include an amorphous protective material. The anode can include a second portion of the first metal oxide material covering the protective barrier. The device can include an OLED material electrically connected to the anode. The device can include a cathode electrically connected to the OLED material.
[0006] In some embodiments, the second portion of the first metal oxide material can cover the amorphous protective material. The protective barrier can include a second metal oxide material between the metal material and the amorphous protective material. The second metal oxide material can be the same metal oxide as the first metal oxide material. At least a portion of the second metal oxide material can be crystallized.
[0007] Some embodiments of the present technology include an OLED device processing method. The method can include forming an anode on a substrate. Forming the anode can include forming a first metal oxide material on the substrate and forming a metal layer on the first metal oxide material. The metal layer can be silver or can include silver. Forming the anode can include forming an amorphous protective material on the metal layer. The amorphous protective material can include a second metal oxide. Forming the anode can include forming a second metal oxide material on the amorphous protective material. The second metal oxide material can include a crystalline material having one or more grain boundaries. The grain boundaries can include one or more voids. The method can include forming an OLED material. The OLED material can be electrically connected to the anode. The method can include forming a cathode. The cathode can be electrically connected to the OLED material.
[0008] In some embodiments, the first metal oxide material, the second metal oxide material, or both can be or can include indium tin oxide (ITO). The first metal oxide material and the second metal oxide material can be the same material or can include the same material. The amorphous protective material can be or can include indium zinc oxide (IZO), indium tin zinc oxide (ITZO), indium gallium zinc oxide (IGZO). The thickness of the amorphous protective material can be less than 50 nm or about 50 nm. The amorphous protective material can be characterized by a volume crystallinity of less than 10 volume % or about 10 volume %. The amorphous protective material can be deposited by physical vapor deposition. The method can include exposing the substrate to an etchant following formation of the second metal oxide material. The amorphous protective material reduces the amount of etchant that interacts with the metal layer. The method can include forming a third metal oxide material on the metal layer following formation of the metal layer. The third metal oxide material can be the same material as the first metal oxide material, the second metal oxide material, or both or can include the same material. The total thickness of the amorphous protective material, the second metal oxide material, and the third metal oxide material can be less than 100 nm or about 100 nm. The third metal oxide material can cover the metal layer. The third metal oxide material can include at least a portion of a crystallized material.
[0009] Some embodiments of the present technology include an OLED device processing method. The method can include forming an anode on a substrate. Forming the anode can include forming a first metal oxide material on the substrate and forming a metal layer on the first metal oxide material. The metal layer can be silver or can include silver. Forming the anode can include forming a protective barrier on the metal layer. The protective barrier can include an amorphous protective material on the metal layer and a second metal oxide material on the amorphous protective material. Forming the anode can include forming the second metal oxide material on the amorphous protective material. The method can include forming an OLED material. The OLED material can be electrically connected to the anode. The method can include forming a cathode. The cathode can be electrically connected to the OLED material.
[0010] In some embodiments, the protective barrier can include a third metal oxide material between the metal layer and the amorphous protective material. The third metal oxide material can be a crystalline material. The protective barrier can be characterized by a thickness of less than 100 nm or about 100 nm.
[0011] The present technology provides many advantages compared to the prior art. Embodiments of the present technology form a protective barrier that can withstand etchants during subsequent operation. In embodiments, the protective barrier can include an amorphous material, and the amorphous material can suppress or prevent etchants, which are both dry and wet etchants, from reaching underlying materials such as the metal layer. Additionally, the protective barrier can reduce the thickness of other layers and improve the performance of the device by reducing light absorption. These and other embodiments will be described in more detail below in conjunction with the following description and the accompanying drawings, along with many of their advantages and features.
[0012] A further understanding of the nature and advantages of the disclosed technology can be realized by referring to the remaining parts of the specification and the drawings.
Brief Description of the Drawings
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Embodiments for Carrying Out the Invention
[0014] Some of the drawings are included as schematic views. It should be understood that the drawings are for illustrative purposes and are not considered to be to scale unless specifically stated so. In addition, as schematic views, the drawings are presented to assist understanding and may not include all aspects or information compared to the actual display, and may include exaggerated materials for illustrative purposes.
[0015] In the accompanying drawings, like components and / or features can have the same reference numerals. Further, by attaching letters distinguishing like components after the reference numerals, various components of the same type can be distinguished. When only the first reference numeral is used in this specification, the description applies to any one of the like components having the same first reference numeral, regardless of the letter.
[0016] Backplane processing includes the operation of fabricating a complexly patterned material on a substrate. The operations include remote and in-situ formation and removal processes that utilize corrosive materials including an acidic material and an ionized plasma of an oxygen-containing, sulfur-containing, and halogen-containing compound, radical, and ion. For example, an etching operation often involves contacting the substrate with a liquid, gas, or plasma etchant flowing into the processing region of a processing apparatus. The etchant is for etching a specific material, but the etchant may react with a material not intended to be etched. Further, a portion of the etchant may move through a layer and into a lower layer through a void in an upper layer. When the etchant moves into the lower layer, the lower layer material may be etched or lifted.
[0017] The OLED formation method endeavors to limit the etching of specific layers of the anode structure such as OLEDs. During OLED formation, a dielectric layer and / or a metal layer covering the anode structure can be deposited and then partially removed. During removal, an etchant can be supplied to remove a portion of the layer. For example, a dry etching process can be performed to remove the dielectric, and a wet etching process can be used to remove the metal material. Due to the metal oxide material covering the metal material of the anode structure, the etchant may be able to reach the metal layer and interact with it. The etchant may lift the metal layer or even remove a portion of the metal layer. To prevent the etchant from interacting with the metal layer, some OLED formation methods deposit a thicker metal oxide material on the metal layer to be protected. However, even with a thicker metal oxide material, the etchant can pass through voids in the material and then be able to interact with the metal layer. Furthermore, the thicker metal oxide material in the final device absorbs more light and reduces the efficiency of the OLED.
[0018] Embodiments of the present technology address these and other problems by forming a protective barrier between the metal layer of the anode structure and the metal oxide material. The protective barrier can include an amorphous protective material. The amorphous protective material can be a transparent material that is resistant to crystallization during subsequent operation. The amorphous protective material does not contain grain boundaries in the material and thus does not contain voids. Therefore, the amorphous protective material can suppress or prevent the etchant from reaching the metal layer. By suppressing or preventing the etchant from reaching the metal layer, the metal layer can maintain its structure. Furthermore, the thickness of the metal oxide layer covering the protective barrier can be made smaller compared to some OLED formation techniques, resulting in better performance of the final device.
[0019] The remaining disclosure identifies specific materials, components, and backplane processing methods according to embodiments of the present technology. It will be readily understood that the methods, materials, components, and systems described may apply to a variety of other methods, materials, components, and systems used in backplane device manufacturing and in the manufacture of other types of devices where a protective barrier protects underlying materials of the structure. Accordingly, the present technology is not limited to the methods, materials, components, and systems described. This disclosure describes non-limiting operations and general structures of exemplary methods that may be protected by embodiments of the present technology.
[0020] FIG. 1A is a schematic cross-sectional view of a subpixel circuit 100 having a progress configuration 101A. FIG. 1B is a schematic cross-sectional view of a subpixel circuit 100 having a plug configuration 101B. Each of the cross-sectional views of FIGS. 1A and 1B is taken along cross-section line 1”-1” of FIGS. 1C and 1D.
[0021] The subpixel circuit 100 can include a substrate 102. A metal-containing layer 104 that can include one or more layers such as a stack of layers can be patterned on the substrate 102 and defined by adjacent pixel definition layer (PDL) structures 126 disposed on the substrate 102. In an embodiment, the metal-containing layer 104 can be pre-patterned on the substrate 102. For example, the substrate 102 can be a pre-patterned indium tin oxide (ITO) glass substrate. The metal-containing layer 104 can be configured to operate the anodes of the respective subpixels. The metal-containing layer 104 can include, but is not limited to, chromium, titanium, gold, silver, copper, aluminum, ITO, combinations thereof, or other suitable conductive materials.
[0022] The PDL structure 126 can be disposed on the substrate 102. The PDL structure 126 can include one of an organic material, an organic material with an inorganic coating disposed thereon, or an inorganic material. The organic material of the PDL structure 126 can include, but is not limited to, polyimide. The inorganic material of the PDL structure 126 is silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (Si 2 N 2 O), magnesium fluoride (MgF 2 ), or a combination thereof, but is not limited thereto. Adjacent PDL structures 126 can each define a subpixel and expose the anode (i.e., the metal-containing layer 104) of each subpixel of the subpixel circuit 100.
[0023] The subpixel circuit 100 can have a plurality of subpixels 106 including at least a first subpixel 108a and a second subpixel 108b. The figure shows the first subpixel 108a and the second subpixel 108b, but the subpixel circuit 100 of the embodiments described herein may include two or more subpixels 106, such as a third subpixel and a fourth subpixel. Each subpixel 106 can include an OLED material 112 configured to emit white, red, green, blue, or light of another color when energized. For example, the OLED material 112 of the first subpixel 108a can emit red light when energized, the OLED material of the second subpixel 108b can emit green light when energized, the OLED material of the third subpixel can emit blue light when energized, and the OLED material of the fourth subpixel can emit light of another color when energized.
[0024] The overhang structure 110 can be disposed on each upper surface 103 of the PDL structure 126. The overhang structure 110 may be permanent to the subpixel circuit. The overhang structure 110 can further define each subpixel 106 of the subpixel circuit 100. The overhang structure 110 includes at least an upper portion 110B disposed on a lower portion 110A. The first configuration of the overhang structure 110 can include an upper portion 110B of a non-conductive inorganic material and a lower portion 110A of a conductive inorganic material. The second configuration of the overhang structure 110 can include an upper portion 110B of a conductive inorganic material and a lower portion 110A of a conductive inorganic material. The third configuration of the overhang structure 110 can include an upper portion 110B of a non-conductive inorganic material, a lower portion 110A of a non-conductive inorganic material, and an auxiliary cathode 202 (shown in FIG. 2) disposed under the lower portion 110A. Although the auxiliary cathode 202 is shown separately from the lower portion 110A, it may be the base of the overhang structure 110. The fourth configuration of the overhang structure 110 can include an upper portion 110B of a conductive inorganic material, a lower portion 110A of a non-conductive inorganic material, and an auxiliary cathode 202 disposed under the lower portion 110A. In an embodiment, the lower portion 110A may be multi-layered, the lowermost layer of the lower portion 110A is a conductive material or a non-conductive material, and another layer such as an upper layer or an intermediate layer of the lower portion 110A is also a conductive material or a non-conductive material. In some embodiments, in addition to or instead of the auxiliary cathode 202, the overhang structure 110 can include an overhang base (not shown). The overhang base can be characterized by a thickness greater than the thickness of the auxiliary cathode 202. The overhang base may or may not be in contact with the cathode 114. Further, the overhang base may be conductive or non-conductive. In an embodiment, the auxiliary cathode 202 can be incorporated into the overhang base. In addition to or instead of this, the overhang base or other portion of the overhang structure 110 can function as the auxiliary cathode 202.The first exemplary embodiment, the second exemplary embodiment, the third exemplary embodiment, and the fourth exemplary embodiment of the subpixel circuit 100 can include at least one overhang structure 110 of the first configuration, the second configuration, the third configuration, or the fourth configuration. The overhang structure 110 can be able to stay in a predetermined position (i.e., the overhang structure 110 can be permanent). Therefore, no organic material remains from the lifted-off overhang structure that impairs the performance of the OLED. By eliminating the need for the lift-off procedure, throughput can also be improved.
[0025] The non-conductive inorganic material can include, but is not limited to, an inorganic silicon-containing material. The silicon-containing material can include an oxide or nitride of silicon, or a combination thereof. The conductive inorganic material can include, but is not limited to, a metal-containing material. The metal-containing material can include copper, titanium, aluminum, molybdenum, silver, indium tin oxide, indium zinc oxide, or a combination thereof.
[0026] The bottom surface 107 of the upper portion 110B is wider than the upper surface 105 of the lower portion 110A and can form an overhang 109. By forming the overhang 109 with the bottom surface 107 larger than the upper surface 105, it may be possible for the upper portion 110B to shadow the lower portion 110A. Due to the shadowing of the overhang 109, the OLED material 112 and the cathode 114 can each be evaporated and deposited.
[0027] The OLED material 112 can include one or more of the HIL, HTL, EML, and ETL. The OLED material 112 can be disposed on the metal-containing layer 104. In an embodiment, the OLED material 112 can be disposed on a part of the metal-containing layer 104 and the PDL structure 126. In each sub-pixel 106, the cathode 114 can be disposed on the OLED material 112 and on the PDL structure 126. The cathode 114 can be electrically connected to the OLED material 112. The cathode 114 can be disposed on a part of the sidewall 111 of the lower portion 110A. Additionally or alternatively, it is also conceivable that the OLED material 112 can be disposed on a part of the lower sidewall 111. The cathode 114 and the auxiliary cathode 202 can include a conductive material such as a metal. The cathode 114 and / or the auxiliary cathode 202 can include, but are not limited to, chromium, titanium, aluminum, ITO, or a combination thereof. In an embodiment, the OLED material 112 and the cathode 114 can be disposed on the sidewall 113 of the upper portion 110B of the overhang structure 110. In an embodiment, the OLED material 112 and the cathode 114 can be disposed on the upper surface 115 of the upper portion 110B of the overhang structure 110.
[0028] Each sub-pixel 106 can include an encapsulation layer 116. The encapsulation layer 116 can be a local passivation layer or equivalent thereto. The encapsulation layer 116 of each sub-pixel can be disposed on the cathode 114 (and the OLED material 112) in a state where the encapsulation layer 116 extends along the respective sidewalls of the overhang structure 110 under at least a part of each of the overhang structures 110. The encapsulation layer 116 can be disposed on the cathode 114 and on at least the sidewall 111 of the lower portion 110A. In an embodiment, the encapsulation layer 116 can be disposed on the sidewall 113 of the upper portion 110B. In an embodiment, the encapsulation layer 116 can be disposed on the upper surface 115 of the upper portion 110B of the overhang structure 110. The encapsulation layer 116 can include an inorganic material such as a silicon-containing material. The silicon-containing material is Si 3 N4 It can contain materials.
[0029] In embodiments including one or more capping layers, the capping layer can be disposed between the cathode 114 and the encapsulation layer 116. As shown in FIG. 1A, the first capping layer 121 and the second capping layer 123 can be disposed between the cathode 114 and the encapsulation layer 116. FIG. 1A shows a subpixel circuit 100 having one or more capping layers, but each of the embodiments described herein can include one or more capping layers disposed between the cathode 114 and the encapsulation layer 116. The first capping layer 121 can contain an organic material. The second capping layer 123 can contain an inorganic material such as lithium fluoride. The first capping layer 121 and the second capping layer 123 can be deposited by evaporation deposition.
[0030] The progress configuration 101A and the plug configuration 101B of the subpixel circuit 100 can include at least a global passivation layer 120 disposed on the overhang structure 110 and on the encapsulation layer 116. The inkjet layer 118 can be disposed between the global passivation layer 120 and the overhang structure 110 and the encapsulation layer 116. The inkjet layer 118 can contain an acrylic material. The plug configuration 101B can include an intermediate passivation layer, and the intermediate passivation layer is disposed on the overhang structure 110 and on each plug 122 of the subpixel 106, and is disposed between each plug 122 of the subpixel 106 and the inkjet layer 118.
[0031] The plug configuration 101B can include plugs 122 disposed on the encapsulation layer 116. Each plug 122 can be disposed in each sub-pixel 106 of the sub-pixel circuit 100. The plug 122 can be disposed on the upper surface 115 of the upper portion 110B of the overhang structure 110. In an embodiment, an additional passivation layer may be disposed on the plug 122. The plug 122 can include, but is not limited to, a photoresist, a color filter, or a photosensitive monomer. The plug 122 can have a plug transmittance that matches or substantially matches the OLED transmittance (e.g., the OLED emission wavelength) of the OLED material 112. The plugs 122 may each be the same material and may match the OLED transmittance. The plugs 122 may be different materials that match the OLED transmittance of each sub-pixel of the plurality of sub-pixels 106. By the resist transmittance and the OLED transmittance matching or substantially matching, the plug 122 can stay on the sub-pixel 106 without blocking the emitted light from the OLED material 112. The plug 122 can be capable of staying in a predetermined position and thus may not require a lift-off procedure to remove it from the sub-pixel circuit 100. Since the plug 122 stays, an additional pattern resist material may not be required on the sub-pixel 106 formed in subsequent operations. The lift-off procedure of the plug 122 and the elimination of the additional pattern resist material in the sub-pixel circuit 100 can improve throughput.
[0032] FIG. 1C is a schematic top cross-sectional view of a sub-pixel circuit 100 having a dot-type architecture 101C. FIG. 1D is a schematic cross-sectional view of a sub-pixel circuit 100 having a line-type architecture 101D. Each of the top cross-sectional views of FIGS. 1C and 1D is taken along the cross-section line 1'-1' of FIGS. 1A and 1B.
[0033] The dot architecture 101C can include a plurality of pixel apertures 124A. Each of the pixel apertures 124A may be surrounded by an overhang structure 110 that defines each of the sub-pixels 106 of the dot architecture 101C. The line architecture 101D can include a plurality of pixel apertures 124B. Each of the pixel apertures 124B may be adjacent to an overhang structure 110 that defines each of the sub-pixels 106 of the line architecture 101D.
[0034] Figure 2 is a schematic cross-sectional view of the overhang structure 110 of the sub-pixel circuit 100. Figure 2 shows the third and fourth configurations of the overhang structure 110, but the description herein applies to the first configuration of the overhang structure 110 including an upper portion 110B of a non-conductive inorganic material and a lower portion 110A of a conductive inorganic material, as well as the second configuration of the overhang structure 110 including an upper portion 110B of a conductive inorganic material and a lower portion 110A of a conductive inorganic material. In the first and second configurations, as shown in Figure 2, the OLED material 112 cannot contact the lower portion 110A of the overhang structure 110, and the cathode 114 can contact the lower portion 110A of the overhang structure 110. In the third and fourth configurations, the OLED material 112 cannot contact the lower portion 110A and the auxiliary cathode 202, and the cathode 114 can contact at least the auxiliary cathode 202.
[0035] The upper portion 110B can include the lower edge 206. The OLED material 112 can be disposed on the anode and on the shadow portion 210 of the PDL structure 126. The OLED material 112 can be electrically connected to the anode (i.e., the metal-containing layer 104). In an embodiment, the HIL 204 of the OLED material 112 may be included. In an embodiment including the HIL 204, the OLED material 112 can include an HTL, an EML, and an ETL. In an embodiment including the HIL 204, the HIL 204 cannot contact the lower portion 110A of the overhang structure 110. In an embodiment including the HIL 204, one or more additional portions (e.g., HTL, EML, and ETL) of the OLED material 112 may or may not contact the lower portion 110A of the overhang structure 110.
[0036] The cathode 114 can be disposed on the OLED material 112 and on the shadow portion 210 of the PDL structure 126. In an embodiment, the cathode 114 can be disposed on a part 220 of the sidewall 111 of the lower portion 110A. In an embodiment, the cathode 114 can contact a part 222 of the auxiliary cathode 202 in the shadow portion 210 of the PDL 126. In an embodiment where the cathode 114 contacts a part 222 of the auxiliary cathode 202, the cathode 114 may contact a part 220 of the sidewall 111 of the lower portion 110A. The encapsulation layer 116 can be disposed on the cathode 114 (and the OLED material 112) in a state where the encapsulation layer 116 extends along the sidewall 111 of the lower portion 110A at least under the upper portion 110B of the overhang structure 110.
[0037] During the evaporation deposition of the OLED material 112, the lower edge 206 of the upper portion 110B can define the position of the OLED edge 214. The OLED material 112 can be evaporated at an OLED maximum angle, which ensures that the OLED material 112 is not deposited beyond the OLED edge 214. In embodiments including the HIL 204, the lower edge 206 of the upper portion 110B can define the position of the HIL edge 218. The HIL 204 can be evaporated at an HIL maximum angle, which ensures that the HIL 204 is not deposited beyond the HIL edge 218. During the evaporation deposition of the cathode 114, the lower edge 206 of the upper portion 110B defines the position of the cathode edge 226. The cathode 114 can be evaporated at a cathode maximum angle, which ensures that the cathode 114 is not deposited beyond the cathode edge 226.
[0038] Figure 3 is a flowchart of a method 300 for backplane processing. The method 300 can correspond to a method of manufacturing the anode of the subpixel circuit 100. FIGS. 4A-4C are schematic cross-sectional views of the substrate 102 during the method 300 for forming the anode (i.e., the metal-containing layer 104) of the subpixel circuit 100 according to the embodiments described herein. The method 300 can form a protective barrier to prevent the etchant from interacting with the metal layer on which the protective barrier can be formed. The protective barrier can include a single metal oxide layer or multiple layers forming a multilayer stacked protective barrier.
[0039] In operation 301, as shown in FIGS. 4A-4C, a first metal oxide material 402 can be formed on substrate 102. In an embodiment, the first metal oxide material 402 can be or include ITO. The first metal oxide material 402 can be characterized by a thickness of less than 50 nm or about 50 nm, for example, less than 45 nm or about 45 nm, less than 40 nm or about 40 nm, less than 35 nm or about 35 nm, less than 30 nm or about 30 nm, less than 25 nm or about 25 nm, less than 20 nm or about 20 nm, less than 18 nm or about 18 nm, less than 16 nm or about 16 nm, less than 14 nm or about 14 nm, less than 12 nm or about 12 nm, less than 10 nm or about 10 nm, less than 9 nm or about 9 nm, less than 8 nm or about 8 nm, less than 7 nm or about 7 nm, or less.
[0040] In operation 302, as shown in FIGS. 4A-4C, a metal layer 404 can be formed on the first metal oxide material 402. The metal layer 404 can be or include silver, among other metals. The metal layer 404 can be characterized by a thickness of less than 150 nm or about 150 nm, for example, less than 140 nm or about 140 nm, less than 130 nm or about 130 nm, less than 120 nm or about 120 nm, less than 115 nm or about 115 nm, less than 110 nm or about 110 nm, less than 105 nm or about 105 nm, less than 100 nm or about 100 nm, or less. Similarly, the metal layer 404 can be characterized by a thickness of greater than 60 nm or about 60 nm, greater than 70 nm or about 70 nm, greater than 80 nm or about 80 nm, greater than 90 nm or about 90 nm, greater than 95 nm or about 95 nm, greater than 100 nm or about 100 nm, or greater.
[0041] In operation 304, as shown in FIGS. 4A-4C, an amorphous protective material 406 of the protective barrier can be formed on the metal layer 404. The amorphous protective material 406 can be or can include a metal oxide. The metal oxide of the amorphous protective material 406 can include any transparent conductive oxide (TCO) that maintains an amorphous structure at a high temperature (e.g., above 300° C. or about 300° C.) during subsequent processing. For example, the metal oxide can be or can include, but is not limited to, indium zinc oxide (IZO), indium tin zinc oxide (ITZO), indium gallium zinc oxide (IGZO). The amorphous protective material 406 can be characterized by a thickness of less than 50 nm or about 50 nm, e.g., less than 45 nm or about 45 nm, less than 40 nm or about 40 nm, less than 35 nm or about 35 nm, less than 30 nm or about 30 nm, less than 25 nm or about 25 nm, less than 20 nm or about 20 nm, less than 15 nm or about 15 nm, less than 10 nm or about 10 nm, less than 9 nm or about 9 nm, less than 8 nm or about 8 nm, less than 7 nm or about 7 nm, less than 6 nm or about 6 nm, less than 5 nm or about 5 nm, or less. Further, the volume crystallinity of the metal oxide material of the amorphous protective material 406 can be less than 10 volume % or about 10 volume %, less than 9 volume % or about 9 volume %, less than 8 volume % or about 8 volume %, less than 7 volume % or about 7 volume %, less than 6 volume % or about 6 volume %, less than 5 volume % or about 5 volume %, less than 4 volume % or about 4 volume %, less than 3 volume % or about 3 volume %, less than 2 volume % or about 2 volume %, less than 1 volume % or about 1 volume %, or less, based on the total volume of the amorphous protective material 406. With a volume crystallinity of less than 10 volume % or about 10 volume %, the amorphous protective material 406 contains little or no grain boundaries in the material and thus little or no voids.
[0042] The amorphous protective material 406 can include any TCO that maintains an amorphous structure during subsequent processing. Due to the transparency of the amorphous protective material 406, high light transmittance of the final device can be maintained. Further, as described later, the amorphous protective material 406 can enable the use of a thinner second metal oxide material 408, and can further enhance the light transmittance of the final device. In addition, the amorphous protective material 406 can have low porosity due to a low level of crystallinity. As described later, the low porosity can function to protect the underlying metal layer 404 during subsequent processing.
[0043] In operation 305, as shown in FIGS. 4A - 4C, a second metal oxide material 408 can be formed on the amorphous protective material 406. The second metal oxide material 408 can be a crystalline material having one or more grain boundaries. The grain boundaries of the second metal oxide material 408 can include one or more voids. One or more voids of the second metal oxide material 408 can provide access or a path to the underlying material (e.g., the amorphous protective material 406). In an embodiment, the second metal oxide material 408 can be the same material as or include the same material as the first metal oxide material 402, or can be a different material or include different materials. That is, the second metal oxide material 408 can be ITO or can include ITO. The second metal oxide material 408 can be characterized by a thickness of less than 50 nm or about 50 nm, e.g., less than 45 nm or about 45 nm, less than 40 nm or about 40 nm, less than 35 nm or about 35 nm, less than 30 nm or about 30 nm, less than 25 nm or about 25 nm, less than 20 nm or about 20 nm, less than 15 nm or about 15 nm, less than 10 nm or about 10 nm, less than 9 nm or about 9 nm, less than 8 nm or about 8 nm, less than 7 nm or about 7 nm, less than 6 nm or about 6 nm, less than 5 nm or about 5 nm, less than 4 nm or about 4 nm, or less. Further, the volume crystallinity of the metal oxide material of the second metal oxide material 408 can be greater than 50 volume % or about 50 volume %, less than 60 volume % or about 60 volume %, less than 70 volume % or about 70 volume %, less than 80 volume % or about 80 volume %, less than 90 volume % or about 90 volume %, less than 95 volume % or about 95 volume %, or greater, based on the total volume of the second metal oxide material 408.
[0044] In any operation 303, as shown in FIGS. 4A - 4C, a third metal oxide material 410 can be formed on the metal layer 404. The third metal oxide material 410 can be formed before the formation of the amorphous protection material 406. The third metal oxide material 410 can enhance the adhesion between the metal layer 404 and the amorphous protection material 406. Alternatively or additionally, in embodiments where the structure can be exposed to the atmosphere during transfer between chambers, etc., the third metal oxide material 410 can be formed before the formation of the amorphous protection material 406 to protect the metal layer 404. In embodiments, the third metal oxide material 410 can include the same material as the first metal oxide material 402, the second metal oxide material 408, or both. That is, the metal oxide of the third metal oxide material 410 can include, but is not limited to, ITO, ITZO, or IGZO. In further embodiments, the third metal oxide material 410 can include the same material as the amorphous protection material 406. That is, the metal oxide of the third metal oxide material 410 can include, but is not limited to, IZO, ITZO, or IGZO.
[0045] The third metal oxide material 410 can be characterized by a thickness of less than 50 nm or about 50 nm, such as less than 45 nm or about 45 nm, less than 40 nm or about 40 nm, less than 35 nm or about 35 nm, less than 30 nm or about 30 nm, less than 25 nm or about 25 nm, less than 20 nm or about 20 nm, less than 15 nm or about 15 nm, less than 10 nm or about 10 nm, less than 9 nm or about 9 nm, less than 8 nm or about 8 nm, less than 7 nm or about 7 nm, less than 6 nm or about 6 nm, less than 5 nm or about 5 nm, less than 4 nm or about 4 nm, or less. In an embodiment, the metal oxide of the third metal oxide material 410 may be a crystalline material. It is also conceivable that the metal oxide of the third metal oxide material 410 may be an amorphous material. Thus, the volume crystallinity of the third metal oxide material 410 may be greater than 50 volume % or about 50 volume %, less than 60 volume % or about 60 volume %, less than 70 volume % or about 70 volume %, less than 80 volume % or about 80 volume %, less than 90 volume % or about 90 volume %, less than 95 volume % or about 95 volume %, or greater, based on the total volume of the third metal oxide material 410. Similarly, the volume crystallinity of the third metal oxide material 410 may be less than 10 volume % or about 10 volume %, less than 9 volume % or about 9 volume %, less than 8 volume % or about 8 volume %, less than 7 volume % or about 7 volume %, less than 6 volume % or about 6 volume %, less than 5 volume % or about 5 volume %, less than 4 volume % or about 4 volume %, less than 3 volume % or about 3 volume %, less than 2 volume % or about 2 volume %, less than 1 volume % or about 1 volume %, or less, based on the total volume of the third metal oxide material 410.
[0046] A protective barrier that may include an amorphous protective material 406, a second metal oxide material 408, and / or a third metal oxide material 410 can be characterized by a thickness of less than 100 nm or about 100 nm. The greater the thickness, the higher the light absorption of the protective barrier, which can reduce the efficiency of the final device. Thus, the protective barrier can be characterized by a thickness of less than 95 nm or about 95 nm, less than 90 nm or about 90 nm, less than 85 nm or about 85 nm, less than 80 nm or about 80 nm, less than 75 nm or about 75 nm, less than 70 nm or about 70 nm, less than 65 nm or about 65 nm, less than 60 nm or about 60 nm, less than 55 nm or about 55 nm, less than 45 nm or about 45 nm, less than 40 nm or about 40 nm, less than 35 nm or about 35 nm, less than 30 nm or about 30 nm, less than 25 nm or about 25 nm, less than 20 nm or about 20 nm, less than 18 nm or about 18 nm, less than 16 nm or about 16 nm, less than 15 nm or about 15 nm, less than 14 nm or about 14 nm, less than 13 nm or about 13 nm, less than 12 nm or about 12 nm, less than 11 nm or about 11 nm, less than 10 nm or about 10 nm, less than 9 nm or about 9 nm, or less. In an embodiment, method 300 can include forming an OLED material such as OLED material 112. Additionally, in some embodiments, method 300 can include forming a cathode such as cathode 114.
[0047] In operation 306, as will be further described below (e.g., operations 504 and / or 507), the substrate 102 can be exposed to an etchant. Between operation 305 and operation 306, additional material can be formed on the substrate, and operation 306 does not necessarily have to be immediately after operation 305. When the additional material is formed and removed from the substrate, an etchant can be used to remove the material. Without the amorphous protective material 406, the dry-etching gas species may move through the voids of the second metal oxide material 408. The plasma may react with the metal layer 404 such as silver to form silver oxide, silver fluoride, silver chloride, and / or silver sulfide. The resulting compound may cause bumps or unevenness on the surface / inside of the metal layer 404. The bumps or unevenness may not be able to reflect light and may degrade the performance of the structure or the final device. Similarly, without the amorphous protective material 406, the liquid species may move through the voids of the second metal oxide material 408. An acidic material may remove the material of the metal layer 404 underlying the second metal oxide material 408 by, for example, pit etching. The removal of the material may cause the metal layer 404 to not be able to reflect light and may degrade the performance of the structure or the final device.
[0048] The amorphous protective material 406 covering the metal layer 404 can be characterized by a low etching rate (e.g., high etching resistance). Thus, the amorphous protective material 406 can maintain the smoothness and / or roughness of the metal layer 404 during the etching operations of the subsequent forming method 500. By maintaining the smooth surface of the metal layer 404, the reflection of light during operation can be maintained, and the light can be properly reflected by the metal layer 404. If the etchant can freely remove or penetrate the amorphous protective material 406, the defects of the metal layer 404 may scatter the light reflected by the metal layer 404 or allow the light to pass through without reflection, thereby degrading the performance of the final device.
[0049] FIG. 5 is a flowchart of a method 500 for forming the sub-pixel circuit 100. The method 500 may correspond to a method of manufacturing the sub-pixel circuit 100. FIGS. 6A-6L are schematic cross-sectional views of the substrate 102 during the method 500 for forming the sub-pixel circuit 100 according to the embodiments described herein. FIGS. 6A-6C, 6E, 6G, 6I, and 6K may correspond to the plug configuration 101A of the first exemplary embodiment or the second exemplary embodiment of the sub-pixel circuit 100. FIGS. 6A, 6B, 6D, 6F, 6H, 6J, and 6L may correspond to the plug configuration 101B of the third exemplary embodiment or the fourth exemplary embodiment of the sub-pixel circuit 100.
[0050] In operation 501, as shown in FIG. 6A, an overhang structure 110 can be formed. Forming the overhang structure 110 can include depositing a lower layer and an upper layer on the substrate 102. The lower layer can be disposed on the PDL structure 126 and the metal-containing layer 104. The upper layer can be disposed on the lower layer. The lower layer may correspond to the lower portion 110A of the overhang structure 110, and the upper layer may correspond to the upper portion 110B. In embodiments including the third and fourth configurations of the overhang structure 110, an auxiliary cathode layer can be disposed between the lower layer 110A and the PDL structure 126. The auxiliary cathode layer may correspond to the auxiliary cathode 202. A resist can be disposed on the upper layer and patterned. To form the overhang structure 110, a portion of the upper layer 110B and the lower layer 110A exposed by the pixel openings 124A, 124B can be removed.
[0051] In operation 502, as shown in FIG. 6B, the OLED material 112, the cathode 114, and the encapsulation layer 116 of the first sub-pixel 108A can be deposited. In an embodiment including a capping layer, the capping layer can be deposited between the cathode 114 and the encapsulation layer 116. The capping layer can be deposited by evaporation deposition. In the first configuration and the second configuration, the OLED material 112 cannot contact the lower portion 110A of the overhang structure 110, and the cathode 114 can contact the lower portion 110A of the overhang structure 110. In the third configuration and the fourth configuration, the OLED material 112 cannot contact the lower portion 110A and the auxiliary cathode 202, and the cathode 114 can contact at least the auxiliary cathode 202. The encapsulation layer 116 can be deposited on the cathode 114.
[0052] In operation 503, as shown in FIG. 6C, a resist 602 can be formed in the well 604 of the first sub-pixel 108A. In operation 504, as shown in FIGS. 6E-6F, the encapsulation layer 116, the cathode 114, and the OLED material 112 exposed by the resist 602 can be removed. The encapsulation layer 116, the cathode 114, and the OLED material 112 exposed by the resist 602 can be removed by a dry etching process or a wet etching process. According to an embodiment including the progress configuration 101A of the sub-pixel circuit 100, as shown in FIG. 6E, the resist 602 can be removed. According to an embodiment including the plug configuration 101B of the sub-pixel circuit 100, as shown in FIGS. 6D and 6F, the resist 602 can correspond to the plug 122 of the first sub-pixel 108A.
[0053] In operation 505, as shown in FIGS. 6G-6H, the OLED material 112, the cathode 114, and the encapsulation layer 116 of the second sub-pixel 108b can be deposited. In embodiments including a capping layer, the capping layer can be deposited between the cathode 114 and the encapsulation layer 116. The capping layer can be deposited by evaporation deposition. Due to the shadowing of the overhang 109, each of the OLED material 112 and the cathode 114 can be evaporated and deposited. In the first configuration and the second configuration, the OLED material 112 cannot contact the lower portion 110A of the overhang structure 110, and the cathode 114 can contact the lower portion 110A of the overhang structure 110. In the third configuration and the fourth configuration, the OLED material 112 cannot contact the lower portion 110A and the auxiliary cathode 202, and the cathode 114 can contact at least the auxiliary cathode 202. The encapsulation layer 116 can be deposited on the cathode 114.
[0054] In operation 506, as shown in FIGS. 6I-6J, a resist 606 can be formed in the well 608 of the second sub-pixel 108B. In operation 507, as shown in FIGS. 6K-6L, the encapsulation layer 116, the cathode 114, and the OLED material 112 exposed by the resist 606 can be removed. The encapsulation layer 116, the cathode 114, and the OLED material 112 exposed by the resist 606 can be removed by a dry etching process or a wet etching process. According to an embodiment including the progress configuration 101A of the sub-pixel circuit 100, as shown in FIG. 6K, the resist 606 can be removed. According to an embodiment including the plug configuration 101B of the sub-pixel circuit 100, as shown in FIGS. 6J and 6L, the resist 606 can correspond to the plug 122 of the second sub-pixel 108B. Operations 501-507 can form a sub-pixel circuit 100 including two or more sub-pixels 106. Operations 505-507 can be repeated for each additional sub-pixel (e.g., the third sub-pixel and / or the fourth sub-pixel).
[0055] Some OLED formation methods increase the thickness of the metal oxide material covering the metal layer to suppress the interaction between the etchant and the metal layer. However, if the thickness of the metal oxide material is increased to more than, for example, 100 nm or up to about 100 nm, the efficiency of the final device is sacrificed. The metal oxide material covering the metal layer may absorb more light and contribute to the problem of white angle dependence (WAD). Embodiments of the present technology solve this problem by incorporating an amorphous protective material between the metal layer and the second metal oxide material. The amorphous protective material has no holes through which the etchant can reach the metal layer. Therefore, the present technology can maintain the second metal oxide material at a thickness sufficient to absorb a minimum amount of light while preventing the etchant from interacting with the metal layer.
[0056] In the above description, for the purpose of explanation, many details have been set forth to provide an understanding of various embodiments of the present technology. However, it will be apparent to those skilled in the art that an embodiment can be practiced without some of these details or with additional details.
[0057] Although some embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative configurations, and equivalents can be used without departing from the spirit of the embodiments. Additionally, to avoid unnecessarily obscuring the present technology, some well-known processes and elements are not described. Therefore, the above description should not be considered as limiting the scope of the present technology.
[0058] When a range of values is presented, it is to be understood that each intervening value, to the minimum fraction of the lower limit unit between the upper and lower limits of that range, is specifically disclosed, unless the context clearly dictates otherwise. Any narrower range between any of the stated values or intervening values not stated in the stated range and any other stated value or intervening value in that stated range is included. The upper and lower limits of these smaller ranges may independently be included in or excluded from the range, and each range where either, or both, of the limiting values are included in the smaller range, or neither are included, is included in the technology according to any specifically excluded limiting value in the stated range. When the stated range includes one or both of the limiting values, ranges excluding one or both of the included limiting values are also included.
[0059] As used in this specification and the appended claims, the singular forms "a", "an", and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, reference to "a layer" includes a plurality of such layers, and reference to "the material" includes reference to one or more materials known to those of ordinary skill in the art and their equivalents.
[0060] Also, as used in this specification and the following claims, the words "comprise", "comprising", "contain", "containing", "include", and "including" are intended to specify the presence of the stated feature, integer, component, or operation, but do not preclude the presence or addition of one or more other features, integers, components, operations, acts, or groups.
Claims
1. An OLED device, comprising: a substrate; an anode, comprising: a first portion of a first metal oxide material covering the substrate; a metal material covering the first portion of the first metal oxide material; a protective barrier covering the metal material, the protective barrier comprising an amorphous protective material; and a second portion of the first metal oxide material covering the protective barrier; the anode; an OLED material electrically connected to the anode; and a cathode electrically connected to the OLED material. The OLED device.
2. The OLED device according to claim 1, wherein the protective barrier further comprises a second metal oxide material between the metal material and the amorphous protective material.
3. The OLED device according to claim 2, wherein the second metal oxide material is the same metal oxide as the first metal oxide material.
4. The OLED device according to claim 2, wherein at least a part of the second metal oxide material is crystallized.
5. A method for processing an OLED device, comprising: forming an anode on a substrate by: forming a first metal oxide material on the substrate; forming a metal layer on the first metal oxide material; forming an amorphous protective material containing a second metal oxide on the metal layer; and forming a second metal oxide material on the amorphous protective material, wherein the second metal oxide material comprises a crystalline material having one or more grain boundaries, and the grain boundaries contain one or more voids; forming the anode; forming an OLED material electrically connected to the anode; and forming a cathode electrically connected to the OLED material. The method for processing an OLED device.
6. The method for processing an OLED device according to claim 5, wherein the first metal oxide material, the second metal oxide material, or both contain indium tin oxide (ITO).
7. The method for processing an OLED device according to claim 5, wherein the metal layer contains silver.
8. The method for processing an OLED device according to claim 5, wherein the second metal oxide of the amorphous protective material contains indium zinc oxide (IZO), indium tin zinc oxide (ITZO), or indium gallium zinc oxide (IGZO).
9. The OLED device processing method according to claim 5, wherein the thickness of the amorphous protective material is less than 50 nm or about 50 nm.
10. The OLED device processing method according to claim 5, wherein the amorphous protective material is characterized by a volume crystallinity of less than 10% by volume or about 10% by volume.
11. The OLED device processing method according to claim 5, wherein the amorphous protective material is deposited by physical vapor deposition.
12. The OLED device processing method according to claim 5, further comprising exposing the substrate to an etchant following the formation of the second metal oxide material, wherein the amorphous protective material reduces the amount of etchant that interacts with the metal layer.
13. The OLED device processing method according to claim 5, further comprising forming a third metal oxide material on the metal layer following the formation of the metal layer.
14. The OLED device processing method according to claim 13, wherein the third metal oxide material is the same material as the first metal oxide material, the second metal oxide material, or both.
15. The OLED device processing method according to claim 13, wherein the total thickness of the amorphous protective material, the second metal oxide material, and the third metal oxide material is less than 100 nm or about 100 nm.
16. The OLED device processing method according to claim 15, wherein the third metal oxide material comprises at least a portion of a crystallized material.
17. An OLED device processing method, comprising: forming an anode on a substrate; forming a first metal oxide material on the substrate; forming a metal layer containing silver on the first metal oxide material; forming a protective barrier comprising an amorphous protective material covering the metal layer on the metal layer; and forming a second metal oxide material on the amorphous protective material to form an anode, forming an OLED material electrically connected to the anode, and forming a cathode electrically connected to the OLED material The OLED device processing method comprising.
18. The OLED device processing method according to claim 17, wherein the protective barrier further comprises a third metal oxide material between the metal layer and the amorphous protective material.
19. The OLED device processing method according to claim 18, wherein the third metal oxide material is a crystalline material.
20. The OLED device processing method according to claim 17, wherein the protective barrier is characterized by a thickness of less than 100 nm or about 100 nm.
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