Field-effect transistor having a multi-step field plate

Abstract

Transistor elements according to some embodiments include a semiconductor barrier layer, a surface dielectric layer on the semiconductor barrier layer, and a gate on the surface dielectric layer. The surface dielectric layer includes an opening therein that is laterally spaced from the gate. The element includes an interlayer dielectric layer on the surface dielectric layer that extends over the gate and into the opening in the surface dielectric layer, and a multi-step field plate on the interlayer dielectric layer. The multi-step field plate is laterally spaced from the gate. The embedded portion of the multi-step field plate is above the opening in the surface dielectric layer, and the multi-step field plate includes a first step adjacent to the embedded portion of the field plate on the side surface of the field plate on the side opposite the gate, and a second step adjacent to the first step.

Description

Technical Field

[0001] The present disclosure relates to transistor structures, and more particularly to field effect transistors including field plates.

Background Art

[0002] Narrow-bandgap semiconductor materials such as silicon (Si) and gallium arsenide (GaAs) are widely used in semiconductor devices for low-power applications and, in the case of Si, for low-frequency applications. However, these semiconductor materials have a relatively small bandgap (1.12 eV for Si and 1.42 eV for GaAs at room temperature) and a relatively small breakdown voltage, and thus may not be very suitable for high-power and / or high-frequency applications.

[0003] Due to the interest in high-power, high-temperature, and / or high-frequency applications and devices, wide-bandgap semiconductor materials such as silicon carbide (3.2 eV for 4H-SiC at room temperature) and group III nitrides (e.g., 3.36 eV for GaN at room temperature) have received attention. These materials can have a higher breakdown field strength and a higher electron saturation velocity than GaAs and Si.

[0004] Particularly interesting devices for high-power and / or high-frequency applications are high electron mobility transistors (HEMTs), also known as modulation doped field effect transistors (MODFETs). In an HEMT device, a two-dimensional electron gas (2DEG) can be formed at the hetero-junction of two semiconductor materials with different bandgap energies, where the material with the smaller bandgap has a higher electron affinity than the wide-bandgap material. The 2DEG is the accumulation layer of the undoped small-bandgap material and has a relatively high sheet electron concentration, e.g., 10 13 carriers / cm 2It can include a sheet electron concentration exceeding [value]. Furthermore, electrons derived from a wider bandgap semiconductor may transfer to the 2DEG, and due to the reduction of scattering by ionized impurities, a relatively high electron mobility becomes possible. This combination of a relatively high carrier concentration and carrier mobility can provide a relatively large mutual conductance to the HEMT, bringing about a performance superiority over metal-semiconductor field effect transistors (MESFETS) for high-frequency applications.

[0005] HEMTs fabricated with a gallium nitride / aluminum gallium nitride (GaN / AlGaN) material system can generate a large amount of RF power due to a combination of material properties such as a relatively high breakdown electric field, a relatively wide bandgap, a relatively large conduction band offset, and / or a relatively high saturation electron drift velocity. Most of the electrons in the 2DEG may be due to the polarization in AlGaN.

[0006] Field plates are used to improve the performance of GaN-based HEMTs at microwave frequencies, and the performance is improved compared to devices without field plates. In many field plate approaches, it involves connecting the field plate to the source of the transistor with the field plate placed on the drain side of the channel. This reduces the electric field on the gate-drain side of the transistor, thereby increasing the breakdown voltage and potentially reducing the high-field trap effect. However, among transistors with a gate-drain field plate, there may be some that exhibit relatively low reliability performance, especially in class C (or higher) operation where the electric field on the source side of the gate is important.

[0007] FIG. 1 shows a GaN-based HEMT 10 formed on a silicon carbide substrate 12. There is a GaN channel layer 16 on the substrate 12, and an AlGaN barrier layer 18 on the channel layer 16. A two-dimensional electron gas (2DEG) 20 is generated in the channel layer 16 adjacent to the barrier layer 18. Source and drain contacts 22 and 24 are formed on the channel layer 16. The conductivity of the 2DEG 20 is modulated by applying a voltage to a gate 26 formed on the barrier layer 18 between the source contact 22 and the drain contact 24. As shown in FIG. 1, the gate 26 may have a mushroom or T-top configuration in a relatively narrow contact region that extends through the surface dielectric layer 25 where the gate 26 contacts the barrier layer 18.

[0008] The HEMT 10 includes a field plate 28 connected to the source contact 22. The field plate 28 is separated from the gate 26 by an interlayer dielectric layer 21 and is separated from the barrier layer 18 by the interlayer dielectric layer 21 and the surface dielectric layer 25. The field plate 28 extends above the gate 26 and extends laterally towards the drain contact 24.

[0009] The field plate 28 is connected to the source contact 22. Connecting the field plate 28 to the source contact 22 can reduce the gate-to-drain capacitance (Cgd), and as a result, increase the gain of the device. In addition to reducing the gate-to-drain capacitance Cgd, the presence of the field plate 28 can improve the linearity of the device and / or reduce the capacitance drain bias dependence. GaN-based HEMTs generally exhibit good linearity, but further improvement may be desired in high-power RF applications. Also, the structure shown in FIG. 1 can reduce the gate-to-drain capacitance Cgd compared to a structure without a field plate, but the gate-to-drain capacitance Cgd may still show a large dependence on the bias of the drain contact 24.

Prior Art Documents

Patent Documents

[0010]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Patent Document 8

Patent Document 9

Patent Document 10

Patent Document 11

Patent Document 12

Patent Document 13

Summary of the Invention

Means for Solving the Problems

[0011] Transistor elements according to some embodiments include a semiconductor barrier layer, a surface dielectric layer on the semiconductor barrier layer, and a gate on the surface dielectric layer. The surface dielectric layer includes therein an opening that is laterally spaced from the gate. The element includes an interlayer dielectric layer on the surface dielectric layer that extends into the opening in the surface dielectric layer over the gate, and a multiple-stepped field plate on the interlayer dielectric layer. The multiple-stepped field plate is laterally spaced from the gate.

[0012] The embedded portion of the multiple-stepped field plate is above the opening in the surface dielectric layer, and the multiple-stepped field plate includes a first step adjacent to the embedded portion of the field plate on the side surface of the field plate on the side opposite to the gate, and a second step adjacent to the first step. The embedded portion of the field plate is vertically spaced from the semiconductor barrier layer by a first distance, the first step is vertically spaced from the semiconductor barrier layer by a second distance, and the second step is vertically spaced from the semiconductor barrier layer by a third distance. The second distance is greater than the first distance, and the third distance is greater than the second distance.

[0013] In some embodiments, the first distance is equal to the thickness of the interlayer dielectric layer. In some embodiments, the second distance is equal to the sum of the thickness of the interlayer dielectric layer and the thickness of the surface dielectric layer.

[0014] The interlayer dielectric layer may include a first interlayer dielectric layer, in which case the third distance is equal to the sum of the thickness of the first interlayer dielectric layer, the thickness of the surface dielectric layer, and the thickness of a second interlayer dielectric layer on the first interlayer dielectric layer.

[0015] The opening in the surface dielectric layer may extend completely through the surface dielectric layer to expose the semiconductor barrier layer, and the gate may extend through the surface dielectric layer to contact the semiconductor barrier layer.

[0016] In some embodiments, the transistor element may include a source contact and a drain contact on a semiconductor barrier layer, in which case the gate is between the source contact and the drain contact, and the field plate includes a source-side wing that extends over the semiconductor barrier layer and toward the source contact.

[0017] The first distance may be from about 0.1 to 0.3 microns, the second distance may be from about 0.15 to 0.4 microns. The third distance may be from about 0.25 to 0.5 microns. The width of the embedded portion of the field plate may be from about 0.3 to 0.6 microns.

[0018] The width of the first step may be from about 0.3 to 0.6 microns, and the width of the second step may be from about 0.3 to 0.6 microns.

[0019] The interlayer dielectric layer has a vertical thickness, and the field plate may be laterally spaced from the gate by a distance approximately equal to the vertical thickness of the interlayer dielectric layer.

[0020] The transistor element may include a third step adjacent to the second step, in which case the third step is vertically spaced from the semiconductor by a fourth distance that is greater than the third distance.

[0021] A method of forming a transistor device according to some embodiments includes forming a surface dielectric layer on a semiconductor barrier layer, forming an opening in the surface dielectric layer to expose the semiconductor barrier layer, forming a gate on the surface dielectric layer that is laterally spaced from the opening, forming an interlayer dielectric layer on the surface dielectric layer and the gate, wherein the interlayer dielectric layer extends into the opening in the surface dielectric layer over the gate, forming a multi-step field plate on the interlayer dielectric layer. The multi-step field plate is laterally spaced from the gate. The embedded portion of the multi-step field plate is above the opening in the surface dielectric layer. The multi-step field plate includes a first step adjacent to the embedded portion of the multi-step field plate on a side surface of the multi-step field plate on the side opposite to the gate, and a second step adjacent to the first step. The embedded portion of the multi-step field plate is vertically spaced from the semiconductor barrier layer by a first distance, the first step is vertically spaced from the semiconductor barrier layer by a second distance, and the second step is vertically spaced from the semiconductor barrier layer by a third distance. The second distance is greater than the first distance, and the third distance is greater than the second distance.

[0022] A high electron mobility transistor device according to some embodiments includes a channel layer, a semiconductor barrier layer on the channel layer, a surface dielectric layer on the semiconductor barrier layer, and a gate on the surface dielectric layer. The surface dielectric layer includes an opening therein that is laterally spaced from the gate.

[0023] The device further includes a source contact and a drain contact on the semiconductor barrier layer, wherein the gate is between the source contact and the drain contact, and an interlayer dielectric layer on the surface dielectric layer, wherein the interlayer dielectric layer extends into the opening in the surface dielectric layer over the gate.

[0024] This element further includes a field plate on the interlayer dielectric layer between the gate contact and the drain contact, where the field plate is laterally spaced from the gate. The embedded portion of the field plate is above an opening in the surface dielectric layer, and the field plate includes a first step adjacent to the embedded portion of the field plate on the side surface of the field plate on the side opposite to the gate, and a second step adjacent to the first step.

[0025] The embedded portion of the field plate is vertically spaced from the semiconductor barrier layer by a first distance, the first step is vertically spaced from the semiconductor barrier layer by a second distance, and the second step is vertically spaced from the semiconductor barrier layer by a third distance. The second distance is greater than the first distance, and the third distance is greater than the second distance.

Brief Description of the Drawings

[0026]

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Embodiments for Carrying Out the Invention

[0027] Next, embodiments of the inventive concept will be described in relation to the accompanying drawings. Some embodiments described herein provide a transistor element including a field plate that is automatically aligned with respect to a gate such that the field plate does not overlap the gate in the vertical direction, and in some embodiments, the field plate is laterally spaced from the gate. In some embodiments, the field plate is embedded toward a barrier layer in an embedded region. In yet another embodiment, the field plate may be connected to a source outside the active region of the element by a connection that does not cross over the gate of the element.

[0028] It should be understood that although ordinal numbers, such as first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be called a second element, and similarly, a second element could be called a first element without departing from the scope of this disclosure.

[0029] Furthermore, relative terms such as "lower" or "bottom", and "upper" or "top" may be used herein to describe the relationship of one element to another as shown in the drawings. It should be understood that relative terms are intended to encompass different orientations of the element in addition to the orientation depicted in the drawings. For example, if an element is turned over in one of the drawings, a feature described as being on the "lower" side of the element will be oriented towards the "upper" side of the element. Thus, the exemplary term "lower" can describe both downward and upward directions depending on the particular orientation of the element. Similarly, if an element is turned over in one of the drawings, an element described as "lower" or "below" another element will be oriented above those other elements. Thus, the exemplary terms "below" or "lower" can describe both upward and downward directions.

[0030] The terms used in the description of the disclosure herein are for the purpose of describing particular embodiments only and are not intended to limit the disclosure. When used in the description of the present disclosure and the appended claims, the singular forms "an" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. The terms "comprise" and "comprising" as used herein, when used, specify the presence of the stated steps, operations, features, elements, and / or components, but do not preclude the presence or addition of one or more other steps, operations, features, elements, components, and / or groups thereof.

[0031] Embodiments of the present disclosure are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments of the present disclosure. As such, variations from the shapes of the figures are to be expected, for example as a result of manufacturing techniques and / or tolerances. Accordingly, embodiments of the present disclosure should not be construed as being limited to the specific shapes of the regions illustrated herein, but should include, for example, departures in shape resulting from manufacturing. The regions illustrated in the drawings are essentially schematic, and their shapes are not intended to illustrate the actual shape of regions of elements, and are not intended to limit the scope of the disclosure, unless otherwise specified. Further, for schematic reasons, lines that appear straight, horizontal, or vertical in the following drawings will often be inclined, curved, non-horizontal, or non-vertical. Further, the thickness of elements is meant to be essentially schematic.

[0032] Unless otherwise defined, all terms used in disclosing embodiments of the present disclosure, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the relevant art, and are not necessarily limited to the specific definitions known at the time of the present disclosure. Accordingly, these terms can include equivalent terms created after such time. Further, terms such as those defined in commonly used dictionaries are to be understood as having a meaning consistent with their meaning in the context of the present specification and the relevant art.

[0033] Referring to FIG. 2A, transistor elements according to some embodiments are illustrated. In particular, FIG. 2A shows a high electron mobility transistor element 100A formed on a substrate 112. A channel layer 116 is formed on the substrate 112, and a barrier layer 118 is on the channel layer 116.

[0034] A source contact 122 and a drain contact 124 are formed on a channel layer 116. A gate 126 is formed on a barrier layer 118 between the source contact 122 and the drain contact 124. As shown in FIG. 2A, the gate 26 may have a mushroom configuration or a T-top configuration, in which the gate 126 contacts the barrier layer 118 in a relatively narrow contact region of the embedded contact portion 127 of the gate 126, and the embedded contact portion 127 extends through the surface dielectric layer 125 inside the gate opening 162 that passes through the surface dielectric layer 125. The width of the gate opening 162 may be from about 0.09 microns to about 0.4 microns.

[0035] The surface dielectric layer 125 also includes a field plate opening 164 that passes through the surface dielectric layer 125, exposing the barrier layer 118.

[0036] In some embodiments, the substrate 112 includes silicon carbide, the channel layer 116 includes GaN, and the barrier layer includes AlGaN. However, it will be understood that other materials or combinations of materials may also be used. Further, the channel layer 116 and / or the barrier layer 118 may include an alloy such as Al x Ga 1-x N, where 0 ≦ x ≦ 1. Although a HEMT device is illustrated, it will be further understood that the device 100A may be another type of transistor device such as a metal-semiconductor field effect transistor (MESFET), a junction field effect transistor (JFET), or a metal oxide semiconductor field effect transistor (MOSFET).

[0037] In the embodiment illustrated in FIG. 2A, the field plate 140 is laterally spaced from the gate 126 by the first interlayer dielectric layer 121, resulting in insufficient step coverage and the possibility of cracks occurring in the metallization of the field plate. As in the structure shown in FIG. 1, it does not overlap, extend over, or cross the gate 126. However, it will be understood that in some embodiments, the field plate 140 may overlap the gate 126 in the lateral dimension. The field plate 140 may be electrically connected to the source contact 122 outside the active region of the device (and outside the plane shown in FIG. 2A).

[0038] Similar to the gate 126, the field plate 140 may have a mushroom configuration or a T-top configuration, which includes a central embedded portion 144 and one or more wing portions extending laterally from the embedded portion 144 and is partially embedded. The central embedded portion 144 is above the field plate opening 164 and is vertically spaced from the barrier layer 118 by a distance d1 equal to the thickness of the first interlayer dielectric layer 121 within the region above the field plate opening 164.

[0039] In the embodiment shown in FIG. 2A, the field plate 140 includes a source-side wing 146 extending laterally towards the source contact 122 and a drain-side wing 148 extending laterally towards the drain contact 124. The central embedded portion 144 of the field plate 140 may be spaced from the barrier layer 118 by a distance d1 of about 0.1 micron to about 0.3 micron, and its width L3 may be about 0.3 micron to about 0.6 micron.

[0040] The drain-side wing 148 of the field plate 140 has a multi-step structure including a first stepped portion 148A adjacent to the central embedded portion 144.

[0041] The embedded portion 144 at the center of the field plate 140 is spaced entirely vertically from the barrier layer 118 by the surface dielectric layer 125. The first stepped portion 148A of the field plate 140 is spaced from the barrier layer 118 by the surface dielectric layer 125 and the first interlayer dielectric layer 121. The source-side wing 146 and the second stepped portion 148B of the field plate 140 are spaced from the barrier layer 118 by the surface dielectric layer 125, the first interlayer dielectric layer 121, and the second interlayer dielectric layer 123.

[0042] In some embodiments, the first stepped portion 148A is spaced from the barrier layer 118 by a distance d2, and the second stepped portion 148B adjacent to the first stepped portion 148A is spaced from the barrier layer 118 by a distance d3 greater than d2. The distance d2 may be from about 0.15 microns to about 0.4 microns. The distances d3 and d4 may be from about 0.25 microns to about 0.5 microns.

[0043] The width L4A of the first stepped portion 148A is from about 0.3 microns to about 0.6 microns, and the width L4B of the second stepped portion 148B is from about 0.3 microns to about 0.6 microns. The total width L4 of the drain-side wing 148 is from about 0.6 microns to about 1.2 microns.

[0044] In the embodiment illustrated in FIG. 2A, the distance d4 between the source-side wing 146 of the field plate 140 and the barrier layer 118 is equal to the total thickness of the first interlayer dielectric layer 121, the second interlayer dielectric layer 123, and the surface dielectric layer 125.

[0045] The field plate 140 has an overall width L1. The source-side wing 146 of the field plate 140 has a width L2, the embedded portion 144 of the field plate 140 has a width L3, and the drain-side wing 148 of the field plate 140 has a width L4. The field plate 140 is laterally spaced from the gate 126 by a distance L5. As will be described below, by adjusting the distances d1 to d4 and the widths L1 to L5, several degrees of freedom are provided for modulating the gate-source capacitance and the gate-drain capacitance of the device.

[0046] A passivation layer 132 is formed over the first interlayer dielectric layer 121, the second interlayer dielectric layer 123, and the field plate 140, and a field dielectric layer 134 is formed over the passivation layer 132. The passivation layer 132 may fill the gap between the field plate 140 and the gate 126 that is not filled by the first interlayer dielectric layer 121.

[0047] The surface dielectric layer 125, the first interlayer dielectric layer 121, the second interlayer dielectric layer 123, the passivation layer 132, and the field dielectric layer 134 may include one or more layers of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, or other atomic layer deposition films, or a multilayer insulator structure such as an oxide-nitride-oxide layer. In a particular embodiment, the surface dielectric layer 125, the first interlayer dielectric layer 121, and the second interlayer dielectric layer 123 include silicon nitride, the passivation layer 132 includes silicon oxynitride, and the field dielectric layer 134 includes silicon nitride.

[0048] Figure 2B illustrates a high electron mobility transistor device 100B according to yet another embodiment. The device 100B is similar to the device 100A shown in Figure 2A, except that the second interlayer dielectric layer 123 is excluded from the source side of the structure between the field plate 140 and the source contact 122, and as a result, the distance d4 between the source side wing 146 and the barrier layer 118 is defined only by the thickness of the surface dielectric layer 125 and the first interlayer dielectric layer 121. Thus, the distance d4 in the device 100B may be from about 0.15 microns to about 0.4 microns.

[0049] Figure 2C illustrates a high electron mobility transistor device 100C according to yet another embodiment. The device 100C is similar to the device 100A shown in Figure 2A, except that a third interlayer dielectric layer 147 is provided on the drain side of the structure on the second interlayer dielectric layer between the field plate 140 and the drain contact 124, and as a result, the field plate has a third stepped portion 148C adjacent to the second stepped portion 148B. The third stepped portion 148A is at a distance d5 from the barrier layer 118 that is greater than d3. The third stepped portion 148C is spaced from the barrier layer 118 by the combined thickness of the surface dielectric layer 125, the first interlayer dielectric layer 121, the second interlayer dielectric layer 123, and the third interlayer dielectric layer 147. It is understood that the field plate 140 may have more than three stepped portions by providing additional interlayer dielectric layers on the drain side of the structure.

[0050] Figure 3A shows a HEMT transistor device structure 200A according to yet another embodiment. The device 200 is similar to the device 100A shown in Figure 2A, and like numbers refer to like elements, except that the device 200 does not include the source side wing 146. That is, the distance between the embedded portion 144 of the field plate 140 and the gate 126 defines the distance L5 between the field plate 140 and the gate 126, and the width L2 of the source side wing 146 is zero.

[0051] In some embodiments, the distance d1 between the embedded portion 144 of the field plate 140 and the barrier layer 118 is from about 60 nm to about 300 nm, and in some embodiments, it is between about 100 nm and 200 nm. As described herein, embedding a portion of the field plate 140 can reduce the gate-drain capacitance Cgd, which can improve the efficiency, linearity, gain, and / or bandwidth of an amplifier fabricated using this device. Further, by using an etching process to form a field plate opening 164 in the surface dielectric layer 125 that defines the position of the embedded portion 144 of the field plate 140, it is possible to precisely control the position of the embedded portion 144, thereby improving the process repeatability and manufacturability of the device while also more precisely controlling the electrical characteristics of the device.

[0052] The overall width of the field plate 140 (L1 in FIGS. 2A and 3A) may be from about 0.6 to about 1.5 microns.

[0053] FIG. 3B illustrates a high electron mobility transistor device 200B according to yet another embodiment. The device 200B has a third interlayer dielectric layer 147 provided on the drain side of the structure on the second interlayer dielectric layer 123 between the field plate 140 and the drain contact 124, such that as a result, the device is similar to the device 200A shown in FIG. 3A except that the field plate has a third stepped portion 148C. The third stepped portion 148C is spaced apart from the barrier layer 118 by the combined thickness of the surface dielectric layer 125, the first interlayer dielectric layer 121, the second interlayer dielectric layer 123, and the third interlayer dielectric layer 147.

[0054] Separating the field plate 140 laterally from the gate 126 (e.g., by preventing the field plate 140 from overlapping the gate 126) can reduce the gate-drain capacitance Cgd and / or the drain-source capacitance Cds of the device by enhancing the ability of the field plate 140 to block the feedback capacitance from the gate to the drain. That is, overlapping the field plate 140 and the gate 126 can introduce additional parasitic capacitance without any additional benefit.

[0055] Providing the embedded portion 144 of the field plate 140 changes the drain-source capacitance Cds and the gate-drain capacitance Cgd of the device. In particular, providing the embedded portion 144 of the field plate 140 can reduce the gate-drain capacitance Cgd of the device, sometimes at the expense of increasing the drain-source capacitance Cds at low drain voltages for a specific level of drain voltage.

[0056] Separating the field plate 140 laterally from the gate 126 is thought to be able to improve the drain-source capacitance Cds while impairing the effect of the field plate 140 on the gate-drain capacitance Cgd. Therefore, the distance of the gap L5 between the field plate 140 and the gate 126 (as shown in FIGS. 2A and 3A) can be selected to reduce the gate-drain capacitance Cgd without adversely affecting the drain-source capacitance Cds. For example, in some embodiments, the gap L5 between the field plate 140 and the gate 126 may be from 0.2 microns to 0.7 microns. If the gap is less than 0.2 microns, reliability issues may occur, and if the gap exceeds 0.7 microns, the gate-drain capacitance Cgd may become undesirably high. In some embodiments, the gap L5 may be from about 0.2 microns to about 0.4 microns.

[0057] In some embodiments, the gate opening 162 and the field plate opening 164 may be formed to have chamfered or rounded edges. Chamfering or rounding the edges of the gate opening 162 and the field plate opening 164 results in a shape corresponding to the embedded contact portion 127 of the gate 126 and the embedded portion 144 of the field plate 140, which helps reduce field crowding around the gate 126 and the field plate 140.

[0058] The widths L2 and L4 of the source-side wing 146 and the drain-side wing 148 of the field plate 140 may also affect the gate-drain capacitance Cgd and / or the drain-source capacitance Cds of the device. The lengths of the wings 146 and 148 may involve a trade-off between the gate-drain capacitance Cgd and the drain-source capacitance Cds. For example, the drain-side wing 148 can reduce the gate-drain capacitance Cgd, but may increase the drain-source capacitance Cds. In particular, as described above, the drain-side wing 148 may have a length L4 from about 0.6 to about 1.2 microns. The source-side wing 146 may have a length L2 (FIGS. 2A and 3A) between about zero and 0.3 microns. In particular, the source-side wing 146 may have a length L2 of zero microns.

[0059] Furthermore, due to the reduced parasitic capacitance, the field plate 140 may not have to handle the same high level of current, and thus may be formed to have a smaller thickness than would be required otherwise.

[0060] By providing the stepped drain-side wing 148, the breakdown voltage in the off state of the devices 100A, 100B, and 200 can be increased while keeping the gate-drain capacitance Cgd and the gate-source capacitance Cgs low, which enables operation at higher operating voltages, higher frequencies, and / or higher power-added efficiencies than can be obtained without such features.

[0061] In some embodiments, this device can have a breakdown voltage in the off state greater than 230V with an off-state current of 1×10 -3 A / mm. In some embodiments, this device can have a breakdown voltage in the off state greater than 250V with an off-state leakage current of 1×10 -3 A / mm. In some embodiments, this device can have a breakdown voltage in the off state greater than 275V with an off-state leakage current of 1×10 -3 A / mm.

[0062] Providing the stepped drain-side wing 148 can slightly increase the drain-source capacitance Cds compared to a device without the stepped drain-side wing 148, which can limit the operation of this device for higher frequency applications (e.g., above about 10 GHz). However, this increased Cds does not substantially impede the operation of the device at frequencies lower than about 10 GHz.

[0063] For example, FIG. 4A is a graph of drain current (Id) as a function of drain voltage (Vd) from simulations for devices with (curve 402) and without (curve 404) a multi-stepped field plate. As shown in FIG. 4A, the breakdown voltage of the device with a multi-stepped field plate is approximately 60V higher (at a drain current of 1 mA / mm) than the breakdown voltage of the device without a multi-stepped field plate.

[0064] FIG. 4B is a graph of drain-source capacitance (Cds) by simulation as a function of drain-source voltage (Vds) for elements with (curve 412) and without (curve 414) a multi-step field plate. As shown in FIG. 4B, the Cds of the element with a multi-step field plate is slightly higher than that of the element without a multi-step field plate for Vds lower than about 130V. As described above, this may limit the performance of the element in high-frequency applications, but the increased Cds does not substantially inhibit the operation of the element at frequencies lower than about 10 GHz.

[0065] FIGS. 5A through 5H are cross-sectional views showing operations for manufacturing a transistor element including a field plate according to some embodiments.

[0066] Referring to FIG. 5A, a substrate 112 is provided on which a channel layer 116 and a barrier layer 118 are formed thereon. A preliminary surface dielectric layer 125' is formed on the barrier layer 118. A layer of photoresist 52 is formed on the preliminary surface dielectric layer 125' and patterned to form two holes 54, 56 therein.

[0067] Referring to FIG. 5B, the preliminary surface dielectric layer 125' is selectively etched through the two holes 54, 56, for example, using reactive ion etching or inductively coupled plasma, to form two corresponding holes 154, 156 therein.

[0068] Referring to FIG. 5C, a sacrificial dielectric layer 165 is blanket deposited on the preliminary surface dielectric layer 125' to fill the holes 154, 156. The sacrificial dielectric layer 165 may be formed of the same material as the preliminary surface dielectric layer 125'. For example, both the sacrificial dielectric layer 165 and the preliminary surface dielectric layer 125' may be formed of silicon nitride.

[0069] Referring to FIG. 5D, the sacrificial dielectric layer 165 is anisotropically etched, for example, using reactive ion etching or inductively coupled plasma 167 to remove portions of the sacrificial dielectric layer 165, except for the side portions 166 on the inner surface of the hole 154 of the preliminary surface dielectric layer 125' and the side portions 168 on the inner surface of the hole 156 of the preliminary surface dielectric layer 125', to form a gate opening 162 and a field plate opening 164 having rounded or chamfered edges as shown in FIG. 5E. Together with the side portions 166, 168, the preliminary surface dielectric layer 125' forms the surface dielectric layer 125 on the barrier layer 118. When the side portion 166 is present, the width of the gate opening 162 is about 250 nm.

[0070] Referring to FIG. 5F, a metal such as gold is deposited and patterned to form a mushroom gate or T-top gate 126 on the surface dielectric layer 125. The embedded contact portion of the gate 126 extends through the gate opening 162 and contacts the barrier layer 118. Next, the first interlayer dielectric layer 121 is blanket deposited over the surface dielectric layer 125 and the gate 126. The first interlayer dielectric layer 121 extends through the field plate opening 164 and contacts the barrier layer 118.

[0071] Referring to FIG. 5G, a second interlayer dielectric layer is blanket deposited over the first interlayer dielectric layer 121 and then masked and anisotropically etched, for example, by a timed etch, to form a second interlayer dielectric layer 123 over a portion of the drain region of the structure. In some embodiments, the first interlayer dielectric layer 121 and the second interlayer dielectric layer 123 may be formed of different materials, and as a result, the first interlayer dielectric layer 121 can act as an etch stop layer for etching the second interlayer dielectric layer 123. As described above, in some embodiments, the second interlayer dielectric layer 123 can be excluded from the source side of the structure.

[0072] Next, a metal such as gold is deposited on the first interlayer dielectric layer 121 above the field plate opening 164 and patterned to form the field plate 140. The field plate extends at least partially over the second interlayer dielectric layer 123 and forms a multi-step profile on the drain side of the field plate 140.

[0073] The field plate 140 is separated from the barrier layer 118 by a distance d1 that matches the thickness of the first interlayer dielectric layer 121 inside the field plate opening 164. In the drain side wing 148 of the field plate 140, the field plate 140 is separated from the barrier layer 118 by a distance d2 that matches the sum of the thicknesses of the first interlayer dielectric layer 121 and the surface dielectric layer 125 in the first stepped region 148A, and by a distance d3 that matches the sum of the thicknesses of the first interlayer dielectric layer 121, the second interlayer dielectric layer 123, and the surface dielectric layer 125 in the second stepped region 148B.

[0074] The field plate 140 is laterally separated from the gate 126 by a distance L6 that is approximately equal to the thickness of the first interlayer dielectric layer 121. Thus, the field plate 140 is automatically aligned with respect to the gate 126 by the distance L6.

[0075] Referring to FIG. 5H, a passivation layer 132, such as a layer of SiON, is formed over the field plate 140 and the first interlayer dielectric layer 121. Finally, a field dielectric layer 134, such as silicon nitride, is formed over the passivation layer 132.

[0076] Referring to FIG. 5I, in some embodiments, after the formation of the second interlayer dielectric layer 123, a third dielectric layer is blanket deposited over the first interlayer dielectric layer 121 and the second interlayer dielectric layer 123, masked, and anisotropically etched, for example, by time-controlled etching, to form a third interlayer dielectric layer 127 over a portion of the drain region of the structure. In some embodiments, the third interlayer dielectric layer 147 can be excluded from the source side of the structure.

[0077] Next, a metal such as gold is deposited over the first interlayer dielectric layer 121 above the field plate opening 164 and patterned to form the field plate 140. The field plate extends at least partially over the second interlayer dielectric layer 123 and the third interlayer dielectric layer 147, forming a multi-step profile on the drain side of the field plate 140. It is understood that a similar operation can be performed to form a field plate having more than three steps.

[0078] Referring to FIG. 5J, a passivation layer 132, such as a layer of SiON, is formed over the field plate 140 and the first interlayer dielectric layer 121. Finally, a field dielectric layer 134, such as silicon nitride, is formed over the passivation layer 132.

[0079] FIG. 6 is a block diagram showing an operation of forming a transistor element according to some embodiments. Referring to FIGS. 6 and 5A through 5H, a method of forming a transistor element according to some embodiments includes forming a surface dielectric layer 125 on a semiconductor layer (block 602), forming an opening 164 in the surface dielectric layer (block 604), forming a gate 126 on the surface dielectric layer 125, the gate being laterally spaced from the opening 164 (block 606), forming a first interlayer dielectric layer 121 on the gate and the surface dielectric layer 125, the surface dielectric layer extending into the opening 164 (block 608), and forming a multi-step field plate 140 on the first interlayer dielectric layer 121 above the opening 164 (block 610). The multi-step field plate 140 is laterally spaced from the gate. The embedded portion 144 of the multi-step field plate 149 is above the opening 164 in the surface dielectric layer, and the multi-step field plate 1140 includes a first stepped portion 148A adjacent to the embedded portion of the multi-step field plate 140 on the side surface of the multi-step field plate on the side opposite to the gate 126, and a second stepped portion 148B adjacent to the first stepped portion 148A.

[0080] The embedded portion 144 of the multi-step field plate is vertically spaced from the barrier layer 118 by a first distance, the first stepped portion 148A is vertically spaced from the barrier layer 118 by a second distance, and the second stepped portion 148B is vertically spaced from the barrier layer 118 by a third distance. The second distance is greater than the first distance, and the third distance is greater than the second distance.

[0081] This method may further include a step of forming a second opening 162 in the surface dielectric layer, wherein the first and second openings 164, 162 are laterally spaced apart from each other. The gate 126 is formed over the second opening 162 and includes an embedded contact portion 127 passing through the second opening 162. The embedded contact portion 127 of the gate may contact the barrier layer 118.

[0082] This method may further include a step of forming source and drain contacts 122, 124 over the barrier layer 118, wherein the gate 126 is between the source and drain contacts 122, 124. The field plate 140 may include an embedded portion 144 above the opening 164 and a drain-side wing 148 extending over the barrier layer 118 towards the drain contact 124. In some embodiments, the field plate 140 includes a source-side wing 146 extending over the barrier layer 118 towards the source contact 122.

[0083] The embedded portion 144 of the field plate 140 may be vertically spaced from the barrier layer 118 by a thickness of the first interlayer dielectric layer 121.

[0084] The drain-side wing 148 of the field plate may include a first stepped portion 148A vertically spaced from the barrier layer 118 by a combined thickness of the first interlayer dielectric layer 121 and the surface dielectric layer 125, and a second stepped portion 148B vertically spaced from the barrier layer 118 by a combined thickness of the first interlayer dielectric layer 121, the second interlayer dielectric layer 123, and the surface dielectric layer 125.

[0085] The steps of forming the first and second openings may include forming a preliminary surface dielectric layer 125' on the barrier layer 118, selectively etching the preliminary surface dielectric layer 125' to form the first and second holes 156, 154 in the preliminary surface dielectric layer 125', and depositing a sacrificial dielectric layer 165 on the barrier layer 118 and the preliminary surface dielectric layer 125', where the sacrificial dielectric layer 165 fills the first and second holes 156, 154. Anisotropic etching may be performed to expose the portions of the barrier layer 118 within the first and second holes 156, 154 and leave the lateral portions of the sacrificial dielectric layer 165 on the inner sidewalls of the holes 156, 154.

[0086] The transistor elements described herein can be used in amplifiers operating in a wide variety of different frequency bands. In some embodiments, an RF transistor amplifier incorporating transistor elements as described herein can be configured to operate at frequencies above 1 GHz. In other embodiments, the RF transistor amplifier can be configured to operate at frequencies above 2.5 GHz. In yet another embodiment, the RF transistor amplifier can be configured to operate at frequencies above 3.1 GHz. In still additional embodiments, the RF transistor amplifier can be configured to operate at frequencies above 5 GHz. In some embodiments, the RF transistor amplifier can be configured to operate in at least one of the frequency bands of 2.5 - 2.7 GHz, 3.4 - 4.2 GHz, 5.1 - 5.8 GHz, 12 - 18 GHz, 18 - 27 GHz, 27 - 40 GHz, or 40 - 75 GHz, or sub - portions thereof.

[0087] Although embodiments of the inventive concept have been discussed above with respect to HEMT elements, it will be understood that the inventive concept described herein can be applied to other types of semiconductor elements such as MOSFETs, DMOS transistors, and / or laterally diffused MOS (LDMOS) transistors.

[0088] The RF transistor amplifier incorporating the transistor element described in this specification can be used in a stand-alone RF transistor amplifier and / or multiple RF transistor amplifiers. Examples of how an RF transistor amplifier according to some embodiments can be used in applications including multiple amplifiers will be discussed with reference to FIGS. 7A-7C.

[0089] Referring to FIG. 7A, an RF transistor amplifier 1000A is schematically illustrated, which includes a preamplifier 1010 and a main amplifier 1030 that are electrically connected in series. As shown in FIG. 7A, the RF transistor amplifier 1000A includes an RF input 1001, a preamplifier 1010, an inter-stage impedance matching network 1020, a main amplifier 1030, and an RF output 1002. The inter-stage impedance matching network 1020 may include inductors and / or capacitors arranged in any suitable configuration, for example, to form a circuit that improves the impedance matching between the output of the preamplifier 1010 and the input of the main amplifier 1030. Although not shown in FIG. 7A, the RF transistor amplifier 1000A may further include an input matching network interposed between the RF input 1001 and the preamplifier 1010, and / or an output matching network interposed between the main amplifier 1030 and the RF output 1002. The RF transistor amplifier according to the embodiment may be used to implement either or both of the preamplifier 1010 and the main amplifier 1030.

[0090] Referring to FIG. 7B, an RF transistor amplifier 1000B including an RF input 1001, a pair of preamplifiers 1010-1 and 1010-2, a pair of inter-stage impedance matching networks 1020-1 and 1020-2, a pair of main amplifiers 1030-1 and 1030-2, and an RF output 1002 is schematically illustrated. A splitter 1003 and a combiner 1004 are also provided. The preamplifier 1010-1 and the main amplifier 1030-1 (electrically connected in series) and the preamplifier 1010-2 and the main amplifier 1030-2 (electrically connected in series) are arranged electrically in parallel. Similar to the RF transistor amplifier 1000A of FIG. 9A, the RF transistor amplifier 1000B may further include an input matching network interposed between the RF input 1001 and the preamplifiers 1010-1 and 1010-2, and / or an output matching network interposed between the main amplifiers 1030-1 and 1030-2 and the RF output 1002.

[0091] As shown in FIG. 7C, RF transistor amplifiers according to some embodiments can also be used to implement Doherty amplifiers. As is known in the art, a Doherty amplifier circuit includes first and second (or higher) power combining amplifiers. The first amplifier is called the "main" or "carrier" amplifier, and the second amplifier is called the "peaking" amplifier. The biasing of the two amplifiers may be different. For example, in one common Doherty amplifier implementation, the main amplifier may comprise a class AB or class B amplifier, while the peaking amplifier may be a class C amplifier. A Doherty amplifier can operate more efficiently than a balanced amplifier when operating at power levels that are backing off from saturation. The RF signal input to the Doherty amplifier is split (e.g., using a quadrature coupler), and the outputs of the two amplifiers are combined. The main amplifier is configured to turn on first (i.e., at a lower input power level), so that only the main amplifier operates at the lower power level. As the input power level increases towards saturation, the peaking amplifier turns on and the input RF signal is split between the main amplifier and the peaking amplifier.

[0092] As shown in FIG. 7C, the Doherty RF transistor amplifier 1000C includes an RF input 1001, an input splitter 1003, a main amplifier 1040, a peaking amplifier 1050, an output combiner 1004, and an RF output 1002. The Doherty RF transistor amplifier 1000C includes a 90° transformer 1007 at the input of the peaking amplifier 1050 and a 90° transformer 1005 at the input of the main amplifier 1040, and optionally may include an input matching network and / or an output matching network (not shown). The main amplifier 1040 and / or the peaking amplifier 1050 can be implemented using any of the above-described RF transistor amplifiers according to the embodiments.

[0093] The RF transistor amplifier according to the embodiments may be formed as discrete elements or as part of a monolithic microwave integrated circuit (MMIC). An MMIC refers to an integrated circuit that operates with radio frequency and / or microwave frequency signals in which all circuits of a specific function are integrated on a single semiconductor chip. An example of an MMIC element is a transistor amplifier that includes associated matching circuits, a power supply network, etc., all mounted on a common substrate. An MMIC transistor amplifier typically includes a plurality of unit cell HEMT transistors connected in parallel.

[0094] Many variations are possible with respect to the features of the above embodiments. Transistor structures having features that can be used in embodiments of the present invention are disclosed in the following commonly assigned publications, each of which is hereby incorporated by reference in its entirety: U.S. Patent No. 6,849,882, Chavarkar et al., "Group-III Nitride Based High Electron Mobility Transistor (HEMT) With Barrier / Spacer Layer"; U.S. Patent No. 7,230,284, Parikh et al., "Insulating Gate AlGaN / GaN HEMT"; U.S. Patent No. 7,501,669, Parikh et al., "Wide Bandgap Transistor Devices With Field Plates"; U.S. Patent No. 7,126,426, Mishra et al., "Cascode Amplifier Structures Including Wide Bandgap Field Effect Transistor With Field Plates"; U.S. Patent No. 7,550,783, Wu et al., "Wide Bandgap HEMTs With Source Connected Field Plates"; U.S. Patent No. 7,573,078, Wu et al., "Wide Bandgap Transistors With Multiple Field Plates"; U.S. Patent Application Publication No. 2005 / 0253167, Wu et al., "Wide Bandgap Field Effect Transistors With Source Connected Field Plates"; U.S. Patent Application Publication No. 2006 / 0202272, Wu et al., "Wide Bandgap Transistors With Gate-Source Field Plates"; U.S. Patent Application Publication No. 2008 / 0128752, Wu, "GaN Based HEMTs With Buried Field Plates"; U.S. Patent Application Publication No. 2010 / 0276698, Moore et al., "Gate Electrodes For Millimeter-Wave Operation and Methods of Fabrication";U.S. Patent Application Publication No. 2012 / 0049973, Smith, Jr. et al., "High Power Gallium Nitride Field Effect Transistor Switches"; U.S. Patent Application Publication No. 2012 / 0194276, Fisher, "Low Noise Amplifiers Including Group III Nitride Based High Electron Mobility Transistors"; and U.S. Patent No. 9,847,411, Sriram et al., "Recessed field plate transistor structures".;

[0095] Although embodiments of the inventive concept have been described in considerable detail with reference to its specific configurations, other versions are possible. The field plates and gates can also have many different shapes and can be connected to the source contact in various ways. Accordingly, the spirit and scope of the invention should not be limited to the specific embodiments described above.

Claims

1. A semiconductor barrier layer, a surface dielectric layer on the semiconductor barrier layer, a gate on the surface dielectric layer, wherein the surface dielectric layer includes an opening laterally spaced from the gate therein, an interlayer dielectric layer on the surface dielectric layer, wherein the interlayer dielectric layer extends over the gate and into the opening in the surface dielectric layer, a field plate on the interlayer dielectric layer, wherein the field plate is laterally spaced from the gate, an embedded portion of the field plate is above the opening in the surface dielectric layer, and the field plate includes a first step adjacent to the embedded portion of the field plate on a side surface of the field plate opposite to the gate and a second step adjacent to the first step, comprising, the embedded portion of the field plate is vertically spaced from the semiconductor barrier layer by a first distance, the first step is vertically spaced from the semiconductor barrier layer by a second distance, the second step is vertically spaced from the semiconductor barrier layer by a third distance, the second distance is greater than the first distance, and the third distance is greater than the second distance, a transistor element.

2. The transistor element according to claim 1, wherein the first distance is equal to a thickness of the interlayer dielectric layer.

3. The transistor element according to claim 2, wherein the second distance is equal to a sum of the thickness of the interlayer dielectric layer and the thickness of the surface dielectric layer.

4. The interlayer dielectric layer includes a first interlayer dielectric layer, and the third distance is equal to a sum of the thickness of the first interlayer dielectric layer, the thickness of the surface dielectric layer, and the thickness of a second interlayer dielectric layer on the first interlayer dielectric layer. The transistor element according to claim 3.

5. The transistor element according to claim 1, wherein the opening in the surface dielectric layer extends completely through the surface dielectric layer to expose the semiconductor barrier layer.

6. The transistor element according to claim 1, wherein the gate extends through the surface dielectric layer and contacts the semiconductor barrier layer.

7. The transistor device according to claim 2, further comprising source and drain contacts on the semiconductor barrier layer, wherein the gate is between the source and drain contacts, and the field plate includes a source-side wing extending over the semiconductor barrier layer and toward the source contact.

8. The transistor device according to claim 1, wherein the first distance is from about 0.1 to 0.3 microns.

9. The transistor device according to claim 1, wherein the second distance is from about 0.15 to 0.4 microns.

10. The transistor device according to claim 1, wherein the third distance is from about 0.25 to 0.5 microns.

11. The transistor device according to claim 1, wherein the width of the embedded portion of the field plate is from about 0.3 to 0.6 microns.

12. The transistor device according to claim 1, wherein the width of the first step is from about 0.3 to 0.6 microns.

13. The transistor device according to claim 1, wherein the width of the second step is from about 0.3 to 0.6 microns.

14. The transistor device according to claim 1, wherein the interlayer dielectric layer has a vertical thickness, and the field plate is laterally spaced from the gate by a distance substantially equal to the vertical thickness of the interlayer dielectric layer.

15. The transistor device according to claim 1, further comprising a third step adjacent to the second step, wherein the third step is vertically spaced from the semiconductor by a fourth distance greater than the third distance.

16. Forming a surface dielectric layer on the semiconductor barrier layer; Forming an opening in the surface dielectric layer to expose the semiconductor barrier layer; Forming a gate on the surface dielectric layer, laterally spaced from the opening; Forming an interlayer dielectric layer on the surface dielectric layer and the gate, wherein the interlayer dielectric layer extends into the opening in the surface dielectric layer over the gate. Forming a multi-step field plate on the interlayer dielectric layer, the multi-step field plate being laterally spaced from the gate, an embedded portion of the multi-step field plate being above the opening in the surface dielectric layer, the multi-step field plate including a first step adjacent to the embedded portion of the multi-step field plate on a side surface of the multi-step field plate on the side opposite to the gate and a second step adjacent to the first step. Including The embedded portion of the multi-step field plate is vertically spaced from the semiconductor barrier layer by a first distance, the first step is vertically spaced from the semiconductor barrier layer by a second distance, the second step is vertically spaced from the semiconductor barrier layer by a third distance, the second distance is greater than the first distance, and the third distance is greater than the second distance. A method of forming a transistor element.

17. The method according to claim 16, wherein the first distance is equal to the thickness of the interlayer dielectric layer.

18. The method according to claim 17, wherein the second distance is equal to the sum of the thickness of the interlayer dielectric layer and the thickness of the surface dielectric layer.

19. The interlayer dielectric layer includes a first interlayer dielectric layer, and the third distance is equal to the sum of the thickness of the first interlayer dielectric layer, the thickness of the surface dielectric layer, and the thickness of a second interlayer dielectric layer on the first interlayer dielectric layer. The method according to claim 18.

20. The method according to claim 16, wherein the opening in the surface dielectric layer extends completely through the surface dielectric layer to expose the semiconductor barrier layer.

21. The method according to claim 16, wherein the multi-step field plate further includes a third step adjacent to the second step, and the third step is vertically spaced from the semiconductor by a fourth distance greater than the third distance.

22. A channel layer, A semiconductor barrier layer on the channel layer, A surface dielectric layer on the semiconductor barrier layer, A gate on the surface dielectric layer, the surface dielectric layer including an opening laterally spaced from the gate therein. Source and drain contacts on the semiconductor barrier layer, wherein the gate is between the source and drain contacts, the source and drain contacts, and An interlayer dielectric layer on the surface dielectric layer, wherein the interlayer dielectric layer extends over the gate and into the opening in the surface dielectric layer, the interlayer dielectric layer, and A field plate on the interlayer dielectric layer between the gate contact and the drain contact, wherein the field plate is laterally spaced from the gate, an embedded portion of the field plate is above the opening in the surface dielectric layer, and the field plate includes a first step adjacent to the embedded portion of the field plate on a side surface of the field plate opposite the gate and a second step adjacent to the first step, the field plate and Comprising The embedded portion of the field plate is vertically spaced from the semiconductor barrier layer by a first distance, the first step is vertically spaced from the semiconductor barrier layer by a second distance, the second step is vertically spaced from the semiconductor barrier layer by a third distance, the second distance is greater than the first distance, and the third distance is greater than the second distance, a high electron mobility transistor device.

23. A channel layer, and A barrier layer on the channel layer, and Source and drain contacts on the barrier layer, and A gate contact on the barrier layer between the source contact and the drain contact A high electron mobility transistor device comprising The high electron mobility transistor has an off-state current of 1×10 －３ A / mm and a breakdown voltage in the off state greater than 230 V, which is a high electron mobility transistor element.

24. The high electron mobility transistor has a leakage current in the off state of 1×10 －３ A / mm and a breakdown voltage in the off state greater than 250 V, the high electron mobility transistor according to claim 23.

24. The high electron mobility transistor has a leakage current in the off state of 1×10 －３ A / mm and a breakdown voltage in the off state greater than 275 V, the high electron mobility transistor according to claim 23.

25. The high electron mobility transistor according to claim 23, wherein the barrier layer includes aluminum nitride and the channel layer includes gallium nitride.

26. A surface dielectric layer on the barrier layer, wherein the surface dielectric layer includes an opening therein that is laterally spaced from the gate, the surface dielectric layer, and An interlayer dielectric layer on the surface dielectric layer, wherein the interlayer dielectric layer extends over the gate and into the opening in the surface dielectric layer, the interlayer dielectric layer, and A field plate on the interlayer dielectric layer, the field plate being laterally spaced from the gate, an embedded portion of the field plate being above the opening in the surface dielectric layer, the field plate including a first step adjacent to the embedded portion of the field plate on a side surface of the field plate on a side opposite to the gate, and a second step adjacent to the first step, the field plate further comprising wherein the embedded portion of the field plate is vertically spaced from the semiconductor barrier layer by a first distance, the first step is vertically spaced from the semiconductor barrier layer by a second distance, the second step is vertically spaced from the semiconductor barrier layer by a third distance, the second distance is greater than the first distance, and the third distance is greater than the second distance, the high electron mobility transistor according to claim 23.

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