Semiconductor device and method of manufacturing the same

Abstract

The present invention relates to a semiconductor device and a method for manufacturing the same. The semiconductor device includes a high-voltage device region, a low-voltage device region, and an insulating region located between the high-voltage device region and the low-voltage device region. Further, it includes a drift region, a second-conductivity-type well region, an insulating well region, an insulating structure, a power device source region, and a power device drain region. The drift region is provided in the high-voltage device region. The second-conductivity-type well region is provided in the insulating region and extends to the low-voltage device region. The insulating well region is provided in the drift region. The insulating well region divides the drift region into a high-voltage drift region and a power device drift region. The insulating structure is provided within the insulating well region. The power device source region is provided in the insulating region and is located within the second-conductivity-type well region. The power device drain region is provided in the power device drift region. By using the semiconductor device, it is possible to reduce the leakage current flowing from the high-voltage device region through the drift region to the power device, without affecting the breakdown voltage of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, particularly to semiconductor devices, and further to a method for manufacturing semiconductor devices.

Background Art

[0002] High-voltage integrated circuits usually include high-voltage integrated circuits, low-voltage integrated circuits, and high-voltage power devices. Among these, for high-voltage power devices, a "source surrounding drain" track type structure is usually used. However, in a method where the source in such a high-voltage power device is connected to a low voltage and the drain is connected to a high voltage, a high-voltage jumper wire passes through the drift region of the device, which affects the breakdown voltage of the device. In addition, there are also drawbacks such as leakage current between the high-voltage integrated circuit and the drain, and the device area of the high-voltage integrated circuit becoming too large.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Based on the above, the present application provides a semiconductor device and a method for manufacturing the same in order to solve at least one of the above-described technical problems.

Means for Solving the Problems

[0004] The semiconductor device includes a high-voltage device region, a low-voltage device region, and an insulating region located between the high-voltage device region and the low-voltage device region. Further, a drift region provided in the high-voltage device region and having a first conductivity type, and a second conductivity type well region provided in the insulating region and extending to the low-voltage device region, wherein the first conductivity type and the second conductivity type are opposite to each other; an insulating well region having the second conductivity type, provided in the drift region, and dividing the drift region into a high-voltage drift region and a power device drift region; an insulating structure provided in the insulating well region and including a conductive structure and a dielectric layer surrounding the bottom surface and side surfaces of the conductive structure; a power device source region provided in the insulating region and located within the second conductivity type well region and having the first conductivity type; and a power device drain region provided in the power device drift region and having the first conductivity type.

[0005] In one embodiment, the power device drift region is completely surrounded by a region surrounded by the insulating well region and the second conductivity type well region.

[0006] In one embodiment, a plurality of trenches are provided at intervals within the insulating well region. The trenches extend from the upper surface of the insulating well region into the insulating well region, and the insulating structure is provided in the trenches.

[0007] In one embodiment, each of the trenches is provided at equal intervals.

[0008] In one embodiment, the trenches further continue to extend to the bottom of the insulating well region.

[0009] In one embodiment, trenches extending from the upper surface of the insulating well region into the insulating well region are provided within the insulating well region. The depth of the trenches is the same as the depth of the insulating well region, and the insulating structure is provided in the trenches.

[0010] In one embodiment, the material of the dielectric layer includes silicon oxide, and / or the material of the conductive structure includes polysilicon.

[0011] In one embodiment, a potential is externally connected to the conductive structure.

[0012] In one embodiment, the power device is a laterally diffused metal oxide semiconductor field effect transistor LDMOS.

[0013] In one embodiment, the power device further includes a field oxide layer provided in the drift region of the power device, a gate provided in the field oxide layer and extending to cover a part of the source region of the power device, and a substrate extraction region having a second conductivity type and provided in the low voltage device region and located within the second conductivity type well region.

[0014] A method for manufacturing a semiconductor device includes the following.

[0015] Form a drift region in the high voltage device region. The drift region has a first conductivity type.

[0016] Form a second conductivity type well region in the insulating region. The second conductivity type well region further extends to the low voltage device region. Also, form an insulating well region in the drift region to divide the drift region into a high voltage drift region and a power device drift region. Note that the first conductivity type and the second conductivity type are opposite.

[0017] Form an insulating structure in the insulating well region. The insulating structure includes a conductive structure and a dielectric layer surrounding the bottom surface and side surfaces of the conductive structure.

[0018] Form a power device source region. The power device source region is provided in the insulating region and is located within the second conductivity type well region. And, form a power device drain region located within the power device drift region. Both the power device source region and the power device drain region have the first conductivity type.

[0019] In one embodiment, forming an insulating structure within the insulating well region as described above includes the following.

[0020] By etching the insulating well region downward, form at least one trench within the insulating well region.

[0021] Form the dielectric layer on the inner wall of each trench.

[0022] Form a conductive structure to be filled in the trench.

Effect of the Invention

[0023] According to the above semiconductor device and its manufacturing method, firstly, an insulating structure is provided in the insulating well region. Therefore, in the process where the high-voltage current passes through the high-voltage drift region and flows into the power device, the dielectric layer of the insulating structure exerts an electrical insulation effect, thereby reducing the leakage current flowing from the high-voltage device region through the high-voltage drift region into the power device. Secondly, by introducing a new depletion region between the insulating well region and the high-voltage drift region, and between the insulating well region and the power device drift region, the peak electric field value in the drift region and the power device drain region of the substrate increases. However, the conductive structure, dielectric layer, and insulating well region constitute a capacitor effect similar to a conductive material - dielectric material - semiconductor. As a result, while being able to assist in the depletion of the drift region, when blocking the reverse current of the power device, it is also possible to push the equipotential line at the bottom of the drift region into the insulating structure. Therefore, the peak electric field value caused by the introduction of the insulating well region is extremely reduced. In this way, by using the semiconductor device, it is possible to reduce the leakage current flowing from the high-voltage device region through the drift region into the power device, and at the same time, it will not affect the breakdown voltage of the semiconductor device.

[0024] For a more solid description and explanation of the embodiments and / or exemplifications of the invention disclosed herein, reference may be made to one or more drawings. It should be noted that additional details or exemplifications for explaining the drawings should not be regarded as limiting the scope of any of the invention disclosed, the embodiments and / or exemplifications currently described, and the optimal form of the invention currently understood.

Brief Description of the Drawings

[0025]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

BEST MODE FOR CARRYING OUT THE INVENTION

[0026] For easier understanding of the present invention, the present invention will be described more comprehensively below with reference to the related drawings. The drawings show the most preferred embodiments of the present invention. However, the present invention can be realized in many different forms and is not limited to the embodiments described in the text. Rather, these embodiments are provided for the purpose of making the disclosure of the present invention clearer and more comprehensive.

[0027] Unless otherwise defined, all technical and scientific terms used in the text have the same meaning as commonly understood by those skilled in the art. Also, in the text, the terms used in the specification of the present invention are for the purpose of only describing specific embodiments and are not intended to limit the present invention. Further, the term "and / or" used in the text includes any and all combinations of one or more of the listed related items.

[0028] It should be understood that when an element or layer is described as being "on another element or layer", "adjacent to another element or layer", "connected to another element or layer", or "coupled to another element or layer", it may be directly on, adjacent to, connected to, or coupled to another element or layer, or there may be intervening elements or layers. Conversely, when an element is described as being "directly on another element or layer", "directly adjacent to another element or layer", "directly connected to another element or layer", or "directly coupled to another element or layer", there are no intervening elements or layers. It should be understood that terms such as first, second, third, etc. can be used to describe various elements, members, regions, layers, and / or portions, but these elements, members, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, member, region, layer, or portion from another. Thus, on the premise of not departing from the teachings of the present invention, the first element, member, region, layer, or portion discussed below may be referred to as the second element, member, region, layer, or portion.

[0029] For example, spatially relative terms such as "under", "below", "lower", "under in", "above in", "upper", etc. may be used herein for convenience of description to explain the relationship between one element or feature shown in the figures and other elements or features. It should be understood that spatially relative terms are intended to include not only the directions shown in the figures but also different directions of the device during use and operation. For example, after inverting the device in the figures, an element or feature described as "below another element", or "beneath it", or "under it" will be in the "above" direction of the other element or feature. Thus, the exemplary terms "below" and "under" can include both the up and down directions. Also, the device can assume another orientation (a 90-degree rotation or other orientation), and the spatially representative terms used in that case will be interpreted accordingly.

[0030] The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the present invention. Also, as used herein, the singular forms "a", "one", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. Further, it should be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the described features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. Also, as used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0031] Herein, embodiments of the present invention will be described with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the present invention. Thereby, for example, changes from the indicated shape due to manufacturing techniques and / or tolerances can be predicted. Therefore, embodiments of the present invention are not limited to the specific shapes of the regions shown herein, and are intended to include, for example, shape errors due to manufacturing. For example, an implantation region shown as a rectangle typically has rounded or curved features and / or an implantation concentration gradient at the edges, and does not change binary from the implantation region to the non-implantation region. Similarly, an embedded region formed by implantation can cause implantation in the region between the embedded region and the surface through which implantation occurs. Therefore, the regions shown in the figures are substantially schematic. Their shapes are not intended to represent the actual shapes of the regions of the device, nor are they intended to limit the scope of the present invention.

[0032] Vocabulary in the semiconductor field used in the present text are technical terms commonly used by those skilled in the art. For example, for P-type and N-type impurities, for the purpose of distinguishing doping concentrations, simply, P+ type represents a P-type with a high doping concentration, P type represents a P-type with a medium doping concentration, P- type represents a P-type with a low doping concentration, N+ type represents an N-type with a high doping concentration, N type represents an N-type with a medium doping concentration, and N- type represents an N-type with a low doping concentration.

[0033] FIG. 1 is a perspective view of a semiconductor device according to an embodiment, and FIG. 2 is a cross-sectional view of the semiconductor device according to an embodiment.

[0034] Referring to FIGS. 1 and 2. The semiconductor device provided in an embodiment of the present application includes a high-voltage device region 101, a low-voltage device region 102, and an insulating region located between the high-voltage device region 101 and the low-voltage device region 102. Further, the semiconductor device includes a drift region 200, a second-conductivity-type well region 310, an insulating well region 320, a power device source region 500, a power device drain region 600, and an insulating structure 700.

[0035] In an embodiment of the present application, the substrate 100 includes a high-voltage device region 101, a low-voltage device region 102, and an insulating region located between the high-voltage device region 101 and the low-voltage device region 102.

[0036] The drift region 200 is provided in the high-voltage device region 101. Also, the second-conductivity-type well region 310 is provided in the insulating region and extends to the low-voltage device region 102. The drift region 200 has a first conductivity type. The first conductivity type is opposite to the second conductivity type. One of the first conductivity type and the second conductivity type is P-type, and the other is N-type. For example, the first conductivity type is N-type and the second conductivity type is P-type. Alternatively, the first conductivity type is P-type and the second conductivity type is N-type. In an embodiment of the present application, the first conductivity type is N-type and the second conductivity type is P-type. Therefore, the conductivity type of the second-conductivity-type well region 310 is P-type, and the conductivity type of the drift region 200 is N-type.

[0037] The insulating well region 320 is provided in the drift region 200. The insulating well region 320 divides the drift region 200 into a high-voltage drift region 210 and a power device drift region 220. The insulating structure 700 is provided in the insulating well region 320. The insulating structure 700 includes a dielectric layer 710 and a conductive structure 720. The dielectric layer 710 surrounds the bottom surface and the side surfaces of the conductive structure 720. Since the dielectric layer 710 is provided in the insulating well region 320, the charges between the doping ions in the drift region 200 and the insulating structure 700 are more easily balanced. This is advantageous for the peak value of the electric field in the drift region 200 and the power device drain region 600 of the substrate 100 to move to the insulating structure 700 in the insulating well region 320, and it is possible to effectively avoid the early breakdown during the reverse voltage withstand of the semiconductor device.

[0038] The power device source region 500 is provided in the insulating region and is located in the second conductivity type well region 310. The power device source region 500 has the first conductivity type. Also, the power device drain region 600 is provided in the power device drift region 220. The power device drain region 600 has the first conductivity type.

[0039] The insulating well region 320 has a second conductivity type, and the high-voltage drift region 210 and the power device drift region 220 have a first conductivity type. A parasitic PN diode is formed between the insulating well region 320 and the high-voltage drift region 210, and a parasitic PN diode is also formed between the insulating well region 320 and the power device drift region 220. When the device in the high-voltage device region 101 is energized, during the process that the high-voltage current passes through the high-voltage drift region 210 and flows into the power device, a reverse bias is generated in the parasitic PN diode formed between the insulating well region 320 and the power device drift region 220. As a result, the concentration of conductive particles near the interfaces between the insulating well region 320 and the high-voltage drift region 210, and between the insulating well region 320 and the power device drift region 220 decreases. Consequently, the parasitic resistance formed between the insulating well region 320 and the high-voltage drift region 210, and between the insulating well region 320 and the power device drift region 220 increases, and the conductive performance deteriorates, so that the leakage current flowing from the high-voltage device region 101 through the drift region 200 to the power device decreases.

[0040] In the above semiconductor device, first, an insulating structure 700 is provided in the insulating well region 320. Therefore, in the process where a high-voltage current passes through the high-voltage drift region 210 and flows into the power device, the dielectric layer 710 of the insulating structure 700 exerts an electrical insulation effect, thereby reducing the leakage current flowing from the high-voltage device region 101 through the high-voltage drift region 210 and into the power device. Second, by introducing a new depletion region between the insulating well region 320 and the high-voltage drift region 210, and between the insulating well region 320 and the power device drift region 220, the peak electric field value in the drift region 200 and the power device drain region 600 of the substrate 100 increases. However, the conductive structure 720, the dielectric layer 710, and the insulating well region 320 constitute a capacitor effect similar to a conductive material-dielectric material-semiconductor. Thereby, while being able to assist in the depletion of the drift region 200, when blocking the reverse current of the power device, it is also possible to push the equipotential line at the bottom of the drift region 200 into the insulating structure 700. Therefore, the peak electric field value caused by the introduction of the insulating well region 320 is extremely reduced. In this way, by using the semiconductor device, it is possible to reduce the leakage current flowing from the high-voltage device region 101 through the drift region 200 and into the power device, and at the same time, it will not affect the breakdown voltage of the semiconductor device.

[0041] In one embodiment of the present application, the semiconductor device further includes a high-voltage power supply extraction region 400 provided in the high-voltage drift region 210 for externally connecting a high-voltage power supply.

[0042] In one embodiment of the present application, referring to FIG. 1, the power device drift region 220 is completely surrounded by a region surrounded by the insulating well region 320 and the second conductivity type well region 310.

[0043] In one embodiment of the present application, the insulating well region 320 is connected to the second conductivity type well region 310. In the embodiment shown in FIG. 1, the insulating well region 320 and the second conductivity type well region 310 surround the power device drift region 220 on three surfaces. When a reverse bias occurs in the parasitic PN diode formed between the insulating well region 320 and the power device drift region 220, the parasitic resistance formed between the insulating well region 320 and the power device drift region 220 increases. Therefore, by combining the insulating well region 320 to surround the power device drain region 600, in the process of high-voltage current passing through the drift region 200 and flowing into the power device drain region 600 of the power device, the insulating well region 320 can be better utilized to reduce the leakage current flowing into the power device drain region 600 of the power device. As a result, the reliability of the semiconductor device is improved.

[0044] In one embodiment of the present application, referring to FIG. 1, a plurality of trenches are provided in the insulating well region 320 at intervals. The trenches extend from the upper surface of the insulating well region 320 into the insulating well region 320. Also, an insulating structure 700 is provided in each trench.

[0045] As can be understood, the plurality of trenches surround the power device drain region 600. And the insulating structure 700 provided in each trench can form a capacitor effect similar to a conductive material - dielectric material - semiconductor, so it can assist in the depletion of the drift region 200, and when blocking the reverse current of the power device, it is also possible to push the equipotential line at the bottom of the drift region 200 into the plurality of insulating structures 700. As a result, the peak value of the electric field caused by the introduction of the insulating well region 320 is greatly reduced, so that the leakage current flowing into the power device drain region 600 of the power device can be better reduced. Therefore, while improving the reliability of the semiconductor device, it does not affect the breakdown voltage resistance of the semiconductor device.

[0046] In one embodiment of the present application, each trench is provided at equal intervals. By doing so, the capacitors between two adjacent insulating structures 700 can be regarded as equivalent.

[0047] In one embodiment of the present application, referring to FIGS. 1 and 2, the trench further continues to extend to the bottom of the insulating well region 320. By doing so, the potential of the ceiling portion of the conductive structure 720 can be made equal to the potential of the bottom portion of the conductive structure 720, which is advantageous for constituting a capacitor effect similar to a conductive material - dielectric material - semiconductor by the conductive structure 720, the dielectric layer 710, and the insulating well region 320. As a result, when blocking reverse current in the power device, the equipotential line at the bottom of the drift region 200 can be pushed into the bottom of the conductive structure 720, so that the peak value of the electric field caused by the introduction of the insulating well region 320 is extremely greatly reduced.

[0048] In one embodiment of the present application, a trench extending from the upper surface of the insulating well region 320 into the insulating well region 320 is provided in the insulating well region 320. The depth of the trench is the same as the depth of the insulating well region 320, and an insulating structure 700 is provided in the trench. Since the insulating structure 700 can constitute a capacitor effect similar to a conductive material - dielectric material - semiconductor, it can assist in depleting the drift region 200 and, when blocking reverse current in the power device, can also push the equipotential line at the bottom of the drift region 200 into the insulating structure 700. As a result, the peak value of the electric field caused by the introduction of the insulating well region 320 is extremely greatly reduced, so that the leakage current flowing into the power device drain region 600 of the power device can be better reduced. Therefore, while improving the reliability of the semiconductor device, it does not affect the breakdown voltage resistance of the semiconductor device.

[0049] In one embodiment of the present application, the material of the dielectric layer 710 includes silicon oxide. Silicon oxide belongs to insulating materials. Thus, by electrically insulating the high-voltage drift region 210 and the power device drift region 220 using an insulating material, the leakage current flowing from the high-voltage device region 101 through the high-voltage drift region 210 to the power device drain region 600 of the power device can be better reduced. Exemplarily, the silicon oxide is silicon dioxide.

[0050] In one embodiment of the present application, the material of the conductive structure 720 includes polysilicon. If the trench is filled with a polysilicon material, it becomes easy to fill the trench and relatively stable. Moreover, a desired resistance value can be obtained by direct impurity implantation or in-situ doping for the polysilicon material (according to the in-situ doping method, it is easy to adjust the resistance of the conductive structure 720). Further, in other embodiments, as the material of the conductive structure 720, other conductive materials well-known in the art may be used.

[0051] In one embodiment of the present application, a potential is externally connected to the conductive structure 720 such that a forward voltage is applied when the device in the high-voltage device region 101 is energized.

[0052] As described above, since the insulating structure 700 can constitute a capacitor effect similar to a conductive material - dielectric material - semiconductor, when a high voltage is applied to the power device drain region 600 and the high-voltage device region 101 when the device in the high-voltage device region 101 is energized, the power device drain region 600 and the high-voltage device region 101 are depleted toward the power device drift region 220. Further, since the depletion of the insulating well region 320 is assisted by applying a forward voltage to the conductive structure 720, it is possible to avoid a situation where the power lines generated due to the introduction of the insulating well region 320 drop to the power device drift region 220. Thereby, the leakage current is reduced and the influence on the breakdown voltage level is almost eliminated.

[0053] In one embodiment of the present application, the power device is a laterally diffused metal oxide semiconductor field effect transistor LDMOS.

[0054] A part of the high-voltage device region 101 and a part of the low-voltage device region 102 are used for the manufacture of LDMOS, but the part not surrounded by the insulating well region 320 in the drift region 200 remains belonging to the high-voltage device region 101. That is, in the present application, LDMOS is embedded in the region between the high-voltage device region 101 and the low-voltage device region 102. Therefore, since an extra region for providing LDMOS alone is not required, the device area is saved and the integration degree of the chip is improved. Moreover, since it is not necessary to use a "source surrounds drain" track type structure for LDMOS, there is no problem that the high-voltage current flowing into the drift region 200 affects the breakdown voltage of the device.

[0055] In one embodiment of the present application, the LDMOS, the device in the high-voltage device region 101, and the device in the low-voltage device region 102 belong to the same drive circuit. Also, the LDMOS is used for level shift. In one embodiment of the present application, the power device further includes a field oxide layer 810, a gate 820, and a substrate extraction region 900. The field oxide layer 810 is provided in a part of the power device drift region 220, and the gate 820 is provided in the second-conductivity-type well region 310 of the insulating region. Moreover, one side of the gate 820 extends to cover up to the field oxide layer 810. Also, the other side of the gate 820 extends to cover up to a part of the power device source region 500. The substrate extraction region 900 is provided in the low-voltage device region 102, is located in the second-conductivity-type well region 310, is located on the side opposite to the gate 820 in the power device source region 500, and is provided at an interval from the power device source region 500. The substrate extraction region 900 has the second conductivity type. It should be pointed out that in FIG. 1, in order to show the planar structure of the insulating well region 320 and the insulating structure 700, only one surface of the field oxide layer 810 is described.

[0056] The power device source region 500 is led out as the source of the power device, the power device drain region 600 is led out as the drain of the power device, and the substrate lead-out region 900 is used to lead out the substrate terminal of the power device.

[0057] One side of the gate 820 extends to cover a part of the power device source region 500. In the process of forming the power device, the gate 820 can serve as an implantation barrier layer in the implantation doping of the power device source region 500. Thereby, by performing self-aligned implantation on the power device source region 500, the width of the conductive channel of the power device is guaranteed.

[0058] This application preferably provides a method for manufacturing a semiconductor device that enables the manufacture of the semiconductor device of any of the above-described embodiments. FIG. 3 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment. The method includes steps S110, S120, S130, and S140.

[0059] In step S110, a drift region is formed in the high-voltage device region. The drift region has a first conductivity type.

[0060] In step S120, a second conductivity type well region is formed in the insulating region. The second conductivity type well region further extends to the low-voltage device region. Also, an insulating well region is formed in the drift region to divide the drift region into a high-voltage drift region and a power device drift region. Note that the first conductivity type and the second conductivity type are opposite.

[0061] In step S130, an insulating structure is formed in the insulating well region. The insulating structure includes a conductive structure and a dielectric layer surrounding the bottom surface and side surfaces of the conductive structure.

[0062] In step S140, a power device source region is formed. The power device source region is provided in the insulating region and is located within the second conductivity type well region. Also, a power device drain region located within the power device drift region is formed. Both the power device source region and the power device drain region have the first conductivity type.

[0063] According to the semiconductor device manufactured by the manufacturing method of the semiconductor device, it is possible to reduce the leakage current flowing from the high-voltage device region through the drift region to the power device, and it will no longer affect the breakdown voltage of the semiconductor device.

[0064] In one embodiment of the present application, before step S110, further providing a substrate 100 is included. The substrate 100 includes a high-voltage device region 101, a low-voltage device region 102, and an insulating region located between the high-voltage device region 101 and the low-voltage device region 102.

[0065] In one embodiment of the present application, referring to FIG. 4, forming an insulating structure within the insulating well region includes the following.

[0066] In step S131, by etching the insulating well region downward, at least one trench is formed within the insulating well region.

[0067] In step S132, a dielectric layer is formed on the inner wall of each trench.

[0068] In step S133, a conductive structure to be filled in the trench is formed.

[0069] In some embodiments, the material of the dielectric layer is silicon oxide, for example, silicon dioxide. Also, the material of the conductive structure is polysilicon.

[0070] In one embodiment of the present application, a long trench extending from the upper surface of the insulating well region into the insulating well region is formed within the insulating well region. Moreover, the depth of the trench is the same as the depth of the insulating well region, and an insulating structure is formed within the trench.

[0071] In one embodiment of the present application, a silicon oxide layer may be formed as a dielectric layer on the inner wall of the trench by thermal oxidation. Also, in other embodiments, a dielectric layer may be formed on the inner wall of the trench by other processes well-known in the art.

[0072] In one embodiment of the present application, polysilicon is selected for the conductive structure within the trench. Then, by depositing polysilicon with a certain doping concentration within the trench through a deposition process, a conductive structure can be formed on the dielectric layer.

[0073] In one embodiment of the present application, the resistance value of the polysilicon can be adjusted by adjusting the doping concentration of the polysilicon through a doping process such as in-situ doping.

[0074] In one embodiment of the present application, the ceiling of the trench and the ceiling of the drift region are flush. By doing so, the ceiling of the conductive structure filled within the trench also becomes flush with the ceiling of the drift region. Thereby, the leakage current flowing from the high-voltage device region through the drift region to the power device can be reduced more favorably.

[0075] In one embodiment of the present application, forming an insulating structure within the insulating well region includes the following.

[0076] By etching the insulating well region downward, a plurality of trenches arranged at intervals along the extending direction of the insulating well region are formed within the insulating well region.

[0077] A dielectric layer is formed on the inner wall of each trench.

[0078] A conductive structure to be filled in the trench is formed.

[0079] In one embodiment of the present application, by means of a doping process, ions of a first conductivity type are implanted into a part of the upper surface layer of a second conductivity type well region, thereby forming a power device source region in a part of the upper surface layer of the second conductivity type well region.

[0080] In one embodiment of the present application, by means of a doping process, ions of a first conductivity type are implanted into a part of the upper surface layer of a power device drift region, thereby forming a power device drain region in a part of the upper surface layer of the power device drift region.

[0081] FIG. 5 is a flowchart of a method for manufacturing a semiconductor device in another embodiment.

[0082] In one embodiment of the present application, referring to FIG. 5, the method for manufacturing a semiconductor device includes steps S210, S220, S230, S240, S250, and S260.

[0083] In step S210, a drift region is formed in a high-voltage device region. The drift region has a first conductivity type.

[0084] In step S220, a second conductivity type well region is formed in an insulating region. The second conductivity type well region further extends to a low-voltage device region. Also, an insulating well region is formed in the drift region to divide the drift region into a high-voltage drift region and a power device drift region. Note that the first conductivity type and the second conductivity type are opposite.

[0085] In step S230, an insulating structure is formed in the insulating well region. The insulating structure includes a conductive structure and a dielectric layer surrounding the bottom surface and side surfaces of the conductive structure.

[0086] In step S240, a field oxide layer is formed on a part of the power device drift region, and a gate is formed in the second conductivity type well region of the insulating region. The gate extends to cover the power device drift region not covered by the field oxide layer, and then continues to extend to cover a part of the field oxide layer.

[0087] In step S250, a power device source region is formed. The power device source region is provided in the insulating region, located within the second conductivity type well region, and extends to below the gate. Also, a power device drain region located within the power device drift region is formed, and a substrate extraction region located on the side opposite to the gate in the power device source region is formed. The substrate extraction region is provided in the low voltage device region and is located within the second conductivity type well region. Both the power device source region and the power device drain region have the first conductivity type. The substrate extraction region and the power device source region are provided at intervals from each other and have the second conductivity type.

[0088] In step S260, a source extraction terminal is extracted from the power device source region, a drain extraction terminal is extracted from the power device drain region, and a substrate extraction terminal is extracted from the substrate extraction region.

[0089] In an embodiment of the present application, the power device source region and the power device drain region are N+ doping regions, and the substrate extraction region is a P+ doping region.

[0090] In an embodiment of the present application, an oxide layer can be formed as a field oxide layer in the power device drift region by a deposition process and patterning.

[0091] In one embodiment of the present application, after the step of forming the field oxide layer, the step of forming a gate is further included. The step of forming a gate may include first forming a gate dielectric layer and then forming a gate conductive layer on the gate dielectric layer. The gate includes a gate dielectric layer and a gate conductive layer.

[0092] In one embodiment of the present application, the material of the gate dielectric layer is silicon oxide, for example, silicon dioxide. Also, the material of the gate is polysilicon.

[0093] According to the method for manufacturing a semiconductor device described above, first, an insulating structure is provided in the insulating well region, and the dielectric layer is included in the insulating structure. Therefore, in the process that the high-voltage current passes through the high-voltage drift region and flows into the power device, the dielectric layer of the insulating structure exerts an electrical insulation effect, thereby reducing the leakage current flowing from the high-voltage device region through the high-voltage drift region into the power device. Second, by introducing a new depletion region between the insulating well region and the high-voltage drift region, and between the insulating well region and the power device drift region, the peak electric field value in the drift region and the power device drain region of the substrate increases. However, the conductive structure, the dielectric layer, and the insulating well region constitute a capacitor effect similar to that of a conductive material-dielectric material-semiconductor. Thereby, while being able to assist in the depletion of the drift region, when blocking the reverse current of the power device, it is also possible to push the equipotential line at the bottom of the drift region into the insulating structure. Therefore, the peak electric field value caused by the introduction of the insulating well region is extremely reduced. In this way, by using the semiconductor device, it is possible to reduce the leakage current flowing from the high-voltage device region through the drift region into the power device, and at the same time, it will not affect the breakdown voltage of the semiconductor device.

[0094] It should be understood that although each step in the flowchart of the present application is shown in sequence according to the indication of the arrow, these steps do not necessarily have to be executed in the order indicated by the arrow. Except when clearly explained in the text, there are no strict order constraints for the execution of these steps, and they may be executed in other orders. Moreover, at least some of the steps in the flowchart of the present application may include multiple steps or multiple stages. These steps or stages do not necessarily have to be executed and completed at the same timing, and they may be executed at different timings. Also, regarding the execution order of these steps or stages, they do not necessarily have to be carried out in sequence, and they may be executed in sequence or alternately with at least some of the other steps, or steps or stages within the other steps.

[0095] In the description of this specification, references to terms such as "any embodiment", "other embodiments", "ideal embodiment", etc. mean that the specific features, structures, materials or characteristics described with reference to the embodiment or exemplification are included in at least one embodiment or exemplification of the present invention. It should be noted that in this specification, the general descriptions of the above terms do not necessarily indicate the same embodiment or exemplification.

[0096] Each technical feature of the embodiments described above may be arbitrarily combined. For the sake of brevity of description, not all possible combinations of each technical feature of the above embodiments are described, but if there is no contradiction in the combination of these technical features, they should all be regarded as within the scope described in this specification.

[0097] The embodiments described above merely represent some embodiments of the present application and are described relatively specifically and in detail, but it should not be understood that the scope of rights of the present application is limited thereby. It should be pointed out that those skilled in the art may make some modifications and improvements on the premise of not departing from the concept of the present application, and all of these belong to the protection scope of the present application. Therefore, the protection scope of the rights of the present application should be in accordance with the appended claims.

Description of Reference Signs

[0098] 100 Substrate 101 High-voltage device region 102 Low-voltage device region 200 Drift region 210 High-voltage drift region 220 Power device drift region 310 Second conductivity type well region 320 Insulated well region 400 High-voltage power extraction region 500 Power device source region 600 Power device drain region 700 Insulation structure 710 Dielectric layer 720 Conductive structure 810 Field oxide layer 820 Gate 900 Substrate extraction region

Claims

1. A semiconductor device including a high-voltage device region, a low-voltage device region, and an insulating region located between the high-voltage device region and the low-voltage device region, Furthermore, A drift region provided in the high-voltage device region and having a first conductivity type, A second conductivity type well region provided in the insulating region and extending to the low-voltage device region, wherein the first conductivity type and the second conductivity type are opposite to each other, An insulating well region having the second conductivity type, provided in the drift region, and dividing the drift region into a high-voltage drift region and a power device drift region, An insulating structure provided in the insulating well region, including a conductive structure and a dielectric layer surrounding the bottom surface and side surfaces of the conductive structure, A power device source region provided in the insulating region and located within the second conductivity type well region and having the first conductivity type, A semiconductor device characterized by including a power device drain region provided in the power device drift region and having the first conductivity type.

2. The semiconductor device according to claim 1, wherein the power device drift region is completely surrounded by a region surrounded by the insulating well region and the second conductivity type well region.

3. A plurality of trenches are provided in the insulating well region at intervals, the trenches extend from the upper surface of the insulating well region into the insulating well region, and the insulating structure is provided in the trenches. The semiconductor device according to claim 1, characterized in that.

4. The semiconductor device according to claim 3, wherein each of the trenches is provided at equal intervals.

5. The semiconductor device according to claim 3, wherein the trench further extends continuously to the bottom of the insulating well region.

6. A trench extending from the upper surface of the insulating well region into the insulating well region is provided in the insulating well region, the depth of the trench is the same as the depth of the insulating well region, and the insulating structure is provided in the trench. The semiconductor device according to claim 2, characterized in that.

7. The semiconductor device according to claim 1, wherein the material of the dielectric layer includes silicon oxide and / or the material of the conductive structure includes polysilicon.

8. The semiconductor device according to claim 1, wherein a potential is externally connected to the conductive structure.

9. The semiconductor device according to claim 1, further comprising a high-voltage power supply extraction region provided in the high-voltage drift region.

10. The semiconductor device according to any one of claims 1 to 9, wherein the power device is a laterally diffused metal oxide semiconductor field effect transistor LD-MOS.

11. The power device further includes a field oxide layer provided in the power device drift region, a gate provided in the field oxide layer and extending to cover a part of the power device source region, a semiconductor device according to claim 10, further comprising a substrate extraction region having a second conductivity type, provided in the low-voltage device region, and located within the second conductivity type well region.

12. Form a drift region in the high-voltage device region, the drift region having a first conductivity type, Form a second conductivity type well region in the insulating region, the second conductivity type well region further extending to the low-voltage device region, and form an insulating well region in the drift region to divide the drift region into a high-voltage drift region and a power device drift region, the first conductivity type and the second conductivity type being opposite, Form an insulating structure in the insulating well region, the insulating structure including a conductive structure and a dielectric layer surrounding the bottom and side surfaces of the conductive structure, A method of manufacturing a semiconductor device, comprising forming a power device source region provided in the insulating region, located within the second conductivity type well region, and forming a power device drain region located within the power device drift region, both the power device source region and the power device drain region having the first conductivity type.

13. Before forming the drift region in the high-voltage device region, further comprising providing a substrate, the substrate including the high-voltage device region, the low-voltage device region, and the insulating region located between the high-voltage device region and the low-voltage device region, the method of manufacturing a semiconductor device according to claim 12.

14. Forming an insulating structure within the above-described insulating well region includes: forming at least one trench within the insulating well region by etching the insulating well region downward; forming the dielectric layer on the inner wall of each trench; forming a conductive structure to be filled in the trench. The method for manufacturing a semiconductor device according to claim 12 is characterized by including the above steps.

15. The method for manufacturing a semiconductor device according to claim 14, wherein the ceiling of the trench and the ceiling of the drift region are flush.

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