Selective Capping of the Contact Layer of a CMOS Device

Abstract

A method of forming an electrical contact to a semiconductor structure includes performing a patterning process to form a hard mask covering an exposed surface of a first semiconductor region within a first opening on a semiconductor structure comprising a first semiconductor region, a second semiconductor region, and a dielectric layer having a first opening over the first semiconductor region and a second opening over the second semiconductor region, performing a first selective deposition process to form a contact layer on an exposed surface of the second semiconductor region within the second opening, and performing a second selective deposition process to form a cap layer over the contact layer.

Description

Technical Field

[0001]

[0001] The embodiments described herein generally relate to semiconductor device manufacturing, and more particularly, to systems and methods for forming contacts within a semiconductor structure.

Background Art

[0002]

[0002] Multi-gate metal-oxide-semiconductor field-effect transistors (MOSFETs), such as complementary metal-oxide-semiconductor (CMOS) devices, have manufacturing challenges due to their three-dimensional (3D) design and small size. In advanced CMOS devices, an epitaxial layer of a silicon (Si) - containing material (e.g., boron-doped p-type silicon germanium or phosphorus-doped n-type silicon) formed at the bottom of a trench contact is often utilized to reduce the contact resistivity to the -9 Ω·cm 2 range and achieve the performance required for advanced CMOS technology. Typically, the p-type epitaxial layer is formed of silicon germanium (SiGe) having a high germanium (Ge) concentration, for example, between about 60% and about 80%, and in some cases 100%, to minimize the contact resistance. However, an epitaxial layer of silicon germanium (SiGe) having a high germanium (Ge) concentration is vulnerable to oxidation and is also affected by wet etching chemicals, and thus can be removed in subsequent process steps.

[0003]

[0003] Therefore, there is a need for a method and system capable of forming a cap material to protect an epitaxial layer of silicon germanium (SiGe) having a high germanium (Ge) concentration from oxidation and contamination.

Summary of the Invention

[0004]

[0004] Embodiments of the present disclosure provide a method for forming an electrical contact to a semiconductor structure. The method includes performing a patterning process for forming a hard mask covering an exposed surface of a first semiconductor region within a first opening, on a semiconductor structure comprising a first semiconductor region, a second semiconductor region, and a dielectric layer having the first opening over the first semiconductor region and the second opening over the second semiconductor region; performing a first selective deposition process for forming a contact layer on the exposed surface of the second semiconductor region within the second opening; and performing a second selective deposition process for forming a cap layer on the contact layer.

[0005]

[0005] Embodiments of the present disclosure further provide a method for forming an electrical contact to a semiconductor structure. The method includes performing a pre-cleaning process on an exposed surface of a semiconductor structure comprising a first semiconductor region, a second semiconductor region, and a dielectric layer having the first opening over the first semiconductor region and the second opening over the second semiconductor region, the exposed surface being disposed over the first semiconductor region within the first opening and over the second semiconductor region within the second opening; performing a patterning process for forming a hard mask on the exposed surface of the first semiconductor region within the first opening; performing an etching process for forming a groove in the exposed surface of the second semiconductor region; performing a first selective deposition process for forming a contact layer on the exposed surface of the second semiconductor region within the second opening; performing a second selective deposition process for forming a cap layer on the contact layer; performing a removal process for removing the hard mask; performing a third selective deposition process for forming a metal layer on the exposed surface of the first semiconductor region and on the cap layer; and performing a metal filling process for forming a first contact plug within the first opening and a second contact plug within the second opening, wherein the first selective deposition process and the second selective deposition process are performed without breaking a vacuum environment.

[0006]

[0006] Embodiments of the present disclosure further provide a processing system. The processing system includes a first processing chamber, a second processing chamber, a third processing chamber, and a system controller. The system controller forms a hard mask for covering an exposed surface of the first semiconductor region in the first opening on a semiconductor structure including a first semiconductor region, a second semiconductor region, and a dielectric layer having a first opening on the first semiconductor region and a second opening on the second semiconductor region in a patterning process in the first processing chamber, executes a first selective deposition process for forming a contact layer on the exposed surface of the second semiconductor region in the second opening in the second processing chamber, and executes a second selective deposition process for forming a cap layer on the contact layer in the third processing chamber, and is configured to cause the processing system to perform the above.

[0007]

[0007] As the above features of the present disclosure can be understood in detail, a more detailed description of the present disclosure briefly summarized above can be obtained by referring to the embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings show only typical embodiments of the present disclosure, and thus the accompanying drawings should not be considered as limiting the scope of the present disclosure because the present disclosure can recognize other equally effective embodiments.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2A

Figure 2B

Figure 3

Figure 4

Figure 5A

Figure 5B

Figure 5C

Figure 5D

Figure 5E

Figure 5F

Figure 5G

Figure 5H

DETAILED DESCRIPTION OF THE INVENTION

[0009]

[0014] For ease of understanding, the same reference numbers are used whenever possible to indicate the same elements common to the figures. It is contemplated that the elements and features of one embodiment may be beneficially incorporated into other embodiments without further explanation.

[0010]

[0015] The embodiments described herein provide a method and system for forming contacts that include an epitaxial layer of a silicon-containing material (e.g., boron-doped p-type silicon germanium or phosphorus-doped n-type silicon) on a selected portion of a structure (e.g., on an exposed surface of a layer of silicon or silicon germanium) used to form a CMOS device. The method and system are particularly useful for selectively forming an epitaxial layer containing silicon germanium on an exposed surface of silicon germanium material within an opening or feature (e.g., a contact trench) formed in a dielectric layer in a semiconductor structure having a region containing silicon, a region containing silicon germanium, and a dielectric layer formed thereon. The processes described herein are configured to form a cap layer for protecting contacts formed within a semiconductor structure from oxidation and contamination.

[0011]

[0016] FIG. 1 is a schematic top view of a multi-chamber processing system 100 according to one or more embodiments of the present disclosure. The processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 each having a respective transfer robot 112, 114, hold chambers 116, 118, and process chambers 120, 122, 124, 126, 128, 130. As detailed herein, substrates within the processing system 100 can be processed in various chambers and transferred between various chambers without exposing the substrates to the ambient environment external to the processing system 100 (e.g., the ambient air environment that may exist within a factory). For example, the substrates can be processed in various chambers maintained at a low pressure (e.g., about 300 Torr or less) or a vacuum environment and transferred between various chambers without breaking the low pressure or vacuum environment during the various processes executed on the substrates within the processing system 100. Accordingly, the processing system 100 can provide an integrated solution for processing a portion of a substrate.

[0012]

[0017] Examples of processing systems that can be suitably modified in accordance with the teachings provided herein include the Endura®, Producer®, or Centura® integrated processing systems, or other suitable processing systems commercially available from Applied Materials, Inc., located in Santa Clara, California. Other processing systems, including those of other manufacturers, are intended to be adapted to benefit from the aspects described herein.

[0013]

[0018] In the example of FIG. 1, the factory interface 102 includes a docking station 132 and a factory interface robot 134 to facilitate the transfer of substrates. The docking station 132 is adapted to receive one or more front-opening unified pods (FOUPs) 136. In some examples, each factory interface robot 134 generally includes a blade 138 disposed at one end of each factory interface robot 134, which is adapted to transfer substrates from the factory interface 102 to the load lock chambers 104, 106.

[0014]

[0019] Load lock chambers 104, 106 have respective ports 140, 142 coupled to the factory interface 102 and respective ports 144, 146 coupled to the transfer chamber 108. The transfer chamber 108 further has respective ports 148, 150 coupled to the holding chambers 116, 118 and respective ports 152, 154 coupled to the processing chambers 120, 122. Similarly, the transfer chamber 110 has respective ports 156, 158 coupled to the holding chambers 116, 118 and respective ports 160, 162, 164, 166 coupled to the processing chambers 124, 126, 128, 130. Ports 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, 166 can be slit valve openings having slit valves for passing substrates therethrough, for example, by transfer robots 112, 114 and for providing a seal between respective chambers to prevent gas from passing between the respective chambers. Generally, any port is opened to pass a substrate therethrough. Otherwise, the port is closed.

[0015]

[0020] Load lock chambers 104, 106, transfer chambers 108, 110, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130 may be fluidly coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system may include one or more gas pumps (e.g., turbo pumps, cryo pumps, roughing pumps), gas sources, various valves, and conduits fluidly coupled to the various chambers. During operation, factory interface robot 134 transfers substrates from FOUP 136 through port 140 or 142 to load lock chamber 104 or 106. Thereafter, the gas and pressure control system pumps down (evacuates) load lock chamber 104 or 106. The gas and pressure control system further maintains transfer chambers 108, 110 and holding chambers 116, 118 in an internal low pressure or vacuum environment (which may include an inert gas). Thus, pumping down load lock chamber 104 or 106 facilitates passing substrates, for example, between the ambient environment of factory interface 102 and the low pressure or vacuum environment of transfer chamber 108.

[0016]

[0021] When the load lock chamber 104 or 106 containing the substrate is pumped down, the transfer robot 112 transfers the substrate from the load lock chamber 104 or 106 into the transfer chamber 108 through the port 144 or 146. Thereafter, the transfer robot 112 can transfer the substrate to either the processing chamber 120 or 122 through the respective ports 152, 154 for processing, and can transfer the substrate to either the holding chamber 116 or 118 through the respective ports 148, 150 to hold for further transfer, and / or can transfer the substrate between any of those chambers. Similarly, the transfer robot 114 can access the substrate in the holding chamber 116 or 118 through the port 156 or 158, can transfer the substrate to either the processing chamber 124, 126, 128, or 130 through the respective ports 160, 162, 164, 166 for processing, can transfer the substrate to either the holding chamber 116 or 118 through the respective ports 156, 158 to hold for further transfer, and / or can transfer the substrate between any of those chambers. The transfer and holding of the substrate within and between the various chambers can be performed in a low pressure or vacuum environment provided by the gas and pressure control system.

[0017]

[0022] The processing chambers 120, 122, 124, 126, 128, 130 can be any suitable chambers for processing a substrate. In some examples, the processing chamber 120 may be capable of performing an etching process, the processing chamber 122 may be capable of performing a cleaning process, the processing chamber 124 may be capable of performing a selective removal process, and the processing chambers 126, 128, 130 may be capable of performing respective epitaxial growth processes. The processing chamber 120 may be a Selectra (trademark) etching chamber available from Applied Materials, Inc. of Santa Clara, California. The processing chamber 122 may be a SiCoNi (trademark) pre-cleaning chamber available from Applied Materials, Inc. of Santa Clara, California. The processing chambers 126, 128, or 130 may be Centura (trademark) epi-chambers available from Applied Materials, Inc. of Santa Clara, California.

[0018]

[0023] The system controller 168 is coupled to the processing system 100 to control the processing system 100 or its components. For example, the system controller 168 can control the operation of the processing system 100 using direct control of the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130 of the processing system 100 or by controlling the controllers associated with the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130. During operation, the system controller 168 enables data collection and feedback from the respective chambers to adjust the performance of the processing system 100.

[0019]

[0024] System controller 168 generally includes a central processing unit (CPU) 170, a memory 172, and support circuitry 174. The CPU 170 may be one of any form of general-purpose processor that can be used in an industrial environment. The memory 172, i.e., a non-transitory computer-readable medium, is accessible by the CPU 170 and may be one or more of memories such as random access memory (RAM), read-only memory (ROM), floppy disks, hard disks, or other forms of digital storage, local or remote. The support circuitry 174 is coupled to the CPU 170 and may include a cache, a clock circuit, an input / output subsystem, a power supply, and the like. The various methods disclosed herein may generally be implemented under the control of the CPU 170 by the CPU 170 executing computer instruction codes stored in the memory 172 (or the memory of a particular processing chamber), for example, as software routines. When the computer instruction codes are executed by the CPU 170, the CPU 170 controls the chamber to execute a process according to various methods.

[0020]

[0025] Other processing systems may have other configurations. For example, more or fewer processing chambers may be coupled to the transfer device. In the illustrated example, the transfer device includes transfer chambers 108, 110 and holding chambers 116, 118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as the transfer device within the processing system.

[0021]

[0026] FIG. 2A is a cross-sectional view of a processing chamber 200 according to one or more embodiments and is adapted to perform a pre-cleaning process as detailed below. The processing chamber 200 may be the processing chamber 122 shown in FIG. 1. FIG. 2B is an enlarged view of a portion of the processing chamber 200 of FIG. 2A.

[0022]

[0027] The processing chamber 200 can be particularly useful for performing heat or plasma-based cleaning processes and / or plasma-assisted dry etching processes. The processing chamber 200 includes a chamber body 202, a lid assembly 204, and a support assembly 206. The lid assembly 204 is disposed at the upper end of the chamber body 202, and the support assembly 206 is at least partially disposed within the chamber body 202. A vacuum system can be used to remove gas from the processing chamber 200. The vacuum system includes a vacuum pump 208 coupled to a vacuum port 210 disposed in the chamber body 202. The processing chamber 200 also includes a controller 212 for controlling the processes within the processing chamber 200.

[0023]

[0028] The lid assembly 204 includes stacked components adapted to supply precursor gas and / or plasma to a processing region 214 within the processing chamber 200. A first plate 216 is coupled to a second plate 218. A third plate 220 is coupled to the second plate 218. The lid assembly 204 can be connected to a power source (not shown) for supplying plasma to a conical chamber 222 formed within the lid assembly 204. The lid assembly 204 can also be connected to a remote plasma source 224 that generates plasma upstream of the lid stack. The remote plasma cavity (e.g., the processing region 214, the first plate 216, and the second plate 218 of FIGS. 2A - 2B) is coupled to a gas source 226 via the remote plasma source 224 (or, the gas source 226 is directly coupled to the lid assembly 204 in the absence of the remote plasma source 224). The gas source 226 can include a gas source adapted to supply helium, argon, or other inert gas. In some configurations, the gas supplied by the gas source 226 can be activated to become the plasma supplied to the lid assembly 204 using the remote plasma source 224. In an alternative embodiment, the gas source 226 may supply a process gas that can be activated by the remote plasma source 224 before being introduced onto the surface of a substrate disposed within the processing chamber 200. Referring to FIG. 2B, the conical chamber 222 has an opening 228 that enables the formed plasma to flow from the remote plasma source 224 into a space region 230 formed in a fourth plate 232 of the lid assembly 204.

[0024]

[0029] In some configurations of the lid assembly 204, plasma is generated in the conical chamber 222 by applying energy supplied from a plasma source. In one example, the energy can be supplied by biasing the lid assembly 204 such that RF, VHF, and / or UHF energy is capacitively coupled to a gas disposed within the conical chamber 222. In this configuration of the lid assembly 204, the remote plasma source 224 may not be used or may not be installed within the lid assembly 204.

[0025]

[0030] The central conduit 234 formed in the fourth plate 232 is adapted to supply plasma generating species supplied from the space region 230 through the fifth plate 236 to the mixing chamber 238 formed in the sixth plate 240 of the lid assembly 204. The central conduit 234 communicates with the mixing chamber 238 through an opening 242 in the fifth plate 236. The diameter of the opening 242 may be smaller than, larger than, or the same as the diameter of the central conduit 234. In the embodiment of FIG. 2B, the opening 242 has the same diameter as the central conduit 234.

[0026]

[0031] The fourth plate 232 also includes inlets 244 and 246 adapted to supply gas to the mixing chamber 238. The inlet 244 is coupled to the first gas source 248, and the inlet 246 is coupled to the second gas source 250. The first gas source 248 and the second gas source 250 can include not only process gases but also inert gases utilized as carrier gases, such as argon and / or helium. The first gas source 248 can include not only argon (Ar) but also ammonia (NH3). The second gas source 250 can include a fluorine-containing gas, a hydrogen-containing gas, or a combination thereof. In one example, the second gas source 250 can include not only argon (Ar) but also hydrogen fluoride (HF).

[0027]

[0032] As shown in FIG. 2B, in some configurations, the inlet 244 is coupled to the mixing chamber 238 through a cylindrical channel 252 (shown in phantom) and a hole 254 formed in the fifth plate 236. The inlet 246 is coupled to the mixing chamber 238 through a cylindrical channel 256 (shown in phantom) and a hole 258 formed in the fifth plate 236. The holes 254, 258 formed in the fifth plate 236 are generally sized to allow a uniform flow of the gas supplied from the respective gas sources 248, 250 into the mixing chamber 238. In one configuration, the hole 258 has a diameter smaller than the width of the opening defined by the opposing sidewalls of the cylindrical channel 256 formed in the fourth plate 232. The holes 258 are typically distributed circumferentially on the centerline of the cylindrical channel 256 to provide a uniform flow of fluid into the mixing chamber 238. In one configuration, the hole 254 has a diameter smaller than the width of the opening defined by the opposing sidewalls of the cylindrical channel 252 formed in the fourth plate 232. The holes 254 are typically distributed circumferentially on the centerline of the cylindrical channel 252 to provide a uniform flow of fluid into the mixing chamber 238.

[0028]

[0033] The inlets 244 and 246 provide respective fluid flow paths that pass laterally through the fourth plate 232, bend toward the fifth plate 236, and pass through the fifth plate 236 to reach the mixing chamber 238. The lid assembly 204 also includes a seventh plate or a first gas distributor 260, which may be a gas distribution plate such as a showerhead, through which the various gases mixed within the lid assembly 204 flow through the perforations 262 formed therein. The perforations 262 are in fluid communication with the mixing chamber 238 and provide a flow path from the mixing chamber 238 through the first gas distributor 260. Returning to FIG. 2A, a blocker plate 264 and a gas distribution plate such as a second gas distributor 266, which may be a gas distribution plate such as a showerhead, are disposed below the lid assembly 204.

[0029]

[0034] Alternatively, another cleaning process can be utilized to clean the substrate surface. For example, a remote plasma containing helium (He) and ammonia (NH3) may be introduced into the processing chamber 200 through the lid assembly 204, while ammonia (NH3) may be directly injected into the processing chamber 200 through a separate gas inlet 268 disposed on the side of the chamber body 202 and coupled to a gas source (not shown).

[0030]

[0035] The support assembly 206 can include a substrate support 270 for supporting the substrate 272 thereon during processing. The substrate support 270 can be coupled to the actuator 274 by a shaft 276 that extends through a centrally located opening formed in the bottom of the chamber body 202. The actuator 274 can be flexibly sealed to the chamber body 202 by a bellows (not shown) that prevents vacuum leakage around the shaft 276. The actuator 274 can vertically move the substrate support 270 between a processing position and a loading position within the chamber body 202. The loading position is slightly below the opening of a tunnel (not shown) formed in the sidewall of the chamber body 202.

[0031]

[0036] The substrate support 270 has a flat or substantially flat substrate support surface for supporting the substrate 272 to be processed thereon. The substrate support 270 can be vertically moved within the chamber body 202 by an actuator 274 coupled to the substrate support 270 by the shaft 276. In some process operations, the substrate support 270 can be raised to a position close to the lid assembly 204 to control the temperature of the substrate 272 being processed. Thus, the substrate 272 can be heated by radiation emitted from the second gas distributor 266 or another radiation source, or by convection or conduction from the second gas distributor 266 through an intervening gas. In some process steps, the substrate can be placed on the lift pins 278 and additional heat treatment operations, such as performing an annealing step, can be carried out.

[0032]

[0037] FIG. 3 is a cross-sectional view of a processing chamber 300 according to one or more embodiments and is adapted to perform an epitaxial (Epi) deposition process as detailed below. The processing chamber 300 may be the processing chamber 126, 128, or 130 shown in FIG. 1.

[0033]

[0038] The processing chamber 300 includes a housing structure 302 made of a process-resistant material such as aluminum or stainless steel (e.g., 316L stainless steel). The housing structure 302 surrounds a quartz chamber 304 that includes various functional elements of the processing chamber 300, such as an upper quartz chamber 306 and a lower quartz chamber 308, and a processing space 310 is included therein. Reactive species are supplied to the quartz chamber 304 by a gas distribution assembly 312, and processing by-products are removed from the processing space 310 by an outlet port 314 that generally communicates with a vacuum source (not shown).

[0034]

[0039] The substrate support 316 is adapted to receive a substrate 318 that is transferred into the processing space 310. The substrate support 316 is disposed along the longitudinal axis 320 of the processing chamber 300. The substrate support 316 can be made of a ceramic material, or a graphite material coated with a silicon material such as silicon carbide, or other process-resistant materials. Reactive species from the precursor reactants are applied to the surface 322 of the substrate 318, and then by-products can be removed from the surface 322 of the substrate 318. Heating of the substrate 318 and / or the processing space 310 may be provided by radiation sources such as an upper lamp module 324A and a lower lamp module 324B.

[0035]

[0040] In one embodiment, the upper lamp module 324A and the lower lamp module 324B are infrared (IR) lamps. The non-thermal energy, i.e., radiation, from the lamp modules 324A and 324B passes through the upper quartz window 326 of the upper quartz chamber 306 and through the lower quartz window 328 of the lower quartz chamber 308. Optionally, a cooling gas for the upper quartz chamber 306 enters through the inlet 330 and exits through the outlet 332. The precursor reactants, as well as the dilution gas, purge gas, and vent gas for the processing chamber 300, enter through the gas distribution assembly 312 and exit through the outlet port 314. Although the upper quartz window 326 is shown as curved or convex, the upper quartz window 326 may be planar or concave since the pressures on both sides of the upper quartz window 326 are substantially the same (i.e., atmospheric pressure).

[0036]

[0041] The low-wavelength radiation in the processing space 310 used to activate reactive species and assist in the adsorption of reactants and the desorption of process by-products from the surface 322 of the substrate 318 is typically in the range from about 0.8 μm to about 1.2 μm, for example, in the range from about 0.95 μm to about 1.05 μm, and various combinations of wavelengths are provided, for example, depending on the composition of the epitaxially growing film.

[0037]

[0042] The component gases enter the processing space 310 via the gas distribution assembly 312. The gases flow from the gas distribution assembly 312 and exit through the outlet port 314 as generally indicated by the flow path 334. The combination of component gases used to clean / passivate the substrate surface or to form silicon- and / or germanium-containing films that grow epitaxially is typically mixed before entering the processing space 310. The overall pressure within the processing space 310 can be adjusted by a valve (not shown) at the outlet port 314. At least a portion of the inner surface of the processing space 310 is covered by a liner 336. In one embodiment, the liner 336 includes an opaque quartz material. In this way, the chamber walls are shielded from the heat within the processing space 310.

[0038]

[0043] The temperature of the surface within the processing space 310 can be controlled within a temperature range of from about 200°C to about 600°C or more by the flow of the cooling gas entering from the inlet 330 and exiting from the outlet 332, in combination with the radiation from the upper lamp module 324A disposed above the upper quartz window 326. The temperature within the lower quartz chamber 308 can be controlled within a temperature range of from about 200°C to about 600°C or more by adjusting the speed of a blower unit (not shown), and also by the radiation from the lower lamp module 324B disposed below the lower quartz chamber 308. The pressure within the processing space 310 can be between about 0.1 Torr and about 600 Torr, for example, between about 5 Torr and about 30 Torr.

[0039]

[0044] The temperature of the surface 322 of the substrate 318 can be controlled by adjusting the power to the lower lamp module 324B within the lower quartz chamber 308, or by adjusting the power to both the upper lamp module 324A above the upper quartz window 326 and the lower lamp module 324B within the lower quartz chamber 308. The power density within the processing space 310 can be between about 40 W / cm 2 and about 400 W / cm 2 , for example, between about 80 W / cm 2 and about 120 W / cm 2 up to.

[0040]

[0045] In one aspect, the gas distribution assembly 312 is disposed perpendicular to the longitudinal axis 320 of the processing chamber 300 or the substrate 318, i.e., in the radial direction 338. In this orientation, the gas distribution assembly 312 is adapted to flow the process gas in the radial direction 338 across the surface 322 of the substrate 318 or parallel to the surface 322 of the substrate 318. In one process application, the process gas is preheated at the time of introduction into the processing chamber 300 to initiate preheating of the gas prior to introduction into the processing space 310 and / or to break certain bonds in the gas. In this way, the surface reaction rate can be varied independently of the thermal temperature of the substrate 318.

[0041]

[0046] During operation, the precursors used to form a blanket or selective epitaxial film of silicon (Si) and silicon germanium (SiGe) are supplied from one or more gas sources 340A and 340B to a gas distribution assembly 312. An IR lamp 342 (only one is shown in FIG. 3) may be utilized to heat the precursors within the gas distribution assembly 312 and along the flow path 334. The gas sources 340A, 340B may be coupled to the gas distribution assembly 312 in a manner adapted to facilitate an introduction zone within the gas distribution assembly 312, such as a radially outer zone and a radially inner zone between the outer zones when viewed in a top view. The gas sources 340A, 340B can include valves (not shown) for controlling the introduction rate into the zones.

[0042]

[0047] The gas sources 340A, 340B can include silicon precursors such as silane, including silane (SiH4), disilane (Si2H6), dichlorosilane (SiH2Cl2), hexachlorodisilane (Si2Cl6), dibromosilane (SiH2Br2), higher-order silanes, derivatives thereof, and combinations thereof. The gas sources 340A, 340B can also include germanium-containing precursors such as germane (GeH4), digermane (Ge2H6), germanium tetrachloride (GeCl4), dichlorogermane (GeH2Cl2), derivatives thereof, and combinations thereof. The silicon and / or germanium-containing precursors can be used in combination with hydrogen chloride (HCl), chlorine gas (Cl2), hydrogen bromide (HBr), and combinations thereof. The gas sources 340A, 340B can include one or more of the silicon and germanium-containing precursors in one or both of the gas sources 340A, 340B.

[0043]

[0048] The precursor material, in this excited state, enters the processing space 310 through the openings or holes 344 (only one is shown in FIG. 3) of the perforated plate 346, which, in one embodiment, is a quartz material in which the holes 344 are formed therethrough. The perforated plate 346 is permeable to IR energy and may be made of a transparent quartz material. In other embodiments, the perforated plate 346 may be any material that is permeable to IR energy and resistant to process chemicals and other processing chemicals. The activated precursor material passes through the holes 344 of the perforated plate 346 and flows through the channel 348 (only one is shown in FIG. 3) towards the processing space 310. A portion of the photons and non-thermal energy from the IR lamp 342 is also facilitated by the reflective material and / or surface disposed on the inner surface of the gas distribution assembly 312 to pass through the holes 344, the perforated plate 346, and the channel 348, thereby irradiating the flow path 334 of the precursor material. In this way, the vibrational energy of the precursor material can be maintained along the flow path from the point of introduction into the processing space 310.

[0044]

[0049] FIG. 4 is a process flow diagram of a method 400 for forming a contact layer on a semiconductor structure 500 according to a first embodiment of the present disclosure. FIGS. 5A, 5B, 5C, 5D, 5E, 5F, 5G, 5H are cross-sectional views of a portion of the semiconductor structure 500 corresponding to various states of the method 400. FIGS. 5A, 5B, 5C, 5D, 5E, 5F, 5G, and 5H show only partial schematic views of the semiconductor structure 500, and it should be understood that the semiconductor structure 500 may include any number of transistor portions and additional materials having the aspects shown. Although the method shown in FIG. 4 is described sequentially, it should also be noted that other process sequences including one or more operations that are omitted and / or added and / or rearranged in another desirable order are within the scope of the embodiments of the disclosure provided herein.

[0045]

[0050] Referring to FIGS. 5A, 5B, 5C, 5D, 5E, 5F, 5G, and 5H, the semiconductor structure 500 may include a first transistor device 502 and a second transistor device 504 formed on a substrate (not shown).

[0046]

[0051] As used herein, the term "substrate" refers to a layer of material that functions as a basis for subsequent processing operations and includes a surface that is cleaned. The substrate may be a silicon-based material, or, if necessary, an appropriate insulating material or conductive material. The substrate may include materials such as crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, and patterned or unpatterned wafers, silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire.

[0047]

[0052] As shown in FIG. 5A, a portion of the first transistor device 502 among a plurality of first transistor devices formed on the substrate includes a first semiconductor region 506 formed of a first material. A portion of the second transistor device 504 among a plurality of second transistor devices formed on the substrate includes a second semiconductor region 508 formed of a second material. The first and second materials include materials having different compositions such that the second material can be selectively etched with respect to the first material (i.e., the etching rate of the second material is higher than the etching rate of the first material). The etching selectivity of the second material (i.e., the ratio of the etching rate of the second material to the etching rate of the first material) is between about 10:1 and 500:1. Examples of combinations of the first material and the second material include silicon (Si) / silicon germanium (SiGe), germanium (Ge) / silicon germanium (SiGe), or silicon (Si) / germanium tin (GeSn), respectively.

[0048]

[0053] The first semiconductor region 506 can be doped with an n-type dopant such as phosphorus (P) or antimony (Sb) at a concentration between about 10 20 cm -3 and 5×10 21 cm -3 according to the desired conductive characteristics of the first transistor device 502. The second semiconductor region 508 can be doped with a p-type dopant such as boron (B) or gallium (Ga) at a concentration between about 10 20 cm -3 and about 5×10 21 cm -3 according to the desired conductive characteristics of the second transistor device 504.

[0049]

[0054] The semiconductor structure 500 further includes a dielectric layer 510 having a first opening 512 formed on each of the first semiconductor regions 506 and a second opening 514 formed on each of the second semiconductor regions 508. The dielectric layer 510 can be formed of a dielectric material such as silicon dioxide (SiO2) or silicon nitride (Si3N4).

[0050]

[0055] The first semiconductor region 506 and the second semiconductor region 508 can be formed using any suitable deposition technique such as epitaxial (Epi) deposition, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), and the openings 512 and 514 are formed by patterning techniques such as lithography and etching processes.

[0051]

[0056] The method 400 begins with the pre-cleaning process in block 410. The pre-cleaning process can be performed in a processing chamber such as the processing chamber 122 shown in FIG. 1 or the processing chamber 200 shown in FIG. 2.

[0052]

[0057] The pre-cleaning process is configured to remove natural oxide layers formed on the exposed surfaces of the first semiconductor region 506 within the first opening 512 and the second semiconductor region 508 within the second opening 514, or contaminants such as patterning residues (e.g., fluorocarbons). The pre-cleaning process is used to prepare the exposed surfaces of the first semiconductor region 506 within the first opening 512 and the second semiconductor region 508 within the second opening 514, on which an epitaxial layer can be formed in a subsequent epitaxial deposition process.

[0053]

[0058] The pre-cleaning process can include an anisotropic remote plasma-assisted dry etching process such as a reactive ion etching (RIE) process that uses a plasma formed from a gas containing argon (Ar), helium (He), or a combination thereof. The plasma emissions are directed to impinge on and remove the dielectric layers remaining within the first opening 512 and the second opening 514.

[0054]

[0059] The pre-cleaning process can include an isotropic plasma etching process such as a SiCoNi (trademark) dry chemical etching process that uses a plasma formed from a gas containing ammonia (NH3), nitrogen trifluoride (NF3), hydrogen fluoride (HF), or a combination thereof and a carrier gas such as nitrogen (N2), hydrogen (H2), or a combination thereof. The dry chemical etching process selectively etches the oxide layer, so silicon, germanium, or nitride layers are not easily etched regardless of whether the layer is amorphous, crystalline, or polycrystalline. The selectivity of the dry chemical etching process for oxide to silicon or germanium is at least about 3:1, typically 5:1 or greater, and in some cases 10:1. The dry chemical etching process also has high selectivity for oxide to nitride. The selectivity of the dry chemical etching process for oxide to nitride is at least about 3:1, typically 5:1 or greater, and in some cases 10:1.

[0055]

[0060] The pre-cleaning process can include an inductively coupled plasma (ICP) etching process that uses a gas containing chlorine (Cl2) and hydrogen (H2), and a plasma formed from a carrier gas containing argon (Ar) and helium (He). The ICP etching process is used to form deep ridges with smooth sidewalls in silicon.

[0056]

[0061] In block 420, as shown in FIG. 5B, a patterning process is performed to form a hard mask 516 within a first opening 512 of a dielectric layer 510 over a first semiconductor region 506 so as to cover an exposed surface of the first semiconductor region 506 within the first opening 512. The patterning process can be performed within a processing chamber such as processing chambers 126, 128, or 130 shown in FIG. 1. The patterning process can be performed using any conventional deposition process such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, and a spin-on process, and then patterning with a patterned photoresist layer (not shown) covering the hard mask 516 by a conventional photolithography process.

[0057]

[0062] The hard mask 516 can be formed from tetraethyl orthosilicate (TEOS) or silicon oxynitride (SiON) and can have a thickness of about 500 nm and about 2 μm.

[0058]

[0063] In block 430, as shown in FIG. 5C, an etching process is performed to form a groove 508A in an exposed surface of a second semiconductor region 508 within a second opening 514. The etching process can be performed within an etching chamber such as etching chamber 120 shown in FIG. 1.

[0059]

[0064] The groove 508A has a V-shaped, U-shaped, or other shape, and can expand the contact area of the contact layer formed between the second semiconductor region 508 and the metal contact plug formed in the second opening 514, and minimize the parasitic resistance.

[0060]

[0065] In block 440, as shown in FIG. 5D, a first selective deposition for epitaxially forming a contact layer 518 is performed on the exposed surface of the second semiconductor region 508 in the groove 508A and in the second opening 514. The first selective deposition can be performed in a processing chamber such as the processing chambers 126, 128, or 130 shown in FIG. 1, or the processing chamber 300 shown in FIG. 3.

[0061]

[0066] The contact layer 518 is formed as an interface between the second semiconductor region 508 and the metal contact plug formed in the second opening 514, and minimizes the parasitic resistance. The contact layer 518 is formed of a third material. Examples of the third material include silicon germanium (SiGe) in which the ratio of germanium (Ge) is between 20% and 100%, for example, between about 60% and about 80%, between about 60% and about 100%, or between about 80% and about 100%. The contact layer 518 can be doped with a p-type dopant such as boron (B) or gallium (Ga) at a concentration between about 10 20 cm -3 and 5×10 21 cm -3 depending on the desired conductive characteristics of the contact layer 518.

[0062]

[0067] In some embodiments, the first selective deposition includes an epitaxial deposition process and an etching process. The selectivity in the first selective deposition can result from the nucleation of the third material on the second semiconductor region 508 (e.g., silicon germanium (SiGe)) being different from the nucleation of the third material on the exposed surface of the dielectric layer 510 (e.g., silicon dioxide (SiO2) or silicon nitride (Si3N4)). Since nucleation can occur at a faster rate on the second semiconductor region 508 (e.g., silicon germanium (SiGe)) than on the exposed surface of the dielectric layer 510 (e.g., silicon dioxide (SiO2) or silicon nitride (Si3N4)), when the semiconductor structure 500 is exposed to the deposition gas in the deposition process, an epitaxial layer of the third material is selectively formed on the exposed surface of the second semiconductor region 508 (e.g., silicon (Si) or silicon germanium (SiGe)), and an amorphous layer of the third material can be formed on the exposed surface of the dielectric layer 510 (e.g., silicon dioxide (SiO2) or silicon nitride (Si3N4)). In a subsequent etching process, the amorphous layer of the third material formed on the exposed surface of the dielectric layer 510 can be etched at a faster rate than the epitaxial layer of the third material formed on the exposed surface of the second semiconductor region 508 with an appropriate etching gas. Thus, as an overall result of combining the epitaxial deposition process and the etching process, the growth of the third material on the exposed surface of the dielectric layer 510 can be minimized, if at all, while the third material can be epitaxially grown on the exposed surface of the second semiconductor region 508.

[0063]

[0068] In some embodiments, the deposition gas includes a silicon-containing precursor, a germanium-containing precursor, and a dopant source. The silicon-containing precursor includes silane (SiH4), disilane (Si2H6), tetrasilane (Si4H 10) or combinations thereof. Examples of germanium-containing precursors include germane (GeH4), germanium tetrachloride (GeCl4), digermane (Ge2H6), etc. The dopant source can contain, for example, boron or gallium according to the desired conductive characteristics of the contact layer 518. The dopant source can contain the precursor diborane (B2H6). The etching gas includes an etchant gas and a carrier gas. The etchant gas can include halogen-containing gases such as hydrogen chloride (HCl), chlorine (Cl2), hydrogen fluoride (HF), etc. Examples of carrier gases include nitrogen (N2), argon (Ar), helium (He), hydrogen (H2), etc.

[0064]

[0069] The first selective deposition can be performed at a low temperature of less than about 450 °C and a pressure between 5 Torr and 600 Torr.

[0065]

[0070] To obtain the desired thickness of the contact layer 518, the cycles of the epitaxial deposition process and the etching process can be repeated as necessary. The thickness of the contact layer 518 can be between about 30 Å and about 100 Å.

[0066]

[0071] In block 450, as shown in FIG. 5E, a second selective deposition process for forming a cap layer 520 on the contact layer 518 is performed. The second selective deposition process can be performed in a processing chamber such as the processing chambers 126, 128, or 130 shown in FIG. 1, or the processing chamber 300 shown in FIG. 3, or the same processing chamber as used for the first selective deposition in block 440. The first selective deposition in block 440 and the second selective deposition process in block 450 can be performed in a multi-chamber processing system such as the multi-chamber processing system 100 shown in FIG. 1 without breaking the vacuum environment.

[0067]

[0072] The cap layer 520 can protect the contact layer 518 from oxidation and contamination in an atmospheric environment during the transition from an epitaxial process to subsequent processes such as silicidation and patterning, while maintaining its electrical connection and reducing parasitic resistance at the same time. The cap layer 520 can be formed of a first metal material such as molybdenum (Mo), ruthenium (Ru), or their silicides.

[0068]

[0073] In some embodiments, the second selective deposition process includes a chemical vapor deposition (CVD) process and an etching process.

[0069]

[0074] In some embodiments, the deposition gas used in the deposition process includes a metal source such as a molybdenum (Mo)-containing halide precursor or a ruthenium (Ru)-containing organometallic containing ruthenium (Ru). The second selective deposition process can be performed at a temperature between about 240°C and about 450°C and a pressure between 3 Torr and 300 Torr. During the deposition process, for example, argon (Ar) gas may be supplied at a flow rate between about 0 sccm and about 1000 sccm, and hydrogen (H2) gas may be supplied at a flow rate between about 500 sccm and about 15000 sccm.

[0070]

[0075] The cycle of the second selective deposition process can be repeated, for example, between about 5 times and about 1000 times as needed to obtain the desired thickness of the cap layer 520.

[0071]

[0076] In block 460, as shown in FIG. 5F, a removal process for removing the hard mask 516 is performed. The removal process may be an appropriate etching process performed in an etching chamber such as the processing chamber 120 shown in FIG. 1.

[0072]

[0077] In block 470, as shown in FIG. 5G, a third selective deposition process for forming a metal layer 522 on the cap layer 520 is performed. The third selective deposition process can be performed in a processing chamber such as processing chambers 126, 128, or 130 shown in FIG. 1, or processing chamber 300 shown in FIG. 3.

[0073]

[0078] The metal layer 522 contacts the cap layer 520 and provides and maintains an electrical connection between the contact plug formed in the second opening 514 and the second semiconductor region 508. The metal layer 522 can be formed of a second metal material such as titanium (Ti), cobalt (Co), nickel (Ni), molybdenum (Mo), tantalum (Ta), or their silicides.

[0074]

[0079] In some embodiments, the third selective deposition process includes deposition processes such as epitaxial deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), and etching processes.

[0075]

[0080] In some embodiments, the deposition gas used in the deposition process includes a metal source such as a precursor containing titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), molybdenum (Mo), or a combination thereof. The third selective deposition process can be performed at a temperature between about 300°C and about 800°C and a pressure between 1 Torr and 50 Torr.

[0076]

[0081] In the third alternative deposition process, a barrier metal layer 524 can also be formed on the exposed surfaces inside the first opening 512 and the second opening 514, as well as on the exposed surface of the dielectric layer 510. The barrier metal layer 524 protects the metal layer 522 and enables the nucleation and growth of contact plugs in the first opening 512 and the second opening 514. The barrier metal layer 524 can be formed of a barrier metal material that is titanium nitride (TiN) or tantalum nitride (TaN). In some embodiments, the metal layer 522 is a silicide layer formed from a portion of the barrier metal layer 524 using a spike annealing process.

[0077]

[0082] In block 480, as shown in FIG. 5G, a metal filling process is performed to form a first contact plug 526 in the first opening 512 and a second contact plug 528 in the second opening 514. The first contact plug 526 and the second contact plug 528 can be formed of a contact plug metal material such as tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo). The first contact plug 526 and the second contact plug 528 can include a metal having a desired work function. The metal filling process in block 470 can include a chemical vapor deposition (CVD) process using a tungsten-containing precursor such as WF6 or a cobalt-containing precursor in a processing chamber such as the processing chambers 126, 128, or 130 shown in FIG. 1.

[0078]

[0083] After the metal filling process, the semiconductor structure 500 can be planarized using a chemical mechanical polishing (CMP) process.

[0079]

[0084] The embodiments described in this specification provide a method and system for forming a contact epitaxial layer in a trench of a selected portion of a transistor structure and forming a cap layer over the contact epitaxial layer to protect the contact epitaxial layer from oxidation and contamination. The contact trench structure includes a metal contact plug formed in a trench between adjacent device modules and a contact that serves as an interface between the contact plug and a silicon-based channel in the device module. The contact is formed by selective deposition, reducing parasitic resistance. The metal contact plug is formed void-free by a deposition-etching-deposition process, reducing contact resistance. The contact epitaxial layer may be p-type silicon germanium formed on an exposed surface of a p-type MOS device (e.g., silicon germanium), while an epitaxial layer may not be formed on an n-type MOS (e.g., silicon) or on a dielectric layer formed on a p-type MOS device and an n-type MOS device. The cap layer reduces damage to the manufactured contact epitaxial layer.

[0080]

[0085] The above is directed to embodiments of the present disclosure, but other further embodiments of the present disclosure can be devised without departing from its basic scope, which is determined by the claims that follow.

Claims

1. A method of forming an electrical contact to a semiconductor structure, comprising: executing a patterning process to form a hard mask covering an exposed surface of the first semiconductor region within the first opening on a semiconductor structure comprising a first semiconductor region, a second semiconductor region, and a dielectric layer having a first opening over the first semiconductor region and a second opening over the second semiconductor region; executing a first selective deposition process to form a contact layer on the exposed surface of the second semiconductor region within the second opening; executing a second selective deposition process to form a cap layer on the contact layer; A method comprising the above steps.

2. The method of claim 1, wherein the first semiconductor region comprises silicon doped with an n-type dopant; the second semiconductor region comprises silicon germanium doped with a p-type dopant; and the contact layer comprises silicon germanium doped with a p-type dopant.

3. The method of claim 1, wherein the cap layer comprises a material selected from molybdenum (Mo) silicide and ruthenium (Ru) silicide.

4. The method of claim 1, further comprising performing a pre-cleaning process on the exposed surface of the first semiconductor region within the first opening and the exposed surface of the second semiconductor region within the second opening prior to the patterning process.

5. The method of claim 1, further comprising performing an etching process to form grooves on the exposed surface of the second semiconductor region prior to the first selective deposition process, wherein the grooves have a V-shape, a U-shape, or any other shape that expands the contact area of the contact layer.

6. The method of claim 5, wherein the first selective deposition process, the second selective deposition process, and the etching process are performed without breaking a vacuum environment.

7. subsequent to the second selective deposition process, performing a removal process to remove the hard mask; executing a third selective deposition process to form a metal layer on the exposed surface of the first semiconductor region and on the cap layer; performing a metal filling process to form a first contact plug in the first opening and a second contact plug in the second opening; The method according to claim 1, further comprising

8. The method according to claim 7, wherein the metal layer comprises a material selected from titanium (Ti) silicide, cobalt (Co) silicide, nickel (Ni) silicide, molybdenum (Mo) silicide, and tantalum (Ta) silicide.

9. A method of forming an electrical contact to a semiconductor structure, comprising: performing a pre-cleaning process on an exposed surface of a semiconductor structure comprising a first semiconductor region, a second semiconductor region, and a dielectric layer having a first opening over the first semiconductor region and a second opening over the second semiconductor region, the exposed surface of the semiconductor structure disposed over the first semiconductor region within the first opening and over the second semiconductor region within the second opening; performing a patterning process to form a hard mask on the exposed surface of the first semiconductor region within the first opening; performing an etching process to form a groove in the exposed surface of the second semiconductor region; performing a first selective deposition process to form a contact layer on the exposed surface of the second semiconductor region within the second opening; performing a second selective deposition process to form a cap layer on the contact layer; performing a removal process to remove the hard mask; performing a third selective deposition process to form a metal layer on the exposed surface of the first semiconductor region and on the cap layer; performing a metal filling process to form a first contact plug in the first opening and a second contact plug in the second opening; A method comprising

10. The method according to claim 9, wherein the etching process, the first selective deposition process, and the second selective deposition process are performed without breaking a vacuum environment.

11. The first semiconductor region comprises silicon doped with an n-type dopant, The second semiconductor region comprises silicon germanium doped with a p-type dopant, The method according to claim 9, wherein the contact layer comprises silicon germanium doped with a p-type dopant.

12. The method according to claim 9, wherein the cap layer comprises a material selected from molybdenum (Mo) silicide and ruthenium (Ru) silicide.

13. The method according to claim 9, wherein the metal layer comprises a material selected from titanium (Ti) silicide, cobalt (Co) silicide, nickel (Ni) silicide, molybdenum (Mo) silicide, and tantalum (Ta) silicide.

14. A processing system, comprising: a first processing chamber, a second processing chamber, a third processing chamber, and a system controller wherein the system controller causes the processing system to: perform, in the first processing chamber, a patterning process for forming a hard mask covering an exposed surface of the first semiconductor region in the first opening on a semiconductor structure including a first semiconductor region, a second semiconductor region, and a dielectric layer having a first opening on the first semiconductor region and a second opening on the second semiconductor region; perform, in the second processing chamber, a first selective deposition process for forming a contact layer on the exposed surface of the second semiconductor region in the second opening; perform, in the third processing chamber, a second selective deposition process for forming a cap layer on the contact layer. A processing system configured to perform the above.

15. The processing system according to claim 14, further comprising a fourth processing chamber, wherein the system controller is further configured to perform, in the fourth processing chamber, an etching process for forming grooves on the exposed surface of the second semiconductor region before the first selective deposition process, and the grooves have a V shape, a U shape, or any other shape that expands the contact area of the contact layer.

16. The processing system according to claim 15, wherein the system controller is further configured to cause the processing system to transfer the semiconductor structure between the second processing chamber, the third processing chamber, and the fourth processing chamber without breaking the vacuum environment.

17. The processing system according to claim 15, further comprising a fifth processing chamber, wherein the system controller is further configured to perform, in the fifth processing chamber, a pre-cleaning process on the exposed surface of the first semiconductor region in the first opening and the exposed surface of the second semiconductor region in the second opening before the patterning process.

18. ​ ​ a sixth processing chamber, a seventh processing chamber, and an eighth processing chamber further comprising, wherein the system controller causes the processing system to perform a removal process for removing the hard mask in the sixth processing chamber following the second selective deposition process; perform a third selective deposition process for forming a metal layer on the exposed surface of the first semiconductor region and on the cap layer in the seventh processing chamber; perform a metal filling process for forming a first contact plug in the first opening and a second contact plug in the second opening in the eighth processing chamber; The processing system according to claim 17, further configured to cause the above to be performed.

19. The first semiconductor region includes silicon doped with an n-type dopant, The second semiconductor region includes silicon germanium doped with a p-type dopant, The processing system according to claim 14, wherein the contact layer includes silicon germanium doped with a p-type dopant.

20. The processing system according to claim 14, wherein the cap layer includes a material selected from molybdenum (Mo) silicide and ruthenium (Ru) silicide.

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