Integrating Strained SiGe Channel PMOS for GAA CMOS Technology

Abstract

A horizontal gate all-around device and a method of manufacturing the same are described. The hGAA device includes a semiconductor material between a source region and a drain region of the device. The method includes forming a cladding material on a first material and a subsequent dry oxidation process that results in a rearrangement of the cladding material and the first material.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to semiconductor devices, and more particularly, to horizontal gate all-around device structures, as well as methods and apparatuses for forming horizontal gate all-around device structures.

Background Art

[0002] Transistors are important components of most integrated circuits. Since the drive current, and thus the speed, of a transistor is proportional to the gate width of the transistor, faster transistors generally require larger gate widths. Thus, there is a trade-off between transistor size and speed, and "fin" field-effect transistors (finFETs) have been developed to address the competing goals of maximum drive current and minimum size. FinFETs are characterized by a fin-shaped channel region that significantly increases the transistor size without significantly increasing the footprint of the transistor and are now applied in many integrated circuits. However, finFETs have their own drawbacks.

[0003] To achieve greater circuit density and higher performance, as the feature sizes of transistor devices continue to shrink, it is necessary to improve the transistor device structure to improve electrostatic coupling and reduce adverse effects such as parasitic capacitance and off-state leakage. Examples of transistor device structures include planar structures, fin field-effect transistor (FinFET) structures, and horizontal gate all-around (hGAA) structures. The hGAA device structure includes several lattice-matched channels suspended in a stacked configuration and connected by source / drain regions. The inventors believe that the hGAA structure provides good electrostatic control and can be widely adopted in complementary metal-oxide-semiconductor (CMOS) wafer manufacturing.

[0004] Logic gate performance is related to the properties of the materials used as well as the thickness and area of the structural layers. However, some gate characteristics are adjusted to adapt to device scaling, which causes problems. Further, the space constraints between wires on a horizontal gate all-around (hGAA) device limit the thickness of the gate dielectric material for I / O transistors.

[0005] Severe dislocations in p-type source / drain silicon germanium (SiGe) epitaxy (EPI) for a gate all-around (GAA) p-type field-effect transistor (PFET) process are one of the major bottlenecks for maintaining compressive stress in the channel for device performance enhancement. Integrating a SiGe channel for PMOS while maintaining a Si channel is also difficult.

[0006] Therefore, an improved method for forming a PMOS electronic device is needed. SUMMARY OF THE INVENTION

[0007] One or more embodiments of the present disclosure are directed to a method of forming a semiconductor device. A superlattice structure on a substrate is selectively etched. The superlattice structure includes a plurality of first layers of a first material and a plurality of corresponding second layers of a second material, which are alternately arranged in a plurality of stacked pairs. Each of the second layers is removed to form a plurality of voids in the superlattice structure and a plurality of nanosheets including a first layer extending between a source region and a drain region. A cladding material is formed around each of the plurality of first layers of the nanosheets to form a nanosheet having the first material with the cladding material around the first material. The nanosheets are dry oxidized to convert the nanosheets such that the cladding material is surrounded by an oxide of the first material. The first material is removed to leave the nanosheets of the cladding material.

[0008] The electronic device includes a PMOS having a SiGe channel between a source region and a drain region, and an NMOS having a Si channel between a source region and a drain region.

[0009] To enable a more detailed understanding of the above-described features of the present disclosure, the more detailed description of the present disclosure, briefly summarized above, may be made by reference to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that since the present disclosure may admit other equally effective embodiments, the accompanying drawings merely show general embodiments of the present disclosure and should not be regarded as limiting its scope.

Brief Description of the Drawings

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[0011] For ease of understanding, the same reference numbers are used, where possible, to designate identical elements common to the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated into other embodiments without further recitation.

Best Mode for Carrying Out the Invention

[0012] Before describing some exemplary embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of the structures or process steps described in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0013] As used herein and in the appended claims, the term "substrate" refers to the surface or portion of a surface upon which a process acts. It will be understood by those skilled in the art that reference to a substrate can also refer to only a portion of the substrate, unless the context clearly dictates otherwise. Further, reference to a deposition on a substrate can mean both the bare substrate and the substrate with one or more films or features deposited or formed thereon.

[0014] As used herein, "substrate" refers to any substrate or the surface of a material formed on a substrate on which film processing is performed during the manufacturing process. For example, the substrate surface on which processing can be performed may, depending on the application, be a material such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other material such as metals, metal nitrides, metal alloys, and other conductive materials. The substrate includes, without limitation, semiconductor wafers. The substrate can be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to directly performing film processing on the surface of the substrate itself, in the present disclosure, any of the disclosed film processing steps can also be performed on an underlying layer formed on the substrate as disclosed in more detail below, and the term "substrate surface" is intended to include such an underlying layer as the context indicates. Thus, for example, when a film / layer or a partial film / layer is deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0015] As used in this specification and the appended claims, the terms "precursor", "reactant", "reactive gas", etc. are used interchangeably to refer to any gas species that can react with the substrate surface.

[0016] A transistor is a circuit component or element often formed on a semiconductor device. Depending on the circuit design, in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements, transistors are formed on the semiconductor device. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source and drain regions include doped regions of the substrate and exhibit a doping profile suitable for a particular application. The gate is disposed over the channel region and includes a gate dielectric inserted between the gate electrode in the substrate and the channel region.

[0017] As used herein, the terms "field effect transistor" or "FET" refer to a transistor that uses an electric field to control the electrical behavior of a device. Enhancement-mode field effect transistors generally exhibit extremely high input impedance at low temperatures. The conductivity between the drain terminal and the source terminal is controlled by an electric field in the device, which is generated by the voltage difference between the body of the device and the gate. The three terminals of an FET are the source (S) through which carriers enter the channel, the drain (D) through which carriers leave the channel, and the gate (G), which is the terminal that modulates the channel conductivity. Conventionally, the current entering the channel at the source (S) is denoted as I S and the current entering the channel at the drain (D) is denoted as I D . The drain-source voltage is denoted as V DS . By applying a voltage to the gate (G), the current entering the channel at the drain (i.e., I D ) can be controlled.

[0018] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). It has an insulated gate, and the voltage of the insulated gate determines the conductivity of the device. This ability to vary the conductivity with the amount of voltage applied is used to amplify or switch electronic signals. A MOSFET is based on the modulation of the charge concentration by the metal-oxide-semiconductor (MOS) capacitance between the body electrode and the gate electrode located above the body and insulated from all other device regions by a gate dielectric layer. Compared to a MOS capacitor, a MOSFET includes two additional terminals (source and drain), each of which is connected to an individual highly doped region separated by the body region. These regions can be either p-type or n-type, but they are both of the same type and of the type opposite to that of the body region. (Unlike the body) The source and drain are highly doped, as represented by the "+" sign after the type of doping.

[0019] When the MOSFET is an n-channel or nMOS FET, the source and drain are n+ regions, and the body is a p-region. When the MOSFET is a p-channel or pMOS FET, the source and drain are p+ regions, and the body is an n-region. The source is so named because it is the source of the charge carriers (electrons for an n-channel, holes for a p-channel) that flow through the channel. Similarly, the drain is where the charge carriers leave the channel.

[0020] As used herein, the term "Fin Field-Effect Transistor (FinFET)" refers to a MOSFET transistor built on a substrate where the gate is placed on two or three sides of the channel, forming a double or triple gate structure. FinFET devices are given their common name because the channel region forms "fins" on the substrate. FinFET devices have fast switching times and high current densities.

[0021] As used herein, the term "Gate-All-Around (GAA)" is used to refer to an electronic device, such as a transistor, where the gate material surrounds the channel region on all sides. The channel region of a GAA transistor can include nanowires or nanoslabs, bar-shaped channels, or other suitable channel configurations known to those skilled in the art. In one or more embodiments, the channel region of a GAA device has a plurality of horizontally spaced-apart horizontal nanowires or horizontal bars in the vertical direction, making the GAA transistor a stacked horizontal gate-all-around (hGAA) transistor.

[0022] In one or more embodiments, a horizontal gate all-around (hGAA) transistor comprises a substrate having an upper surface, a source region having a source and a source contact, the source region being on the upper surface of the substrate, a drain region having a drain and a drain contact, the drain region being on the upper surface of the substrate, a channel positioned between the source and the drain and having an axis substantially parallel to the upper surface of the substrate, a gate surrounding the channel between the source region and the drain region, a thermal oxide layer on one or more of the gate, the source contact, or the drain contact and in contact with one or more of them, and a low-k dielectric layer on the thermal oxide layer. In one or more embodiments, the low-k dielectric layer has a thickness less than about 5 nm.

[0023] One or more embodiments of the present disclosure are directed to a method of forming a horizontal gate all-around device. Some embodiments advantageously provide an integrated method for forming a complementary metal oxide semiconductor (CMOS) device using strained SiGe as a channel material for PMOS while maintaining a silicon channel material for NMOS. In some embodiments, the strained SiGe channel is formed using a SiGe oxidation / condensation technique that provides capping or improved compressive stress in the channel.

[0024] In some embodiments, a method for forming an hGAA device is augmented to insert one or more processes between a wire release (etching a SiGe release layer to free a nanowire) and a replacement metal gate (deposition of a gate dielectric, work function metal, and associated material films).

[0025] FIG. 1 shows a flowchart for a method 100 for forming a semiconductor device according to some embodiments of the present disclosure. Method 100 is described below with respect to FIGS. 2-15B, which show stages of the manufacture of a semiconductor structure according to some embodiments of the present disclosure. The method 100 of the present invention can be part of a multi-step manufacturing process of a semiconductor device. Thus, the method can be implemented in any suitable process chamber coupled to a cluster tool. The cluster tool can include process chambers for manufacturing semiconductor devices, such as chambers configured for etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, or any other suitable chamber used for manufacturing semiconductor devices.

[0026] Method 100 begins in operation 102 by providing a substrate 200 having a top surface 202 (as shown in FIG. 2). The term "providing" as used in this way means that the substrate 200 has been made available for processing. For example, the substrate 200 can be provided by being placed within a suitable processing chamber. In some embodiments, the substrate 200 can be a bulk semiconductor substrate. The term "bulk semiconductor substrate" refers to a substrate in which the entirety of the substrate is composed of semiconductor material. The bulk semiconductor substrate can comprise any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, the semiconductor layer can comprise one or more materials such as crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In some embodiments, the semiconductor material is silicon (Si). In some embodiments, the semiconductor material can be a doped material such as N-type doped silicon (n-Si), or P-type doped silicon (p-Si). In some embodiments, the substrate can be doped using any suitable process such as an ion implantation process. In some embodiments, the substrate can be doped to provide a high-dose dopant at a first location on the surface of the substrate 200 to prevent turn-on of parasitic bottom devices. A superlattice structure is formed over the first location. For example, in some embodiments, the surface of the substrate has a dopant density of about 10 18 atoms / cm 3 ~ about 10 19 atoms / cm 3 and can have a dopant density of about 10

[0027] In operation 104, at least one superlattice structure 204 is formed on the upper surface 202 of the substrate 200 (as shown in FIG. 2). The superlattice structure 204 includes a plurality of first layers 224 and corresponding plurality of second layers 226 that are alternately arranged in a plurality of stacked pairs. In some embodiments, the plurality of stacked layer groups include silicon (Si) and silicon germanium (SiGe) groups, and indium phosphide (InP) and indium gallium phosphide (InGaP) groups. In some embodiments, the plurality of first layers and the corresponding plurality of second layers can include any number of lattice-matched material pairs suitable for forming the superlattice structure 204. In some embodiments, the plurality of first layers 224 and the corresponding plurality of second layers 226 include two to fifty pairs of lattice-matched materials.

[0028] Generally, parasitic devices will be present at the bottom of the superlattice structure 204. In some embodiments, as described above, implantation of dopants in the substrate is used to suppress the turn-on of parasitic devices. In some embodiments, the substrate 200 is etched such that the bottom portion of the superlattice structure 204 includes a substrate portion that is not removed, enabling that substrate portion to act as a bottom release layer for the superlattice structure 204.

[0029] In some embodiments, the thicknesses of the first layer 224 and the second layer 226 are in the range of about 2 nm to about 50 nm, or in the range of about 3 nm to about 20 nm. In some embodiments, the average thickness of the first layer 224 is within 0.5 to 2 times the average thickness of the second layer 226.

[0030] In some embodiments, the dielectric material 246 is deposited on the substrate 200 using conventional chemical vapor deposition methods. In some embodiments, the dielectric material 246 is recessed below the upper surface 202 of the substrate 200 such that the bottom portion of the superlattice structure 204 is formed from the substrate 200.

[0031] In some embodiments, a replacement gate structure (e.g., dummy gate structure 208) is formed over the superlattice structure 204. The dummy gate structure 208 defines the channel region of the transistor device. The dummy gate structure 208 can be formed using any suitable conventional deposition and patterning processes known in the art.

[0032] In some embodiments, sidewall spacers 210 are formed along the outer sidewalls of the dummy gate structure 208. The sidewall spacers 210 in some embodiments comprise a suitable insulating material known in the art, such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, etc. In some embodiments, the sidewall spacers 210 are formed using any suitable conventional deposition and patterning processes known in the art, such as atomic layer deposition, plasma atomic layer deposition, plasma chemical vapor deposition, or low-pressure chemical vapor deposition.

[0033] In some embodiments, implanted source regions 232 and drain regions 234 are formed in source trenches and drain trenches, respectively. In some embodiments, the source region 232 is formed adjacent to a first end of the superlattice structure 204, and the drain region 234 is formed adjacent to a second opposite end of the superlattice structure. In the embodiment shown in FIG. 2, a view of one of the source region 232 or the drain region 234 is not shown in the front of the superlattice structure 204. The other end of the superlattice structure 204 has the other of the source region 232 or the drain region 234. In some embodiments, the source region 232 and / or the drain region 234 are formed from any suitable semiconductor material, including but not limited to silicon, germanium, silicon germanium, etc. In some embodiments, the source region 232 and the drain region 234 can be formed using any suitable deposition process, such as an epitaxial deposition process.

[0034] In some embodiments, an interlayer dielectric (ILD) layer 220 includes a source region 232 / drain region 234, a dummy gate structure 208, and sidewall spacers 210, and is blanket deposited on a substrate 200. The ILD layer 220 can be deposited using conventional chemical vapor deposition methods (e.g., plasma enhanced chemical vapor deposition and low pressure chemical vapor deposition). In one embodiment, the ILD layer 220 is formed from any well-known dielectric material such as, but not limited to, undoped silicon oxide, doped silicon oxide (e.g., BPSG, PSG), silicon nitride, and silicon oxynitride. The ILD layer 220 is then polished using a conventional chemical mechanical planarization method to expose the top of the dummy gate structure 208. In some embodiments, the ILD layer 220 is polished to expose the top of the dummy gate structure 208 and the top of the sidewall spacers 210.

[0035] In some embodiments, as shown in FIG. 3, the dummy gate structure 208 is removed to expose the channel region 214 of the superlattice structure 204. The ILD layer 220 protects the source region 232 / drain region 234 during removal of the dummy gate structure 208. The dummy gate structure 208 can be removed using conventional etching methods such as plasma dry etching or wet etching. In some embodiments, the dummy gate structure 208 comprises polysilicon, and the dummy gate structure is removed by a selective etching process. In some embodiments, the dummy gate structure 208 comprises polysilicon, and the superlattice structure 204 comprises alternating layers of silicon (Si) and silicon germanium (SiGe).

[0036] Figure 4 shows a relevant part of the electronic device of FIG. 3, and shows an end-on view of a superlattice structure 204 having alternating layers of a first material 224 and a second material 226. In operation 106, as shown in FIG. 5, a wire release process selectively etches between the first material 224 layers in the superlattice structure 204. The wire release process forms a plurality of voids 225 between the first material 224 layers, resulting in a plurality of nanosheets 244 comprising a first layer 224 that extend between the source region and the drain region.

[0037] For example, when the superlattice structure 204 is composed of silicon layers and silicon germanium layers, the silicon germanium is selectively etched to form channel nanowires (also referred to as nanosheets). The release layer (second material 226), for example, silicon germanium, can be removed using any well-known etchant that is selective to the layer of the semiconductor material layer 224, where the etchant etches the layer of the release layer (second material 226) at a significantly higher rate than the layer of the semiconductor material layer (first material 224). In some embodiments, a selective dry etching or wet etching process can be used. In some embodiments, when the semiconductor material layer (first material 224) is silicon and the release layer (second material 226) is silicon germanium, the layer of silicon germanium can be selectively removed using wet etchants such as, but not limited to, aqueous carboxylic acid / nitric acid / HF solution, and aqueous citric acid / nitric acid / HF solution. The removal of the release layer (second material 226) leaves voids 225 between the semiconductor material layers (first material 224). The voids 225 between the semiconductor material layers (first material 224) have a thickness of about 3 nm to about 20 nm. The remaining semiconductor material layers form a vertical array of channel nanowires coupled to the source region 232 / drain region 234. The channel nanowires extend parallel to the upper surface 202 of the substrate 200 and are aligned with each other to form a single row of channel nanowires. The formation of the source region 232 and drain region 234, as well as the formation of an optional lateral etch stop layer (not shown), advantageously provides self-alignment and structural integrity in the formation of the channel structure.

[0038] In optional operation 108, patterning for the formation of a PMOS device, formed by method 100, is performed. Those skilled in the art are familiar with patterning processes, including but not limited to the formation of a hard mask and / or photoresist layer, masking and etching processes. Optional operation 108 may be performed at any suitable stage in method 100 and is not limited to being performed between operation 106 and operation 110. For example, in some embodiments, optional operation 108 is performed before operation 106.

[0039] In some embodiments, an n-type metal oxide semiconductor (NMOS) portion of a complementary metal oxide semiconductor (CMOS) device is formed prior to one or more of operations 102 through 106. For example, in some embodiments, the NMOS portion of the CMOS device is formed first and then covered with a suitable hard mask. An opening is created in the hard mask for subsequent formation of the p-type metal oxide semiconductor (PMOS) portion of the CMOS without interfering with the previously formed NMOS portion. In some embodiments, the PMOS portion of the CMOS is formed prior to the formation of the NMOS portion of the CMOS.

[0040] In optional operation 110, as shown in FIG. 6, nanosheet 244 is exposed to an optional process in which nanosheet 244 of the first material 224 is trimmed from an initial thickness T0 (shown in FIG. 5) to a reduced thickness T1 (shown in FIG. 6).

[0041] Nanosheet 244 is trimmed by any suitable etching process known to those skilled in the art that is compatible with the first material 224. In some embodiments, nanosheet 244 is trimmed by exposure to a wet etching process, such as an aqueous alkaline medium such as a KOH solution, an NaOH solution, or a TMAH solution.

[0042] According to some embodiments, the reduction in the thickness of the nanosheet is greater than or equal to 50% of the initial thickness T0. In some embodiments, the initial thickness T0 is in the range of 4 nm to 10 nm, or in the range of 5 nm to 9 nm, or in the range of 6 nm to 8 nm. In some embodiments, the reduced thickness T1 is in the range of 1 / 3 to 1 / 5 of the initial thickness T0, or in the range of 1 nm to 3 nm. In some embodiments, trimming the nanosheet reduces the thickness of the nanosheet from an initial thickness T0 in the range of 6 nm to 8 nm to a reduced thickness T1 in the range of 1 nm to 3 nm.

[0043] In operation 112, a cladding material 150 is formed around each of the plurality of first layers 224 of the nanosheet 244. The cladding material 150 is formed on the nanosheet regardless of whether an optional operation 110 is performed. The cladding material 150 can be formed by any suitable process known to those skilled in the art. In some embodiments, the cladding material 150 comprises silicon germanium (SiGe) or Ge. In some embodiments, the cladding material 150 is epitaxially grown on the plurality of first layers 224 of the nanosheet 244. The cladding material is manufactured via CVD epitaxy at a temperature ranging from 450 °C to 850 °C.

[0044] Referring to FIG. 8A, in some embodiments, trimming the first layer 224 results in the nanosheet 244 closer to the substrate 200 having a reduced thickness T1 that is greater than the nanosheet 244 farther from the substrate 200. The thickness of the cladding material 250 remains uniform around each of the first layers in some embodiments.

[0045] Referring to FIG. 8B, in some embodiments where the thickness of the nanosheet 244 varies, the thickness of the cladding material 250 varies inversely with the variation in the thickness of the nanosheet. For example, as shown, the nanosheet 244 farther from the substrate has a first layer 224 of smaller, reduced thickness and a thicker layer of cladding material 250.

[0046] In some embodiments, as shown in FIG. 9, forming the cladding material 250 on the first layer 224 of the nanosheet 244 results in a cladding with a non-uniform thickness. For example, as shown, the cladding material 250 formed on the nanosheet 244 closest to the substrate 200 has a smaller thickness than the cladding material 250 formed on the nanosheet farthest from the substrate 200.

[0047] In operation 118 of method 100, as shown in FIG. 10, the nanosheet 244 undergoes a dry oxidation process. The dry oxidation process converts the nanosheet 244 such that the cladding material 250 is surrounded by an oxide 227 of the first material 224. For example, in an embodiment where the first layer 224 comprises silicon (Si) and the cladding material 250 comprises silicon germanium (SiGe), the dry oxidation causes the silicon germanium (SiGe) cladding material 250 to be in the center of the nanosheet 244 surrounded by the silicon (Si) first layer 224 and a small layer of silicon dioxide 227 on the surface of the silicon (Si) first layer 224, rearranging the materials.

[0048] Dry oxidation can be carried out by any suitable technique known to those skilled in the art. In some embodiments, the dry oxidation process is carried out by exposing the semiconductor device to a rapid thermal oxidation (RTO) process. In some embodiments, the RTO process ramps the temperature of the substrate from an initial temperature (e.g., room temperature) to a maximum temperature in the range of 700 °C to 1050 °C at a rate greater than or equal to 25 °C / second, 50 °C / second or more, at 5 to 780 torr for between 1 and 5 minutes. During the dry oxidation process, the process environment of some embodiments includes one or more of water vapor, oxygen (O2) or ozone (O3), in some cases, under a mixture of O2 / N2 gases.

[0049] The dry oxidation process of operation 118 results in a rearrangement of the layers of the nanosheet 244 such that the cladding material 250 effectively replaces the first layer 224. In this configuration, the cladding material 250 becomes the semiconductor material layer 245.

[0050] In operation 120 of method 100, as shown in FIG. 11, the first layer 224 and the oxide 227 of the first layer 224 are removed from the semiconductor material layer 245 by any suitable etching process. In some embodiments, removing the oxide 227 and the first layer 224 includes exposing the substrate to a solution of diluted hydrofluoric acid (about 1:100 to 1:150 HF:H2O) at room temperature.

[0051] The method 100 of some embodiments includes operation 114 in which an oxide is formed on the cladding material 250 before dry oxidation in operation 118. FIG. 12A shows an embodiment in which a first layer 224 of the nanosheet 244 is surrounded by the cladding material 250 and an oxide 251 of the cladding material 250. The oxide 251 of the cladding material 250 can be formed by any suitable oxidation process known to those skilled in the art. In some embodiments, the oxide 251 of the cladding material 250 is formed by an atomic layer deposition (ALD) process at a low processing temperature ranging from 250° C. to 450° C. and, in some cases, using plasma treatment or an extended function. In some embodiments, the oxide 251 of the cladding material 250 is formed by rapid plasma oxidation (RPO). In some embodiments, the RPO process exposes the substrate 200 to an oxygen-containing plasma (e.g., molecular oxygen (O2), ozone (O3)) at a temperature within the range of 350° C. to 650° C. and at a pressure ranging from 5 to 300 torr.

[0052] FIG. 12B shows the embodiment of FIG. 12A after exposure to the dry oxidation process in operation 118, which results in the rearrangement of various material layers. For example, if the first layer 224 comprises silicon and the cladding material 250 comprises SiGe, the oxide 251 of the cladding material is silicon germanium oxide (SiGeO), and the dry oxidation process moves the SiGe to the center of the nanosheet surrounded by an oxide layer 229 comprising silicon, and silicon, germanium, and oxygen atoms.

[0053] FIG. 13A shows another embodiment of the oxide formation process according to operation 114 of the method 100. In the illustrated embodiment, the first layer 224 and the nanosheet 244 of the cladding material 250 are surrounded by a fluid oxide 253. In some embodiments, the fluid oxide 253 is formed by a high density plasma process with a film density of about 2.1 to about 2.3 g-cm -3 In some embodiments, the fluid oxide 253 of some embodiments comprises silicon oxide.

[0054] FIG. 13B shows the embodiment of FIG. 13A after exposure to a dry oxidation process in operation 118 of method 100. The dry oxidation process results in the rearrangement of various material layers. For example, if the first layer 224 comprises silicon, the cladding material 250 comprises SiGe, and the flowable oxide 253 comprises silicon oxide, the dry oxidation process results in a rearrangement such that the SiGe moves to the center of the nanosheet surrounded by silicon and the flowable oxide 253.

[0055] The method 100 of some embodiments further includes operation 116 in which the oxide is removed prior to (in operation 118) dry oxidation. For example, the oxide of FIG. 12A or FIG. 13A is removed, and then the dry oxidation process follows. In some embodiments, the oxide is removed by exposure to a dilute HF / H2O2 solution (HF:H2O of about 1:100 to 1:150) prior to dry oxidation.

[0056] Operations 120, 122, and / or 126 of method 100 represent one or more oxide removal post-treatments according to some embodiments. The one or more oxide removal post-processes can be any of the processes known to those skilled in the art for the completion of the hGAA device. Referring to FIGS. 14 and 15, in some embodiments, in operation 122, an oxide layer 252 (also referred to as a capping layer) is formed or grown on the semiconductor material layer 245. The oxide layer 252 can be any suitable oxide formed by any suitable technique known to those skilled in the art. In some embodiments, the oxide layer comprises a silicon capping layer. In some embodiments, at a temperature of 500°C to 800°C, a separated selectively CVD epitaxial growth Si layer (e.g., 5 to 30 Å).

[0057] During optional operation 124, the hard mask (PMOS patterning) formed during optional operation 108 is removed. Optional operation 124 can be formed at any suitable time during method 100 and is not limited to being performed between operation 122 and operation 126. The hard mask can be removed by any suitable technique known to those skilled in the art. For example, in some embodiments, the hard mask is removed by a wet etching process.

[0058] In the illustrated embodiment, during operation 126, a high-k dielectric 254 is formed on oxide layer 252. The high-k dielectric 254 can be any suitable high-k dielectric material deposited by any suitable deposition technique known to those skilled in the art. The high-k dielectric 254 of some embodiments comprises hafnium oxide. In some embodiments, a conductive material 256 such as titanium nitride, tungsten, cobalt, aluminum, etc. is on the high-k dielectric 254. The conductive material 256 is formed using any suitable deposition process such as atomic layer deposition (ALD) to ensure the formation of a layer having a uniform thickness around each of the semiconductor material layers 245.

[0059] In some embodiments, a gate electrode 242 is formed on substrate 200 and surrounds each of the doped semiconductor material layers 245. The gate electrode 242 can be formed from any suitable gate electrode material known in the art. The gate electrode material is deposited using any suitable deposition process such as atomic layer deposition (ALD) to ensure that the gate electrode 242 is formed around and between each of the semiconductor material layers 245. The resulting device formed using the method described herein is a horizontal gate all-around device according to one embodiment of the present disclosure. Some embodiments of the present disclosure are directed to horizontal gate all-around devices comprising semiconductor material layers 245 as nanowires or nanosheets in the channel between the source region and the drain region.

[0060] Some embodiments of the present disclosure are directed to an electronic device 300 comprising a PMOS 310 and an NMOS 320, as shown in FIG. 16. The PMOS 310 includes a SiGe nanowire 312 between a p-type source region 332 and a p-type drain region 334. Those skilled in the art will recognize that the p-type source region 332 and the p-type drain region 334 may be positioned in any particular order and will be familiar with their structures. The SiGe nanowire 312 is separated by an oxide layer 252, a high-k dielectric 254, and a conductive material 256, as described above. The NMOS 320 includes a Si nanowire 314 between an n-type source region 342 and an n-type drain region 344. Those skilled in the art will recognize that the n-type source region 342 and the n-type drain region 344 may be positioned in any particular order and will be familiar with their structures. The Si nanowire 314 is separated by an oxide layer 252, a high-k dielectric 254, and a conductive material 256, as described above.

[0061] Some embodiments of the present disclosure are directed to an integrated process implemented within a single cluster tool. FIG. 17 is a schematic plan view of an exemplary multi-chamber processing system according to one or more embodiments. FIG. 17 shows a schematic plan view of an example of a multi-chamber processing system 400 according to an embodiment of the present disclosure. The processing system 400 generally includes a factory interface 402, load lock chambers 404, 406, transfer chambers 408, 410 each having a respective transfer robot 412, 414, holding chambers 416, 418, and processing chambers 420, 422, 424, 426, 428, 430. As detailed herein, wafers within the processing system 400 can be processed in various chambers and transferred between various chambers without exposing the wafers to the ambient environment outside the processing system 400 (e.g., an atmospheric ambient environment such as may exist within a fab). For example, wafers can be processed in various chambers and transferred between various chambers in a low pressure (e.g., about 300 Torr or less) or vacuum environment without breaking the low pressure or vacuum environment during various processes implemented on the wafers within the processing system 400. Thus, the processing system 400 can provide an integrated solution for some processing of wafers.

[0062] In the illustrated example of FIG. 17, the factory interface 402 includes a docking station 440 and a factory interface robot 442 to facilitate wafer transfer. The docking station 440 is configured to receive one or more front-opening unified pods (FOUPs) 444. In some examples, each factory interface robot 442 generally includes a blade 448 disposed on one end of each respective factory interface robot 442 configured to transfer wafers from the factory interface 402 to the load lock chambers 404, 406.

[0063] The load lock chambers 404, 406 have respective ports 450, 452 coupled to the factory interface 402 and respective ports 454, 456 coupled to the transfer chamber 408. The transfer chamber 408 further has respective ports 458, 460 coupled to the holding chambers 416, 418 and respective ports 462, 464 coupled to the processing chambers 420, 422. Similarly, the transfer chamber 410 has respective ports 466, 468 coupled to the holding chambers 416, 418 and respective ports 470, 472, 474, 476 coupled to the processing chambers 424, 426, 428, 430. The ports 454, 456, 458, 460, 462, 464, 466, 468, 470, 472, 474, 476 can be slit valve openings with slit valves for passing a wafer therethrough by the transfer robots 412, 414 and for providing a seal between the respective chambers to prevent gas from passing between the respective chambers. Generally, any port is open for transferring a wafer therethrough. In some cases, the port is closed.

[0064] The load lock chambers 404, 406, the transfer chambers 408, 410, the holding chambers 416, 418, and the processing chambers 420, 422, 424, 426, 428, 430 can be fluidly coupled to a gas and pressure control system (not shown in detail). The gas and pressure control system can include one or more gas pumps (e.g., turbo pumps, cryo pumps, roughing pumps), a gas source, various valves, and conduits fluidly coupled to the various chambers. During operation, the factory interface robot 142 transfers wafers from the FOUP 444 through port 450 or 452 to the load lock chamber 404 or 406. The gas and pressure control system then pumps down the load lock chamber 404 or 406. The gas and pressure control system further maintains the transfer chambers 408, 410 and the holding chambers 416, 418 in an internal low pressure or vacuum environment (which may include an inert gas). Thus, pumping down the load lock chamber 404 or 406 facilitates passing wafers, for example, between the atmospheric environment of the factory interface 402 and the low pressure or vacuum environment of the transfer chamber 408.

[0065] For the wafers in the pumped-down load lock chambers 404 or 406, transfer robot 412 transfers the wafers from the load lock chambers 404 or 406 into the transfer chamber 408 through ports 454 or 456. Transfer robot 412 can then transfer the wafers to any one of and / or between the processing chambers 420, 422 through their respective ports 462, 464 for processing, and / or to any one of and / or between the holding chambers 416, 418 through their respective ports 458, 460 to hold waiting for further transfer. Similarly, transfer robot 414 can access the wafers in the holding chambers 416 or 418 through ports 466 or 468, and transfer the wafers to any one of and / or between the processing chambers 424, 426, 428, 430 through their respective ports 470, 472, 474, 476 for processing, and / or to any one of and / or between the holding chambers 416, 418 through their respective ports 466, 468 to hold waiting for further transfer. The transfer and holding of wafers within and between the various chambers can be in a low pressure or vacuum environment provided by the gas and pressure control system.

[0066] The processing chambers 420, 422, 424, 426, 428, 430 can be any suitable chambers for processing wafers. In some embodiments, processing chamber 420 may be capable of performing an annealing process, processing chamber 422 may be capable of performing a cleaning process, and processing chambers 424, 426, 428, 430 may be capable of performing an epitaxial growth process. In some examples, processing chamber 422 may be capable of performing a cleaning process, processing chamber 420 may be capable of performing an etching process, and processing chambers 424, 426, 428, 430 may be capable of performing their respective epitaxial growth processes.

[0067] The system controller 490 is coupled to the processing system 400 to control the processing system 400 or its components. For example, the system controller 490 can control the operation of the processing system 400 by using direct control of chambers 404, 406, 408, 416, 418, 410, 420, 422, 424, 426, 428, 430 of the processing system 400 or by controlling controllers associated with chambers 404, 406, 408, 416, 418, 410, 420, 422, 424, 426, 428, 430. During operation, the system controller 490 enables data collection and feedback from each chamber to coordinate the performance of the processing system 400.

[0068] The system controller 490 generally includes a central processing unit (CPU) 492, a memory 494, and a support circuit 496. The CPU 492 can be one of any form of general-purpose processor that can be used in an industrial setting. The memory 494, or non-transitory computer-readable medium, is accessible by the CPU 492 and can be one or more of memories such as random access memory (RAM), read-only memory (ROM), floppy disks, hard disks, or any other form of local or remote digital storage. The support circuit 496 is coupled to the CPU 492 and can include a cache, a clock circuit, an input / output subsystem, a power supply, and the like. The various methods disclosed herein can generally be implemented under the control of the CPU 492 by the CPU 492 executing computer instruction codes stored in the memory 494 (or in the memory of a specific process chamber), for example, as software routines. When the computer instruction codes are executed by the CPU 492, the CPU 492 controls the chamber to perform a process according to various methods.

[0069] Other processing systems can be of other configurations. For example, more or fewer processing chambers can be coupled to the transfer device. In the illustrated example, the transfer device includes transfer chambers 408, 410 and holding chambers 416, 418. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) can be implemented as the transfer device in the processing system.

[0070] References throughout this specification to "one embodiment", "certain embodiments", "one or more embodiments" or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one or more embodiments", "in certain embodiments" or "in an embodiment" etc. throughout this specification are not necessarily referring to the same embodiment of the present disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0071] Although the disclosure herein has been described with reference to particular embodiments, those skilled in the art will understand that the described embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatuses of the present disclosure without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure can include modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. A method of forming a semiconductor device, comprising: selectively etching a superlattice structure on a substrate, the superlattice structure comprising a plurality of first layers of a first material and a plurality of corresponding second layers of a second material alternately arranged in a plurality of stacked pairs, removing each of the second layers to form a plurality of voids in the superlattice structure and a plurality of nanosheets comprising the first layers extending between a source region and a drain region; forming a cladding material around each of the plurality of first layers of the nanosheets to form a nanosheet having the first material with the cladding material around the first material; dry oxidizing the nanosheet to convert the nanosheet such that the cladding material is surrounded by an oxide of the first material; removing the first material to leave the nanosheets of the cladding material; A method comprising the steps of:

2. The method of claim 1, wherein the first material comprises silicon (Si).

3. The method of claim 1, wherein the second material comprises silicon germanium (SiGe).

4. The method of claim 1, wherein the cladding material comprises silicon germanium (SiGe).

5. The method of claim 4, wherein the cladding material is epitaxially grown on the plurality of first layers of the nanosheets.

6. The method of claim 1, wherein dry oxidizing the nanosheet comprises exposing the semiconductor device to a rapid thermal oxidation process at a temperature in the range of 700 °C to 950 °C.

7. The method of claim 1, wherein removing the oxide of the first material comprises exposing the first material to a dilute HF solution.

8. The method of claim 1, further comprising trimming the nanosheets before forming the cladding material to reduce the thickness of the nanosheets from an initial thickness in the range of 6 nm to 8 nm to a reduced thickness in the range of 2 nm to 3 nm.

9. The method of claim 8, wherein the nanosheets closer to the substrate have a reduced thickness that is greater than the nanosheets farther from the substrate.

10. The method according to claim 1, further comprising forming an oxide on the cladding material before dry oxidation.

11. The method according to claim 10, wherein the oxide on the cladding material is formed by atomic layer deposition.

12. The method according to claim 10, wherein the oxide on the cladding material comprises a flowable oxide formed by high density plasma.

13. The method according to claim 10, wherein the oxide on the cladding material is formed by rapid plasma oxidation at a temperature in the range of 400°C to 600°C.

14. Prior to dry oxidation, further comprising removing said oxide by exposure to a dilute HF / H ２ O ２ solution, the method of claim 10.

15. The method according to claim 1, further comprising forming a silicon cap on the nanosheet of the cladding material by epitaxial growth or by chemical vapor deposition.

16. The method according to claim 15, wherein the silicon cap has a thickness in the range of 2 Å to 20 Å.

17. The method according to claim 15, further comprising forming a high-k metal gate in contact with the nanosheet of the cladding material.

18. The method according to claim 1, further comprising forming the superlattice structure on the upper surface of a substrate, wherein each of the first layer and the second layer has a thickness separately in the range of 3 nm to 20 nm.

19. The method according to claim 18, further comprising forming the source region adjacent to the first end of the superlattice structure and the drain region adjacent to the second opposite end of the superlattice structure.

20. A PMOS having a SiGe channel between the source region and the drain region, and an NMOS having a Si channel between the source region and the drain region comprising an electronic device.

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