Memory Controller and Memory System for Executing Data Search

Abstract

In some embodiments, the memory system includes a volatile memory device and a memory controller operably coupled to the volatile memory device. The volatile memory device is configured to store a logical-to-physical (L2P) mapping table. The memory controller maintains the L2P mapping table stored within the volatile memory device such that the L2P mapping table is configured to map a first set of logical addresses to identifiers (IDs) of memory blocks of the cache, respectively.

Description

Technical Field

[0001] The present disclosure relates to a memory device and an operating method thereof.

Background Art

[0002] Solid State Drives (SSDs) have gained overwhelming popularity in recent years due to many advantages over traditional Hard Disk Drives (HDDs), such as faster read and write speeds, durability and reliability, reduced power consumption, silent operation, and a smaller form factor. SSDs generally use NAND flash memory for non-volatile storage. Some SSDs, especially enterprise SSDs, also use volatile memory (e.g., Dynamic Random Access Memory (DRAM)) to enhance their performance, enabling faster access to data and more efficient handling of read and write operations.

Summary of the Invention

Means for Solving the Problems

[0003] In one aspect, a memory system includes a volatile memory device and a memory controller operatively coupled to the volatile memory device. The volatile memory device is configured to store a Logical-to-Physical (L2P) mapping table. The memory controller maintains the L2P mapping table stored within the volatile memory device, such that the L2P mapping table is configured to map a first set of logical addresses to identifiers (IDs) of memory blocks of the cache, respectively.

[0004] In some implementations, the memory controller is further configured to cache a first set of data within the memory blocks. In some implementations, the first set of data is associated with the first set of logical addresses, respectively.

[0005] In some implementations, the memory controller is further configured to retrieve a first set of cached data within a memory block based on an L2P mapping table.

[0006] In some implementations, the volatile memory device includes a cache.

[0007] In some implementations, the memory system further includes a non-volatile memory device operatively coupled to the memory controller. In some implementations, the memory controller is further configured to store a second set of data within a memory region of the non-volatile memory device. In some implementations, the second set of data is respectively associated with a second set of logical addresses. In some implementations, the memory controller maintains an L2P mapping table stored within the volatile memory device, such that the L2P mapping table is further configured to map the second set of logical addresses to physical addresses of the memory region of the non-volatile memory device, respectively.

[0008] In some implementations, the volatile memory device includes DRAM and the non-volatile memory device includes NAND flash memory.

[0009] In some implementations, in response to receiving a write request indicating one data of the first set of data associated with a first logical address of the first set of logical addresses, the memory controller is further configured to allocate one data of the first set of data to a first memory block of the memory blocks. In some implementations, the first memory block has a first ID among the IDs. The memory controller is further configured to fetch one data of the first set of data to cache the one data of the first set of data within the first memory block.

[0010] In some implementations, to maintain the L2P mapping table, in response to the memory controller fetching one piece of data from the first set of data into the first memory block, the L2P mapping table is updated to map the first logical address to the first ID by an L2P search engine configured to do so.

[0011] In some implementations, in response to the memory controller receiving a read request indicating one piece of data from the first set of data associated with the second logical address of the first set of logical addresses, the memory controller is further configured to fetch one piece of data from the first set of data from the second memory block among the memory blocks in the cache based on the L2P mapping table.

[0012] In some implementations, the memory controller includes an L2P search engine configured to determine the address of the L2P mapping table in the volatile memory device based on the second logical address and identify the second ID among the IDs at the address of the L2P mapping table in the volatile memory device. In some implementations, the second memory block has the second ID.

[0013] In another aspect, a memory system includes a non-volatile memory device including memory regions respectively associated with physical addresses, a volatile memory device including memory blocks respectively associated with IDs, and a memory controller operatively coupled to the volatile memory device and the non-volatile memory device. The volatile memory device is configured to store an L2P mapping table. The L2P mapping table maps a logical address of data to an ID of a memory block in the volatile memory device and to a physical address of a memory region in the non-volatile memory device, respectively. The memory controller is configured to search for one piece of data based on the L2P mapping table.

[0014] In some implementations, to retrieve a single piece of data, the memory controller is configured to determine the address of an L2P mapping table in a volatile memory device based on a logical address associated with the single piece of data and to determine the value at the address of the L2P mapping table.

[0015] In some implementations, to retrieve a single piece of data, the memory controller is further configured to fetch a single piece of data from a memory block in the volatile memory device having that ID in response to the value being one of the IDs of the memory blocks in the volatile memory device, and to fetch a single piece of data from a memory region in the non-volatile memory device having a physical address in response to the value being one of the addresses of the memory regions in the non-volatile memory device.

[0016] In some implementations, to retrieve a single piece of data, the memory controller includes a plurality of L2P search engines configured to search for a plurality of pieces of data in parallel respectively based on an L2P mapping table.

[0017] In some implementations, the memory controller is further configured to cache a single piece of data in the volatile memory device or to flush a single piece of data from the volatile memory device to the non-volatile memory device.

[0018] In another aspect, the memory controller includes a volatile memory device interface operably coupled to the volatile memory device and maintains an L2P mapping table stored in the volatile memory device via the volatile memory device interface, whereby the L2P mapping table includes an L2P search engine configured to map a first set of logical addresses to the IDs of cache memory blocks respectively.

[0019] In some implementations, the L2P search engine is further configured to search for a first set of data that is associated with a first set of logical addresses and cached within a memory block based on an L2P mapping table.

[0020] In some implementations, the memory controller further includes a non-volatile memory device interface operably coupled to a non-volatile memory device. In some implementations, the L2P search engine maintains an L2P mapping table stored within a volatile memory device, such that the L2P mapping table is also further configured to map a second set of logical addresses to physical addresses of memory regions of the non-volatile memory device, respectively.

[0021] In some implementations, the L2P search engine is further configured to search for a second set of data that is associated with a second set of logical addresses and stored within a memory region based on an L2P mapping table.

[0022] In some implementations, the volatile memory device includes DRAM and the non-volatile memory device includes NAND flash memory.

[0023] In some implementations, the memory controller further includes a range splitting accelerator further configured to allocate one data of the first set of data to a first memory block of the memory blocks in response to receiving a write request indicating one data of the first set of data associated with a first logical address of the first set of logical addresses. In some implementations, the first memory block has a first ID among the IDs. In some implementations, the memory controller further includes a host interface configured to fetch one data of the first set of data to cache one data of the first set of data within the first memory block.

[0024] In some implementations, to maintain the L2P mapping table, the L2P search engine is further configured to update the L2P mapping table to map the first logical address to the first ID in response to the host interface fetching one piece of data from the first set of data into the first memory block.

[0025] In some implementations, the memory controller further includes a host interface configured to fetch one piece of data from the first set of data from the second memory block among the memory blocks in the cache based on the L2P mapping table in response to receiving a read request indicating one piece of data from the first set of data associated with the second logical address of the first set of logical addresses.

[0026] In some implementations, the L2P search engine is further configured to determine the address of the L2P mapping table in the volatile memory device based on the second logical address and identify the second ID among the IDs at the address of the L2P mapping table in the volatile memory device, and the second memory block has the second ID.

[0027] In another aspect, a method for operating a memory controller is provided. An L2P mapping table stored in a volatile memory device is generated. The L2P mapping table is maintained such that the L2P mapping table maps the first set of logical addresses to the IDs of the memory blocks in the cache, respectively.

[0028] In some implementations, the first set of data is cached in a memory block. In some implementations, the first set of data is associated with the first set of logical addresses, respectively.

[0029] In some implementations, the first set of data in the memory block is searched based on the L2P mapping table.

[0030] In some implementations, the volatile memory device includes a cache.

[0031] In some implementations, a second set of data is stored within a memory region of the non-volatile memory device. In some implementations, the second set of data is respectively associated with a second set of logical addresses. In some implementations, an L2P mapping table stored within the volatile memory device is maintained, whereby the L2P mapping table also maps each second set of logical addresses to a physical address of the memory region of the non-volatile memory device.

[0032] In some implementations, the volatile memory device includes DRAM and the non-volatile memory device includes NAND flash memory.

[0033] In some implementations, in response to receiving a write request indicating one piece of data of a first set of data associated with a first logical address of a first set of logical addresses, one piece of data of the first set of data is allocated to a first memory block among the memory blocks. In some implementations, the first memory block has a first ID among the IDs. In some implementations, one piece of data of the first set of data is fetched to cache one piece of data of the first set of data within the first memory block.

[0034] In some implementations, in response to fetching one piece of data of the first set of data to the first memory block to maintain the L2P mapping table, the L2P mapping table is updated to map the first logical address to the first ID.

[0035] In some implementations, in response to receiving a read request indicating one piece of data of a first set of data associated with a second logical address of a first set of logical addresses, one piece of data of the first set of data is fetched from a second memory block among the memory blocks in the cache based on the L2P mapping table.

[0036] In some implementations, the address of the L2P mapping table in the volatile memory device is determined based on the second logical address, and a second ID among the IDs is identified at the address of the L2P mapping table in the volatile memory device. In some implementations, the second memory block has the second ID.

[0037] The accompanying drawings, which are incorporated herein and form a part of this specification, illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure and to enable one of ordinary skill in the art to make and use the disclosure.

Brief Description of the Drawings

[0038]

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DETAILED DESCRIPTION OF THE INVENTION

[0039] The present disclosure will be described with reference to the accompanying drawings.

[0040] In general, terms can be understood, at least in part, from their usage in context. For example, the term "one or more" as used herein can be used, at least in part, depending on the context, to describe any feature, structure, or property in a singular sense, or to describe a combination of features, structures, or properties in a plural sense. Similarly, terms such as "a", "an", or "the" can again be understood, at least in part, depending on the context, to convey a singular usage or a plural usage. Additionally, the term "based on" is not necessarily intended to convey an exclusive set of factors, but rather can again be understood, at least in part, depending on the context, to allow for the presence of additional factors that are not necessarily explicitly described.

[0041] Data search within an SSD involves identifying and accessing the requested data stored in a non-volatile memory device such as NAND flash memory. The purpose of data search is to efficiently search for and modify data as required by the system. This can be achieved through the translation layer of the memory controller that maps the logical addresses used by the operating system to physical addresses within the SSD. Therefore, the memory controller plays an important role in the management of data search and ensuring optimal performance.

[0042] For enterprise SSDs, or any SSD with volatile memory such as DRAM, "hot data" refers to data that is stored in the cache, frequently used, and / or recently accessed. Hot data is often cached in DRAM to speed up future access requests. However, the efficiency of known search algorithms for hot data within enterprise SSDs is limited by their O(n) or O(log n) time complexity, which can become a performance bottleneck, especially when the data volume is huge.

[0043] To address one or more of the foregoing problems, the present disclosure introduces a data search method in a memory system that extends the use of the L2P mapping table to both non-volatile memory and volatile memory to reduce the computational complexity of cache data search in the volatile memory and improve search efficiency. In some implementations, similar to the physical address of a memory region in non-volatile memory (e.g., the physical page address (PPA) in a NAND flash memory), the physical address of a memory block in volatile memory (e.g., the block identifier (ID)) is mapped to the logical address of host / user data (e.g., the logical block address (LBA)) in a uniform and extended L2P mapping table for data search across non-volatile memory and volatile memory. Accordingly, the time complexity for hot data search can be reduced to O(1). In some implementations, the memory controller maintains a uniform and extended L2P mapping table and updates the L2P mapping table in response to handling write requests and read requests from the host. In some implementations, in contrast to firmware, multiple dedicated circuits are used to handle data search requests in parallel to further improve search efficiency and reduce firmware overhead.

[0044] Figure 1 shows a block diagram of a system 100 including a memory system 102 according to some aspects of the present disclosure. The system 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. As shown in Figure 1, the system 100 can include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 can be an electronic device such as a central processing unit (CPU), or a processor of a system-on-chip (SoC) such as an application processor (AP). The host 108 can be configured to send data (also known as user data or host data) to or receive data from the memory system 102. The memory system 102 can be a storage product that integrates a memory controller 106 and one or more memory devices 104 such as an SSD.

[0045] The memory device 104 can be any memory device disclosed in the present disclosure, including a non-volatile memory device such as a NAND flash memory device. In some implementations, the memory device 104 can also include one or more volatile memory devices such as a DRAM device or a static random access memory (SRAM) device.

[0046] According to some implementations, the memory controller 106 is operably coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some implementations, the memory controller 106 is designed to operate in a low-duty cycle environment, such as a Secure Digital (SD) card, a CompactFlash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in an electronic device, such as a personal computer, a digital camera, a mobile phone, etc. In some implementations, the memory controller 106 is designed to operate in a high-duty cycle environment using a solid state drive (SSD) or an embedded multimedia card (eMMC) as a data storage device for mobile devices, such as smartphones, tablets, laptop computers, etc., and enterprise storage arrays. The memory controller 106 can be configured to control the operations of the memory device 104, such as read operations, program / write operations, and / or erase operations. The memory controller 106 can also be configured to manage various functions for the data stored in or to be stored in the memory device 104, including, but not limited to, bad block management, garbage collection, L2P address translation, wear leveling, etc. In some implementations, the memory controller 106 is further configured to process an error correction code (ECC) for data read from or written to the memory device 104. Any other suitable functions can similarly be performed by the memory controller 106, such as formatting the memory device 104. The memory controller 106 can communicate with an external device (e.g., the host 108) according to a specific communication protocol.For example, the memory controller 106 can communicate with an external device via at least one of various interface protocols such as the Non-Volatile Memory Express (NVMe) protocol, the NVMe over Fabrics (NVMe-oF) protocol, the Peripheral Component Interconnect Express (PCI-E) protocol, the Universal Serial Bus (USB) protocol, the Multimedia Card (MMC) protocol, the Peripheral Component Interconnection (PCI) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer System Interface (SCSI) protocol, the Enhanced Small Disk Interface (ESDI) protocol, the Integrated Drive Electronics (IDE) protocol, the FireWire protocol, etc.

[0047] In accordance with the scope of the present disclosure and as disclosed in detail below, the memory controller 106 can be configured to maintain an L2P mapping table that maps the logical addresses of host / user data to the ID of a memory block within the volatile memory device of the memory device 104 and the address of a memory area within the non-volatile memory device of the memory device 104, respectively. The memory controller 106 can also be configured to retrieve one piece of data based on the L2P mapping table.

[0048] Memory controllers 106 and one or more memory devices 104 can be integrated into various types of storage devices and can be included within the same package, for example, a universal flash storage (UFS) package or an eMMC package. That is, the memory system 102 can be implemented and packaged into different types of end electronic products. In one example shown in FIG. 2A, a memory controller 106 and a single memory device 104 can be integrated within a memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMC micro), an SD card (SD, mini SD, micro SD, SDHC), a UFS, etc. The memory card 202 can further include a memory card connector 204 that couples the memory card 202 to a host (e.g., host 108 in FIG. 1). In another example shown in FIG. 2B, a memory controller 106 and multiple memory devices 104 can be integrated within an SSD 206. The SSD 206 can further include an SSD connector 208 that couples the SSD 206 to a host (e.g., host 108 in FIG. 1). In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than that of the memory card 202. In some implementations, the memory system 102 is implemented as an SSD 206 that includes both non-volatile memory devices and volatile memory devices as memory devices 104 such as enterprise SSDs.

[0049] FIG. 3 shows a block diagram of a memory controller 300 according to some aspects of the present disclosure. The memory controller 300 can be an example of the memory controller 106 of FIG. 1. As shown in FIG. 3, the memory controller 300 can include a processing unit 308, a SRAM 310, and a read-only memory (ROM) 311. In some implementations, the processing unit 308 is implemented by a microprocessor (e.g., a digital signal processor (DSP)) or a microcontroller (also known as a microcontroller unit (MCU)) that executes firmware and / or software modules to perform the various functions described herein. The various firmware modules within the memory controller 300 described herein can be implemented as firmware code or instructions stored in the ROM 311 and executed by the processing unit 308. In some implementations, the processing unit 308 includes one or more hardware circuits, such as fixed logic units including logic gates, multiplexers, flip-flops, state machines, field programmable gate arrays (FPGAs), programmable logic devices (PLDs), etc. For example, the hardware circuit can include a dedicated circuit that performs a given logic function known at the time of device manufacture, such as an application specific integrated circuit (ASIC).

[0050] As shown in FIG. 3, the memory controller 300 can also include various input / output (I / O) interfaces (I / F), such as a NAND interface 312, a DRAM interface 314, and a host interface 316, which are operably coupled to a NAND flash memory 302 (e.g., an example of a non-volatile memory device), a DRAM 304 (e.g., an example of a volatile memory device), and a host 306 (e.g., an example of host 108), respectively. The NAND interface 312, the DRAM interface 314, and the host interface 316 can be configured to transfer data, commands, clocks, or any suitable signals between the processing unit 308 and each of the NAND flash memory 302, the DRAM 304, and the host 306. The NAND interface 312, the DRAM interface 314, and the host interface 316 can implement any suitable communication protocol, such as the NVMe protocol and the PCI-E protocol, the double data rate (DDR) protocol, etc., to facilitate data transfer, communication, and management.

[0051] As described above, both the SRAM 310 and the DRAM 304 can be regarded as volatile memory devices that can be controlled and accessed by the memory controller 300 within the memory system. Consistent with the scope of the present disclosure, the cache can be implemented by, for example, the SRAM 310 and / or the DRAM 304 as part of the volatile memory device. FIG. 3 shows that the SRAM 310 is within the memory controller 300 and the DRAM 304 is outside the memory controller 300, but it is understood that in some examples, both the SRAM 310 and the DRAM 304 can be within or outside the memory controller 300.

[0052] FIG. 4 shows a schematic circuit diagram of a NAND flash memory device 400 including a peripheral circuit 402 according to some aspects of the present disclosure. The NAND flash memory device 400 can be an example of the NAND flash memory 302 of FIG. 3. The NAND flash memory device 400 can include a memory cell array 401 and a peripheral circuit 402 operatively coupled to the memory cell array 401. The memory cells 406 within the memory cell array 401 are provided in the form of an array of NAND memory strings 408 each extending perpendicularly over a substrate (not shown). In some implementations, each NAND memory string 408 includes a plurality of memory cells 406 operatively coupled in series and stacked vertically. Each memory cell 406 can hold a continuous analog value, such as a voltage or charge, depending on the number of electrons trapped within the region of the memory cell 406. Each memory cell 406 can be either a floating gate type memory cell including a floating gate transistor or a charge trap type memory cell including a charge trap transistor.

[0053] In some implementations, each memory cell 406 is a single level cell (SLC) having two possible levels (memory states) and thus can store 1-bit of data. For example, a first state “0” can correspond to a first range of threshold voltages and a second state “1” can correspond to a second range of threshold voltages. In some implementations, each memory cell 406 is an xLC that can store 2 or more bits of data at 5 or more levels. For example, the xLC can store 2 bits per cell (also known as a multi-level cell (MLC)), 3 bits per cell (also known as a triple-level cell (TLC)), or 4 bits per cell (also known as a quad-level cell (QLC)). Each xLC can be programmed to take on a range of possible nominal stored values (i.e., corresponding to 2 N sets of N-bit data). In some implementations, each memory cell 406 is programmed to take on 2 Nis set to one of the levels, where N is an integer greater than 2.

[0054] As shown in FIG. 4, each NAND memory string 408 can also include a source select gate (SSG) transistor 410 at its source end and a drain select gate (DSG) transistor 412 at its drain end. The SSG transistor 410 and the DSG transistor 412 can be configured to activate the selected NAND memory string 408 (a column of the array) during read and program operations. In some implementations, the sources of the NAND memory strings 408 within the same block 404 are coupled via the same source line (SL) 414, e.g., a common SL. In other words, according to some implementations, all of the NAND memory strings 408 within the same block 404 have an array common source (ACS). According to some implementations, the drain of each NAND memory string 408 is coupled to a respective bit line 416 through which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 408 is configured to be selected or deselected by applying a select voltage or a deselect voltage to the gate of each respective DSG transistor 412 via one or more DSG lines 413 and / or by applying a select voltage or a deselect voltage to the gate of each respective SSG transistor 410 via one or more SSG lines 415.

[0055] As shown in FIG. 4, the NAND memory string 408 can be configured among a plurality of blocks 404, and each of the plurality of blocks 404 can have, for example, a common source line 414 coupled to the ACS. In some implementations, each block 404 is a basic data unit for an erase operation, that is, all memory cells 406 on the same block 404 are erased simultaneously. To erase the memory cells 406 within the selected block 404, the source lines 414 coupled to the selected block 404 as well as the unselected blocks 404 in the same plane as the selected block 404 can be biased with an erase voltage (Vers) such as a high positive bias voltage (e.g., 20 V or higher).

[0056] Memory cells 406 of adjacent NAND memory strings 408 can be coupled via word lines 418 that select which rows of the memory cells 406 are affected by read and program operations. In some implementations, each word line 418 is coupled to a physical page 420 of the memory cells 406, which is the basic data unit for read and write (program) operations. The size of one physical page 420 in bits can be related to the number of NAND memory strings 408 coupled by the word lines 418 within one block 404. Each word line 418 can include a plurality of control gates (gate electrodes) at each memory cell 406 within the respective physical page 420 and a gate line that couples the control gates.

[0057] The peripheral circuit 402 can be operably coupled to the memory cell array 401 via bit lines 416, word lines 418, source lines 414, SSG lines 415, and DSG lines 413. The peripheral circuit 402 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 401 by applying voltage signals and / or current signals to each selected memory cell 406 via the bit lines 416, word lines 418, source lines 414, SSG lines 415, and DSG lines 413 and sensing voltage signals and / or current signals therefrom. The peripheral circuit 402 can include various types of peripheral circuits formed using complementary metal oxide semiconductor (CMOS) technology.

[0058] FIG. 5 shows a schematic circuit diagram of a DRAM device 500 including a peripheral circuit 502, according to some aspects of the present disclosure. The DRAM device 500 can be an example of the DRAM 304 of FIG. 3. The DRAM device 500 can include a memory cell array 501 and a peripheral circuit 502 operably coupled to the memory cell array 501. Memory cells 503 can be arranged within the memory cell array 501 having rows and columns. The DRAM device 500 requires periodic refreshing of the memory cells 503. In some implementations, each memory cell 503 includes a capacitor 507 for storing one bit of data as a positive or negative charge and a transistor 505 for controlling access to the capacitor 507. That is, each memory cell 503 shown in FIG. 5 is a one-transistor one-capacitor (1T1C) cell according to some implementations.

[0059] The DRAM device 500 can include a word line 504 that couples the peripheral circuit 502 and the memory cell array 501 to control the switch of the transistor 505 in the memory cell 503 installed in one row, and a bit line 506 that couples the peripheral circuit 502 and the memory cell array 501 to transmit data to and / or receive data from the memory cell 503 installed in one column. That is, each word line 504 is coupled to each row of the memory cell 503, and each bit line 506 is coupled to each column of the memory cell 503. The gate of the transistor 505 can be coupled to the word line 504, one of the source and drain of the transistor 505 can be coupled to the bit line 506, the other of the source and drain of the transistor 505 can be coupled to one electrode of the capacitor 507, and the other electrode of the capacitor 507 can be coupled to the ground.

[0060] The peripheral circuit 502 can be coupled to the memory cell array 501 via the bit line 506, the word line 504, and any other suitable metal wiring. The peripheral circuit 502 can include any suitable circuit for facilitating the operation of the memory cell array 501 by applying and sensing voltage signals and / or current signals to and / or from each memory cell 503 via the word line 504 and the bit line 506. The peripheral circuit 502 can include various types of peripheral circuits formed using CMOS technology.

[0061] FIG. 6 shows a detailed schematic diagram of a memory system 600 that performs data retrieval, according to some aspects of the present disclosure. The memory system 600 may be an example of the memory system 102 of FIG. 1. As shown in FIG. 6, the memory system 600 can include a memory controller 601, a volatile memory device 602, and a non-volatile memory device 604. The memory controller 601 may be an example of the memory controller 106 of FIG. 1. The volatile memory device 602 and the non-volatile memory device 604 may be examples of the memory device 104 of FIG. 1. In some implementations, the volatile memory device 602 includes DRAM (e.g., the DRAM device 500 of FIG. 5), and the non-volatile memory device 604 includes NAND flash memory (e.g., the NAND flash memory device 400 of FIG. 4). Data from a host (not shown, e.g., the host 108 of FIG. 1) can be stored in the volatile memory device 602 as "hot data" or in the non-volatile memory device 604 as "cold data". In some examples, "hot data" may be stored in the non-volatile memory device 604 while "cold data" is stored in the volatile memory device 602, or both "hot data" and "cold data" may be stored in the volatile memory device 602 or in the non-volatile memory device 604. As described above, "hot data" refers to data that is frequently used and / or recently accessed, and "hot data" is stored, for example, in the cache 606 within the volatile memory device 602. In contrast, "cold data" refers to data stored in the non-volatile memory device 604, such as data that is flushed from the cache 606 to the non-volatile memory device 604 under some conditions (e.g., the cache 606 is full, the data has not been accessed or used for a certain time period, etc.). In some implementations, the memory controller 601 is further configured to cache one host / user data within the volatile memory device 602 or to flush one host / user data from the volatile memory device 602 to the non-volatile memory device 604.

[0062] To enable the search and access of cold data, the non-volatile memory device 604 can be divided into a plurality of memory regions 605 each having a unique physical address. In some implementations, each memory region 605 includes one or more logical pages, for example, a part (e.g., 1 / 2, 1 / 4, or 1 / 8) of one physical page 420 of the NAND flash memory device 400. For example, the size of each memory region 605 can be 4,096 bytes. It is understood that the memory regions 605 can correspond to any suitable memory cell group within the non-volatile memory device 604 in addition to pages such as parts of pages, blocks (e.g., block 404 of the NAND flash memory device 400), etc. The physical address of the memory region 605 can be, for example, a physical page address (PPA) when the memory region 605 corresponds to one page of the non-volatile memory device 604.

[0063] In accordance with the scope of the present disclosure, to enable the search and access of hot data, the cache 606 of the volatile memory device 602 can be divided into a plurality of memory blocks 607 each having a unique identifier (ID, also known as a memory block ID). In some implementations, each memory block 607 includes one or more pages, for example, rows or columns of the memory cells 503 of the DRAM device 500. In some implementations, to enable uniform data search between the non-volatile memory device 604 and the volatile memory device 602, the size of each memory region 605 and the size of each memory block 607 can be the same. It is understood that in some examples, the size of each memory region 605 and the size of each memory block 607 can be different. For example, the size of each memory block 607 can also be 4,096 bytes. It is understood that the memory blocks 607 can correspond to any suitable memory cell group within the volatile memory device 602 in addition to pages such as parts of pages, codewords, etc.

[0064] Cache 606 can be part of a volatile memory device 602 that temporarily stores (caches) frequently used and / or recently accessed data (i.e., hot data) to speed up the read and write operations of the non-volatile memory device 604. Any suitable cache algorithm can be used to determine which data should be stored in cache 606 and when that data should be replaced, including, for example, least recently used (LRU), most recently used (MRU), and first in first out (FIFO). In some implementations, data from a host (host / user data) is first cached as hot data in cache 606 of the volatile memory device 602 and then flushed as cold data to the non-volatile memory device 604 under some conditions based on the cache algorithm. For example, when the size of the data in cache 606 reaches a preset threshold (maximum cache size), the data in cache 606 can be flushed to the non-volatile memory device 604. Cache 606 can be implemented by any suitable type of volatile memory device 602, such as, for example, DRAM 304 and / or SRAM 310 of FIG. 3.

[0065] In accordance with the scope of the present disclosure, a uniform and extended L2P mapping table 612 is maintained to enable uniform search and access to both hot data and cold data, mapping the logical address of data to the physical address 616 (e.g., PPA) of each memory region 605 within the non-volatile memory device 604 as well as to the ID 614 of each memory block 607 within the cache 606 of the volatile memory device 602, and is stored in the volatile memory device 602. The logical address can identify host / user data and inform the memory controller 601. In some implementations, the logical address indicates the basic logical unit of data for each read or write operation, such as a logical block address (LBA). In some implementations, to enable uniform data search between the non-volatile memory device 604 and the volatile memory device 602, the size of each memory region 605, the size of each memory block 607, and the size of the data corresponding to each logical address can be the same. For example, the size of the data corresponding to each logical address can also be 4,096 bytes. Since the memory controller 601 operates based on the logical address, in contrast to the physical address (e.g., physical address 616 or ID 614), the L2P mapping table 612 can be used to enable conversion between the logical address and the physical address uniformly across both the non-volatile memory device 604 and the volatile memory device 602, as will be described in detail below.

[0066] The L2P mapping table 612 can be stored in any suitable type of volatile memory device 602, such as the DRAM 304 of FIG. 3. In some implementations, the same volatile memory device 602, such as the DRAM 304 of FIG. 3, includes both the cache 606 and the L2P mapping table 612. It is understood that in some examples, the cache 606 and the L2P mapping table 612 may be included in different volatile memory devices 602. For example, the SRAM 310 may include the cache 606, while the DRAM 304 may include the L2P mapping table 612. Although the L2P mapping table 612 is shown in FIG. 6 as being outside the cache 606, it is understood that in some examples, the L2P mapping table 612 may also be stored within the cache 606.

[0067] The L2P mapping table 612 may be stored in the volatile memory device 602 together with the addresses in the volatile memory device 602. For example, as shown in FIG. 7, the L2P mapping table 612 may include addresses 704 (VM Add) in the volatile memory device 602 respectively associated with values 706. The value 706 may include two types of information, namely, the ID 614 (e.g., ID1, ID2, ID3, etc.) of the memory block 607 in the cache 606 and the physical address 616 (PPA) (e.g., PPA1, PPA2, PPA3, PPA4, etc.) of the memory area 605 in the non-volatile memory device 604. As shown in FIG. 7, the L2P mapping table 612 may also map the logical address 702 (LBA) of the host / user data to the ID 614 of the memory block 607 in the cache 606 and the physical address 616 of the memory area 605 in the non-volatile memory device 604 via the address 704. For example, for each piece of host / user data, the corresponding address 704 of the L2P mapping table 612 in the volatile memory device 602 may be determined based on the respective LBA 702 associated with the piece of host / user data. In an example shown in FIG. 7, each address 704 may be calculated by adding an address offset (OFF) to the respective LBA 702 (e.g., 0, 1, 2, 3, 4, 5, 6, etc.). The address offset may be determined based on, for example, the location where the L2P mapping table 612 is stored in the volatile memory device 602. Therefore, the corresponding value 706 at the determined address 704 of the L2P mapping table 612 is determined, and the value indicates either the ID 614 of the memory block 607 in the cache or the physical address 616 of the memory area in the non-volatile memory device 604 via the address 704. Thus, the LBA 702 of the host / user data may be mapped by the L2P mapping table 612 to the ID 614 of the memory block 607 in the cache 606 and the physical address 616 of the memory area 605 in the non-volatile memory device 604 respectively.

[0068] Referring back to FIG. 6, the memory controller 601 can include a plurality of I / O interfaces including a volatile memory interface 620 operably coupled to a volatile memory device 602, a non-volatile memory interface 622 operably coupled to a non-volatile memory device 604, and a host interface 618 operably coupled to the volatile memory device 602 and a cache 606 of a host (not shown). Examples of those I / O interfaces can include the DRAM interface 314, the NAND interface 312, and the host interface 316 of FIG. 3, which can implement any suitable communication protocol, such as the NVMe protocol, the PCI-E protocol, the DDR protocol, etc., to facilitate data transfer, communication, and management, to name a few.

[0069] The host interface 618 can be configured to receive write requests and read requests from the host. Each write request can indicate one piece of data associated with a logical address (e.g., LBA) to be written to the memory system 600. Similarly, each read request can indicate one piece of data associated with a logical address (e.g., LBA) to be read from the memory system 600. In some implementations, in response to receiving a write request or a read request, the host interface 618 can also be configured to fetch one piece of data from the host to temporarily store (cache) the one piece of data in the cache 606, or vice versa. For example, the host interface 618 can include a direct memory access (DMA) unit to access data from or to the cache 606.

[0070] The non-volatile memory interface 622 can be configured to enable the memory controller 601 to access data stored in the non-volatile memory device 604 based on the physical address (e.g., PPA) of the memory region 605. The volatile memory interface 620 can be configured to enable the memory controller 601 to access data stored in the volatile memory device 602, for example, to maintain the L2P mapping table 612 and to access data in the cache 606. In some implementations, the volatile memory interface 620 is configured to convert the ID 614 of the memory block 607 in the cache 606 into a physical address of the volatile memory device 602 that can be directly used by the memory controller 601 to operate the memory cells of the volatile memory device 602. In other words, the ID 614 of the memory block 607 in the cache 606 can be used to facilitate hot data search by the L2P mapping table 612, while the memory controller 601 can still access data in the volatile memory device 602 using the physical address of the volatile memory device 602. As a result, according to some implementations, the volatile memory device 602 does not need to be modified to adapt to the usage of the ID 614 of the memory block 607 for hot data search.

[0071] As shown in FIG. 6, the memory controller 601 can further include a range division accelerator 608 and one or more L2P search engines 610 operably coupled to the volatile memory device 602, the non-volatile memory interface 622, and the volatile memory interface 620. In some implementations, the range division accelerator 608 and the L2P search engine 610 are firmware modules implemented by firmware code / instructions stored in a memory (e.g., ROM 311 in FIG. 3) and executed by a processing unit (e.g., processing unit 308 in FIG. 8). In some implementations, the range division accelerator 608 and the L2P search engine 610 are hardware modules implemented by dedicated circuits such as ASICs to perform their dedicated functions described herein. The hardware implementations of the range division accelerator 608 and the L2P search engine 610 can improve search parallel processing and reduce the overhead of the firmware, thereby further improving the data search performance.

[0072] The range split accelerator 608 can be configured to generate data search requests based on read and write requests from a host via the host interface 618 and assign the search requests to the L2P search engine 610. That is, the range split accelerator 608 can split a read or write request into search requests to be handled in parallel by multiple L2P search engines 610, for example, based on different logical addresses associated with the data of the read or write request. For example, for each search request, the range split accelerator 608 can identify an idle L2P search engine 610 to handle the search request. In some implementations, in response to receiving a write request indicating one piece of data associated with a logical address (e.g., LBA), the range split accelerator 608 uses one of the unique IDs 614 to trigger the host interface 618 to fetch the corresponding one piece of data from the host into the corresponding memory block 607 in the cache 606, and is configured to assign the one piece of data to one of the memory blocks 607 in the cache 606.

[0073] The L2P search engine 610 may be configured to handle search requests and maintain an L2P mapping table 612 stored in the volatile memory device 602 via the volatile memory interface 620 based on the handling of the search requests. In some implementations, a single L2P mapping table 612 is maintained for the memory system 600, and multiple L2P search engines 610 are configured to maintain the same L2P mapping table 612 and use the same L2P mapping table 612 for searching hot and cold data. For example, multiple L2P search engines 610 may be configured to search multiple pieces of data in parallel respectively based on the same L2P mapping table 612. It is understood that in some examples, a single L2P search engine 610 may be used to handle search requests. In some implementations, in response to the host interface 618 fetching one piece of data from the host into the corresponding memory block 607 in the cache 606 in response to a write request, the L2P search engine 610 is configured to update the L2P mapping table 612 to map the logical address (e.g., LBA) associated with the one piece of data to the unique ID 614 of the corresponding memory block 607. For example, as shown in FIG. 7, assuming that the LBA 702 of one piece of data is "3", the value 706 may be updated by the search engine 610 to be "ID3", which is the unique ID 614 of the corresponding memory block 607. The value 706 may be stored at the address 704 "OFF+3" of the L2P mapping table 612 in the volatile memory device 602. In some implementations, in response to one piece of cached data in the cache 606 being flushed to one of the memory regions 605 in the non-volatile memory device 604 together with one of the unique physical addresses 616 (e.g., PPA), the L2P search engine 610 is further configured to update the L2P mapping table 612 to map the logical address (e.g., LBA) associated with the one piece of data to the unique physical address 616 of the corresponding memory region 605.For example, as shown in FIG. 7, assuming that the LBA 702 of one piece of data is "3", the value 706 can be updated by the L2P search engine 610 to be "PPA5", which is the unique physical address 616 of the corresponding memory area 605. This is because the one piece of data associated with LBA3 has been moved from ID3 in the cache 606 to PPA5 in the non-volatile memory device 604.

[0074] In some implementations, in response to receiving a search request for a read request indicating one piece of data having a logical address (e.g., LBA), the L2P search engine 610 is configured to search for the one piece of data based on the logical address and the L2P mapping table 612. The L2P mapping table 612 can be configured to determine the address of the L2P mapping table 612 in the volatile memory device 602 based on the logical address, and then determine the value at the address of the L2P mapping table 612. The value can be the ID 614 of the memory block 607 in the cache, or the physical address 616 of the memory area 605 in the non-volatile memory device 604. In one example, as shown in FIG. 7, assuming that the LBA 702 of one piece of data is "0", the search engine 610 first adds the LBA 702 "0" to the address offset "OFF" to obtain the address 704 "OFF", and then can identify that the value 706 at the address 704 "OFF" is "ID1", which means that the one piece of data to be read is hot data that was most recently cached in the memory block ID1 in the cache 606. In another example, as shown in FIG. 7, assuming that the LBA 702 of one piece of data is "2", the L2P search engine 610 first adds the LBA 702 "2" to the address offset "OFF" to obtain the address 704 "OFF + 2", and then can identify that the value 706 at the address 704 "OFF + 2" is "PPA1", which means that the one piece of data to be read is cold data that was most recently stored in the memory area PPA1 in the non-volatile memory device 604.

[0075] In some implementations, in response to identifying the ID 614 of the memory block 607 in the cache 606, the L2P search engine 610 provides the identified ID 614 to the volatile memory interface 620, and the volatile memory interface 620 converts the ID 614 to the corresponding physical address in the volatile memory device 602, whereby the host interface 618 can fetch one data from the corresponding physical address in the volatile memory device 602, for example, using DMA. In some implementations, in response to identifying the physical address 616 of the memory region 605 in the non-volatile memory device 604, the L2P search engine 610 provides the identified physical address 616 (e.g., PPA) to the non-volatile memory interface 622, whereby the non-volatile memory interface 622 can fetch one data from the corresponding physical address in the non-volatile memory device 604.

[0076] FIG. 8 shows a flowchart of a method 800 for operating a memory controller according to some aspects of the present disclosure. The memory controller can be any suitable memory controller disclosed herein, such as the memory controller 601. It is understood that the operations shown in the method 800 are not inclusive and that other operations can be similarly performed before, after, or between any of the operations described. Further, some of the operations can be performed simultaneously or in an order different from the order shown in FIG. 8.

[0077] The memory controller is operably coupled to a volatile memory device and a non-volatile memory device. The volatile memory device can include a cache. The cache is divided into memory blocks each having a respective unique one of the IDs. The non-volatile memory device is divided into memory regions each having a respective unique one of the physical addresses. For example, as shown in FIG. 6, the volatile memory device 602 can include a cache 606 that can be divided into memory blocks 607 each having a respective unique ID 614, and the non-volatile memory device 604 can be divided into memory regions 605 each having a respective unique physical address 616.

[0078] Referring to FIG. 8, method 800 begins at operation 802 where an L2P mapping table is generated and stored within the volatile memory device. For example, as shown in FIG. 6, the memory controller 601 can generate an L2P mapping table 612 during the start of the memory system 600 and store the L2P mapping table 612 within the volatile memory device 602 during the operation of the memory system 600. For example, as shown in FIG. 7, the L2P mapping table 612 can include values 706 at each of its addresses 704 that can each be mapped to an LBA 702.

[0079] Method 800 proceeds to operation 804 where a first set of data is cached within a memory block of the cache, as shown in FIG. 8. The first set of data is each associated with a first set of logical addresses. For example, as shown in FIG. 6, the memory controller 601 can cache a plurality of host / user data within the memory blocks 607 within the cache 606. Each individual host / user data can be associated with a respective one of the logical addresses (e.g., LBA). In one example, the host interface 618 of the memory controller 601 can fetch host / user data from the host to cache the host / user data within the memory block 607 using DMA.

[0080] As shown in FIG. 8, method 800 proceeds to operation 806 where an L2P mapping table is maintained such that the L2P mapping table maps a first set of logical addresses to the IDs of the memory blocks of the cache. For example, as shown in FIGS. 6 and 7, memory controller 601 may maintain an L2P mapping table 612 such that a set of LBAs 702 may be mapped to the ID 614 of memory block 607 via address 704, respectively.

[0081] As shown in FIG. 8, method 800 proceeds to operation 808 where a second set of data is stored within the memory area of the non-volatile memory device. The second set of data is associated with a second set of logical addresses, respectively. For example, as shown in FIG. 6, memory controller 601 may store a plurality of host / user data within memory area 605 of non-volatile memory device 604, respectively. Each piece of host / user data may be associated with one of the logical addresses (e.g., LBA). In one example, the plurality of host / user data may be flushed from cache 606 to non-volatile memory device 604.

[0082] As shown in FIG. 8, method 800 proceeds to operation 810 where an L2P mapping table is maintained such that the L2P mapping table maps a second set of logical addresses to the physical addresses of the memory area of the non-volatile memory device. For example, as shown in FIGS. 6 and 7, memory controller 601 may maintain an L2P mapping table 612 such that another set of LBAs 702 may be mapped to the physical address 616 (e.g., PPA) of memory area 605 via address 704, respectively.

[0083] As shown in FIG. 8, method 800 proceeds to operation 812 where one piece of data is retrieved based on the L2P mapping table. As shown in FIG. 6, a plurality of L2P search engines 610 of memory controller 601 may perform hot data search and cold data search for a plurality of pieces of data in parallel based on the logical addresses of the plurality of pieces of data and the L2P mapping table 612.

[0084] In some implementations, to retrieve one piece of data, the address of the L2P mapping table in the volatile memory device is determined based on the logical address associated with the one piece of data, and the value at the address of the L2P mapping table is determined. For example, as shown in FIGS. 6 and 7, each L2P search engine 610 calculates the address 704 of the L2P mapping table 612 based on the LBA 702 and the address offset, and can identify that the value 706 at address 704 is either an ID or a physical address (e.g., PPA). In some implementations, in response to the value being one of the IDs of the memory blocks in the volatile memory device to retrieve one piece of data, the one piece of data is fetched from the memory block in the volatile memory device having the ID. In some implementations, in response to the value being one of the physical addresses of the memory regions in the non-volatile memory device to retrieve one piece of data, the one piece of data is fetched from the memory region in the non-volatile memory device having the physical address. For example, as shown in FIGS. 6 and 7, when the L2P search engine 610 identifies that the value 706 at address 704 is the ID 614, the host interface 618 may fetch one piece of data from the memory block 607 in the cache 606 having the identified ID 614, for example, using DMA. In contrast, when the L2P search engine 610 identifies that the value 706 at address 704 is the physical address 616 (e.g., PPA), the non-volatile memory interface 622 may fetch one piece of data from the memory region 605 in the non-volatile memory device 604 having the identified physical address 616.

[0085] In some implementations, in response to receiving a write request indicating one data of a first set of data associated with a first logical address of a first set of logical addresses, the one data of the first set of data is assigned to a first memory block of memory blocks having a first ID among the IDs. For example, as shown in FIG. 9, at 902, the write request can be split by the range splitter 608 into a plurality of search requests respectively associated with one host / user data and its logical address. For example, at 904, a plurality of memory block IDs can be respectively assigned by the range splitter 608 to a plurality of host / user data, whereby each one host / user data can be associated with a respective memory block ID. In some implementations, the one data of the first set of data is fetched to cache the one data of the first set of data within the first memory block. For example, at 906, the range splitter 608 can trigger the host interface 618 to fetch each one host / user data to a respective memory block using DMA.

[0086] In some implementations, in response to fetching one piece of data from a first set of data into a first memory block, the L2P mapping table is updated to map a first logical address to a first ID. For example, at 908, the memory block ID into which one piece of host / user data is cached can be updated by the L2P search engine 610 within the L2P mapping table 612 to map to the logical address of the one piece of host / user data. In some implementations, in response to flushing one piece of data from a first memory block of a cache to a memory region of a non-volatile memory device having a physical address, the L2P mapping table is updated to map the first logical address to the physical address. For example, at 910, it can be checked whether NAND flash memory programming is to be performed. NAND flash memory programming can be performed by flushing cached host / user data from the cache to the NAND flash memory. When NAND flash memory programming is performed, each piece of host / user data can be stored within one of each of the memory regions respectively associated with the PPA. If the response to 910 is yes, at 912, the PPA in which one piece of host / user data is stored in the NAND flash memory can be updated by the L2P search engine 610 within the L2P mapping table 612 to map to the logical address of the one piece of host / user data and replace the memory block ID. At 914, it can be checked whether a newly arriving write request has been received to determine whether the process can continue again from 902 for the newly arriving write request. If the response to 910 is no, the process can bypass 912 without updating the L2P mapping table 612 and proceed directly to 914.

[0087] In some implementations, in response to receiving a read request indicating one piece of data of a first set of data associated with a second logical address of a first set of logical addresses, an address of an L2P mapping table in the volatile memory device is determined based on the second logical address, and a second ID of a second memory block is identified at the address of the L2P mapping table in the volatile memory device. For example, as shown in FIG. 10, at 1002, the read request can be split by the range split accelerator 608 into a plurality of search requests each associated with a logical address. At 1004, an idle L2P search engine 610 can be identified by the range split accelerator 608 to execute the search requests. At 1006, a DRAM address can be specified by the L2P search engine 610 by calculating the logical address, for example, by adding the logical address to an address offset to obtain the DRAM address. At 1008, a value at the DRAM address can be fetched by the L2P search engine 610.

[0088] In some implementations, in response to a value being one of the IDs of the memory blocks within the volatile memory device, one piece of data of the first set of data is fetched from a second memory block among the memory blocks in the cache based on the L2P mapping table. For example, at 1010, whether one piece of host / user data is in the NAND flash memory can be determined based on the value fetched at 1008, either the memory block ID or the PPA. If the response to 1010 is no, it means that one piece of host / user data is still in the cache, and at 1014, one piece of host / user data can be fetched from the cache by the volatile memory interface 620 based on the memory block ID fetched at the DRAM address. If the response to 1010 is yes, it means that one piece of host / user data is in the NAND flash memory, and at 1012, one piece of host / user data can be read from the NAND flash memory by the non-volatile memory interface 622 based on the PPA fetched at the DRAM address. In either case, at 1016, one piece of host / user data can be sent to the host by the host interface 618.

[0089] In various aspects of the present disclosure, the functions described herein can be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, the functions can be stored as instructions on a non-transitory computer-readable medium. The computer-readable medium includes computer storage media. The storage media can be any available media that can be accessed by a memory controller, such as the memory controller 601 of FIG. 6. By way of example and not limitation, such computer-readable media can include RAM, ROM, electrically erasable programmable ROM (EEPROM), compact disc read only memory (CD-ROM) or other optical disk storage, hard disk drive (HDD) such as magnetic disk storage or other magnetic storage devices, flash drive, SSD, or any other media that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a processing system such as a mobile device or a computer. As used herein, disk and disc include CD, laser disc, optical disc, digital video disc (DVD), and floppy disk, and disk typically magnetically reproduces data, while disc optically reproduces data using a laser. Combinations of the above should also be included within the scope of computer-readable media.

[0090] The foregoing description of specific implementations can be readily modified and / or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and scope of equivalents of the implementations disclosed based on the teachings and guidance presented herein.

[0091] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined only in accordance with the following claims and their equivalents.

[0092] Although specific configurations and arrangements are described, it should be understood that this is only for the purpose of aiding understanding. Therefore, other configurations and arrangements may be used without departing from the scope of the present disclosure. Similarly, the subject matter described in the present disclosure may also be used in various other applications. The functional and structural features described in the present disclosure may be combined, adjusted, modified, and rearranged with each other in a manner consistent with the scope of the present disclosure.

Description of Reference Numerals

[0093] 100 System 102 Memory System 104 Memory Device 106 Memory Controller 108 Host 202 Memory Card 204 Memory Card Connector 206 Solid State Drive (SSD) 208 SSD Connector 300 Memory Controller 302 NAND Flash Memory 304 DRAM 306 Host 308 Processing Unit 310 SRAM 311 ROM 312 NAND Interface 314 DRAM Interface 316 Host Interface 400 NAND Flash Memory Device 401 Memory Cell Array 402 Peripheral Circuit 404 Block 406 Memory Cell 408 Memory String 410 Source Select Gate (SSG) Transistor 412 Drain Select Gate (DSG) Transistor 413 DSG Line 414 Source Line (SL) 415 SSG Line 416 Bit Line 418 Word Line 500 DRAM Device 501 Memory Cell Array 502 Peripheral Circuit 503 Memory Cell 504 Word Line 505 Transistor 506 Bit Line 507 Capacitor 600 Memory System 601 Memory Controller 602 Volatile Memory Device 604 Non-Volatile Memory Device 605 Memory Region 606 Cache 607 Memory Block 608 Range Partition Accelerator 610 Logical to Physical (L2P) Search Engine 612 L2P Mapping Table 614 Identifier (ID) 616 Physical Address 618 Host Interface 620 Volatile Memory Interface 622 Non-Volatile Memory Interface 702 Logical Block Address (LBA) 704 Address 706 Value

Claims

1. A volatile memory device configured to store a logical-to-physical (L2P) mapping table, and a memory controller operably coupled to the volatile memory device and configured to maintain the L2P mapping table stored within the volatile memory device, whereby the L2P mapping table is configured to map a first set of logical addresses to identifiers (IDs) of memory blocks of a cache, respectively A memory system comprising.

2. The memory system according to claim 1, wherein the memory controller is further configured to cache a first set of data within the memory block, and the first set of data is associated with the first set of logical addresses, respectively.

3. The memory system according to claim 2, wherein the memory controller is further configured to retrieve the first set of cached data within the memory block based on the L2P mapping table.

4. The memory system according to any one of claims 1 to 3, wherein the volatile memory device includes the cache.

5. Further comprising a non-volatile memory device operably coupled to the memory controller, and the memory controller is configured to store a second set of data within a memory area of the non-volatile memory device, wherein the second set of data is associated with a second set of logical addresses, respectively, and maintain the L2P mapping table stored within the volatile memory device, whereby the L2P mapping table further maps the second set of logical addresses to physical addresses of the memory area of the non-volatile memory device, respectively The memory system according to any one of claims 1 to 4, further configured to perform.

6. The memory system according to claim 5, wherein the volatile memory device includes a dynamic random access memory (DRAM), and the non-volatile memory device includes a NAND flash memory.

7. The memory controller is configured to In response to receiving a write request indicating one piece of data of the first set of data associated with the first logical address of the first set of logical addresses, allocating the one piece of data of the first set of data to a first memory block among the memory blocks, where the first memory block has a first ID among the IDs. Fetching the one piece of data of the first set of data to cache the one piece of data of the first set of data within the first memory block. The memory system according to any one of claims 1 to 6, further configured to perform the above.

8. To maintain the L2P mapping table, the memory controller includes an L2P search engine configured to update the L2P mapping table to map the first logical address to the first ID in response to fetching the one piece of data of the first set of data to the first memory block. The memory system according to claim 7.

9. In response to the memory controller receiving a read request indicating one piece of data of the first set of data associated with a second logical address of the first set of logical addresses, the memory system according to any one of claims 1 to 6 is further configured to fetch the one piece of data of the first set of data from a second memory block among the memory blocks in the cache based on the L2P mapping table.

10. The memory controller Determining the address of the L2P mapping table in the volatile memory device based on the second logical address. Identifying a second ID among the IDs at the address of the L2P mapping table in the volatile memory device, where the second memory block has the second ID. The memory system according to claim 9, including an L2P search engine configured to perform the above.

11. A non-volatile memory device including memory regions respectively associated with physical addresses. A volatile memory device including memory blocks each associated with an identifier (ID) and configured to store a logical-to-physical (L2P) mapping table, wherein the L2P mapping table maps a logical address of data to the ID of the memory block in the volatile memory device and the physical address of the memory region in the non-volatile memory device, respectively. A memory controller operably coupled to the volatile memory device and the non-volatile memory device and configured to retrieve one of the data based on the L2P mapping table. A memory system including the above.

12. To retrieve the one data, the memory controller Determines the address of the L2P mapping table in the volatile memory device based on the logical address associated with the one data. Determines the value at the address of the L2P mapping table. The memory system according to claim 11, configured to perform the above.

13. To retrieve the one data, the memory controller In response to the value being one of the IDs of the memory blocks in the volatile memory device, fetches the one data from the memory block in the volatile memory device having the ID, or In response to the value being one of the physical addresses of the memory regions in the non-volatile memory device, fetches the one data from the memory region in the non-volatile memory device having the physical address. The memory system according to claim 12, further configured to perform the above.

14. To retrieve the one data, the memory controller includes a plurality of L2P search engines configured to retrieve a plurality of the data in parallel based on the L2P mapping table. The memory system according to any one of claims 11 to 13.

15. The memory system according to any one of claims 11 to 14, wherein the memory controller is further configured to cache the one piece of data in the volatile memory device or flash the one piece of data from the volatile memory device to the non-volatile memory device.

16. A volatile memory device interface operably coupled to a volatile memory device, and an L2P search engine that maintains a logical-to-physical (L2P) mapping table stored in the volatile memory device via the volatile memory device interface, such that the L2P mapping table is configured to map each first set of logical addresses to an identifier (ID) of a memory block in the cache The memory controller includes.

17. The memory controller according to claim 16, wherein the L2P search engine is further configured to search for a first set of data, which is associated with the first set of logical addresses and cached in the memory block based on the L2P mapping table.

18. Further including a non-volatile memory device interface operably coupled to a non-volatile memory device, wherein the L2P search engine maintains the L2P mapping table stored in the volatile memory device, such that the L2P mapping table is further configured to map each second set of logical addresses to a physical address of a memory region of the non-volatile memory device, respectively. The memory controller according to claim 16 or 17.

19. The memory controller according to claim 18, wherein the L2P search engine is further configured to search for a second set of data, which is associated with the second set of logical addresses and stored in the memory region based on the L2P mapping table.

20. The memory controller according to claim 18 or 19, wherein the volatile memory device includes a dynamic random access memory (DRAM), and the non-volatile memory device includes a NAND flash memory.

21. In response to receiving a write request indicating one piece of data of the first set of data associated with the first logical address of the first set of logical addresses, a range division accelerator configured to allocate the one piece of data of the first set of data to a first memory block among the memory blocks, wherein the first memory block has a first ID among the IDs, the range division accelerator; A host interface configured to fetch the one piece of data of the first set of data to cache the one piece of data of the first set of data within the first memory block The memory controller according to any one of claims 16 to 20, further comprising. **Claim 22** The L2P search engine is further configured to update the L2P mapping table to map the first logical address to the first ID in response to the host interface fetching the one piece of data of the first set of data to the first memory block to maintain the L2P mapping table. The memory controller according to claim 21. **Claim 23** The memory controller according to any one of claims 16 to 20, further comprising a host interface further configured to fetch the one piece of data of the first set of data from a second memory block among the memory blocks in the cache based on the L2P mapping table in response to receiving a read request indicating one piece of data of the first set of data associated with a second logical address of the first set of logical addresses. **Claim 24** The L2P search engine is Determining an address of the L2P mapping table in the volatile memory device based on the second logical address; Identifying a second ID among the IDs at the address of the L2P mapping table in the volatile memory device, wherein the second memory block has the second ID; The memory controller according to claim 23, configured to perform. **Claim 25** A method for operating a memory controller, Generating a logical-to-physical (L2P) mapping table stored in a volatile memory device; Maintaining the L2P mapping table, whereby the L2P mapping table maps a first set of logical addresses to identifiers (IDs) of memory blocks of a cache respectively; A method comprising the above. **Claim 26** The method according to claim 25, further comprising caching a first set of data in the memory block, wherein the first set of data is respectively associated with the first set of logical addresses. **Claim 27** The method according to claim 26, further comprising searching for the first set of data in the memory block based on the L2P mapping table. **Claim 28** The method according to any one of claims 25 to 27, wherein the volatile memory device includes the cache. **Claim 29** Storing a second set of data in a memory area of a non-volatile memory device, wherein the second set of data is respectively associated with a second set of logical addresses; Maintaining the L2P mapping table stored in the volatile memory device, whereby the L2P mapping table further maps the second set of logical addresses to physical addresses of the memory area of the non-volatile memory device respectively; The method according to any one of claims 25 to 28, further comprising the above. **Claim 30** The method according to claim 29, wherein the volatile memory device includes a dynamic random access memory (DRAM), and the non-volatile memory device includes a NAND flash memory. **Claim 31** In response to receiving a write request indicating one piece of data from the first set of data associated with a first logical address of the first set of logical addresses, allocating the one piece of data from the first set of data to a first memory block among the memory blocks, wherein the first memory block has a first ID among the IDs; Fetching the one piece of data from the first set of data to cache the one piece of data in the first memory block; The method according to any one of claims 25 to 30, further comprising

32. The step of maintaining the L2P mapping table includes updating the L2P mapping table to map the first logical address to the first ID in response to fetching the one data of the first set of data to the first memory block. The method according to claim 31.

33. In response to receiving a read request indicating the one data of the first set of data associated with the second logical address of the first set of logical addresses, fetching the one data of the first set of data from the second memory block among the memory blocks in the cache based on the L2P mapping table. The method according to any one of claims 25 to 30, further comprising

34. Determining an address of the L2P mapping table in the volatile memory device based on the second logical address; and Identifying a second ID among the IDs at the address of the L2P mapping table in the volatile memory device, wherein the second memory block has the second ID. The method according to claim 33, further comprising

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