Flip-chip Doherty amplifier device

Abstract

The power amplifier includes a substrate, a first transistor amplifier and a second transistor amplifier, and at least one matching circuit. Output terminals of the first transistor amplifier and the second transistor amplifier are each connected to a combined node, and the matching circuit includes one or more passive electrical components connected between one of the output terminals and the combined node. At least one of the first transistor amplifier and the second transistor amplifier or one or more passive electrical components are mounted on the substrate in a flip-chip configuration. The matching circuit may include a shunt inductance connected by a conductive bump to one of the respective drain terminals. Related devices are also discussed.

Description

Technical Field

[0001] This application claims priority from European Patent Application No. 22305921.3, filed on Jun. 24, 2022, with the French Patent Office, the disclosure of which is incorporated herein by reference in its entirety.

[0002] This disclosure relates to transistor devices, and more particularly to high-power transistor devices.

Background Art

[0003] In recent years, electric circuits that operate at high frequencies such as radio frequencies (500 MHz), S-band (3 GHz), and X-band (10 GHz) while requiring high output processing capabilities have become increasingly widespread. With the increase in high-output, high-frequency circuits, the demand for semiconductor devices that can process high-output loads while reliably operating at radio frequencies and microwave frequencies has increased accordingly.

[0004] A radio frequency (RF) power amplifier in a communication system can be used to generate the high power required for wireless communication. A power amplifier (PA) can include one or more active transistors and passive matching networks at input and output nodes. Various RF power applications can have various requirements for the power amplifier, for example, with respect to output power and efficiency. Generally, a power amplifier operates with maximum power efficiency when the power amplifier transmits power close to the saturation power. However, the power efficiency tends to deteriorate as the output power decreases. For example, an RF PA used in a base station may need to be efficient not only at peak power but also at average power, which may be several decibels (dB) lower than the peak power. However, since the peak efficiency can be reached at approximately the peak power, it will be difficult to achieve this goal. At the back-off power or average power, the efficiency tends to drop extremely.

[0005] To address the efficiency at back-off power, several PA architecture solutions, including Doherty implementations, have been proposed. The Doherty type linear amplifier configuration can provide increased linearity and efficiency in a linear amplifier topology. Generally, a Doherty amplifier includes two amplifiers having output power synthesized by a load modulation network. Thus, a Doherty amplifier includes at least two amplifier paths, namely, a carrier amplifier path and a peaking amplifier path, and the outputs of these two paths are synthesized at an additive junction (or node) to provide increased linearity and efficiency. Various Doherty amplifier implementation forms are described in U.S. Patent No. 6,700,444 to Pengelly, U.S. Patent No. 6,737,922 to Pengelly et al., U.S. Patent No. 6,791,417 by Pengelly et al., U.S. Patent No. 7,193,473 to Pengelly et al., U.S. Patent No. 9,407,214 to Pribble et al., and "A Wideband and Compact GaN MMIC Doherty Amplifier for Microwave Link Applications" by Gustafsson et al., IEEE Transaction on Microwave Theory and Techniques, Vol. 61, No. 2 (February 2013).

[0006] In a conventional Doherty amplifier configuration, the carrier amplifier receives an undelayed input signal for amplification, and the peaking amplifier receives a phase-delayed input signal for amplification. An integrated Doherty configuration can achieve this phase delay using a lumped element impedance inverter. More recently, electronic systems have been designed using a so-called "inverted" Doherty amplifier configuration. In the inverted Doherty configuration, the carrier amplifier receives a delayed input signal for amplification, and the peaking amplifier receives an undelayed input signal for amplification.

[0007] The high efficiency of the Doherty architecture would be desirable for current and next-generation wireless systems. However, this architecture presents challenges with respect to semiconductor package design. Depending on the Doherty amplifier semiconductor package design, individual devices, conductors, and integrated circuits may be used to implement each amplification path. For example, the carrier amplification path and the peaking amplification path may each include different power transistor dies, along with different inductance components and capacitance components. These different power transistor dies and components are kept at a distance from each other in a typical device package to suppress the potential for performance degradation that can occur due to signal coupling between the carrier amplifier and the peaking amplifier. More specifically, unwanted signal coupling between the carrier amplifier and the peaking amplifier may involve energy transfer between the components of the carrier amplifier path and the components of the peaking amplifier path due to magnetic and / or electric fields associated with the signals carried in the carrier amplifier path and the peaking amplifier path.

Prior Art Documents

Patent Documents

[0008]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Non-Patent Documents

[0009]

Non-Patent Document 1

[0010] According to some embodiments of the present disclosure, a power amplifier includes a substrate, a first transistor amplifier and a second transistor amplifier each having an output terminal connected to a combining node, and a matching circuit including one or more passive electrical components connected between one of the output terminals and the combining node. At least one of the first transistor amplifier and the second transistor amplifier or one or more passive electrical components are mounted on the substrate in a flip-chip configuration.

[0011] In some embodiments, one of the output terminals is a drain terminal, and the one or more passive electrical components include a shunt inductance connected to the drain terminal by a conductive bump.

[0012] In some embodiments, the one or more passive electrical components include at least one integrated passive device (IPD) that is mounted on the substrate in a flip-chip configuration and provides a shunt inductance.

[0013] In some embodiments, the substrate includes a multilayer laminate, and the one or more passive electrical components are in the multilayer laminate and include at least one inductor that provides a shunt inductance.

[0014] In some embodiments, there is no wire bond in the shunt inductance.

[0015] In some embodiments, the drain terminal is connected to the shunt inductance without wire bond pads therebetween.

[0016] In some embodiments, there is no wire bond in the electrical path between one of each output terminal and the combining node.

[0017] In some embodiments, one of each output terminal is the drain terminal of the first transistor amplifier, the matching circuit is the first output matching circuit, and the shunt inductance is the first shunt inductance. A second output matching circuit is connected between the drain terminal of the second transistor amplifier and the combining node and includes a second shunt inductance connected to the drain terminal of the second transistor amplifier by a conductive bump.

[0018] In some embodiments, the first transistor amplifier die and the second transistor amplifier die each include a main amplifier and a peaking amplifier in a Doherty configuration.

[0019] In some embodiments, a load impedance matching circuit may be connected between the combining node and the output lead. The impedance of the load impedance matching circuit is based on the asymmetry factor between the peaking amplifier and the main amplifier and is about 1.5 to 4 times the impedance at the output terminal of the main amplifier.

[0020] In some embodiments, the matching circuit is configured to delay the phase of the output signal from one of each output terminal by a quarter wavelength.

[0021] In some embodiments, the package housing may internally include a substrate, the first transistor amplifier and the second transistor amplifier, and the matching circuit.

[0022] According to some embodiments, a transistor amplifier package includes a main transistor amplifier and a peaking transistor amplifier. Output terminals of the main transistor amplifier and the peaking transistor amplifier are each connected to a combined node. There is no wire bond in the electrical path between one of each output terminal and the combined node.

[0023] In some embodiments, a matching circuit including one or more passive electrical components may be connected between one of each output terminal and the combined node.

[0024] In some embodiments, one of each output terminal is a drain terminal, and the one or more passive electrical components include a shunt inductance connected to the drain terminal by a conductive bump.

[0025] In some embodiments, the package may include a substrate, and at least one of the main transistor amplifier and the peaking transistor amplifier or the one or more passive electrical components may be mounted on the substrate in a flip-chip configuration.

[0026] In some embodiments, the one or more passive electrical components include at least one integrated passive device (IPD) that is mounted on the substrate in a flip-chip configuration and provides a shunt inductance.

[0027] In some embodiments, the substrate includes a multilayer laminate, and the one or more passive electrical components are in the multilayer laminate and include at least one inductor that provides a shunt inductance.

[0028] In some embodiments, one of each output terminal is the drain terminal of the main transistor amplifier, the matching circuit is a first output matching circuit configured to delay the phase of the output signal from the main transistor amplifier by a quarter wavelength, and the shunt inductance is the first shunt inductance. A second output matching circuit is connected between the drain terminal of the peaking transistor amplifier and the combining node, and is configured to delay the phase of the output signal from the peaking transistor amplifier by a quarter wavelength, and includes a second shunt inductance connected to the drain terminal of the peaking transistor amplifier by a conductive bump.

[0029] In some embodiments, a load impedance matching circuit may be connected between the combining node and the output lead of the transistor amplifier package. The impedance of the load impedance matching circuit is about 1.5 to 4 times the impedance at the output terminal of the main transistor amplifier.

[0030] According to some embodiments, a power amplifier includes a first transistor amplifier and a second transistor amplifier each having a drain terminal connected to a combining node, and a matching circuit connected between one of each drain terminal and the combining node, the matching circuit including a shunt inductance connected to one of each drain terminal by a conductive bump.

[0031] In some embodiments, one of each drain terminal is connected to the shunt inductance without a wire bond pad therebetween.

[0032] In some embodiments, there is no wire bond in the electrical path between one of each drain terminal and the combining node.

[0033] In some embodiments, at least one of the first transistor amplifier and the second transistor amplifier or one or more passive electrical components are mounted on the substrate in a flip chip configuration.

[0034] In some embodiments, one or more passive electrical components include at least one integrated passive device (IPD) that is mounted on a substrate in a flip-chip configuration and provides a shunt inductance.

[0035] In some embodiments, the substrate includes a multilayer laminate, and one or more passive electrical components are within the multilayer laminate and include at least one inductor that provides a shunt inductance.

[0036] In some embodiments, the first transistor amplifier die and the second transistor amplifier die each include a Doherty configuration for a main amplifier and a peaking amplifier.

[0037] In some embodiments, the impedance at the synthetic node is about 1.5 to 4 times the impedance at the drain terminal of the main amplifier.

[0038] In some embodiments, a package housing internally includes the first transistor amplifier and the second transistor amplifier and a matching circuit.

[0039] Other devices, apparatuses, and / or methods according to some embodiments will be apparent to those of ordinary skill in the art upon review of the following drawings and detailed description. In addition to any and all combinations of the above embodiments, all such additional embodiments are included within this specification, are within the scope of the present invention, and are intended to be protected by the appended claims.

[0040] The accompanying drawings, which are incorporated in and constitute a part of this application, are included to provide a further understanding of the invention and illustrate specific embodiments of the disclosure.

Brief Description of the Drawings

[0041]

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DETAILED DESCRIPTION OF THE INVENTION

[0042] Some of the power amplifier configurations described herein may be implemented using a plurality of “unit cell” transistors fabricated on a common semiconductor die, with the plurality of unit cells defining each transistor amplifier device. Each unit cell transistor may include a source region, a drain region, and a channel region in a semiconductor material, with the channel region being between the source region and the drain region. As schematically shown in FIG. 1, a gate electrode or gate terminal (or “gate”), which may be implemented as an elongated gate fin, is formed over the channel region and extends parallel between a source contact and a drain contact. Although described herein primarily with reference to high electron mobility transistors (“HEMTs”), embodiments of the present disclosure are not limited to any particular type of transistor and may include, for example, embodiments of metal-oxide-semiconductor field effect transistors (MOSFETs), such as embodiments of laterally diffused MOSFETs (LDMOS).

[0043] As shown in FIG. 1, the unit cell transistors of the power amplifier semiconductor device 100 are shown in box 40 and include conductive gate fingers 16 extending between adjacent source fingers 26 and drain fingers 36 in a semiconductor structure 10 such as a gallium nitride (GaN) and / or silicon carbide (SiC) semiconductor structure. The gate fingers 16 of each unit cell 40 are spaced apart from each other along a first direction (e.g., the x direction in FIG. 1) and extend in a second direction (e.g., the y direction in FIG. 1) (e.g., parallel).

[0044] The gate fingers 16 are electrically connected to each other via a gate bus 14, and the gate bus 14 may be coupled to or include a gate pad (also referred to herein as a gate terminal) for external connection. The conductive source fingers 26 are spaced apart from each other along the first direction and extend in the second direction. The source fingers 26 may be electrically connected to each other by through vias 28 or other structures (not visible in FIG. 1) and may be coupled to or include a source pad (also referred to herein as a source terminal) for external connection. In some embodiments, the source fingers 26 may be electrically connected to a source contact or pad (not visible in FIG. 1) on the bottom surface of the semiconductor structure 10. Similarly, the conductive drain fingers 36 are spaced apart from each other along the first direction, extend in the second direction, are electrically connected to each other via a drain bus 34, and the drain bus 34 may be coupled to or include a drain pad (also referred to herein as a drain terminal) for external connection.

[0045] The gate fingers 16, source fingers 26, and drain fingers 36 may each include a respective conductive material such as a metal or metal alloy. Each gate finger 16 extends along the y-direction between a pair of adjacent source fingers 26 and drain fingers 36. The "gate length" refers to the distance of the gate metallization in the x-direction (between the source finger 26 and the drain finger 36), while the "gate width" is the distance by which the gate finger 16 overlaps with the source contact 26 and the drain contact 36 in the y-direction. That is, the "width" of the gate finger 16 refers to the dimension of the gate finger 16 (distance along the y-direction) that extends parallel to the adjacent source contact 26 / drain contact 36. The power handling capacity of the semiconductor device 10 may be proportional to its "gate periphery". The gate periphery of the semiconductor device 10 may refer to the sum of the gate lengths for each gate finger 16 of each unit cell transistor 40 thereof.

[0046] Some embodiments of the present disclosure are directed to a power amplifier configuration that includes two or more transistor amplifier devices that are fabricated in a common package and electrically connected in parallel. Some multistage power amplifier configurations may include a high-power transistor structure that can maintain efficiency when operating at back-off power or average power, such as a Doherty configuration. A typical two-way Doherty amplifier configuration includes an RF signal splitter configured to split an input RF signal into two signals (referred to herein as a carrier signal and a peaking signal). The Doherty amplifier also includes a parallel carrier amplifier path and a peaking amplifier path configured to amplify the carrier signal and the peaking signal, respectively, and a signal combiner configured to combine the amplified carrier signal and the peaking signal. The carrier amplifier may also be referred to herein as the main amplifier. In addition, various phase shift elements or phase delay elements are provided along the main amplifier path and / or the peaking amplifier path. The terms phase shift and phase delay may be used interchangeably herein.

[0047] The Doherty configuration may include two RF bandwidths (peak power / total power and average power) as well as the instantaneous bandwidth. The peak power bandwidth or total power bandwidth may represent the signal bandwidth when both current sources (the main amplifier and the peaking amplifier) are on. The average power or back-off power bandwidth may represent the signal bandwidth when only one current source (the main amplifier) is on and the other (the peaking amplifier) is off. The instantaneous bandwidth (IBW) may represent the maximum modulation signal bandwidth that can be amplified without asymmetric distortion and may also be referred to as the video bandwidth (VBW).

[0048] The main amplifier and the peaking amplifier may each be implemented using single-stage or multi-stage power transistor devices. Using terminology typically applied to field effect transistors (FETs), the main amplifier and the peaking amplifier may each include an input terminal or control terminal (e.g., a gate) configured to receive an input RF signal and two output terminals or energization terminals (e.g., a drain terminal and a source terminal). In some configurations, each source terminal is connected to a ground reference node, and the amplified carrier signal and peaking signal are output to the drain terminal of the main amplifier and the drain terminal of the peaking amplifier, respectively, and may be combined at a combining node to provide an RF output signal.

[0049] For example, in a typical non-inverting Doherty amplifier architecture, a 1 / 4 wavelength (λ / 4) transmission line applies a 90° phase shift to the peaking signal before amplification along the peaking amplifier path, and a corresponding transmission line applies a 90° phase shift to the carrier signal after amplification along the main amplifier path but before the amplified carrier signal and peaking signal are combined in phase. The drain of the peaking amplifier may serve as a combining node for the amplified RF signals generated by the carrier amplifier and the peaking amplifier in a non-inverting Doherty configuration.

[0050] In contrast, in a typical inverted Doherty amplifier architecture, a 90° phase shift is applied to the carrier signal before amplification along the main amplifier path, and after amplification along the peaking amplifier path and before the amplified carrier signal and the peaking signal are combined in phase. The drain of the main amplifier can serve as a combining node for the amplified RF signals generated by the carrier amplifier and the peaking amplifier in an inverted Doherty configuration.

[0051] FIG. 2A is a circuit diagram of PA200 according to some embodiments of the present disclosure. In the example of FIG. 2A, the PA is implemented in a Doherty configuration, but it will be understood that embodiments of the present invention can include any amplifier configuration having two or more parallel amplification stages.

[0052] As shown in FIG. 2A, PA200 includes at least two transistor amplifiers, shown as a carrier (or “main”) transistor amplifier 220 and at least one peaking transistor amplifier 230 that are electrically connected in parallel. A power splitter circuit or power divider circuit 214 receives an input power signal (e.g., an RF input signal or other AC input signal) at input lead 205 and is configured to provide respective component input signals to the input of main amplifier 220 and the input of peaking amplifier 230 via respective input impedance matching circuits 215 and 216. In some embodiments, power splitter 214 may be implemented as part of an input transmission line connecting the input of main amplifier 220 and the input of peaking amplifier 230 or may include the input transmission line. The electrical components (e.g., power splitter 214 and input matching circuits 215 and 216) between input lead 205 and the inputs of transistor amplifiers 220 and 230 may be referred to as the input section 210 of PA200.

[0053] The main amplifier 220 and the peaking amplifier 230 are configured to receive and amplify respective component input signals of the component input signal to generate amplified component output signals, and are configured to turn on at various power levels of the input signal. For example, the main amplifier 220 may be biased to operate in class B mode or class AB mode, while the peaking amplifier 230 may be biased to amplify only signals exceeding some minimum threshold by DC biasing the transistors of the peaking amplifier 230 below the pinch-off voltage, for example, for an operation similar to class C.

[0054] The synthesizer and impedance inverter circuit 234 is configured to connect the output of the main amplifier 220 to the output of the peaking amplifier 230 via respective output impedance matching circuits 225 and 226, receive the amplified component output signals, and synthesize them at the output synthesis node 250. In some embodiments, the impedance inverter circuit 234 and the synthesis node 250 may be implemented as part of an output transmission line connecting the output of the main amplifier 220 and the output of the peaking amplifier 230 to the output lead 295 or may include the output transmission line. Electrical components (e.g., output matching circuits 225 and 226, impedance inverter circuit 234) between the outputs of the transistor amplifiers 220 and 230 and the output lead 295 may be referred to as the output section 290 of the PA200.

[0055] Therefore, the outputs of the main amplifier 220 and the peak amplifier 230 are not isolated from each other. Therefore, when the peaking amplifier 230 is turned on, the apparent load presented to the main amplifier 220 changes. If the input RF power to the Doherty amplifier 200 is not sufficient to turn on the peak amplifier 230, substantially all of the output power is supplied by the main amplifier 220. When the peak amplifier 230 is off, its output impedance is very high and essentially all of the output power of the main amplifier 220 is delivered to the load. The peaking amplifier 230 can be active only during the peaks of the input signal. When the peak amplifier 230 is active, the apparent load impedance at the output of the main amplifier 220 decreases. The peak amplifier 230 can be designed to start operating when the main amplifier 220 begins to saturate, thereby increasing the linear efficiency. The power splitter 214, transistor amplifiers 220 and 230, and the combiner and impedance inverter circuit 234 can be included in an integrated circuit package such as the transistor amplifier package 300 discussed below.

[0056] The impedance inverter circuit 234 can include one or more phase delay elements and can be represented as a transmission line having an electrical length (also called phase length) configured to provide a predetermined phase shift and impedance inversion between the output of the main amplifier 220 and the output of the peak amplifier 230. The drain of the main amplifier 220 is electrically connected to the first end of the transmission line 234 by the output matching circuit 225, and the drain of the peak amplifier 230 is electrically connected to the second end of the transmission line 234 by the output matching circuit 226. The electrical length of the impedance inverter circuit 234 can be configured such that both amplifiers 220 and 230 receive their optimum load resistances and provide maximum power and efficiency.

[0057] The PA200 shown in FIG. 2A is shown as an example in an inverse Doherty configuration that can be configured to balance the total power RF bandwidth and the average power RF bandwidth. The power splitter 214 may have an electrical length configured to provide a predetermined phase shift to the signal input to the main amplifier 220 to compensate for a similar phase shift introduced by the electrical length of the impedance inverter 234 in the output of the peaking amplifier 230. For example, in response to an RF input signal at the input lead 205, the power splitter 214 may generate two signals that are 90 degrees out of phase with each other as inputs to the main amplifier 220 and the peaking amplifier 230, respectively. After a 90-degree phase shift is introduced by the impedance inverter 234, a 90-degree phase split (corresponding to a quarter wavelength with respect to the operating frequency of the PA200) may be used such that the output of the peaking amplifier 230 is in phase with the output of the main amplifier 220. The output of the peaking amplifier 230, after passing through the impedance inverter 234, is combined with the output of the peaking amplifier 230 at the combining node 250. In some embodiments, a load impedance matching circuit 254 may be connected to the output combining node 250 and may be configured to supply an RF output signal at the output lead 295 to a load.

[0058] FIG. 2B is a circuit diagram showing the output section 290 of the PA200 in more detail. The electrical length provided by the phase delay element of the impedance inverter circuit 234 connected to the drain terminal 220d of the main transistor amplifier 220 and the drain terminal 230d of the peaking transistor amplifier 230 may be determined by the output (e.g., drain) capacitances of the transistor amplifiers 220 and 230 and the inductance interconnecting the drain terminals 220d and 230d to the transmission line 234. For example, a 90° inverter 234 may require a specific characteristic impedance, and the characteristic impedance may be the drain-source capacitance C of each transistor amplifier 220 and 230 dscan be at least partially defined by, and the inductance can be adjusted to implement a 90° inverter 234. This inductance adjustment can be implemented using wire bonds having corresponding physical lengths, but at higher frequencies, the electrical length can be converted to a very short physical length. Thus, as the fundamental operating frequency increases, the physical length of the transmission line 234 can become shorter and shorter, and the physical distance between the drain terminals 220d and 230d can become closer and closer. That is, the electrical length and physical length required for the impedance inverter circuit 234 can be determined by the drain capacitance C ds of the amplifier 200 and the fundamental operating frequency.

[0059] Output matching circuits 225 and 226 (including passive components 235 and 236) can be configured taking into account the above constraints. The two RF bandwidths (total power and average power) as well as the instantaneous bandwidth of the Doherty power amplifier 200 can be directly related to the electrical length of the main amplifier path 225 between the transistor current source and the combined node 250, together with the peaking amplifier path 226 which is to be configured to provide a phase difference of approximately 90 degrees. Minimizing the phase delay (e.g., up to 90 degrees) can increase the relative bandwidth (compared to phase delays such as 270 degrees, 450 degrees, etc.). However, implementing output matching circuits 225 and 226 that can meet all three Doherty amplifier requirements (peak power, average power, and instantaneous bandwidth) to provide broadband performance can be particularly difficult to achieve given a particular package size constraint.

[0060] Some conventional Doherty designs may use wire bonds and / or bonding pads having a physical length configured to provide a required electrical length within a desired operating frequency range. For example, some conventional Doherty amplifiers may use wire bonds as interconnections between various components of the main amplifier path and various components of the peaking amplifier path, especially in combination with active transistor devices characterized by a relatively large output capacitance. However, such wire bonds introduce strong coupling between the wires (e.g., between series wires and shunt wires), resulting in power loss and reduced conversion. Reducing the coupling between paths presents a challenge in the design of small Doherty amplifier modules. Also, in the case of GaN-based devices (which may have a relatively low output capacitance and thus may require a larger inductance for resonance), it can be difficult to achieve the required inductance in the low GHz range (e.g., in the case of communication-related operating frequency bands).

[0061] Some other conventional Doherty designs may vary the size and / or shape of the bonding pads to orient the wire bonds differently for coupling reduction. For example, the shunt wire may be oriented orthogonal to the series wire (and thus orthogonal to the signal propagation between the RF input and output terminals), thereby reducing or preventing coupling between the series and shunt wires, resulting in reduced loss and an improved conversion ratio. This arrangement can be used with transistor devices having a relatively low output capacitance (e.g., GaN-based devices), while requiring a bonding pad layout with specific size and / or shape requirements (e.g., C-shaped or L-shaped bonding pads having an increased physical length) to provide a higher inductance and / or additional complexity (e.g., multiple wires for sufficient current handling) due to resonance from the low output capacitance.

[0062] Embodiments of the present invention can arise, in particular, from the recognition that as the physical distance between drain terminals becomes increasingly shorter, a matching circuit using wirebond-based interconnections can become impractical, or can be problematic in other cases, for transistor devices having low output capacitance (such as GaN-based transistor devices including GaN-on-SiC transistor devices). Accordingly, embodiments of the present disclosure include transistor amplifiers having respective matching circuits, wherein one or more of the matching circuits are implemented in a configuration that can reduce or eliminate wirebonds and / or wirebond pads. Although described herein primarily with respect to group-III nitride-based or GaN-based semiconductor devices (such as GaN on SiC devices), it will be understood that embodiments of the present disclosure are not limited to any particular semiconductor material.

[0063] In some embodiments, one or more wire bond-based interconnects or integrated circuit components may be replaced by components or circuits that are electrically connected, e.g., in a flip-chip configuration, by conductive bumps (e.g., solder bumps). As used herein, "flip-chip" may refer to a configuration in which pads or terminals of a transistor device or other components are electrically connected by conductive bumps rather than by wire bonds. Additionally or alternatively, wire bond-based interconnects or integrated circuit components may be replaced by components or circuits within or on a multilayer laminate structure, which may be connected by conductive bumps to one or more terminals of an active transistor device. In particular, the inductor, capacitor, and / or other components of each integrated circuit may be provided by one or more passive electrical components implemented in a flip-chip configuration by individual devices (e.g., integrated passive devices (IPDs) having thin film substrates such as silicon, alumina, or glass) and / or by elements integrated in a multilayer laminate structure (e.g., spiral inductors), either of which may be connected by conductive bumps to one or more terminals of an active transistor device. In the embodiments described herein, at least one of the transistor amplifiers or integrated circuit components may be implemented in a flip-chip configuration (i.e., flip-chip implementation of a transistor device, or flip-chip implementation of a passive component, or flip-chip implementation of both a transistor device and a passive component), which may also be referred to herein as a flip-chip implementation component.

[0064] The implementation of matching circuits or passive circuits and / or transistor amplifiers in a flip-chip configuration can enable a desired electrical length to be more physically realizable, particularly in the case of Doherty amplifiers configured to operate at a relatively high fundamental operating frequency and / or to fit within a relatively compact footprint. For example, implementing a shunt inductance using an IPD connected to the output (e.g., drain) terminal of each transistor amplifier can achieve a relatively long electrical length in a relatively small area (as may be required to provide a larger inductance due to resonance from the low output capacitance of some semiconductor materials such as GaN), which can be important because the package size / pitch between terminals is reduced and / or the operating frequency is increased (especially due to the removal of wire bonds). Also, reducing the size of the bonding pads and / or eliminating the use of wire bonds can reduce and / or eliminate the complexity of signal line connections and / or the complexity of bonding pad manufacturing that some conventional devices may face. Additionally, in some embodiments, the inductance value realized in a matching circuit or passive circuit can be easily changeable without redesigning the amplifier layout and / or the transmission line configuration. For example, the change can be made by changing the value of an IPD or other chip inductor in the amplifier package, which can enable relatively easy customization and / or tuning of the power amplifier described herein.

[0065] FIG. 3A is a partial transparent plan view of a PA300 including a plurality of transistor amplifiers 220, 230 connected in parallel and respective matching circuits and phase delay circuits, according to some embodiments of the present invention. FIG. 3B is a partial transparent plan view showing the transistor amplifiers 220, 230 of FIG. 3A in more detail.

[0066] As shown in FIGS. 3A and 3B, PA300 includes a first transistor amplifier 220 and a second transistor amplifier 230 connected between an input section 210 and an output section 290 in a substrate 260. The transistor amplifiers 220 and 230 may be formed (e.g., by epitaxial growth and other semiconductor processing and metallization steps) or otherwise provided in a semiconductor structure 10. For example, the semiconductor structure 10 may include a group III nitride-based material (e.g., gallium nitride (GaN)) and / or silicon carbide (SiC). Other materials of the semiconductor structure 10 may include, but are not limited to, sapphire, diamond, aluminum nitride, aluminum gallium nitride, gallium nitride, silicon, GaAs, LGO, ZnO, LAO, InP, etc.

[0067] The substrate 260 may be a single-layer or multi-layer laminate such as a single-layer or multi-layer printed circuit board (PCB). The substrate 260 includes conductive wiring or connection patterns 262 (e.g., traces, vias, interlayer wiring, etc. as shown in FIGS. 4A, 4B, 5A, and 5B) extending within or on the substrate. The substrate 260 may provide a structural element or base to which the semiconductor structure 10 is attached or mounted in a transistor amplifier package such as exemplary packages 400a, 400b, 500a, and 500b discussed below with reference to FIGS. 4A, 4B, 5A, and 5B.

[0068] The conductive wiring or connection pattern 262 in the substrate 260 can electrically connect and / or implement one or more of the passive electrical components of the impedance matching circuits 215, 216, 225, 226 described herein. Accordingly, each of the input impedance matching circuits 215 and 216 can be connected to the respective input terminals (e.g., gate pads or gate terminals 14) of the first transistor amplifier 220 and the second transistor amplifier 230. The respective output terminals (e.g., drain pads or drain terminals 34) of the first transistor amplifier 220 and the second transistor amplifier 230 are connected to the combined node 250, and the respective output impedance matching circuits 225 and 226 are connected between the respective output terminals 220d and 230d and the combined node 250. Other electrical components (e.g., components of the input phase delay circuit 204, power splitter 214, impedance inverter 234, and / or load impedance matching circuit 254) can also be implemented by the conductive connection pattern 262 within or on the substrate 260. The substrate 260 can further include input leads 205 and / or output leads 295 on its surface. Accordingly, the transistor amplifier package can include the semiconductor structures 10 of the transistor amplifiers 220, 230, as well as the impedance matching circuits 216, 216, 225, 226, 254, phase delay elements 214, 234, and / or other circuit components that can be used to define the power amplifier 300.

[0069] At least one of the first transistor amplifier 220 and the second transistor amplifier 230, or one or more passive electrical components 235 and 236, are implemented in a flip-chip configuration on the substrate 10, in which one or more terminals of the first transistor amplifier 220 or the second transistor amplifier 230 are connected to one or more passive electrical components 235, 236 of the matching circuits 215, 216, 225, 226 by one or more conductive bumps 201. In the examples of FIGS. 3A and 3B, a semiconductor structure 10 including the first transistor amplifier 220 and the second transistor amplifier 230 within or on the semiconductor structure 10 is implemented in a flip-chip configuration on the substrate 260. The semiconductor structure 10 is shown transparently to show each component of the transistor amplifiers 220 and 230 (i.e., the gate pad 14, the source pad 26, and the drain pad 34), and the conductive bumps 201 that electrically connect the pads 14 and 34 to the matching circuits 215, 216 and 225, 226 or their passive electrical components 235, 236.

[0070] In some embodiments, the PA300 may be implemented in a Doherty configuration, where the first transistor amplifier 220 is the main amplifier and the second transistor amplifier 230 is the peaking amplifier. The output matching circuits 225 and 226 may each be configured to delay the phase of the output signal from one of their respective output terminals 34 so as to provide a predetermined phase shift. For example, the passive components 235 and 236 of the output matching circuits may provide an impedance that is 90 degrees long (i.e., provide a 1 / 4 wavelength phase shift based on the wavelength corresponding to the frequency component of the output signal) between their respective output terminals 34 and the combining node 250. In the inverted Doherty configuration shown in FIG. 3A, the impedance converter 234 provides an additional 1 / 4 wavelength or 90 degree phase between the output of the peaking amplifier matching circuit 226 and the combining node 250.

[0071] In some embodiments, the passive electrical components 235, 236 of the matching circuits 225, 226 provide respective shunt inductance circuits that are connected by conductive bumps 201 to the respective drain terminals 34 of the main amplifier 220 and / or the peaking amplifier 230. Each shunt inductance circuit includes a shunt inductance L_shunt having an inductance value that provides at least partial resonance by the output capacitance (e.g., drain-source capacitance C ds ) of the transistor device 220 or 230. That is, the shunt inductance L_shunt has an inductance value configured to resonate at least a portion of the parasitic drain-source capacitance C ds of the transistor devices 220, 230. In various embodiments, each shunt inductance may be terminated with a capacitance C_dec (see FIG. 2B) that provides an RF decoupling node at the fundamental operating frequency f0 of the amplifiers 220, 230.

[0072] In some embodiments, the shunt inductance L_shunt can be implemented by one or more IPDs or other flip-chip mounted discrete components. As described above, the IPD can include discrete inductors and / or other passive electrical components and can be fabricated using standard semiconductor processing techniques such as thin-film processing and / or photolithography. The IPD can be made flip-chip mountable and can include a thin-film substrate such as silicon, alumina, or glass. The IPD can be mounted in a flip-chip configuration on the surface of substrate 260 and connected to the output terminal 34 of main amplifier 220 or peaking amplifier 230 by conductive bumps 201. In some embodiments, the shunt inductance L_shunt can be implemented by a distributed element or structure within substrate 260 (e.g., by a conductive layer pattern and / or an insulating layer pattern fabricated using semiconductor processing techniques) and connected to the output terminal 34 of main amplifier 220 or the output terminal 34 of peaking amplifier 230 by conductive bumps 201. More generally, the shunt inductance L_shunt can be implemented without using wire bonds or without wire bonds, and the drain terminal 34 can be connected to the shunt inductance L_shunt without an intervening wire-bond pad.

[0073] Similarly, other passive electrical components 235, 236 of impedance matching circuits 215, 216, 225, 226 (e.g., series inductance L_ser, capacitance C_dec, C_ser, C_shunt, see FIG. 2B) can be implemented using flip-chip mounted discrete components and / or structures within substrate 260. As shown in the example of FIG. 3A, the decoupling capacitance C_dec can be implemented by one or more capacitor dies 304 mounted in a flip-chip configuration on the surface of substrate 206. The capacitor die 304 can also implement other capacitances (e.g., C_ser, C_shunt) of impedance matching circuits 215, 216, 225, 226.

[0074] Accordingly, the matching circuits 215, 216, 225, and / or 226 may be implemented by one or more flip-chip IPDs and capacitor dies, which provide an L-C matching circuit at the fundamental frequency f0, as well as a shunt inductance L_shunt and a decoupling capacitance C_dec connected to the ground lead GND. However, as also shown above, the inductance (e.g., L_shunt, L_ser) and / or capacitance (e.g., C_dec, C_ser, C_shunt) may alternatively or additionally be implemented by one or more structures on the substrate 260. More generally, one or more passive electrical components may be implemented using individual flip-chip components and / or distributed components within the substrate or laminate 260, such that there are no wire bonds and / or wire bond pads in the electrical path between at least one of each output terminal 34 and the combined node 250.

[0075] In some embodiments, the elimination of wire bonds and / or wire bond pads in parallel-stage transistor amplifier packages according to some embodiments of the present disclosure, such as in the Doherty amplifier configurations described herein, may enable an increase in bit rate and / or efficiency, for example, in telecommunications applications. In certain embodiments, a shunt inductance Ls sufficient for resonance with GaN-based and / or other low C ds / mm materials may be directly connected (e.g., by conductive bumps 201) to the output terminals 34 (e.g., drain pads) of each transistor amplifier 220 and / or 230 by implementing at least one of the transistor amplifiers 220, 230 or the passive electrical components 235, 236 using a flip-chip configuration. The shunt inductance Ls may be provided as a first element (e.g., directly connected to the drain terminal so as to be implemented as close as possible to the output of each transistor amplifier 220, 230) of the matching circuits 225, 226, which may reduce or minimize the required inductance.

[0076] Figures 3A and 3B show an asymmetric Doherty PA arrangement 300 in which the peaking amplifier 330 includes more unit cell transistors 40 than the main amplifier 320, thereby providing higher power handling performance. However, it will be understood that the embodiments described herein are not limited to such an arrangement. Some embodiments may include a symmetric Doherty arrangement or other load modulation amplifier arrangement in which the main amplifier 320 and the peaking amplifier 330 include the same number of unit cell transistors 40 to provide the same power handling performance. As will be discussed in more detail below, the bandwidth can be optimized by giving each electrical length based on the relative power characteristics between the main amplifier 220 and the peaking amplifier 230 to the output impedance matching circuits 225, 226 and / or the load impedance matching circuits 254, and this electrical length can be quantified as the ratio of peaking amplifier power to main amplifier power (also called the asymmetry factor).

[0077] Figures 4A, 4B, 5A, and 5B are cross-sectional views showing exemplary transistor amplifier packages according to some embodiments of the present disclosure. In particular, FIGS. 4A and 5A show transistor amplifier packages 400a and 500a in which a semiconductor structure 10 (including transistor amplifiers 220, 230) is flip-chip mounted on a substrate 260' by conductive bumps 201, and input sections 210 and output sections 290 (including matching circuits 215, 216 and 225, 226) of the power amplifier 300 are realized by distributed element structures within the layers of the substrate 260'. FIGS. 4B and 5B show transistor amplifier packages 400b and 500b in which a semiconductor structure 10 (including transistor amplifiers 220, 230) and one or more passive components of the input section 210 and the output section 290 are flip-chip mounted on a substrate 260'' by conductive bumps 201.

[0078] In the examples of FIGS. 4A and 5A, the substrate 260’ is a multilayer laminate (such as a PCB) including a conductive layer pattern 262’’ and / or a conductive via 262’ (collectively referred to as the conductive connection pattern 262) that is electrically connected to respective terminals 14, 26, 34 of the transistor amplifiers 220, 230 by the conductive bumps 201. The multilayer laminate 260’ and the conductive connection pattern 262 can be manufactured using semiconductor processing techniques by depositing conductive layers and insulating layers and / or conductive patterns and insulating patterns on a base material, and also by forming vias and conductive routing patterns within the structure.

[0079] Still referring to FIGS. 4A and 5A, the conductive connection pattern 262 and related structures in the multilayer laminate 260’ can be configured to provide distributed circuit elements that implement the passive components of the matching circuits 215, 216, 225, 226 and other circuits 204, 214, 234, 254 in the input section 210 and output section 290 of the PA300 shown in FIG. 3A. For example, the conductive connection pattern 262 and related structures in the multilayer laminate 260’ can be configured to provide the matching circuits 225, 226 in the output section 290, each including a shunt inductance L_shunt connected to the drain terminal 34 of the respective transistor amplifiers 220, 230 by the conductive bumps 201. The conductive connection pattern 262 and related structures in the multilayer laminate 260’ can be similarly configured to provide the matching circuits 215, 216 in the input section 210 that are connected to the gate terminals 14 of the transistor amplifiers 220, 230 by the conductive bumps 201, and also to connect the source terminals 26 of the respective transistor amplifiers 220, 230 to the ground reference GND.

[0080] In the examples of FIGS. 4B and 5B, the substrate 260'' is a single-layer laminate or a multi-layer laminate (such as a PCB) including conductive vias 262' electrically connected to the respective terminals 14, 26, 34 of the transistor amplifiers 220, 230 by conductive bumps 201. The passive components of the matching circuits 215, 216, 225, 226 of the input section 210 and the output section 290 of the PA300 shown in FIG. 3A and / or the passive components of the circuits 204, 214, 234, 254 are implemented by flip-chip components shown as input IPDs 415, 416 and output IPDs 425, 426. For example, the output IPDs 425, 426 may be configured to provide the matching circuits 225, 226 of the output section 290, each including a shunt inductance L_shunt connected to the drain terminals 34 of the respective transistor amplifiers 220, 230 of the semiconductor structure 10 by conductive bumps 201. The input IPDs 415, 416 may be similarly configured to provide the matching circuits 215, 216 of the input section 210 connected to the gate terminals 14 of the transistor amplifiers 220, 230 by conductive bumps 201. The source terminals 26 of the respective transistor amplifiers 220, 230 may be connected to the ground reference GND by conductive bumps 201 and conductive vias 262' extending through the substrate 260''.

[0081] In FIGS. 4A, 4B, 5A, and 5B, a semiconductor structure 10 (including transistor amplifiers 220, 230) is flip-chip mounted on substrates 260', 260''. Gate terminals 14, source terminals 26, and drain terminals 34 are provided on one surface of the semiconductor structure 10 mounted face down on substrates 260', 260'', so that the terminals 14, 26, 34 are conductively connected to a conductive connection pattern 262 by conductive bumps 201. The opposite surface of the semiconductor structure 10 includes a thermal interface material (TIM) 460. The TIM 460 is configured to transfer heat generated from the semiconductor structure 10 to a heat sink (shown as a heat spreader 480 in FIG. 4A). The TIM 460 may be electrically conductive and thermally conductive, or may be thermally conductive but electrically insulating. In some embodiments, the TIM 460 may not be present.

[0082] The transistor amplifier packages 400a, 400b, 500a, and 500b of FIGS. 4A, 4B, 5A, and 5B each include a semiconductor structure 10 (including a first transistor amplifier 220 and a second transistor amplifier 230) and an input section 210 and an output section 290 (including integrated circuits 215, 216, 225, 226, phase delay circuits 204, 234, and other circuits 214, 254) that are encapsulated in a package housing or otherwise protected. For example, FIGS. 4A and 4B show overmolded packages 400a and 400b, while FIGS. 5A and 5B show open cavity packages 500a and 500b.

[0083] In FIGS. 4A and 4B, transistor amplifier packages 400a, 400b each include an overmold structure 470 that covers or at least partially encapsulates semiconductor structure 10 and substrates 260', 260''. Exemplary transistor amplifier packages 400a, 400b also include a heat dissipating member having a surface exposed by the overmold structure 470 for top surface cooling (the top surface of heat spreader 480 in FIG. 4A, the top surface of TIM 460 in FIG. 4B), although it will be understood that in some embodiments the overmold structure 470 may completely encapsulate semiconductor structure 10.

[0084] In FIGS. 5A and 5B, transistor amplifier packages 500a, 500b each include a lid member 570 that protects semiconductor structure 10 and substrates 260', 260''. The lid member 570 may include a ceramic material (e.g., alumina) and may define an open cavity that at least partially surrounds components 10, 260', 260''. In some embodiments, the lid member 570 may be a thermally conductive material that dissipates heat or otherwise transfers heat outside of packages 500a, 500b. Exemplary transistor amplifier packages 500a, 500b also include a heat dissipating member having a surface that contacts the lid member 570 (the top surface of heat spreader 480 in FIG. 5A, the top surface of TIM 460 in FIG. 5B).

[0085] Referring still to FIGS. 4A, 4B, 5A, and 5B, RF input leads 205 and RF output leads 295 are provided on the surfaces of substrates 260', 260'' for attachment and / or coupling to an external device such as circuit board 660 shown in FIGS. 6A and 6B. In these figures, they are shown as being provided on the surfaces of substrates 260', 260'' opposite the semiconductor structure 10 side, but the transistor amplifier packages described herein are not limited to such an arrangement, and it will be understood that in some embodiments, the RF input leads 205 and RF output leads 295 may be provided on the same surface of substrates 260', 260'' as the semiconductor structure 10. Similarly, it will be understood that in some embodiments, the heat dissipation members 480 and / or 460 may not be present.

[0086] FIGS. 6A and 6B are cross-sectional views showing an exemplary product or application including a transistor amplifier package according to some embodiments of the present disclosure. Although shown in FIGS. 6A and 6B with reference to the packages 400a and 400b of FIGS. 4A and 4B for illustrative purposes, it will be understood that the packages 500a and 500b of FIGS. 5A and 5B (or more generally, other packages according to embodiments of the present disclosure) may be provided as well.

[0087] In FIGS. 6A and 6B, the exemplary products 600a, 600b may electrically connect the RF input leads 205 and RF output leads 295 of the transistor amplifier packages 400a, 400b to the surface of an external integrated circuit such as circuit board 660. The circuit board 660 includes conductive elements or traces 662 on its surface, and the transistor amplifier packages 400a, 400b may be configured such that the RF input leads 205, RF output leads 295, and ground reference GND are aligned with corresponding conductive elements among the conductive elements 662 for electrical connection.

[0088] In the examples of FIGS. 6A and 6B, the circuit board 660 further includes an integrated heat dissipation member shown as an example as a thermally conductive coin 681 extending through the circuit board 660, and a heat sink 680 on a surface of the circuit board 660 opposite to the surface on which the transistor amplifier packages 400a, 400b are mounted. Accordingly, the exemplary product applications 600a, 600b may include a plurality of thermally conductive paths for dissipating heat away from the semiconductor structure 10. In particular, heat may be dissipated from a first heat path on the upper surface of the products 600a, 600b defined by the heat spreader 480 (in FIG. 6A) and the TIM 460 (in FIG. 6B) exposed by the respective overmold members 470 of the packages 400a, 400b. Heat may also be dissipated by a second heat path (which may also provide an electrical path to the ground connection) on the bottom surface of the products 600a, 600b defined by the conductive connection 262, the ground reference GND, the conductive element 662, the coin 681, and the heat sink 680.

[0089] The circuit board 660 may include additional active and / or passive electrical components in some embodiments. For example, the circuit board 660 may include additional passive electrical components configured to provide input pre-matching circuitry and / or output pre-matching circuitry for the transistor amplifiers 220, 230.

[0090] FIGS. 7A and 7B respectively show a plan view and a perspective view showing examples of the IPDs 415, 416, 425, 426 that can be used to implement passive electrical components for matching circuitry and / or phase delay circuitry according to some embodiments of the present disclosure. As described above, the IPD may include an inductor and / or other passive electrical components and may be manufactured using standard semiconductor processing techniques such as thin film processing and / or photolithography processing. The IPD can be a flip-chip mountable or wire-bondable component and may include a thin film substrate such as silicon, alumina, or glass.

[0091] In the examples of FIGS. 7A and 7B, IPDs 415, 416, 425, 426 can be configured to provide a shunt inductance having an accurate inductance value for bandwidth optimization, for example, using a coil inductor or a spiral inductor L_shunt. The shape, width, and general design of the coil inductor L_shunt can be configured and / or optimized to reduce losses. One end of the coil inductor L_shunt can include a bump pad or contact pad 101 that can be pre-attached by a conductive bump (e.g., 201) for flip-chip connection to the respective input terminal 14 or output terminal 34 of the transistor amplifiers 220, 230.

[0092] IPDs 415, 416, 425, 426 can also be configured to provide additional impedance, such as a series inductance, using a series-connected strip L_ser. The width of the series-connected strip L_ser can be configured to provide a desired impedance transformation for the matching circuits 215, 216, 225, 226 and / or the phase delay circuits 204, 234. The series-connected strip L_ser can extend between bump pads or contact pads 102, and the width of each series-connected strip L_ser can be configured to provide a desired characteristic impedance. More generally, any of the passive electrical components described herein can be implemented by IPDs 415, 416, 425, 426 that include a series-connected strip L_ser coupled to a contact pad 102 for connection to the respective terminals 14, 34 of the transistor amplifiers 220, 230 described herein and / or a coil inductor Ls coupled to a contact pad 101.

[0093] Additionally or alternatively, the passive electrical components described herein can be implemented by one or more distributed elements configured to provide respective phase shifts.

[0094] FIG. 8A and FIG. 8B are cross-sectional views showing a distributed element circuit 245 in a substrate 260' that can be used to implement passive electrical components for a matching circuit and / or a phase delay circuit according to some embodiments of the present disclosure. For example, passive electrical components that define output matching circuits 225 and / or 226 can be implemented as inductors and / or capacitors 245 realized by metal layers and / or wiring layers 262 within and / or on one or more layers of the substrate or laminate 260', and this metal layer and / or wiring layer can be connected to the input terminals 14 (in FIG. 8A) or output terminals 34 (in FIG. 8B) of the transistor amplifiers 220, 230 by conductive vias 262'.

[0095] As shown by way of example in the cross-sectional views of FIGS. 8A and 8B, the distributed circuit element 245 in the substrate or laminate 260' can include inductive elements L_shunt, L_ser formed by conductive elements 262'' (e.g., wiring layers) and electrically connected to the gate 14 or drain 34 by respective conductive vias 262'. Additionally or alternatively, the distributed circuit element 245 can include a capacitance C formed between a conductive element 262'' (e.g., wiring layer) separated by one or more dielectric layers 237 and a ground conductor GC. The capacitance C can be coupled to the gate 14 or drain 34 by respective conductive vias 262' and can be configured to provide any of the capacitances (e.g., C_dec, C_shunt, C_ser) described herein. The dielectric layer 237 can include one or more dielectrics or layers having electrical properties suitable for forming a capacitance between the wiring layer 262 and the ground conductor GC, such as silicon oxide, silicon nitride, silicon oxynitride, high-k dielectrics, or combinations thereof, but the embodiments described herein are not limited thereto.

[0096] Figures 9A, 9B, 9C, and 9D are graphs showing the performance of an output matching circuit configured for increasing or optimizing bandwidth (including both RF bandwidth and instantaneous bandwidth) in a PA according to some embodiments of the present disclosure. In particular, the graphs of FIGS. 9A - 9D show the performance of an embodiment of the present disclosure (shown by line 900) including an output matching circuit having a shunt inductance connected to the drain terminal of each transistor amplifier as compared to an output matching circuit (shown by line 990) that omits the shunt inductance and includes a series inductance connected to the drain terminal of each transistor amplifier. More specifically, FIG. 9A shows main current source plane matching, FIG. 9B shows the current source for load power transmission, FIG. 9C shows the current source for load power transmission phase, and FIG. 9C shows VBW performance as baseband resonance in the current source plane.

[0097] As shown in FIGS. 9A - 9D, a matching circuit including a shunt inductance connected to the drain terminal of each transistor amplifier described herein may be important in terms of substantially increased PF bandwidth (e.g., from about 1.4 GHz to about 2.6 GHz) and baseband resonance (e.g., about 531 MHz) as compared to the implementation of a series inductance (having a narrower RF bandwidth from about 1.9 GHz to about 2.1 GHz and a baseband resonance of about 341 MHz). For example, Doherty RF bandwidth optimization according to some embodiments may provide a matching network between the main current source and a combined node having an electrical length of 90° using a shunt inductance as the first matching element (i.e., directly connected to the drain terminal). Additionally, providing a shunt inductance at the drain plane (for impedance matching rather than as a choke) may achieve improved or optimal SBW performance.

[0098] In some embodiments, the transistor amplifier can be configured in a Doherty configuration, and the matching circuit can be configured to simultaneously improve and / or optimize a plurality of Doherty amplifier bandwidths (e.g., peak RF power / total RF power, average RF power / back-off RF power, and IBW). For example, the load impedance matching circuit 254 can be configured to provide an electrical length based on the relative power characteristics between the main amplifier 220 and the peaking amplifier 230. In particular, the asymmetry coefficient α can be defined as the ratio of the peaking amplifier power P_Peak to the main amplifier power P_Main, while the load modulation degree can be defined as 1 + α.

[0099] Some embodiments can result from the recognition that the impedance R_match of each of the output matching circuits 225, 226 of the PA300 (e.g., of the transistor amplifiers 220, 230 in an inverse Doherty configuration) can be based on the cascade of the main output matching circuit 225 and the load impedance matching circuit 254 between the combined node 250 and the load. The main output matching circuit 225 having an electrical length of 90° can be fully balanced with respect to total power and average power. The load impedance matching circuit 254 (between the combined node 250 and the output lead 295 / load) can have an unrestricted electrical length and thus can be configured as needed for bandwidth optimization. In particular, one or more PA bandwidths can be improved or optimized by providing a load impedance matching circuit 254 (section between the combined node 250 and the output lead 295) having an electrical length based on the asymmetry coefficient (or modulation degree) of the main amplifier 220 and the peaking amplifier 230.

[0100] For example, in a symmetric Doherty configuration where P_Peak = P_Main, the asymmetry factor α = 1, and the load modulation degree = 2, an improved or optimal bandwidth can be achieved when the impedance at the combining node 250 is equal to approximately twice the impedance R_main seen at the input to the main output matching circuit 225. In an exemplary asymmetric Doherty configuration where P_Peak = 2 × P_Main, the asymmetry factor α = 2, and the load modulation degree = 3, an improved or optimal bandwidth can be achieved when the impedance at the combining node 250 is equal to approximately three times the impedance R_main seen at the input to the main output matching circuit 225. Thus, in some embodiments, the impedance at the combining node 250 (e.g., the impedance of the load impedance matching circuit 254) can be approximately 1.5 to 4 times (e.g., approximately 2 to 3 times) the impedance R_main at the output terminal of the main amplifier 220 (i.e., at the input to the matching circuit 225) for an asymmetry factor of 1 to 2. In some embodiments, an optimal RF bandwidth can be achieved when the impedance ratio (i.e., the ratio of the impedance at the combining node 250 to the impedance R_main seen at the input to the main output matching circuit 225) is equal to the load modulation degree.

[0101] As described herein, embodiments of the present disclosure provide transistor structures and matching topologies that can reduce or eliminate the use of wire bonds and / or wire bond pads and are configured using conductive bumps and / or flip-chip arrangements (which may include flip-chip implementations of transistor amplifiers, passive components of matching circuits, or both). In particular, some embodiments described herein provide an output matching circuit that directly includes a shunt inductance on the drain side of a transistor amplifier, i.e., directly connected to the drain terminal of the transistor amplifier by one or more conductive bumps. Certain embodiments may provide an output section that includes a shunt inductance by a bumped GaN on SiC transistor.

[0102] As described above, providing the shunt inductance Ls as the first element of the matching circuits 225, 226 (e.g., as close as possible to the output terminals of the respective transistor amplifiers 220, 230) can reduce or minimize the inductance required for resonance due to the output capacitance, thereby reducing the operating frequency limit. The frequency limit can be further reduced by eliminating the capacitive parasitics associated with the bonding pads used for wire bond connections. Some embodiments can also improve the thermal performance by including multiple thermal paths / heat dissipation paths. The improved thermal performance can also allow for an increase in the RF bandwidth due to the use of the basic load. More specifically, since the thermal performance is improved, a smaller device can be used with a power loading closer to the maximum power. This electrical effect can be a lower output impedance Q, which can allow for a wider RF bandwidth.

[0103] Embodiments of the present disclosure can be used in various cellular infrastructure (CIFR) RF power products (including, but not limited to, 5W, 10W, 20W, 40W, 60W, 80W, and various frequency bands) for, for example, 5G and base station applications, as well as radar and monolithic microwave integrated circuit (MMIC) type applications. The broadband Doherty amplifiers described herein (e.g., having a relative bandwidth of greater than about 40%) can also be used in aerospace and defense (A&D) and portable applications. Although described herein mainly with reference to Doherty implementations, in some embodiments, the packaged transistor amplifiers can more generally include multiple transistor dies connected in parallel amplifier paths to form transistor devices having multiple transistor dies and multiple paths, such as in dual-path driver amplifiers or other multi-stage power amplifiers.

[0104] The terms "first", "second", etc. may be used herein to describe various elements, but it will be understood that these elements are not limited to these terms. These terms are only used when distinguishing one element from another. For example, without departing from the scope of the present invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0105] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used herein, the terms "comprises", "comprising", "includes" and / or "including" specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0106] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terms used herein should be construed to have a meaning that is consistent with their meaning in the context of this specification and the relevant art, and should not be construed in an idealized or overly formal sense unless expressly defined herein.

[0107] When an element such as a layer, region, or substrate is referred to as being "on" another element or extending "onto" another element, it will be understood that the element may be directly on or extend directly onto the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly on" another element or extending "directly onto" another element, there are no intervening elements. When an element is referred to as being "connected" or "coupled" to another element, it will be understood that the element may be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0108] Relative terms such as "below" or "above", or "upper" or "lower", or "horizontal" or "lateral" or "vertical" may be used in this specification to describe the relationship of one element, layer, or region to another element, layer, or region as shown in the figures. It will be understood that these terms are intended to encompass various orientations of the device in addition to the orientation depicted in the figures.

[0109] Embodiments of the present invention are described herein in connection with cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present invention. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. Further, differences from the illustrated shapes are to be expected, for example, as a result of manufacturing techniques and / or manufacturing tolerances. Accordingly, embodiments of the present invention should not be construed as limited to the particular shapes of the regions illustrated herein, but should include, for example, departures in shape due to manufacturing. Elements shown in dashed lines may be optional in the illustrated embodiments.

[0110] Throughout, the same numbers refer to the same elements. Thus, the same or similar numbers may be described with reference to other drawings even if they are not stated or depicted in the corresponding drawings. Also, elements not indicated by reference numbers may be described with reference to other drawings.

[0111] In the drawings and the specification, typical embodiments of the present invention are disclosed and specific terms are employed, but they are used only in a general and illustrative sense and not for purposes of limitation, and the scope of the present invention is set forth in the following claims.

Claims

1. A substrate, a first transistor amplifier and a second transistor amplifier each having an output terminal connected to a combined node, a matching circuit including one or more passive electrical components connected between one of the respective output terminals and the combined node, comprising: a power amplifier, wherein at least one of the first transistor amplifier and the second transistor amplifier or the one or more passive electrical components is mounted on the substrate in a flip-chip configuration.

2. The power amplifier according to claim 1, wherein the one of the respective output terminals is a drain terminal, and the one or more passive electrical components include a shunt inductance connected to the drain terminal by a conductive bump.

3. The power amplifier according to claim 2, wherein the one or more passive electrical components include at least one integrated passive device (IPD) mounted on the substrate in the flip-chip configuration and providing the shunt inductance.

4. The power amplifier according to claim 2, wherein the substrate includes a multilayer laminate, and the one or more passive electrical components are in the multilayer laminate and include at least one inductor providing the shunt inductance.

5. The power amplifier according to any one of claims 2 to 4, wherein there is no wire bond in the shunt inductance.

6. The power amplifier according to any one of claims 2 to 5, wherein the drain terminal is connected to the shunt inductance without a wire bond pad therebetween.

7. The power amplifier according to any one of claims 1 to 6, wherein there is no wire bond in the electrical path between the one of the respective output terminals and the combined node.

8. The power amplifier, wherein the one of the respective output terminals is a drain terminal of the first transistor amplifier, the matching circuit is a first output matching circuit, the shunt inductance is a first shunt inductance, A second output matching circuit connected between the drain terminal of the second transistor amplifier and the combining node, the second output matching circuit further comprising a second shunt inductance connected to the drain terminal of the second transistor amplifier by a conductive bump, the power amplifier according to any one of claims 2 to 7.

9. The first transistor amplifier die and the second transistor amplifier die each include a main amplifier and a peaking amplifier in a Doherty configuration, the power amplifier according to any one of claims 1 to 8.

10. The power amplifier further comprises a load impedance matching circuit connected between the combining node and the output lead, The impedance of the load impedance matching circuit is based on an asymmetry factor between the peaking amplifier and the main amplifier, and is about 1.5 times to 4 times the impedance at the output terminal of the main amplifier, the power amplifier according to claim 9.

11. The matching circuit is configured to delay the phase of the output signal from one of the respective output terminals by a quarter wavelength, the power amplifier according to any one of claims 1 to 10.

12. The power amplifier according to any one of claims 1 to 11 further comprises a package housing internally including the substrate, the first transistor amplifier and the second transistor amplifier, and the matching circuit.

13. A main transistor amplifier, A peaking transistor amplifier, Including, the respective output terminals of the main transistor amplifier and the peaking transistor amplifier are connected to a combining node, A transistor amplifier package having no wire bond in the electrical path between one of the respective output terminals and the combining node.

14. The transistor amplifier package according to claim 13 further comprising a matching circuit including one or more passive electrical components connected between one of the respective output terminals and the combining node.

15. One of the respective output terminals is a drain terminal, and the one or more passive electrical components include a shunt inductance connected to the drain terminal by a conductive bump, the transistor amplifier package according to claim 14.

16. Further comprising a substrate, wherein at least one of the main transistor amplifier and the peaking transistor amplifier or the one or more passive electrical components is mounted on the substrate in a flip-chip configuration, the transistor amplifier package according to claim 15.

17. The transistor amplifier package according to claim 16, wherein the one or more passive electrical components are mounted on the substrate in the flip-chip configuration and include at least one integrated passive device (IPD) providing the shunt inductance.

18. The transistor amplifier package according to claim 16, wherein the substrate includes a multilayer laminate, and the one or more passive electrical components are in the multilayer laminate and include at least one inductor providing the shunt inductance.

19. One of the respective output terminals is the drain terminal of the main transistor amplifier, the matching circuit is a first output matching circuit configured to delay the phase of the output signal from the main transistor amplifier by a quarter wavelength, the shunt inductance is a first shunt inductance, and the transistor amplifier package is A second output matching circuit connected between the drain terminal of the peaking transistor amplifier and the combined node and configured to delay the phase of the output signal from the peaking transistor amplifier by a quarter wavelength, the second output matching circuit including a second shunt inductance connected to the drain terminal of the peaking transistor amplifier by a conductive bump, the transistor amplifier package according to any one of claims 15 to 18.

20. Further comprising a load impedance matching circuit connected between the combined node and the output lead of the transistor amplifier package, The transistor amplifier package according to any one of claims 13 to 19, wherein the impedance of the load impedance matching circuit is about 1.5 times to 4 times the impedance at the output terminal of the main transistor amplifier.

21. A power amplifier, A first transistor amplifier, A second transistor amplifier, wherein drain terminals of the first transistor amplifier and the second transistor amplifier are each connected to a combined node, The power amplifier further includes A matching circuit connected between one of the respective drain terminals and the combined node, the matching circuit including a shunt inductance connected to the one of the respective drain terminals by a conductive bump A power amplifier comprising

22. The power amplifier according to claim 21, wherein the one of the respective drain terminals is connected to the shunt inductance without a wire bond pad therebetween.

23. The power amplifier according to claim 21 or 22, wherein there is no wire bond in an electrical path between the one of the respective drain terminals and the combined node.

24. The power amplifier according to any one of claims 21 to 23, further comprising a substrate, wherein at least one of the first transistor amplifier and the second transistor amplifier or the one or more passive electrical components is mounted on the substrate in a flip chip configuration.

25. The power amplifier according to claim 24, wherein the one or more passive electrical components are mounted on the substrate in the flip chip configuration and include at least one integrated passive device (IPD) providing the shunt inductance.

26. The power amplifier according to claim 24, wherein the substrate includes a multilayer laminate, and the one or more passive electrical components are in the multilayer laminate and include at least one inductor providing the shunt inductance.

27. The power amplifier according to any one of claims 21 to 26, wherein the first transistor amplifier die and the second transistor amplifier die each include a main amplifier and a peaking amplifier in a Doherty configuration.

28. The power amplifier according to claim 27, wherein the impedance at the combined node is about 1.5 times to 4 times the impedance at the drain terminal of the main amplifier.

29. The power amplifier according to any one of claims 21 to 28, further comprising a package housing including the first transistor amplifier, the second transistor amplifier, and the matching circuit therein.

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