Oxide barrier using a CVD deposition process

Abstract

A method of forming an oxide barrier layer in a semiconductor structure includes forming a contact layer on an exposed surface of a semiconductor region of the semiconductor structure in a first processing chamber, where the semiconductor region includes silicon germanium doped with a p-type dopant, and the contact layer includes silicon germanium (SiGe) having a germanium (Ge) ratio in the range between 60% and 100%, forming the contact layer, and forming an oxide barrier layer containing gallium (Ga) on the contact layer by applying a gallium (Ga)-containing liquid precursor to the surface of the contact layer in the first processing chamber.

Description

Technical Field

[0001] The embodiments described herein generally relate to semiconductor device manufacturing, and more particularly, to systems and methods for forming contacts within a semiconductor structure.

Background Art

[0002] Multi-gate metal oxide semiconductor field effect transistors (MOSFETs), such as complementary metal oxide semiconductor (CMOS) devices, present challenges in manufacturability due to their three-dimensional (3D) design and small size. In advanced CMOS devices, contact resistivity is 10 -9 Ωcm 2To reduce to a regime and achieve the required performance for advanced CMOS technology, an epitaxial layer of a silicon-containing material (e.g., boron-doped p-type silicon germanium or phosphorus-doped n-type silicon) formed at the bottom of a trench contact is often utilized. Generally, p-type epitaxial layers are formed from silicon germanium (SiGe) having a high germanium (Ge) concentration, e.g., about 60% and about 80%, or in some cases 100%, to minimize contact resistance. However, epitaxial layers of silicon germanium (SiGe) with a high germanium (Ge) concentration are known to undergo rapid surface oxidation in an air atmosphere, thereby forming germanium oxides and suboxides. These oxide layers introduce residual oxygen at the interface between the epitaxial layer of silicon germanium (SiGe) and the metal silicide layer formed on top of the epitaxial layer, which may increase the contact resistance. These oxide layers can be removed by a sputtering-based pre-cleaning process, but such pre-cleaning processes have adverse effects such as crystal defect generation, dopant deactivation, and material removal in the epitaxial layer, all of which can lead to degradation of electrical performance. The sputtering-based pre-cleaning process can also cause degradation of the surrounding dielectric structure (e.g., enlargement of trench critical dimension (CD), top corner rounding).

[0003] Accordingly, there is a need for methods and systems that can prevent or delay the oxidation of a portion of a semiconductor device of silicon germanium (SiGe) having a high germanium (Ge) concentration in an air atmosphere. SUMMARY OF THE INVENTION

[0004] Embodiments of the present disclosure provide a method for forming a barrier oxide layer in a semiconductor structure. The method includes forming a contact layer on an exposed surface of a semiconductor region of a semiconductor structure in a first processing chamber, wherein the semiconductor region includes silicon germanium doped with a p-type dopant, and the contact layer includes silicon germanium (SiGe) having a germanium (Ge) ratio in the range between 60% and 100%, and forming a barrier oxide layer containing gallium (Ga) on the contact layer by applying a gallium (Ga)-containing liquid precursor to the surface of the contact layer in the first processing chamber.

[0005] Embodiments of the present disclosure also provide a method for forming an electrical contact in a semiconductor structure. The method includes performing a pre-cleaning process on an exposed surface of a semiconductor region containing a first material, wherein the exposed surface of the semiconductor region is disposed within an opening formed in a dielectric layer disposed on the semiconductor region, performing the pre-cleaning process, and performing a selective epitaxial deposition process including a first deposition process and a first etching process to form a contact layer containing a second material on the exposed surface of the semiconductor region, performing an immersion process to form a barrier oxide layer on the contact layer, performing a second deposition process to form a metal layer on the barrier oxide layer, and performing a metal filling process to form a contact plug in the opening in the dielectric layer, wherein the selective epitaxial deposition process and the immersion process are performed without breaking a vacuum environment.

[0006] Embodiments of the present disclosure further provide a processing system. The processing system includes a first processing chamber and a system controller. The system controller is configured to cause the processing system to form a contact layer on an exposed surface of a semiconductor region of a semiconductor structure in the first processing chamber, wherein the semiconductor region includes silicon germanium doped with a p-type dopant, and the contact layer includes silicon germanium (SiGe) having a germanium (Ge) ratio in the range between 60% and 100%, and to form a barrier oxide layer containing gallium (Ga) on the contact layer in the first processing chamber.

[0007] To enable a more detailed understanding of the features of the present disclosure set forth above, some of which are illustrated in the embodiments shown in the accompanying drawings, a more detailed description of the present disclosure briefly summarized above can be obtained. However, it should be noted that the accompanying drawings only illustrate typical embodiments of the present disclosure, and therefore, the present disclosure may permit other equally effective embodiments, and should not be considered as limiting the scope of the present disclosure.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2A

Figure 2B

Figure 3

Figure 4

Figure 5A - 5E

Modes for Carrying Out the Invention

[0009] For purposes of illustration, like reference numerals are used, where possible, to designate like elements common to the figures. It is contemplated that elements and features of one embodiment can be advantageously incorporated into other embodiments without further recitation.

[0010] The embodiments described herein provide a method and system for forming a contact that includes an epitaxial layer of a silicon-containing material (e.g., boron-doped p-type silicon germanium) having an oxide barrier layer thereon, in a selected portion of a structure used to form a CMOS device (e.g., on an exposed surface of a layer of silicon germanium). The method and system are particularly useful for selectively forming an epitaxial layer containing silicon germanium having a high germanium concentration on an exposed surface of silicon germanium material within an opening or feature (e.g., a contact trench) formed in a dielectric layer, in a semiconductor structure having a region containing silicon germanium and a dielectric layer formed thereon. Unlike conventional processes that require an etching process to remove oxides of germanium on the surface of the epitaxial layer after exposure to an air atmosphere, which tend to damage the fabricated semiconductor structure, the processes described herein are configured to form an oxide barrier layer on the epitaxial layer to avoid or delay oxidation of the epitaxial layer in an air atmosphere during transitions to subsequent processes, such as silicidation, patterning, etc., from the epitaxial process.

[0011] FIG. 1 is a schematic top view of a multi-chamber processing system 100 according to one or more embodiments of the present disclosure. The processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 each having a respective transfer robot 112, 114, hold chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130. As detailed herein, substrates within the processing system 100 can be processed in various chambers and transferred between various chambers without exposing the substrates to the ambient atmosphere environment outside the processing system 100 (e.g., an atmospheric ambient atmosphere environment such as may exist in a manufacturing factory). For example, the substrates can be processed in various chambers maintained in a low pressure (e.g., about 300 Torr or less) or vacuum environment and transferred between such various chambers without breaking the low pressure or vacuum environment during various processes executed on the substrates within the processing system 100. Thus, the processing system 100 can contribute to an integrated solution for some processing of the substrates.

[0012] Examples of processing systems that can be suitably modified in accordance with the teachings provided herein include Endura®, Producer® or Centura® integrated processing systems, or other suitable processing systems commercially available from Applied Materials, Inc. located in Santa Clara, California. Other processing systems (including those from other manufacturers) are contemplated to be adaptable to benefit from the aspects described herein.

[0013] In the illustrated example of FIG. 1, the factory interface 102 includes a docking station 132 and a factory interface robot 134 to facilitate the transfer of substrates. The docking station 132 is adapted to receive one or more front-opening unified pods (FOUPs) 136. In some examples, each factory interface robot 134 generally includes a blade 138 disposed on one end of each factory interface robot 134 adapted to transfer substrates from the factory interface 102 to the load lock chambers 104, 106.

[0014] The load lock chambers 104, 106 have respective ports 140, 142 coupled to the factory interface 102 and respective ports 144, 146 coupled to the transfer chamber 108. The transfer chamber 108 further has respective ports 148, 150 coupled to the holding chambers 116, 118 and respective ports 152, 154 coupled to the processing chambers 120, 122. Similarly, the transfer chamber 110 has respective ports 156, 158 coupled to the holding chambers 116, 118 and respective ports 160, 162, 164, 166 coupled to the processing chambers 124, 126, 128, 130. The ports 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, 166 can be slit valve openings with slit valves, for example, for passing substrates through by transfer robots 112, 114 and for providing seals between respective chambers to prevent gas from passing between the respective chambers. Generally, one of the ports is open to transfer a substrate therethrough. In other cases, the ports are closed.

[0015] Load lock chambers 104, 106, transfer chambers 108, 110, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130 may be fluidly coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system may include one or more gas pumps (e.g., turbo pumps, cryogenic pumps, roughing pumps), a gas source, various valves, and conduits fluidly coupled to the various chambers. During operation, the factory interface robot 134 transfers a substrate from the FOUP 136 through port 140 or 142 to load lock chamber 104 or 106. The gas and pressure control system then pumps down load lock chamber 104 or 106. The gas and pressure control system further maintains transfer chambers 108, 110 and holding chambers 116, 118 in an internal low pressure or vacuum environment (which may include an inert gas). Thus, pumping down load lock chamber 104 or 106 facilitates passing the substrate between, for example, the ambient environment of the factory interface 102 and the low pressure or vacuum environment of transfer chamber 108.

[0016] Using the substrate in the pumped-down load lock chamber 104 or 106, transfer robot 112 transfers the substrate from the load lock chamber 104 or 106 into the transfer chamber 108 through ports 144 or 146. Transfer robot 112 can then transfer the substrate to either of the processing chambers 120, 122 through respective ports 152, 154 for processing and to either of the holding chambers 116, 118 through respective ports 148, 150 for holding while waiting for further transfer and / or between any of them. Similarly, transfer robot 114 can access the substrate in the holding chamber 116 or 118 through port 156 or 158 and transfer the substrate to either of the processing chambers 124, 126, 128, 130 through respective ports 160, 162, 164, 166 for processing and to either of the holding chambers 116, 118 through respective ports 156, 158 for holding while waiting for further transfer and / or between any of them. Transfer and holding of substrates within and between the various chambers can be performed in a low pressure or vacuum environment provided by the gas and pressure control system.

[0017] The processing chambers 120, 122, 124, 126, 128, 130 can be any suitable chambers for processing a substrate. In some examples, the processing chamber 120 can be capable of performing an etching process, the processing chamber 122 can be capable of performing a cleaning process, and the processing chambers 126, 128, 130 can be capable of performing respective epitaxial growth processes. The processing chamber 120 can be a Selectra (trademark) Etch chamber available from Applied Materials of Santa Clara, California. The processing chamber 122 can be a SiCoNi (trademark) Pre-clean chamber available from Applied Materials of Santa Clara, California. The processing chamber 126, 128, or 130 can be a Centura (trademark) Epi chamber available from Applied Materials of Santa Clara, California.

[0018] The system controller 168 is coupled to the processing system 100 to control the processing system 100 or its components. For example, the system controller 168 can control the operation of the processing system 100 using direct control of the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130 of the processing system 100, or by controlling controllers associated with the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130. During operation, the system controller 168 enables data collection and feedback from the respective chambers to adjust the performance of the processing system 100.

[0019] The system controller 168 generally includes a central processing unit (CPU) 170, a memory 172, and support circuitry 174. The CPU 170 can be one of any form of general-purpose processor that can be used in an industrial environment. The memory 172, or non-transitory computer-readable medium, is accessible by the CPU 170 and can be one or more of memories such as random access memory (RAM), read-only memory (ROM), floppy disks, hard disks, or any other form of digital storage, local or remote. The support circuitry 174 is coupled to the CPU 170 and can include a cache, a clock circuit, an input / output subsystem, a power supply, and the like. The various methods disclosed herein can generally be implemented under the control of the CPU 170 by the CPU 170 executing computer instruction codes stored in the memory 172 (or the memory of a particular processing chamber), for example, as software routines. When the computer instruction codes are executed by the CPU 170, the CPU 170 controls the chamber to execute processes according to various methods.

[0020] Other processing systems can have other configurations. For example, more or fewer processing chambers can be coupled to the transfer device. In the illustrated example, the transfer device includes transfer chambers 108, 110 and holding chambers 116, 118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) can be implemented as the transfer device in the processing system.

[0021] FIG. 2A is a cross-sectional view of a processing chamber 200 according to one or more embodiments adapted to perform a pre-cleaning process detailed below. The processing chamber 200 can be the processing chamber 122 shown in FIG. 1. FIG. 2B is an enlarged view of a portion of the processing chamber 200 of FIG. 2A.

[0022] The processing chamber 200 can be particularly useful for performing thermal or plasma-based cleaning processes and / or plasma-assisted dry etching processes. The processing chamber 200 includes a chamber body 202, a lid assembly 204, and a support assembly 206. The lid assembly 204 is disposed at the upper end of the chamber body 202, and the support assembly 206 is at least partially disposed within the chamber body 202. A vacuum system can be used to remove gas from the processing chamber 200. The vacuum system includes a vacuum pump 208 coupled to a vacuum port 210 disposed in the chamber body 202. The processing chamber 200 also includes a controller 212 for controlling the processes within the processing chamber 200.

[0023] The lid assembly 204 includes stacked components adapted to provide precursor gas and / or plasma to a processing region 214 within the processing chamber 200. A first plate 216 is coupled to a second plate 218. A third plate 220 is coupled to the second plate 218. The lid assembly 204 can be connected to a power source (not shown) for supplying plasma to a conical chamber 222 formed within the lid assembly 204. The lid assembly 204 can also be connected to a remote plasma source 224 that generates plasma upstream of the lid stack. A remote plasma cavity (e.g., the processing region 214, the first plate 216, and the second plate 218 in FIGS. 2A-2B) is coupled to a gas source 226 via the remote plasma source 224 (or, in the absence of the remote plasma source 224, the gas source 226 is directly coupled to the lid assembly 204). The gas source 226 can include a gas source adapted to provide helium, argon, or other inert gas. In some configurations, the gas provided by the gas source 226 can be energized to become the plasma provided to the lid assembly 204 by use of the remote plasma source 224. In an alternative embodiment, the gas source 226 can provide a process gas that can be activated by the remote plasma source 224 before being introduced to the surface of a substrate disposed within the processing chamber 200. Referring to FIG. 2B, the conical chamber 222 has an opening 228 that allows the formed plasma to flow from the remote plasma source 224 into a volume 230 formed within a fourth plate 232 of the lid assembly 204.

[0024] In some configurations of the lid assembly 204, plasma is generated within the conical chamber 222 by application of energy supplied from a plasma source. In one example, the energy can be provided by biasing the lid assembly 204 to capacitively couple RF, VHF, and / or UHF energy to a gas located within the conical chamber 222. In this configuration of the lid assembly 204, the remote plasma source 224 may not be used and may not be installed within the lid assembly 204.

[0025] The central conduit 234 formed in the fourth plate 232 is adapted to supply plasma generating species from the volume 230, through the fifth plate 236, into the mixing chamber 238 formed in the sixth plate 240 of the lid assembly 204. The central conduit 234 is connected to the mixing chamber 238 through an opening 242 in the fifth plate 236. The opening 242 may have a diameter smaller than the diameter of the central conduit 234, may have a diameter larger than the diameter of the central conduit 234, or may have the same diameter as the diameter of the central conduit 234. In the embodiment of FIG. 2B, the opening 242 has the same diameter as the central conduit 234.

[0026] The fourth plate 232 also includes inlets 244 and 246 adapted to supply gas to the mixing chamber 238. The inlet 244 is coupled to a first gas source 248, and the inlet 246 is coupled to a second gas source 250. The first gas source 248 and the second gas source 250 may include a process gas and an inert gas, such as an inert gas such as argon and / or helium used as a carrier gas. The first gas source 248 may include ammonia (NH3) as well as argon (Ar). The second gas source 250 may contain a fluorine-containing gas, a hydrogen-containing gas, or a combination thereof. In one example, the second gas source 250 may contain hydrogen fluoride (HF) as well as argon (Ar).

[0027] As shown in FIG. 2B, in some configurations, the inlet 244 is coupled to the mixing chamber 238 through a cylindrical channel 252 (shown in hidden lines) and a hole 254 formed in the fifth plate 236. The inlet 246 is coupled to the mixing chamber 238 through a cylindrical channel 256 (shown in hidden lines) and a hole 258 formed in the fifth plate 236. The holes 254, 258 formed in the fifth plate 236 are generally sized such that they allow a uniform flow of the gases supplied from their respective gas sources 248, 250 into the mixing chamber 238. In one configuration, the hole 258 has a diameter smaller than the width of the opening defined by the sidewall on the opposite side of the cylindrical channel 256 formed in the fourth plate 232. The hole 258 is generally distributed around the centerline of the cylindrical channel 256 to provide a uniform fluid flow in the mixing chamber 238. In one configuration, the hole 254 has a diameter smaller than the width of the opening defined by the sidewall on the opposite side of the cylindrical channel 252 formed in the fourth plate 232. The hole 254 is generally distributed around the centerline of the cylindrical channel 252 to provide a uniform fluid flow in the mixing chamber 238.

[0028] Inlets 244 and 246 provide respective fluid flow paths that pass laterally through the fourth plate 232, turn towards the fifth plate 236, pass through the fifth plate 236, and reach the mixing chamber 238. The lid assembly 204 also includes a seventh plate or a first gas distributor 260, which can be a gas distribution plate such as a showerhead, and the various gases mixed in the lid assembly 204 flow through through-holes 262 formed in the lid assembly 204. The through-holes 262 are in fluid communication with the mixing chamber 238 to provide a flow path through the first gas distributor 260 from the mixing chamber 238. Referring again to FIG. 2A, a blocker plate 264 and a gas distribution plate such as a second gas distributor 266, which can be a gas distribution plate such as a showerhead, are disposed below the lid assembly 204.

[0029] Alternatively, different cleaning processes can be utilized to clean the substrate surface. For example, a remote plasma containing helium (He) and ammonia (NH3) can be introduced into the processing chamber 200 through the lid assembly 204, while ammonia (NH3) can be directly injected into the processing chamber 200 through a separate gas inlet 268 disposed on the side of the chamber body 202 and coupled to a gas source (not shown).

[0030] The support assembly 206 can include a substrate support 270 for supporting the substrate 272 thereon during processing. The substrate support 270 can be coupled to the actuator 274 by a shaft 276 extending through a centrally located opening formed in the bottom of the chamber body 202. The actuator 274 can be flexibly sealed to the chamber body 202 by a bellows (not shown) that prevents vacuum leakage around the shaft 276. The actuator 274 enables the substrate support 270 to move vertically within the chamber body 202 between a processing position and a loading position. The loading position is slightly below the opening of a tunnel (not shown) formed in the sidewall of the chamber body 202.

[0031] The substrate support 270 has a flat or substantially flat substrate support surface for supporting the substrate 272 to be processed thereon. The substrate support 270 can be moved vertically within the chamber body 202 by an actuator 274 coupled to the substrate support 270 by a shaft 276. For some process operations, the substrate support 270 can be raised to a position extremely close to the lid assembly 204 to control the temperature of the substrate 272 being processed. Thus, the substrate 272 can be heated via radiation emitted from the second gas distributor 266 or another radiation source, or by convection or conduction from the second gas distributor 266 through an intervening gas. In some process operations, the substrate can be disposed on the lift pins 278 to perform additional heat treatment steps such as performing an annealing step.

[0032] FIG. 3 is a cross-sectional view of a processing chamber 300 according to one or more embodiments adapted to perform an epitaxial (Epi) deposition process detailed below. The processing chamber 300 can be the processing chamber 126, 128, or 130 shown in FIG. 1.

[0033] The processing chamber 300 includes a housing structure 302 made of a process-resistant material such as aluminum or stainless steel, such as 316L stainless steel. The housing structure 302 surrounds various functional elements of the processing chamber 300, such as a quartz chamber 304 that includes an upper quartz chamber 306 and a lower quartz chamber 308 within which a processing volume 310 is contained. Reactant species are provided to the quartz chamber 304 by a gas distribution assembly 312, and processing by-products are removed from the processing volume 310 by an outlet port 314 that is generally connected to a vacuum source (not shown).

[0034] A substrate support 316 is adapted to receive a substrate 318 transferred to the processing volume 310. The substrate support 316 is disposed along a vertical axis 320 of the processing chamber 300. The substrate support 316 can be made of a ceramic material or a graphite material coated with a silicon material such as silicon carbide or other process-resistant materials. Reactant species from a precursor reactant material are applied to a surface 322 of the substrate 318, and then by-products can be removed from the surface 322 of the substrate 318. Heating of the substrate 318 and / or the processing volume 310 can be performed by radiation sources such as an upper lamp module 324A and a lower lamp module 324B.

[0035] In one embodiment, the upper lamp module 324A and the lower lamp module 324B are infrared (IR) lamps. The non-thermal energy or radiation from the lamp modules 324A and 324B travels through the upper quartz window 326 of the upper quartz chamber 306 and through the lower quartz window 328 of the lower quartz chamber 308. Cooling gas for the upper quartz chamber 306 enters through the inlet 330 and exits through the outlet 332 if necessary. The precursor reactant material, as well as the dilution gas, purge gas, and vent gas for the processing chamber 300, enter through the gas distribution assembly 312 and exit through the outlet port 314. Although the upper quartz window 326 is shown as being curved or convex, the upper quartz window 326 can be flat or concave because the pressures on both sides of the upper quartz window 326 are substantially the same (i.e., atmospheric pressure).

[0036] The low wavelength radiation in the processing volume 310, which is used to energize the reactive species and assist in the adsorption of reactants from the surface 322 of the substrate 318 and the desorption of process by-products, generally ranges from about 0.8 μm to about 1.2 μm, for example, between about 0.95 μm and about 1.05 μm, and various combinations of wavelengths are provided depending on, for example, the composition of the film being epitaxially grown.

[0037] The component gases enter the processing volume 310 through the gas distribution assembly 312. The gas flows from the gas distribution assembly 312 as generally indicated by the flow path 334 and exits through the outlet port 314. The combination of component gases used to clean / passivate the substrate surface or to form silicon and / or germanium-containing films being epitaxially grown is generally mixed before entering the processing volume 310. The overall pressure in the processing volume 310 can be adjusted by a valve (not shown) on the outlet port 314. At least a portion of the inner surface of the processing volume 310 is covered by a liner 336. In one embodiment, the liner 336 includes an opaque quartz material. In this way, the chamber walls are insulated from the heat in the processing volume 310.

[0038] The temperature of the surface in the processing volume 310 can be controlled within a temperature range of about 200°C to about 600°C or higher by the flow of cooling gas that enters through the inlet 330 and exits through the outlet 332, in combination with the radiation from the upper lamp module 324A disposed above the upper quartz window 326. The temperature in the lower quartz chamber 308 can be controlled within a temperature range of about 200°C to about 600°C or higher by adjusting the speed of a blower unit (not shown) and by the radiation from the lower lamp module 324B disposed below the lower quartz chamber 308. The pressure in the processing volume 310 can be between about 0.1 torr and about 600 torr, such as between about 5 torr and about 30 torr.

[0039] The temperature on the surface 322 of the substrate 318 can be controlled by adjusting the power to the lower lamp module 324B in the lower quartz chamber 308, or by adjusting the power to both the upper lamp module 324A above the upper quartz window 326 and the lower lamp module 324B in the lower quartz chamber 308. The power density in the processing volume 310 can be between about 40 W / cm 2 ~ about 120 W / cm 2 such as between about 40 W / cm 2 and about 400 W / cm 2 and can be between.

[0040] In one aspect, the gas distribution assembly 312 is disposed perpendicular to the longitudinal axis 320 of the processing chamber 300 or the substrate 318, or in the radial direction 338 with respect to the longitudinal axis 320 of the processing chamber 300 or the substrate 318. In this orientation, the gas distribution assembly 312 is adapted to flow the process gas in the radial direction 338 across the surface 322 of the substrate 318 or parallel to the surface 322 of the substrate 318. In one processing application, the process gas is preheated at the time of introduction into the processing chamber 300 to initiate preheating of the gas prior to introduction into the processing volume 310 and / or to break certain bonds in the gas. In this way, the surface reaction kinetics can be modified independently of the thermal temperature of the substrate 318.

[0041] During operation, precursors used to form silicon (Si) and silicon germanium (SiGe) blankets or selective epitaxial films are provided from one or more gas sources 340A and 340B to a gas distribution assembly 312. (Only one is shown in FIG. 3) An IR lamp 342 can be utilized to heat the precursors within the gas distribution assembly 312 and along a flow path 334. The gas sources 340A, 340B can be coupled to the gas distribution assembly 312 in a manner adapted to facilitate an introduction zone within the gas distribution assembly 312, such as a radially outer zone and a radially inner zone between outer zones when viewed in a plan view. The gas sources 340A, 340B can include valves (not shown) for controlling the rate of introduction into the zones.

[0042] The gas sources 340A, 340B can include silicon precursors such as silanes, including silane (SiH4), disilane (Si2H6), dichlorosilane (SiH2Cl2), hexachlorodisilane (Si2Cl6), dibromosilane (SiH2Br2), higher order silanes, their derivatives, and combinations thereof. The gas sources 340A, 340B can also include germanium-containing precursors such as germane (GeH4), digermane (Ge2H6), germanium tetrachloride (GeCl4), dichlorogermane (GeH2Cl2), their derivatives, and combinations thereof. The silicon and / or germanium-containing precursors can be used in combination with hydrogen chloride (HCl), chlorine gas (Cl2), hydrogen bromide (HBr), and combinations thereof. The gas sources 340A, 340B can include one or more of the silicon and germanium-containing precursors in one or both of the gas sources 340A, 340B.

[0043] The precursor material, in one embodiment, is a quartz material having holes 344 formed therethrough, and enters the processing volume 310 through an opening or hole 344 (only one is shown in FIG. 3) in the perforated plate 346 in this excited state. The perforated plate 346 can be manufactured from a transparent quartz material that transmits IR energy. In other embodiments, the perforated plate 346 can be any material that transmits IR energy and is resistant to process chemistry and other processing chemistries. The energized precursor material flows through the holes 344 in the perforated plate 346 and through a channel 348 (only one is shown in FIG. 3) toward the processing volume 310. Also, a portion of the photons and non-thermal energy from the IR lamp 342 passes through the holes 344, the perforated plate 346, and the channel 348, facilitated by a reflective material and / or surface disposed on the inner surface of the gas distribution assembly 312, thereby illuminating the flow path 334 of the precursor material. In this way, the vibrational energy of the precursor material can be maintained from the point of introduction into the processing volume 310 along the flow path.

[0044] FIG. 4 shows a process flow diagram of a method 400 for forming a contact layer in a semiconductor structure 500 formed on a substrate, according to one embodiment of the present disclosure. FIGS. 5A, 5B, 5C, 5D, and 5E are cross-sectional views of a portion of the semiconductor structure 500 corresponding to various states of the method 400. It should be understood that FIGS. 5A, 5B, 5C, 5D, and 5E only show schematic partial views of the semiconductor structure 500, and the semiconductor structure 500 may include any number of transistor sections and additional materials having the aspects shown in the figures. Also, although the method shown in FIG. 4 is described sequentially, it should be noted that other process sequences including one or more operations that are omitted and / or added and / or rearranged in another desirable order fall within the scope of the embodiments of the present disclosure provided herein.

[0045] As used herein, the term "substrate" refers to a layer of material that serves as a basis for subsequent processing operations and includes a surface to be cleaned. The substrate can be a silicon-based material or any suitable insulating or conductive material, as needed. The substrate can include materials such as crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, strained silicon (developed by IBM), silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire.

[0046] As shown in FIG. 5A, the semiconductor structure 500 includes a semiconductor region 502 formed on a substrate (not shown). The semiconductor region 502 is formed from a first material such as silicon germanium (SiGe) or germanium tin (GeSn) and can be doped with a p-type dopant such as boron (B) or gallium (Ga) having a concentration between about 10 20 cm -3 and 5×10 21 cm -3 and.

[0047] The semiconductor structure 500 further includes a dielectric layer 504 having an opening 506 formed on the semiconductor region 502. The dielectric layer 504 can be formed from a dielectric material such as silicon dioxide (SiO2) or silicon nitride (Si3N4).

[0048] The semiconductor region 502 can be formed using any suitable deposition technique such as epitaxial (Epi) deposition, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), and the opening 506 can be formed by a patterning technique such as a lithography and etching process.

[0049] Method 400 begins with a pre-cleaning process at block 410. The pre-cleaning process may be performed in an etching chamber, such as the processing chamber 122 shown in FIG. 1 or the processing chamber 200 shown in FIG. 2.

[0050] The pre-cleaning process removes contaminants, such as a native oxide layer formed on the exposed surface of the semiconductor region 502 within the aperture 506 or patterning residues (e.g., fluorocarbons). The pre-cleaning process is used to prepare the exposed surface of the semiconductor region 502 within the aperture 506 such that an epitaxial layer may be formed on such an exposed surface during a subsequent epitaxial deposition process.

[0051] The pre-cleaning process may include an anisotropic remote plasma-assisted dry etching process, such as a reactive ion etching (RIE) process using a plasma formed from a gas including argon (Ar), helium (He), or a combination thereof. The plasma emissions impinge in one direction on the residual dielectric layer within the aperture 506 to remove the residual dielectric layer.

[0052] The pre-cleaning process may include an isotropic plasma etching process, such as a SiCoNi (trademark) dry chemical etching process, using a plasma formed from a gas containing ammonia (NH3), nitrogen trifluoride (NF3), hydrogen fluoride (HF), or a combination thereof, and a carrier gas such as nitrogen (N2), hydrogen (H2), or a combination thereof. The dry chemical etching process is selective for oxide layers and thus does not readily etch silicon, germanium, or nitride layers, whether those layers are amorphous, crystalline, or polycrystalline. The selectivity of the dry chemical etching process for oxide to silicon or germanium is at least about 3:1, typically 5:1 or greater, and may be 10:1. The dry chemical etching process is also highly selective for oxide to nitride. The selectivity of the dry chemical etching process for nitride is at least about 3:1, typically 5:1 or greater, and may be 10:1.

[0053] The pre-cleaning process may include an inductively coupled plasma (ICP) etching process using a plasma formed from a gas containing chlorine (Cl2) and hydrogen (H2) and a carrier gas containing argon (Ar) and helium (He).

[0054] In block 420, as shown in FIG. 5B, a selective epitaxial deposition process is performed to epitaxially form a contact layer 508 on the exposed surface of the semiconductor region 502 within the opening 506. The selective epitaxial deposition process may be performed in an epi chamber, such as the processing chambers 126, 128, or 130 shown in FIG. 1, or the processing chamber 300 shown in FIG. 3.

[0055] The contact layer 508 is formed as an interface between the semiconductor region 502 and a metal contact plug to be formed within the opening 506 to minimize parasitic resistance. The contact layer 508 can be formed from a second material such as silicon germanium (SiGe) having a germanium (Ge) ratio in the range between about 20% and about 100%, for example, between about 60% and about 80%, between about 60% and about 100%, or between about 80% and about 100%. The contact layer 508 can be doped with a p-type dopant such as boron (B) or gallium (Ga) having a concentration between about 10 20 cm -3 and 5×10 21 cm -3 .

[0056] In some embodiments, the selective epitaxial deposition process includes a first deposition process and a first etching process. The first deposition process is an epitaxial deposition process. The selectivity in the selective epitaxial deposition process can result from the difference in nucleation of a second material on the exposed surface of the semiconductor region 502 (e.g., silicon germanium (SiGe)) and nucleation on the exposed surface of the dielectric layer 504 (e.g., silicon dioxide (SiO2) or silicon nitride (Si3N4)). Nucleation can occur at a faster rate of change on the exposed surface of the semiconductor region 502 (e.g., silicon germanium (SiGe)) than on the exposed surface of the dielectric layer 504 (e.g., silicon dioxide (SiO2) or silicon nitride (Si3N4)), and thus, an epitaxial layer of the second material can be formed on the exposed surface of the semiconductor region 502 (e.g., silicon germanium (SiGe)), while an amorphous layer of the second material can be formed on the exposed surface of the dielectric layer 504 when the semiconductor structure 500 is exposed to the deposition gas during the first deposition process. In a subsequent first etching process, the amorphous layer of the second material formed on the exposed surface of the dielectric layer 504 can be removed at a faster rate of change by a suitable etching gas than the epitaxial layer of the second material formed on the exposed surface of the semiconductor region 502. Thus, as an overall result of combining the first deposition process and the first etching process, if any, epitaxial growth of the second material on the exposed surface of the semiconductor region 502 is enabled while minimizing growth of the second material on the exposed surface of the dielectric layer 504.

[0057] In some embodiments, the deposition gas includes a silicon-containing precursor, a germanium-containing precursor, and a dopant source. The silicon-containing precursor is silane (SiH4), disilane (Si2H6), tetrasilane (Si4H 10) or combinations thereof. The germanium-containing precursor may include germane (GeH4), germanium tetrachloride (GeCl4), and digermane (Ge2H6). The dopant source may include boron or gallium, for example, depending on the desired conductive properties of the contact layer 508. The dopant source may include the precursor diborane (B2H6). The etching gas includes an etchant gas and a carrier gas. The etchant gas may include a halogen-containing gas such as hydrogen chloride (HCl), chlorine (Cl2), or hydrogen fluoride (HF). The carrier gas may include nitrogen (N2), argon (Ar), helium (He), or hydrogen (H2).

[0058] The first deposition process and the first etching process may be performed at a low temperature of less than about 450 °C and at a pressure between 5 Torr and 600 Torr.

[0059] The cycle of the first deposition and the first etching process may be repeated as necessary to obtain the desired thickness of the contact layer 508. The thickness of the contact layer 508 may be between about 30 Å and about 100 Å.

[0060] In block 430, as shown in FIG. 5C, a CVD immersion process is performed to form an oxide barrier layer 510 on the contact layer 508. The CVD immersion process may be performed in situ (in place) in the same epi chamber as in the selective epitaxial deposition process in block 420, such as the processing chambers 126, 128, or 130 shown in FIG. 1 or the processing chamber 300 shown in FIG. 3.

[0061] In a CVD dipping process, to form a thin gallium layer (e.g., the barrier oxide layer 510) on the contact layer 508, the surface of the contact layer 508 is exposed to a gallium (Ga)-containing liquid precursor at a temperature in the range of about 300 °C to about 400 °C. The processing chamber or the semiconductor structure 500 can be heated to a temperature in the range of about 300 °C to about 400 °C. The CVD dipping process can last for a time period of about 1 second to about 60 seconds, for example, about 2 seconds to about 30 seconds. In the CVD dipping process, gallium atoms in the gallium-containing liquid precursor diffuse and deposit on the surface of the contact layer 508 to form a thin gallium layer. This thin gallium layer acts as the barrier oxide layer 510 and can avoid or delay the oxidation of the contact layer 508 during the air break for transferring the semiconductor structure 500 from the epi chamber to another processing chamber, such as during the deposition process in block 440 or the patterning process.

[0062] In block 440, as shown in FIG. 5D, a second deposition process is performed. The second deposition process can be performed in a processing chamber different from the epi chambers in blocks 420 and 430, such as the processing chamber 126, 128, or 130 shown in FIG. 1, or the processing chamber 300 shown in FIG. 3. The semiconductor structure 500 can be exposed to the atmosphere during the transfer from the epi chamber used in blocks 420 and 430 to the processing chamber used in block 440. However, the barrier oxide layer 510 on the contact layer 508 can protect the contact layer 508 from oxidation during the transfer or delay the oxidation of the contact layer 508.

[0063] In the second deposition process, a metal layer 512 is formed over the barrier oxide layer 510. The metal layer 512 contacts the contact layer 508 while maintaining an electrical connection therethrough, providing an electrical connection between the contact plug to be formed within the opening 506 and the semiconductor region 502. The metal layer 512 can be formed from a metal material such as titanium (Ti), cobalt (Co), nickel (Ni), molybdenum (Mo), or tantalum (Ta), or silicides thereof.

[0064] In some embodiments, the metal source can include a precursor that includes titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), or molybdenum (Mo), or combinations thereof. The second deposition process can be performed at a temperature between about 300 °C and about 800 °C, and at a pressure between 1 torr and 50 torr, respectively.

[0065] The second deposition process performed at block 440 can include any suitable deposition process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. at a temperature between about 100 °C and about 300 °C.

[0066] At block 450, as shown in FIG. 5E, a metal fill process is performed to form a contact plug 514 within the opening 506. The contact plug 514 can be formed from a contact plug metal material such as tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo). The contact plug 514 can include a metal having a desired work function. The metal fill process at block 450 can include a chemical vapor deposition (CVD) process using a tungsten-containing precursor such as WF6, or a cobalt-containing precursor, within a processing chamber such as the processing chambers 126, 128, or 130 shown in FIG. 1.

[0067] After the metal fill process, the semiconductor structure 500 can be planarized by use of a chemical mechanical planarization (CMP) process.

[0068] The embodiments described in this specification provide a method and system for forming a contact epitaxial layer having an oxide barrier layer thereon within a trench on a semiconductor device. The contact trench structure includes a metal contact plug formed within the trench and a contact that interfaces between the contact plug and a silicon-based channel in the semiconductor device. The contact is formed from silicon germanium having a high germanium concentration by a selective epitaxial deposition process, thereby reducing parasitic resistance. The oxide barrier layer is formed from gallium (Ga) by a CVD dipping process. The method and system do not require an etching process to remove the oxide of germanium (Ge), and thus reduce damage to the manufactured semiconductor structure.

[0069] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof, and the scope of the present disclosure is determined by the following claims.

Claims

1. A method for forming an oxidation barrier layer in a semiconductor structure, comprising: forming a contact layer on an exposed surface of a semiconductor region of a semiconductor structure in a first processing chamber, wherein the semiconductor region comprises silicon germanium doped with a p-type dopant, and the contact layer comprises silicon germanium (SiGe) having a germanium (Ge) ratio in the range between 60% and 100%; forming an oxidation barrier layer containing gallium (Ga) on the contact layer by applying a gallium (Ga)-containing liquid precursor to the surface of the contact layer in the first processing chamber; and a method.

2. The forming of the contact layer comprises: The method according to claim 1, comprising selective epitaxial deposition of silicon germanium (SiGe) on the exposed surface of the semiconductor region.

3. The method according to claim 1, wherein the applying of the gallium (Ga)-containing liquid precursor is performed at a temperature in the range of 300 °C to 400 °C.

4. Before forming the contact layer, performing a pre-cleaning process on the exposed surface of the semiconductor region in a second processing chamber, wherein the exposed surface of the semiconductor region is disposed within an opening formed in a dielectric layer disposed on the semiconductor region; after forming the oxidation barrier layer, performing a deposition process in a third processing chamber to form a metal layer on the oxidation barrier layer; and the method according to claim 1.

5. further comprising performing a metal filling process to form a contact plug in the opening in the dielectric layer; and the method according to claim 4.

6. The method according to claim 5, wherein the metal layer comprises a material selected from silicides of titanium (Ti), cobalt (Co), nickel (Ni), molybdenum (Mo), and tantalum (Ta).

7. The method according to claim 5, wherein the contact plug comprises a material selected from tungsten (W), cobalt (Co), ruthenium (Ru), and molybdenum (Mo).

8. A method for forming an electrical contact in a semiconductor structure, comprising: Performing a pre-cleaning process on the exposed surface of a semiconductor region containing a first material, wherein the exposed surface of the semiconductor region is disposed within an opening formed in a dielectric layer disposed over the semiconductor region, and performing the pre-cleaning process; Performing a selective epitaxial deposition process including a first deposition process and a first etching process to form a contact layer containing a second material on the exposed surface of the semiconductor region; Performing an immersion process to form an oxide barrier layer over the contact layer; Performing a second deposition process to form a metal layer over the oxide barrier layer; Performing a metal filling process to form a contact plug within the opening in the dielectric layer; comprising; A method, wherein the selective epitaxial deposition process and the immersion process are performed without breaking a vacuum environment.

9. The method according to claim 8, wherein the first material comprises silicon germanium doped with a p-type dopant.

10. The method according to claim 8, wherein the second material comprises silicon germanium (SiGe) having a germanium (Ge) ratio in the range between 60% and 100%.

11. The first deposition process includes epitaxial deposition of the second material on the exposed surface of the semiconductor region, The first etching process includes an etching process for removing an amorphous layer of the second material formed on the exposed surface of the dielectric layer, The method according to claim 8.

12. The immersion process includes applying a gallium (Ga)-containing liquid precursor to the surface of the contact layer at a temperature within the range of 300 °C to 400 °C, The oxide barrier layer contains gallium (Ga), The method according to claim 8.

13. The method according to claim 8, wherein the metal layer comprises a material selected from titanium (Ti) silicide, cobalt (Co) silicide, nickel (Ni) silicide, molybdenum (Mo) silicide, and tantalum (Ta) silicide.

14. The method according to claim 8, wherein the contact plug comprises a material selected from tungsten (W), cobalt (Co), ruthenium (Ru), and molybdenum (Mo).

15. A first processing chamber, A system controller A processing system comprising, wherein the system controller Forming a contact layer on the exposed surface of the semiconductor region of the semiconductor structure in the first processing chamber, wherein the semiconductor region comprises silicon germanium doped with a p-type dopant, and the contact layer comprises silicon germanium (SiGe) having a germanium (Ge) ratio in the range between 60% and 100%, forming a contact layer; Forming a barrier oxide layer containing gallium (Ga) on the contact layer in the first processing chamber A processing system configured to cause the processing system to perform.

16. The processing system according to claim 15, wherein the application of the gallium (Ga)-containing liquid precursor is performed at a temperature within the range of 300 °C to 400 °C.

17. A second processing chamber, A third processing chamber Further comprising, wherein the system controller Before forming the contact layer, performing a pre-cleaning process on the exposed surface of the semiconductor region in the second processing chamber, wherein the exposed surface of the semiconductor region is disposed within an opening formed in a dielectric layer disposed on the semiconductor region, performing a pre-cleaning process; After forming the barrier oxide layer, performing a deposition process in the third processing chamber to form a metal layer on the barrier oxide layer The processing system according to claim 15, further configured to cause the processing system to perform.

18. A fourth processing chamber Further comprising Wherein the system controller Performing a metal filling process to form a contact plug in the opening in the dielectric layer The processing system according to claim 15, further configured to cause the processing system to perform.

19. The processing system according to claim 18, wherein the metal layer comprises a material selected from titanium (Ti) silicide, cobalt (Co) silicide, nickel (Ni) silicide, molybdenum (Mo) silicide, and tantalum (Ta) silicide.

20. The processing system according to claim 18, wherein the contact plug comprises a material selected from tungsten (W), cobalt (Co), ruthenium (Ru), and molybdenum (Mo).

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