Semiconductor element manufacturing method

Abstract

According to an embodiment, a method for manufacturing a semiconductor device may include stacking a plurality of insulating layers and a plurality of sacrificial layers on a substrate, forming an opening through the insulating layers and the sacrificial layers, removing the sacrificial layers to form a trench, stacking a barrier layer in the trench, stacking a first electrode layer on the barrier layer, stacking a dielectric layer on the first electrode layer, performing a heat treatment on the dielectric layer, and stacking a second electrode layer on the dielectric layer.

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] Electronic systems requiring data storage are in need of semiconductor device devices capable of storing high volumes of data. To increase data storage capacity while meeting consumer demands for superior performance and low prices, there is a need to increase the integration density of semiconductor device devices. In the case of two-dimensional (or planar) semiconductor device devices, the integration density is primarily determined by the area occupied by a unit memory cell, and is therefore greatly influenced by the level of technology for forming fine patterns. However, because pattern miniaturization requires extremely expensive equipment, the integration density of two-dimensional semiconductor device devices, although increasing, remains limited. Accordingly, three-dimensional semiconductor device memory devices having memory cells arranged in three dimensions have been proposed. Summary of the Invention [Problem to be solved by the invention]

[0003] SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for manufacturing semiconductor devices with improved stability and electrical characteristics.

[0004] Another object of the present invention is to provide a method for manufacturing a semiconductor device that can reduce the magnitude of leakage current.

[0005] The objects of the present specification are not limited to those mentioned above, and other objects and advantages of the present specification not mentioned above can be more clearly understood from the examples of the present specification described below. In addition, the objects and advantages of the present specification can be realized by the elements and combinations thereof described in the claims. [Means for solving the problem]

[0006] According to one embodiment, a method for manufacturing a semiconductor device may include stacking a plurality of insulating layers and a plurality of sacrificial layers on a substrate, forming an opening penetrating the plurality of insulating layers and the plurality of sacrificial layers, removing the sacrificial layers to form a trench, stacking a barrier layer inside the trench, stacking a first electrode layer on the barrier layer, stacking a dielectric layer on the first electrode layer, performing a heat treatment on the dielectric layer, and stacking a second electrode layer on the dielectric layer.

[0007] In one embodiment, the heat treatment may include a first heat treatment performed in a hydrogen atmosphere.

[0008] In one embodiment, the heat treatment may include a first heat treatment performed in a hydrogen atmosphere and a second heat treatment performed in an oxygen atmosphere.

[0009] In one embodiment, the heat treatment can be performed at a temperature of 200°C to 1000°C.

[0010] In one embodiment, the pressure of the gas supplied when the heat treatment is performed may be 2 atmospheres to 50 atmospheres.

[0011] In one embodiment, the insulating layer may include silicon (Si) and the sacrificial layer may include silicon germanium (SiGe).

[0012] In one embodiment, the dielectric layer may include at least one of hafnium oxide (HfO2), zirconium oxide (ZrO2), vanadium oxide (VO2), titanium oxide (TiO2), tin oxide (SnO2), aluminum oxide (Al2O3), zinc oxide (ZnO), hafnium silicate (HfSiO), zirconium silicate (ZrSiO), or niobium pentoxide (Nb2O5). [Effects of the Invention]

[0013] According to the embodiment, defects or impurities in the dielectric layer can be removed by the heat treatment performed under a hydrogen atmosphere, thereby improving the performance and reliability of the semiconductor device and reducing leakage current of the semiconductor device. [Brief explanation of the drawings]

[0014] [Figure 1] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to an embodiment. [Figure 2] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to an embodiment. [Figure 3] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to an embodiment. [Figure 4] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to an embodiment. [Figure 5] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to an embodiment. [Figure 6] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to an embodiment. [Figure 7] 10 is a graph comparing leakage current of a conventional semiconductor device with leakage current of a semiconductor device manufactured by a method for manufacturing a semiconductor device according to an embodiment; [Figure 8] 10 is a graph comparing the thin film density of a dielectric layer of a conventional semiconductor device with the thin film density of a dielectric layer of a semiconductor device manufactured by a method for manufacturing a semiconductor device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0015] The above-mentioned objects, features, and advantages will be described in detail below with reference to the accompanying drawings, so that those skilled in the art can easily implement the embodiments of the present specification. In describing the present specification, if a detailed description of known technologies related to the present specification is deemed to obscure the gist of the present specification, the detailed description will be omitted. Hereinafter, preferred embodiments of the present specification will be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings indicate the same or similar components.

[0016] 1 to 6 show a manufacturing process of a semiconductor device according to one embodiment.

[0017] Referring to FIG. 1 , a plurality of insulating layers 12 and a plurality of sacrificial layers 14 may be alternately and repeatedly stacked on a substrate 10. The plurality of insulating layers 12 and the plurality of sacrificial layers 14 may be epitaxially grown. In one embodiment, the substrate 10 may be made of a single crystal silicon wafer. Each of the insulating layers 12 may include silicon (Si). Each of the sacrificial layers 14 may include silicon germanium (SiGe). Each of the sacrificial layers 14 may have a substantially equal thickness, and each of the insulating layers 12 may have a thickness that varies in some regions.

[0018] When the sacrificial layer 14 is made of silicon germanium (SiGe), the proportion of germanium (Ge) in the sacrificial layer 14 may be higher than the proportion of silicon (Si). If the proportion of germanium (Ge) in the sacrificial layer 14 is higher than the proportion of silicon (Si), the etching selectivity with respect to the insulating layer 12 can be increased in the manufacturing process described below. However, the components and component ratios of the sacrificial layer 14 are not limited to those in the above-described embodiment, and the components and component ratios of the sacrificial layer 14 can be changed as necessary.

[0019] 2, an opening 16 may be formed vertically through the sacrificial layer 14 and the insulating layer 12. For example, the sacrificial layer 14 and the insulating layer 12 may be etched by patterning to form the opening 16. The opening 16 may expose the sidewalls of the sacrificial layer 14 and the insulating layer 12. The opening 16 may be used to remove the sacrificial layer 14 in a subsequent process.

[0020] Next, referring to FIG. 3, the sacrificial layer 14 can be removed using an etching selectivity between the sacrificial layer 14 and the insulating layer 12. By removing the sacrificial layer 14, a plurality of trenches 18 are formed. The sacrificial layer 14 may be made of, for example, silicon germanium (SiGe). In this case, if the specific gravity of germanium (Ge) constituting the sacrificial layer 14 is higher than that of silicon (Si), the etching selectivity with respect to silicon (Si) contained in the insulating layer 12 may be high. Therefore, the sacrificial layer 14 can be removed by wet etching using, for example, hydrochloric acid (HCl).

[0021] Referring now to FIG. 4 , a barrier layer 20, a first electrode layer 21, and a dielectric layer 22 may be sequentially stacked inside each trench 18. The barrier layer 20 may include a metal material (e.g., Ti, TiN, or Co). The first electrode layer 21 may also include a metal material. For example, the first electrode layer 21 may include a conductive layer such as a metal nitride, a metal oxide, a metal silicide, conductive carbon, polysilicon, or a combination thereof. In another example, the first electrode layer 21 may include TiN, Al, W, or Ru. However, the type of metal material included in the first electrode layer 21 is not limited to the above-mentioned materials.

[0022] The dielectric layer 22 may comprise a high dielectric constant material (high-k). The dielectric layer 22 may be deposited by an atomic layer deposition (ALD) process.

[0023] In one embodiment, the high-dielectric-constant material included in the dielectric layer 22 may include at least one of hafnium oxide (HfO), zirconium oxide (ZrO), vanadium oxide (VO), titanium oxide (TiO), tin oxide (SnO), aluminum oxide (AlO), zinc oxide (ZnO), hafnium silicate (HfSiO), zirconium silicate (ZrSiO), or niobium pentoxide (NbO). However, the type of high-dielectric-constant material is not limited to the above embodiment.

[0024] As shown in FIG. 4, after the dielectric layer 22 is formed, a first heat treatment may be performed on the dielectric layer 22. In one embodiment, the first heat treatment on the dielectric layer 22 may be performed in a gas atmosphere containing a hydrogen component. For example, the first heat treatment on the dielectric layer 22 may be performed in an H2 or D2 atmosphere. In one embodiment, the pressure of the gas containing a hydrogen component supplied when the first heat treatment on the dielectric layer 22 is performed may be 2 atmospheres to 50 atmospheres. In one embodiment, the first heat treatment on the dielectric layer 22 may be performed at a temperature of 200°C to 1000°C.

[0025] In another embodiment, the first heat treatment on the dielectric layer 22 may be performed in a gas atmosphere containing a nitrogen component. For example, the first heat treatment on the dielectric layer 22 may be performed in an N2 atmosphere. In one embodiment, the gas containing a nitrogen component supplied when the first heat treatment on the dielectric layer 22 is performed may be at a pressure of 2 atmospheres to 50 atmospheres. In one embodiment, the first heat treatment on the dielectric layer 22 may be performed at a temperature of 200°C to 1000°C.

[0026] As semiconductor devices are scaled down, the thickness of the dielectric layer 22 becomes thinner than the limit, which can increase leakage current. Leakage current occurs due to defects or impurities present in the dielectric layer 22. In particular, the number of defects in the structure of the dielectric layer 22 made of a high-k material is about 100 times greater than the number of defects in the structure of other insulating films (e.g., SiO2), increasing the likelihood of leakage current. However, the above-mentioned first heat treatment can remove the defects or impurities in the dielectric layer 22. This improves the film quality of the dielectric layer 22 and can reduce leakage current.

[0027] In another embodiment, after the first heat treatment on the dielectric layer 22, a second heat treatment on the dielectric layer 22 may be further performed. In another embodiment, the second heat treatment on the dielectric layer 22 may be performed in a gas atmosphere containing an oxygen component. For example, the second heat treatment on the dielectric layer 22 may be performed in an O2, O3, or H2O atmosphere. In one embodiment, the pressure of the gas containing an oxygen component supplied when the second heat treatment on the dielectric layer 22 is performed may be 2 atmospheres to 50 atmospheres. In one embodiment, the second heat treatment on the dielectric layer 22 may be performed at a temperature of 200°C to 1000°C. The second heat treatment on the dielectric layer 22 may further improve the film quality of the dielectric layer 22 and further reduce leakage current.

[0028] In some embodiments, dielectric layer 22 may undergo only a first heat treatment.

[0029] 5, a second electrode layer 23 may be formed on the dielectric layer 22. The second electrode layer 23 may include a metal material. For example, the second electrode layer 23 may include a conductive layer such as a metal nitride, a metal oxide, a metal silicide, conductive carbon, polysilicon, or a combination thereof. In other examples, the second electrode layer 23 may include TiN, Al, W, or Ru. However, the type of metal material included in the second electrode layer 23 is not limited to the above-mentioned materials.

[0030] 6, a cell structure 30 may be formed inside the opening 16. In one embodiment, the cell structure 30 may include at least one component (e.g., a transistor) electrically coupled to the first electrode layer 21 or the second electrode layer 23, or at least a portion of a conductive line (e.g., a word line or a bit line) electrically coupling at least one component electrically coupled to the first electrode layer 21 or the second electrode layer 23.

[0031] FIG. 7 is a graph comparing leakage current of a conventional semiconductor device with leakage current of a semiconductor device manufactured by a method for manufacturing a semiconductor device according to an embodiment.

[0032] "No anneal" in Figure 7 indicates the leakage current value of a conventional semiconductor device in which no heat treatment was performed on the dielectric layer. Also, "HPA" in Figure 7 indicates the leakage current value of a semiconductor device in which a first heat treatment was performed on the dielectric layer according to one embodiment. Also, "HPA+HPO" in Figure 7 indicates the leakage current value of a semiconductor device in which a first heat treatment and a second heat treatment were sequentially performed on the dielectric layer according to another embodiment. For reference, the first and second heat treatments were each performed at 500°C / 20 atmospheres for 1 hour, with the first heat treatment being performed in a hydrogen atmosphere and the second heat treatment being performed in an oxygen atmosphere.

[0033] As shown in Figure 7, when the leakage current value of a semiconductor device that has not undergone a heat treatment on its dielectric layer is 1, the leakage current value of a semiconductor device that has undergone a first heat treatment on its dielectric layer according to one embodiment is 0.87. Also, the leakage current value of a semiconductor device that has undergone a first and second heat treatment on its dielectric layer sequentially according to another embodiment is 0.79. Experimental results show that the leakage current of a semiconductor device is reduced by removing defects or impurities in the dielectric layer through the first heat treatment or the first and second heat treatments. In particular, when the second heat treatment is performed in an oxygen atmosphere, the leakage current is further reduced by about 10% compared to when only the first heat treatment is performed.

[0034] FIG. 8 is a graph comparing the thin film density of the dielectric layer of a conventional semiconductor device with the thin film density of the dielectric layer of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to an embodiment.

[0035] "No anneal" in Figure 8 indicates the thin film density of the dielectric layer of a conventional semiconductor device in which no heat treatment is performed on the dielectric layer. Also, "HPA" in Figure 8 indicates the thin film density of the dielectric layer of a semiconductor device in which a first heat treatment is performed on the dielectric layer according to one embodiment. Also, "HPA+HPO" in Figure 8 indicates the thin film density of the dielectric layer of a semiconductor device in which a first heat treatment and a second heat treatment are performed sequentially on the dielectric layer according to another embodiment. For reference, the first and second heat treatments are each performed at 500°C / 20 atmospheres for 1 hour, with the first heat treatment being performed in a hydrogen atmosphere and the second heat treatment being performed in an oxygen atmosphere.

[0036] As shown in Figure 8, when the film density of a typical semiconductor device in which the dielectric layer is not subjected to a heat treatment is 1, the film density of the dielectric layer of a semiconductor device in which the first heat treatment is performed according to one embodiment is 1.05. Furthermore, the film density of a semiconductor device in which the dielectric layer is subjected to a first and second heat treatment in sequence according to another embodiment is 1.21. Experimental results show that the first heat treatment or the first and second heat treatments remove defects or impurities in the dielectric layer, thereby improving the film quality of the dielectric layer. In particular, when the second heat treatment is performed in an oxygen atmosphere, the film density increases by about 20% compared to when only the first heat treatment is performed.

[0037] According to the above-described embodiment, defects or impurities in the dielectric layer can be removed by performing a first heat treatment on the dielectric layer in a hydrogen atmosphere, or by performing a first heat treatment on the dielectric layer in a hydrogen atmosphere and then performing a second heat treatment on the dielectric layer in an oxygen atmosphere. This improves the film quality of the dielectric layer and reduces leakage current. As a result, the stability and electrical characteristics of the semiconductor device can be improved. An example of a semiconductor device according to one embodiment is a dynamic random access memory (DRAM).

[0038] As described above, the present specification has been described with reference to exemplary drawings, but the present specification is not limited to the embodiments and drawings disclosed in the present specification, and various modifications may be made by those skilled in the art. Note that even if the effects of the configurations of the present specification are not explicitly described in the above-described embodiments of the present specification, the effects that can be predicted by the configurations should also be recognized.

Claims

1. depositing a plurality of insulating layers and a plurality of sacrificial layers on a substrate; forming openings through the insulating layers and the sacrificial layers; removing the sacrificial layer to form a trench; depositing a barrier layer within the trench; depositing a first electrode layer on the barrier layer; depositing a dielectric layer on the first electrode layer; performing a heat treatment on the dielectric layer; depositing a second electrode layer on the dielectric layer; Including, A method for manufacturing semiconductor devices.

2. The heat treatment is A first heat treatment is carried out in a hydrogen atmosphere. The method for manufacturing a semiconductor device according to claim 1 .

3. The heat treatment is A first heat treatment is performed in a hydrogen atmosphere, and a second heat treatment is performed in an oxygen atmosphere. The method for manufacturing a semiconductor device according to claim 1 .

4. The heat treatment is carried out at a temperature of 200°C to 1000°C, The method for manufacturing a semiconductor device according to claim 1 .

5. The pressure of the gas supplied during the heat treatment is 2 to 50 atmospheres. The method for manufacturing a semiconductor device according to claim 1 .

6. the insulating layer includes silicon (Si), the sacrificial layer comprises silicon germanium (SiGe); The method for manufacturing a semiconductor device according to claim 1 .

7. The dielectric layer is Hafnium oxide (HfO ２ ), zirconium oxide (ZrO ２ ), vanadium oxide (VO ２ ), titanium oxide (TiO ２ ), tin oxide (SnO ２ ), aluminum oxide (Al ２ O ３ ), zinc oxide (ZnO), hafnium silicate (HfSiO), zirconium silicate (ZrSiO), or niobium pentoxide (Nb ２ O ５ ) including at least one of The method for manufacturing a semiconductor device according to claim 1 .

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