Substrate modification for improving superlattice critical thickness

Abstract

A method and apparatus are provided for forming a strain-relieved buffer usable in semiconductor devices incorporating superlattice structures. The method includes epitaxially depositing a first silicon-germanium layer on a substrate. The first silicon-germanium layer has a first surface in contact with the front surface of the substrate and a second surface opposite the first surface. The first silicon-germanium layer has a first thickness and a germanium concentration gradient that increases from the first surface to the second surface. The method further includes epitaxially depositing a silicon-germanium capping layer on the first silicon-germanium layer. The silicon-germanium capping layer has a second thickness and a substantially uniform germanium concentration that is equal to, substantially equal to, or greater than a maximum germanium concentration of the germanium concentration gradient.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE The present disclosure relates to semiconductor devices and methods of fabricating semiconductor devices. In particular, the present disclosure relates to strain relaxed buffers (SRBs) that can be used in conductor devices incorporating superlattice structures and methods of fabricating the same. [Background technology]

[0002] III-V and IV compound films are commonly formed by heteroepitaxy, a form of epitaxy. In epitaxy, a single-crystalline film is deposited on a single-crystalline substrate from gaseous or liquid precursors. The substrate acts as a seed crystal during deposition, and the deposited film adopts the same lattice structure and orientation as the substrate. The deposited film is typically referred to as an epitaxial film or layer. In heteroepitaxy, the epitaxial film and substrate typically comprise different materials with different properties, such as lattice constants and thermal expansion coefficients. These differences in properties can lead to defects in the epitaxial film and even cracks in the substrate during epitaxial film growth. For example, when growing silicon germanium (SiGe) material on a silicon substrate, the differences in lattice constants and thermal expansion coefficients can create mechanical and thermal stresses that can warp the silicon substrate and cause cracks in the epitaxial SiGe material and even the silicon substrate.

[0003] One approach to reducing defect density involves growing a thick SRB layer on the substrate. Such thick SRB layers, which may be targeted for strain relaxation, can be expensive to grow. Other approaches have attempted to grow foreign materials that tend to relax quickly on the selected substrate, or alternatively, to grow thicker films that eventually relax due to strain accumulation. However, these processes are often time-consuming and require costly materials.

[0004] Therefore, there is a need for thinner SRB layers that reduce defect density while shortening processing time and reducing costs. Summary of the Invention

[0005] FIELD OF THE DISCLOSURE The present disclosure relates to semiconductor devices and methods of fabricating semiconductor devices. In particular, the present disclosure relates to strain-relieved buffer (SRB) layers that can be used in semiconductor devices incorporating superlattice structures and methods of fabricating the same.

[0006] In one aspect, a method for forming a strain-relieved buffer (SRB) on a substrate is provided. The method includes epitaxially depositing a first silicon-germanium layer on the substrate. The first silicon-germanium layer has a first surface in contact with the front surface of the substrate and a second surface opposite the first surface. The first silicon-germanium layer has a first thickness and a germanium concentration gradient that increases from the first surface to the second surface. The method further includes epitaxially depositing a silicon-germanium capping layer on the first silicon-germanium layer. The silicon-germanium capping layer has a second thickness and a substantially uniform germanium concentration that is equal to, substantially equal to, or greater than a maximum germanium concentration of the germanium concentration gradient.

[0007] Embodiments may include one or more of the following: the first thickness is in the range of about 2000 nm to about 2500 nm, and the germanium concentration gradient increases from 0 at.% near the interface with the substrate to a maximum germanium concentration in the range of about 10 at.% to about 15 at.%; the second thickness is in the range of about 1000 nm to about 1200 nm, and the substantially uniform germanium concentration is substantially equal to, equal to, or greater than the maximum germanium concentration of the first silicon germanium layer; the germanium concentration gradient increases from a first germanium concentration in the range of about 0 at.% to about 2 at.% germanium to a second germanium concentration in the range of about 10 at.% to about 15 at.%; the substrate comprises silicon. The method further includes polishing the silicon germanium capping layer to reduce the second thickness to a third thickness. After polishing the silicon germanium capping layer, the silicon germanium capping layer has a top surface with a root mean square (RMS) roughness of 5 Å or less. The method further includes, after polishing the silicon germanium capping layer, subjecting the silicon germanium capping layer to a wet cleaning process. Epitaxially depositing the first silicon germanium layer on the substrate includes increasing the flow rate of a germanium source gas to form an increasing germanium concentration gradient from the first surface to the second surface.

[0008] In another embodiment, a device structure is provided. The device structure includes a substrate. The device structure further includes a strain-relaxed buffer layer formed on the substrate. The strain-relaxed buffer layer includes a first silicon germanium layer having a first surface in contact with the front surface of the substrate and a second surface opposite the first surface. The first silicon germanium layer has a first thickness and a germanium concentration gradient that increases from the first surface to the second surface. The strain-relaxed buffer layer further includes a silicon germanium capping layer in contact with the second surface of the first silicon germanium layer. The silicon germanium capping layer has a second thickness and a substantially uniform germanium concentration that is equal to, substantially equal to, or greater than a maximum germanium concentration of the germanium concentration gradient. The device structure further includes a superlattice structure formed on the strain-relaxed buffer layer. The superlattice structure includes a silicon germanium spacer layer and a silicon channel layer, the silicon germanium spacer layer and the silicon channel layer being deposited in an alternating layer-by-layer arrangement.

[0009] Embodiments may include one or more of the following: the first thickness is in the range of about 2000 nm to about 2500 nm, and the germanium concentration gradient increases from 0 at.% near the interface with the substrate to a maximum germanium concentration in the range of about 10 at.% to about 15 at.%; the second thickness is in the range of about 1000 nm to about 1200 nm, and the substantially uniform germanium concentration is substantially equal to, equal to, or greater than the maximum germanium concentration of the first silicon germanium layer; the germanium concentration gradient increases from a first germanium concentration in the range of about 0 at.% to about 2 at.% germanium to a second germanium concentration in the range of about 10 at.% to about 15 at.%; the device structure is a dynamic random-access memory (DRAM) device; and the silicon germanium capping layer has a top surface with a root mean square (RMS) roughness of 5 Å or less. The device structure further includes a plurality of trenches formed through the strain-relaxed buffer layer and the superlattice structure. The device structure further includes one or more etch holes formed through the strain-relaxed buffer layer and the superlattice structure. The one or more etch holes are filled with one or more of a poly material and an oxide material. The poly material is a polycrystalline silicon material and the oxide material is silicon oxide. The substrate includes silicon.

[0010] In yet another aspect, a method for forming a semiconductor device is provided. The method includes epitaxially depositing a strain-relaxed buffer layer on a substrate in a first processing chamber. Epitaxially depositing the strain-relaxed buffer layer includes epitaxially depositing a first silicon-germanium layer on the substrate. The first silicon-germanium layer has a first thickness and has a germanium concentration gradient that increases from the first surface to the second surface. Epitaxially depositing the strain-relaxed buffer layer further includes epitaxially depositing a silicon-germanium capping layer on the first silicon-germanium layer. The silicon-germanium capping layer has a second thickness and has a substantially uniform germanium concentration that is equal to, substantially equal to, or greater than a maximum germanium concentration of the germanium concentration gradient. The method further includes transferring the substrate to a second processing chamber disposed ex-situ in an integrated processing system. The method further includes polishing the silicon germanium capping layer to reduce the second thickness to a third thickness in the second processing chamber. The method further includes transferring the substrate to a third processing chamber disposed ex-situ in the integrated processing system. The method further includes subjecting the silicon germanium capping layer to a wet cleaning process in the third processing chamber after polishing the silicon germanium capping layer. The method further includes transferring the substrate to a first processing chamber of the integrated processing system. The method further includes subjecting the substrate to a dry cleaning process in the first processing chamber of the integrated processing system using a remote plasma source that generates etchant species from a fluorine-containing precursor and a hydrogen-containing precursor. The method further includes transferring the substrate to a second processing chamber of the integrated processing system. The method further includes epitaxially depositing a superlattice structure on the strain-relaxed buffer layer in the second processing chamber of the integrated processing system.

[0011] Embodiments may include one or more of the following: the first thickness is in the range of about 2000 nm to about 2500 nm, and the germanium concentration gradient increases from 0 at.% near the interface with the substrate to a maximum germanium concentration in the range of about 10 at.% to about 15 at.%; the second thickness is in the range of about 1000 nm to about 1200 nm, and the substantially uniform germanium concentration is substantially equal to, equal to, or greater than the maximum germanium concentration of the first silicon germanium layer; the germanium concentration gradient increases from a first germanium concentration in the range of about 0 at.% to about 2 at.% germanium to a second germanium concentration in the range of about 10 at.% to about 15 at.%; the substrate comprises silicon.

[0012] In another aspect, a non-transitory computer-readable medium has stored thereon instructions that, when executed by a processor, cause a process chamber to perform the operations of the apparatus and / or methods described above.

[0013] In order that the above-described features of the present disclosure may be understood in detail, a more particular description of the above briefly summarized aspects will be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the present disclosure may admit of other equally effective embodiments, and therefore, the accompanying drawings illustrate only typical embodiments of the present disclosure and are not to be considered as limiting the scope of the present disclosure. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 shows a schematic cross-sectional view of a deposition chamber that may be used to form an SRB layer in accordance with one or more embodiments of the present disclosure. [Figure 2] 1 illustrates an exemplary flow diagram in accordance with one or more embodiments of the present disclosure. [Figure 3A] 1A-1D illustrate cross-sectional views of a semiconductor device structure during different stages of fabrication in accordance with one or more embodiments of the present disclosure. [Figure 3B]1A-1D illustrate cross-sectional views of a semiconductor device structure during different stages of fabrication in accordance with one or more embodiments of the present disclosure. [Figure 3C] 1A-1D illustrate cross-sectional views of a semiconductor device structure during different stages of fabrication in accordance with one or more embodiments of the present disclosure. [Figure 3D] 1A-1D illustrate cross-sectional views of a semiconductor device structure during different stages of fabrication in accordance with one or more embodiments of the present disclosure. [Figure 3E] 1A-1D illustrate cross-sectional views of a semiconductor device structure during different stages of fabrication in accordance with one or more embodiments of the present disclosure. [Figure 3F] 1A-1D illustrate cross-sectional views of a semiconductor device structure during different stages of fabrication in accordance with one or more embodiments of the present disclosure. [Figure 4] 1 illustrates a partial device structure of a memory device in accordance with one or more embodiments of the present disclosure. [Figure 5] FIG. 1 illustrates a top view of a class chamber in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0015] For ease of understanding, wherever possible, the same reference numerals will be used to designate identical elements common to the figures. It is contemplated that components and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0016] Superlattice structures can be utilized in the fabrication of devices that form integrated circuits. Such superlattice structures incorporate multiple stacks of films, such as silicon and silicon germanium films, with varying properties depending on the specific application for which the films are deposited. One of the key properties to control for a specific application is film stress. For example, in some applications, it may be appropriate to form a silicon germanium film with higher stress (compared to the underlying silicon substrate) to improve electron mobility through the silicon. Such improved electron mobility increases the speed of the device structure.

[0017] In other applications, it may be appropriate to form silicon germanium films with lower stress (compared to the underlying silicon substrate), for example, to minimize dislocations in the layers from the underlying substrate or to minimize the formation of dislocations in the substrate itself. Such dislocations are detrimental to device function because they scatter electron / hole movement and / or enhance diffusion where not appropriate. Furthermore, as the number of film stacks in a superlattice structure increases, differences in lattice constants and thermal expansion coefficients can create additional mechanical and thermal stresses that can cause the silicon substrate to bow and even crack the epitaxial SiGe material and silicon substrate of the superlattice structure.

[0018] Various embodiments described herein provide strain-relieved buffer (SRB) or other similar virtual / compliant substrates, allowing for increased unit cell count or additional composition / film thickness flexibility. In some embodiments, the SRB / virtual / compliant substrate also provides defect reduction for the 3D dynamic random access memory (DRAM) superlattice itself. The additional flexibility in 3D DRAM superlattice processing allows for simultaneous optimization of cell count and post-processing integration, such as etch selectivity. One of the parameters of 3D DRAM superlattice processing is the maximum cell count that can be achieved without defects. The use of pre-strain compensated or compliant substrates described herein allows for correction of the SiGe lattice mismatch underlying the superlattice, thus increasing the effective cell count.

[0019] 1 shows a schematic cross-sectional view of a deposition chamber 100 that may be used to form a strain-relaxed buffer in accordance with one or more embodiments of the present disclosure. The deposition chamber 100 may be utilized to grow an epitaxial film on a substrate, such as a substrate 102. The deposition chamber 100 generates a cross-flow of precursors across a top surface 150 of the substrate 102.

[0020] The deposition chamber 100 includes an upper body 156, a lower body 148 disposed below the upper body 156, and a flow module 112 disposed between the upper body 156 and the lower body 148. The upper body 156, the flow module 112, and the lower body 148 form a chamber body. Disposed within the chamber body are a substrate support 106, an upper dome 108, a lower dome 110, a plurality of upper lamps 141, and a plurality of lower lamps 143. As shown, a controller 120 is in communication with the deposition chamber 100 and is used to control processes as described herein. The controller 120 includes a memory 135, a CPU 159, and support circuits 158. The substrate support 106 is disposed between the upper dome 108 and the lower dome 110. The plurality of upper lamps 141 are disposed between the upper dome 108 and the lid 154. The lid 154 includes a plurality of sensors 153 positioned to measure the temperature within the deposition chamber 100. A plurality of lower lamps 143 are positioned between the lower dome 110 and the floor 152. The plurality of lower lamps 143 form a lower lamp assembly 145.

[0021] A processing space 136 is defined between the upper dome 108 and the lower dome 110. A substrate support 106 is disposed within the processing space 136. The substrate support 106 includes an upper surface on which the substrate 102 rests. The substrate support 106 is attached to a shaft 118. The shaft 118 is connected to a motion assembly 121. The motion assembly 121 includes one or more actuators and / or adjustment devices that effect movement and / or adjustment of the shaft 118 and / or the substrate support 106 within the processing space 136. For example, the motion assembly 121 includes a rotary actuator 122 that rotates the shaft 118 and / or the substrate support 106 about the longitudinal axis A of the deposition chamber 100. The motion assembly 121 further includes a vertical actuator 124 that raises and lowers the substrate support 106 in the Z direction. The motion assembly 121 includes a tilt adjustment device 126 used to adjust the planar orientation of the substrate support 106 and a lateral adjustment device 128 used to adjust the lateral position of the shaft 118 and the substrate support 106 within the processing space 136.

[0022] The substrate support 106 may include lift pin holes 107 disposed therein. The lift pin holes 107 are sized to accommodate lift pins 132 for lifting the substrate 102 off the substrate support 106 either before or after a deposition process. The lift pins 132 may rest on lift pin stops 134 when the substrate support 106 is lowered from a processing position to a transfer position.

[0023] The flow module 112 includes multiple process gas inlets 114, multiple purge gas inlets 164, and one or more exhaust gas outlets 116. The multiple process gas inlets 114 and the multiple purge gas inlets 164 are located on the opposite side of the flow module 112 from the one or more exhaust gas outlets 116. One or more flow guides 146 are located below the multiple process gas inlets 114 and the one or more exhaust gas outlets 116. The flow guides 146 are located above the purge gas inlets 164. A liner 163 is located on the inner surface of the flow module 112 and protects the flow module 112 from reactive gases used during the deposition process. The process gas inlets 114 and the purge gas inlets 164 are positioned to flow gases parallel to an upper surface 150 of a substrate 102 disposed within the processing space 136. The process gas inlets 114 are fluidly connected to a process gas source 151. The purge gas inlet 164 is fluidly connected to the purge gas source 162. The one or more exhaust gas outlets 116 are fluidly connected to the exhaust pump 157. Each of the process gas source 151 and the purge gas source 162 may be configured to supply one or more precursor or process gases to the processing space 136.

[0024] 2 illustrates an exemplary flow diagram of a method 200 according to one or more embodiments of the present disclosure. The method 200 may be part of a multi-operation manufacturing process for semiconductor devices incorporating superlattice structures, such as DRAM devices or gate-all-around (GAA) transistor devices. The method 200 may be used to form a strain-relieved buffer according to one or more embodiments of the present disclosure.

[0025] 3A-3F, cross-sectional views of several embodiments of device structures of a semiconductor device at various stages of fabrication are provided to illustrate method 200 of FIG. 2. While FIGS. 3A-3F are described with respect to method 200, it will be understood that the structures disclosed in FIGS. 3A-3F are not limited to method 200 and may instead stand alone as structures independent of method 200. Similarly, while method 200 is described with respect to FIGS. 3A-3F, it will be understood that method 200 is not limited to the structures disclosed in FIGS. 3A-3F and may instead stand alone as structures independent of method 200.

[0026] In step 210 of method 200, a substrate is provided. The substrate may be substrate 310, which is part of semiconductor device structure 300, as shown in FIGS. 3A-3F. In some embodiments, the substrate may be or include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like. The term "bulk semiconductor substrate" refers to a substrate composed entirely of semiconductor material. A bulk semiconductor substrate may include any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, a semiconductor layer may include one or more materials such as crystalline silicon (e.g., Si(100), Si(110), or Si(111)), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon substrate, patterned or unpatterned substrate, doped silicon, germanium, gallium arsenide, or other suitable semiconductor material. In some embodiments, the semiconductor material is silicon. In some embodiments, the semiconductor material is a doped material, such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In some embodiments, the substrate includes an additional material, such as a silicide layer, a metal silicide layer, a semiconductor layer, an etch stop layer (ESL), or a metal layer.

[0027] 3A, which illustrates a cross-sectional view of a semiconductor device structure 300 at an intermediate stage of fabrication corresponding to steps 210 and 220 of method 200, according to some embodiments. The electronic device structure 300 includes a substrate 310. The substrate 310 may be the substrate described in step 210. The substrate 310 has a front surface 310f (also referred to as the front side) and a back surface 310b (also referred to as the back side) opposite the front surface 310f.

[0028] At step 220 of method 200, in some embodiments, the substrate 310 may be subjected to an optional pre-cleaning or surface treatment process. In some embodiments, the substrate 310 is subjected to a surface treatment to improve mobility and bias temperature instability (BTI). In some embodiments, the surface treatment includes annealing the substrate 310 in a hydrogen (H) ambient. The annealing may be any suitable annealing process known to those skilled in the art. In some embodiments, the annealing is a rapid thermal process (RTP) anneal. In some embodiments, the annealing is performed at a temperature in the range of about 500 degrees Celsius to about 900 degrees Celsius, or in the range of about 600 degrees Celsius to about 900 degrees Celsius, or in the range of about 600 degrees Celsius to about 800 degrees Celsius. In some embodiments, the annealing is performed at a pressure in the range of about 5 mTorr to about 20 Torr.

[0029] Next, as shown in Figures 3B and 3C, a strain relaxed buffer (SRB) layer 319 is formed on the front surface 310f of the substrate 310.

[0030] 3B and 3C illustrate cross-sectional views of a semiconductor device structure 300 at intermediate stages of fabrication corresponding to steps 230 and 240 of method 200, according to some embodiments. As illustrated in FIG. 3C, an SRB layer 319 is formed on the front surface 310f of the substrate. The SRB layer 319 may include any material that helps accommodate the lattice mismatch between the substrate 310 and the subsequently formed superlattice structure 330 (see FIG. 3F). The SRB layer 319 may be a multi-layer structure. As shown in FIG. 3C, in some embodiments, the SRB layer 319 includes a first material layer 312 having a graded concentration of at least one component (e.g., germanium) and a second material layer 314, or capping layer, having a uniform or substantially uniform concentration of the at least one component.

[0031] In some embodiments, step 230 includes steps 240 and 250. In some embodiments, a first portion of the SRB layer 319, e.g., first material layer 312, is formed during step 230, and a second portion of the SRB layer 319, e.g., second material layer 314 or a capping layer, is formed during step 240. In some embodiments, first material layer 312 is a silicon germanium (SiGe) layer having a germanium concentration gradient. The germanium concentration gradient may increase from the lower surface to the upper surface of the SiGe layer. In some embodiments, in step 250, a capping layer, e.g., a SiGe capping layer having a uniform or substantially uniform germanium concentration, is formed on the SiGe layer having the germanium concentration gradient. While first material layer 312 is depicted as a single layer, it should be understood that multiple layers may be used to form the germanium concentration gradient.

[0032] 3B, the first material layer 312 has a backside surface 312b (also referred to as a back surface) and a frontside surface 312f (also referred to as a front surface) opposite the backside surface 312b. The backside surface 312b is in contact with the frontside surface 310f of the substrate 310. The first material layer 312 has a germanium concentration gradient. The germanium concentration gradient may increase from the backside surface 312b of the first material layer 312 to the frontside surface 312f of the first material layer 312. The first material layer 312 may be a SiGe spacer layer.

[0033] The first material layer 312 has a thickness 313. In some embodiments, the thickness 313 is in the range of about 1000 nm to about 5000 nm, or in the range of about 1500 nm to about 4000 nm, or in the range of about 1500 nm to about 3500 nm, or in the range of about 2000 nm to about 2500 nm, for example, about 2000 nm.

[0034] 3C, second material layer 314 has a backside surface 314b (also referred to as a back surface) and a frontside surface 314f (also referred to as a front surface) opposite backside surface 314b. Backside surface 314b is in contact with frontside surface 312f of first material layer 312. Second material layer 314 has a uniform or substantially uniform concentration. The uniform or substantially uniform germanium concentration may be equal to, substantially equal to, or greater than the maximum germanium concentration of the germanium concentration gradient.

[0035] The second material layer 314 has a thickness 315. In some embodiments, the thickness 315 is in the range of about 500 nm to about 2000 nm, or in the range of about 800 nm to about 1500 nm, or in the range of about 800 nm to about 1200 nm, or in the range of about 1000 nm to about 1200 nm, for example, about 1000 nm.

[0036] In some embodiments, the first material layer 312 and / or the second material layer 314 of the SRB may be silicon and germanium (e.g., Si 1-x Ge x, where x is the germanium concentration. In some embodiments, the germanium concentration (at %) in the first material layer 312 may be graded. For example, the germanium concentration may be lowest near the interface with the front surface 310f of the substrate 310 (e.g., near the back surface 312b of the first material layer 312) and may increase to be highest near the interface with the back surface 314b of the second material layer 314 (e.g., near the front surface 312f of the first material layer 312). For example, in some embodiments, the first material layer 312 is a SiGe layer having a graded germanium concentration, where the germanium concentration at the interface between the front surface 310f of the substrate 310 and the back surface 312b of the first material layer 312 is similar to the germanium concentration of the substrate 310 (e.g., 0 at%), the germanium concentration at the interface between the front surface 312f of the first material layer and the back surface 314b of the second material layer 314 (e.g., 10-15 at%) is similar to the uniform or substantially uniform germanium concentration of the second material layer 314 (e.g., 10-15 at%), and the uniform or substantially uniform germanium concentration of the second material layer 314 is similar to the germanium concentration of an adjacent SiGe layer in the superlattice structure (e.g., 10-15 at%).

[0037] In some embodiments, the graded germanium concentration of the first material layer 312 has an increasing germanium content in the range of about 0% to about 20%, or in the range of about 0% to about 15%, or in the range of about 0.1% to about 15%, or in the range of about 0.5% to about 15%, or in the range of about 1% to about 15%, or in the range of about 1% to about 10%. The silicon content of the first material layer 312 can be in the range of about 80% to about 100%, or in the range of about 85% to about 100%, or in the range of about 85% to about 99.9%, or in the range of about 85% to about 99.5%, or in the range of about 90% to about 99%. The first material layer 312 can have a maximum germanium content of 10% or less, 15% or less, or 20% or less.

[0038] In some embodiments, the second material layer 314 or capping layer has a germanium content that is substantially equal to, equal to, or greater than the graded germanium concentration of the first material layer 312. The second material layer 314 can have a germanium content of 10% or more, 15% or more, or 20% or more. The second material layer 314 can have a germanium content in the range of about 10% to about 50%, or in the range of about 10% to about 30%, or in the range of about 10% to about 20%, or in the range of about 10% to about 15%, or in the range of about 15% to about 30%, or in the range of about 15% to about 20%. The silicon content of the second material layer 314 can be in the range of about 50% to about 90%, or in the range of about 70% to about 90%, or in the range of about 80% to about 90%, or in the range of about 85% to about 90%, or in the range of about 70% to about 85%, or in the range of about 80% to about 85%.

[0039] In a particular embodiment, first material layer 312 is a SiGe layer having a thickness in the range of about 2000 nm to about 2500 nm and having a graded concentration of germanium, the graded concentration increasing from a first germanium concentration in the range of about 0 at.% to about 2 at.% near its interface with substrate 310, e.g., a silicon substrate, to a second or maximum germanium concentration in the range of about 10 at.% to about 15 at.% near its interface with first material layer 312, e.g., and second material layer 314 is a SiGe capping layer having a thickness in the range of about 1000 nm to about 1200 nm and having a substantially uniform concentration that is substantially equal to, the same as, or greater than the maximum germanium concentration of the graded germanium concentration of first material layer 312.

[0040] In some embodiments, the first material layer 312 and the second material layer 314 are formed via an epitaxial chemical vapor deposition process. The epitaxial deposition process provides precise control of the germanium content in each of the first material layer 312 and the second material layer 314, which provides advantageous control of the lattice match with either the underlying substrate 310 or a subsequently deposited superlattice structure. In some embodiments, the epitaxial deposition process includes loading a substrate, such as substrate 310, into a deposition chamber, such as deposition chamber 100, and adjusting conditions within the deposition chamber to a target temperature and pressure. A deposition process is then initiated to form one or more epitaxial layers on the monocrystalline surface of the substrate. The deposition process is then terminated. The thickness of the epitaxial layer is then determined. If the epitaxial layer reaches a predetermined thickness, the epitaxial process is terminated. However, if the predetermined thickness is not reached, the epitaxial process can be continued until the predetermined thickness is reached. Further details of this exemplary process are described below.

[0041] After loading a substrate into a process chamber, such as deposition chamber 100, conditions within the deposition chamber are adjusted to a predetermined temperature and pressure. The temperature is adjusted to suit the particular process being performed. The appropriate temperature for performing an epitaxial process may depend on the particular precursors used to deposit the silicon-containing and silicon germanium-containing materials. In some embodiments, the process chamber and / or substrate are maintained at a temperature of 900 degrees Celsius or greater, or 1000 degrees Celsius or greater, or 1100 degrees Celsius or greater, or 1200 degrees Celsius or greater. In some embodiments, the process chamber and / or substrate are maintained at a temperature within a range of about 900 degrees Celsius to about 1200 degrees Celsius, or within a range of about 900 degrees Celsius to about 1100 degrees Celsius, or within a range of about 1000 degrees Celsius to about 1100 degrees Celsius. Without being bound by theory, in some embodiments where the deposition process is performed at higher temperatures, for example, above 1000 degrees Celsius, the higher temperatures during deposition make a subsequent annealing process unnecessary. In some embodiments, the process chamber is maintained at a pressure within a range of about 10 mTorr to about 50 Torr, or within a range of about 1 Torr to about 20 Torr, or within a range of about 5 Torr to about 10 Torr during the epitaxial deposition process. The pressure can vary during and between processes, but is typically kept constant.

[0042] During the epitaxial deposition process, the substrate 310 is exposed to a deposition gas to form a first material layer 312 and a second material layer 314. In some embodiments, the substrate 310 is exposed to the deposition gas for a period of time ranging from about 0.5 seconds to about 30 seconds, or from about 1 second to about 20 seconds, or from about 5 seconds to about 10 seconds. In particular embodiments, the deposition process lasts for about 10-11 seconds. The specific exposure time during the epitaxial deposition process is generally related to the specific precursors and temperature used in the epitaxial deposition process. Generally, the substrate is exposed to the deposition gas for a length of time sufficient to form an epitaxial layer of a desired thickness in the SRB layer 319.

[0043] In some embodiments, the deposition gas includes at least a silicon source and may include a carrier gas and / or at least one secondary element source, such as a germanium source and / or a carbon source.

[0044] In some embodiments, a silicon source is typically supplied into the process chamber at a flow rate ranging from about 5 sccm to about 500 sccm, or from about 10 sccm to about 300 sccm, or from about 50 sccm to about 200 sccm, for example, at a flow rate of about 100 sccm. Useful silicon sources in deposition gases for depositing silicon-containing compounds include silane, halogenated silanes, and organosilanes. Silanes include silane (SiH4) and silane (SiH4), which has the empirical formula SiH4. x H (2x+2) Higher silanes represented by the formula: disilane (Si2H6), trisilane (Si3H8), tetrasilane (Si4H 10 ), neopentasilane, and others. Halogenated silanes have the empirical formula X' y Si x H (2x+2-y) (where X' = F, Cl, Br, or I), such as hexachlorodisilane (SiCl), tetrachlorosilane (SiCl), dichlorosilane (ClSiH), and trichlorosilane (ClSiH). Organosilanes are compounds with the empirical formula R y Si x H (2x+2-y) (where R = methyl, ethyl, propyl, or butyl), including, for example, methylsilane ((CH3)SiH3), dimethylsilane ((CH3)2SiH2), ethylsilane ((CH3CH2)SiH3), methyldisilane ((CH3)Si2H5), dimethyldisilane ((CH3)2Si2H4), and hexamethyldisilane ((CH3)6Si2). Organosilane compounds have been found to be advantageous sources of silicon and carbon in embodiments incorporating carbon into the deposited silicon-containing compound.

[0045] In some embodiments where the silicon source is supplied by a carrier gas, the carrier gas has a flow rate within the range of about 1 slm (standard liters per minute) to about 100 slm, or within the range of about 5 slm to about 75 slm, or within the range of about 10 slm to about 50 slm, or within the range of about 10 slm to about 20 slm. The carrier gas may include nitrogen (N), hydrogen (H), argon, helium, or a combination thereof. In some embodiments, an inert carrier gas is preferred and is selected from nitrogen, argon, helium, or a combination thereof. The carrier gas may be selected based on the precursors used and / or the process temperature during the epitaxial process.

[0046] In some embodiments, the deposition gas used also includes at least one secondary element source, such as a germanium source and / or a carbon source. The germanium source may be added to the process chamber along with the silicon source and, optionally, a carrier gas to form a silicon-containing compound, such as a silicon germanium material layer. In some embodiments, the germanium source is supplied into the process chamber at a flow rate in the range of about 0.1 sccm to about 20 sccm, e.g., in the range of about 0.5 sccm to about 10 sccm, or in the range of about 1 sccm to about 5 sccm. In some embodiments, the flow rate of the germanium source can be changed or increased during deposition of the first material layer 312 to form an increasing germanium concentration gradient. Useful germanium sources for depositing silicon-containing compounds include germane (GeH4), higher germanes, and organogermanes. Higher germanes have the empirical formula Ge x H (2x+2) These include compounds represented by the formula: digermane (Ge2H6), trigermane (Ge3H8), tetragermane (Ge4H 10), and others. Organogermanes include compounds such as methylgermane ((CH3)GeH3), dimethylgermane ((CH3)2GeH2), ethylgermane ((CH3CH2)GeH3), methyldigermane ((CH3)Ge2H5), dimethyldigermane ((CH3)2Ge2H4), and hexamethyldigermane ((CH3)6Ge2). Germanium and organogermanium compounds, i.e., SiGe and SiGe:C compounds, have been found to be advantageous germanium and carbon sources in embodiments for incorporating germanium and carbon into deposited silicon-containing compounds. In some embodiments, the germanium concentration in the epitaxial layer is in the range of about 1 at% to about 30 at%, e.g., about 20 at%. In some embodiments, the germanium concentration can be graded within the epitaxial layer, as described herein.

[0047] A carbon source may be added to the process chamber during deposition along with a silicon source and / or a germanium source, and optionally a carrier gas, to form a silicon-containing compound such as a silicon carbon material (e.g., Si:C) or a silicon germanium carbon material (e.g., SiGe:C). In some embodiments, the carbon source is supplied into the process chamber at a flow rate within a range from about 0.1 sccm to about 40 sccm, or within a range from about 3 sccm to about 25 sccm, or within a range from about 5 sccm to about 25 sccm. The carbon source may be diluted 5% with argon or nitrogen gas and flowed at a flow rate of 750 sccm. Useful carbon sources for depositing silicon-containing compounds include organosilanes, ethyl, propyl, and butyl alkyls, alkenes, and alkynes. Such carbon sources include methylsilane (CHSiH), dimethylsilane ((CH)SiH), ethylsilane (CHCHSiH), methane (CH), ethylene (CH), ethyne (CH), propane (CH), propene (CH), butyne (CH), and others. In some embodiments, the carbon concentration of the epitaxial layer is in the range of about 200 ppm to about 5 at.%, or in the range of about 1 at.% to about 3 at.%. In some embodiments, the carbon concentration can be graded within the epitaxial layer, preferably such that the carbon concentration in the initial portion of the epitaxial layer is lower than that in the final portion of the epitaxial layer. Alternatively, both a germanium source and a carbon source can be added to the process chamber along with a silicon source and carrier gas during deposition to form silicon-containing compounds such as silicon carbon materials or silicon germanium carbon materials.

[0048] In a specific embodiment, the first material layer 312, which may be an epitaxial SiGe layer with a graded germanium concentration, and the second material layer 314, which may be an epitaxial SiGe layer with a uniform or substantially uniform germanium concentration, are formed using either DCS or TCS as a silicon source gas and GeH4 or GeCl4 as a germanium source gas. The use of DCS or TCS as the silicon source gas provides a high growth rate process with chlorine surface termination, which leads to excellent interfacial abruptness. This interfacial abruptness contributes to improved etch selectivity of the SiGe SRB layer relative to the layers of the superlattice structure. Furthermore, the use of DCS or TCS allows the first material layer 312, the second material layer 314, or both the first material layer 312 and the second material layer 314 to be deposited at higher deposition temperatures, for example, at deposition temperatures of 900°C or higher.

[0049] In some embodiments, after the deposition processes of steps 240 and 250 are completed, the process chamber may be flushed with a purge gas or carrier gas and / or the process chamber may be evacuated with a vacuum pump. The purging and / or evacuation process removes excess deposition gas, reaction by-products, and other contaminants. In some embodiments, the process chamber may be purged between the deposition of the first material layer 312 and the deposition of the second material layer 314. In one embodiment, the process chamber may be purged for about 10 seconds by flowing a carrier gas at about 5 slm. The deposition and purging cycle may be repeated for numerous cycles.

[0050] In some embodiments, the SRB layer 319 can be subjected to a heating or rapid heating process to relax the SRB layer 319. The heating or rapid heating process can occur between steps 240 and 250, after step 250, or both between steps 240 and 250 and after step 250. To ensure complete relaxation in a controlled and repeatable manner, thermal processes such as rapid thermal processing (RTP), soak annealing, spike annealing, millisecond annealing, and nanosecond annealing (sub-melt or molten state in the time-temperature scaling) are contemplated for use.

[0051] In some embodiments, steps 240 and 250 are integrated such that there is no vacuum break between steps 240 and 250. For example, steps 240 and 250 can be performed in the same processing chamber, such as deposition chamber 100. In some embodiments, steps 240 and 250 are performed in separate processing chambers integrated on the same platform, such as cluster tool 500, such that there is no vacuum break.

[0052] In step 260, the SRB layer 319 may be subjected to a planarization process. In some embodiments, the front surface 314f of the second material layer 314 or capping layer of the SRB layer 319 has a high surface roughness. This high surface roughness of the front surface 314f of the SRB layer 319 makes it difficult to use the SRB layer 319 as a template for subsequent growth of the superlattice structure 330 on the SRB layer 319. The planarization process of step 260 removes a portion of the front surface 314f of the second material layer 314 or capping layer to form a smoothed surface 317 and expose the underlying native surface. In some embodiments, the smoothed surface 317 has a root mean square (RMS) roughness of 20 Å or less, 10 Å or less, 5 Å or less, or 3 Å or less. Any suitable planarization process may be used during step 260. The smoothing process may be a chemical mechanical polishing (CMP) process. In some embodiments, after the planarization process, the second material layer 314 or capping layer of the SRB layer 319 may have a reduced thickness 321 relative to thickness 315, as shown in FIG. 3E , in the range of about 200 nm to about 1700 nm, or about 500 nm to about 1200 nm, or about 500 nm to about 900 nm, or about 700 nm to about 900 nm, such as a thickness 321 of about 700 nm. In some embodiments, the reduced thickness 321 of the second material layer 314 or capping layer may be reduced relative to thickness 315 by about 40% or less, about 30% or less, or about 20% or less, such as by about 10% to about 30%.

[0053] In some embodiments, a vacuum break occurs between step 230, in which the SRB layer 319 is formed, and step 260, in which the SRB layer 319 is planarized. This vacuum break can lead to the formation of oxides on the SRB. Furthermore, the planarization process can lead to the formation of additional contaminants or debris on the surface of the SRB layer 319. Therefore, it may be appropriate to clean the SRB layer 319 before forming the superlattice structure on the SRB layer 319 in step 280.

[0054] In step 270, before forming the superlattice structure 330 on the SRB layer 319, the SRB layer 319 may be subjected to one or more cleaning processes. The one or more cleaning processes in step 270 may include one or more of a wet cleaning process and a dry cleaning process. The wet cleaning process may be, for example, a standard clean-1 (SC-1) process, a standard clean-2 (SC-2) process, and / or an HF process. The dry cleaning process may include a plasma etching process, such as a two-step dry chemical cleaning process using NF3 and NH3. In some embodiments, step 270 includes one or more wet cleaning processes followed by one or more dry cleaning processes.

[0055] In some embodiments, the SRB layer 319 is subjected to a wet cleaning process before forming the superlattice structure 330 on the SRB layer 319. The wet cleaning process may be used to remove oxides or other contaminants from the SRB layer 319 after the planarization process of step 260. The wet cleaning process may be an SC-1 process, an SC-2 process, an HF-first process, an HF-last process, or a combination thereof. The wet cleaning process may include an acidic cleaning process (a solution containing hydrofluoric acid and hydrogen peroxide held at an elevated temperature, e.g., an SC-2 process), a basic cleaning process (a solution containing ammonium hydroxide and hydrogen peroxide held at an elevated temperature, e.g., an SC-1 clean), or a series of wet cleans including both an acidic cleaning process and a basic cleaning process. In certain embodiments, the SRB layer 319 is exposed to an SC-1 solution (e.g., TMAH and HO) to remove organic residues and other contaminants, followed by an SC-2 solution (e.g., HO and HCl) to remove native oxide.

[0056] In some embodiments, oxides and / or contaminants on the smoothed surface 317 of the second material layer 314 or capping layer of the SRB layer 319 can be removed by an HF-first or HF-last process. In one example, the wet cleaning process utilizes an HF-first or HF-last solution containing water, HF, and optional additives including chelating agents, surfactants, reducing agents, other acids, or combinations thereof. In one example, the hydrogen fluoride concentration of the wet cleaning solution is in the range of about 10 ppm to about 5 wt %, or in the range of about 50 ppm to about 2 wt %, or in the range of about 100 to about 1 wt %, e.g., about 0.5 wt %.

[0057] In some embodiments, the SRB layer 319 may be exposed to an SC-1 cleaning solution during step 270 to remove contaminants, such as organic and inorganic residues and particulates, from the SRB layer 319. In one example, the SC-1 cleaning solution includes hydrogen peroxide and at least one basic compound, such as ammonium hydroxide, tetramethylammonium hydroxide, ethanolamine, diethanolamine, triethanolamine, derivatives thereof, salts thereof, or combinations thereof. During the SC-1 cleaning, the substrate 310 may be heated to a temperature ranging from about 50 degrees Celsius to about 100 degrees Celsius, or from about 70 degrees Celsius to about 90 degrees Celsius.

[0058] In some embodiments, the SRB layer 319 may be exposed to an SC-2 cleaning solution during step 270. In one example, the SC-2 cleaning solution includes hydrogen peroxide and hydrogen chloride. During the SC-2 cleaning, the substrate 310 may be heated to a temperature in the range of about 50 degrees Celsius to about 100 degrees Celsius, or in the range of about 70 degrees Celsius to about 90 degrees Celsius.

[0059] In certain embodiments, the SRB layer 319 is exposed to HF and then to SC-1 and / or SC-2 cleaning solutions.

[0060] In some embodiments, the SRB layer 319 is subjected to a dry cleaning process and / or a degassing process before forming the superlattice structure 330 on the SRB layer 319. The SRB layer 319 may be subjected to a dry cleaning process and / or a degassing process after the wet cleaning process and before forming the superlattice structure 330 on the SRB layer 319. The dry cleaning process may be used to remove oxides from the surface of the SRB layer 319. In some embodiments, the wet cleaning process may be performed ex-situ in the cluster tool 500, and the SRB layer 319 may be subjected to a dry cleaning process and / or a degassing process after entering the cluster tool 500. For example, if the SRB layer 319 comprises silicon, an Applied Materials SICONI® cleaning process may be performed on the SRB layer 319 to remove oxides from the formed SRB layer 319. The SICONI® cleaning process removes native oxide through a low-temperature, two-step dry chemical cleaning process using NF3 and NH3. The cleaning process may be performed in a processing chamber located on a cluster tool, such as cluster tool 500 (see FIG. 5). An exemplary pre-clean chamber that may perform the dry cleaning process of step 270 may include a SICONI® cleaning chamber available from Applied Materials, Inc. of Santa Clara, California.

[0061] In some embodiments, the SRB layer 319 can be exposed to a fluorine-containing precursor and a hydrogen-containing precursor in a two-part dry chemical cleaning process. In some embodiments, the fluorine-containing precursor can include nitrogen trifluoride (NF), hydrogen fluoride (HF), diatomic fluorine (F), monoatomic fluorine (F), a fluorine-substituted hydrocarbon, or a combination thereof. In some embodiments, the hydrogen-containing precursor can include monoatomic hydrogen (H), diatomic hydrogen (H), ammonia (NH), a hydrocarbon, a partially halogen-substituted hydrocarbon, or a combination thereof.

[0062] In some embodiments, the first part of a two-step dry cleaning process can involve using a remote plasma source to generate etchant species (e.g., ammonium fluoride (NHF)) from a fluorine-containing precursor (e.g., nitrogen trifluoride (NF)) and a hydrogen-containing precursor (e.g., ammonia (NH)). Using a remote plasma source can minimize damage to the SRB layer 319. The etchant species are then introduced into the pre-clean chamber and condense onto the surface of the SRB layer 319 through reaction with the native oxide layer to form solid by-products. The second process then involves an in-situ annealing process using convection and radiant heating to decompose the by-products. The by-products then sublimate and are removed from the surface of the SRB layer 319 via a gas flow and exhausted from the pre-clean chamber.

[0063] In some embodiments, the SRB layer 319 is subjected to a surface treatment process before forming the superlattice structure 330 on the SRB layer 319. The SRB layer 319 may be subjected to a surface treatment process after a dry cleaning process and / or a wet cleaning process and before forming the superlattice structure 330 on the SRB layer 319. In some embodiments, the surface treatment includes annealing the SRB layer 319 in a hydrogen (H) ambient. The annealing process may be any suitable annealing process known to those skilled in the art. In some embodiments, the annealing process includes a rapid thermal process (RTP) anneal. In some embodiments, the annealing process is performed at a temperature in the range of about 500 degrees Celsius to about 1000 degrees Celsius, or in the range of about 600 degrees Celsius to about 900 degrees Celsius, or in the range of about 600 degrees Celsius to about 800 degrees Celsius. In some embodiments, the annealing is carried out at a pressure in the range of about 10 mTorr to about 30 Torr, or in the range of about 5 Torr to about 20 Torr, or in the range of about 5 Torr to about 10 Torr.

[0064] In step 280, a superlattice structure 330 is formed on the SRB layer 319. As used herein, the term superlattice generally refers to a stack of material layers that are closely lattice-matched but sufficiently different in composition to allow a selective removal process to be performed on the superlattice structure 330. More generally, the composition of the various material layers within the stack may be specific to one or more of the material layers within the stack. In one example, the superlattice structure 330 includes one or more layers of a silicon-containing material (e.g., Si) and a silicon-germanium-containing material (e.g., SiGe). In some embodiments, the superlattice structure 330 includes a first material layer and a second material layer. In some embodiments, the superlattice structure 330 includes a first material layer, a second material layer, a third material layer, and a fourth material layer. In this embodiment, the second material layer, the third material layer, and the fourth material layer are formed from the same compound material but may have different material properties.

[0065] Forming the superlattice structure 330 in step 280 includes forming a first material layer and forming a second material layer on the first material layer. Forming the first material layer and forming the second material layer may be repeated until the superlattice structure reaches a target thickness and / or number of layers. The first material layers and second material layers may be arranged in alternating stacked pairs. The superlattice structure 330 may include a plurality of first material layers 324a-f (collectively 324) and a corresponding plurality of second material layers 326a-f (collectively 326) arranged in alternating stacked pairs. In one embodiment, the plurality of first material layers 324a-f are formed from at least a silicon-containing material and a germanium-containing material, and the plurality of second material layers 326a-f are formed from a silicon-containing material. In some embodiments, the plurality of first material layers 324a-f are SiGe spacer layers, and the plurality of second material layers 326a-f are silicon channel layers. Thus, the first and second material layers are different materials. In some embodiments, the plurality of first material layers 324a-f and the corresponding plurality of second material layers 326a-f are lattice-matched materials with sufficient compositional difference to allow subsequent selective layer removal.

[0066] In some embodiments, the plurality of first material layers 324a-f include a Group IV material, such as silicon and germanium (e.g., SiGe). The plurality of second material layers 326a-f include a Group IV material, such as silicon (e.g., Si). In some embodiments, the silicon germanium layer has a silicon:germanium molar ratio of about 1:1 to about 5:1. In some embodiments, the silicon germanium layer has a germanium content in the range of about 10% to about 50%, or in the range of about 20% to about 50%, or in the range of about 20% to about 40%, or in the range of about 30% to about 40%. The silicon content can be in the range of about 50% to about 90%, or in the range of about 50% to about 80%, or in the range of about 60% to about 80%, or in the range of about 60% to about 70%. In other embodiments, the silicon germanium layer has a germanium content in the range of about 20% to about 90%, or in the range of about 50% to about 80%. The silicon content can be in the range of about 10% to about 80%, or in the range of about 20% to about 50%.

[0067] In some embodiments, the plurality of first material layers 324a-f and the corresponding plurality of second material layers 326a-f can be any number of lattice-matched material pairs suitable for forming the superlattice structure 330. For example, the plurality of first material layers 324a-f and the corresponding plurality of second material layers 326a-f can include from about 2 pairs to about 100 pairs of lattice-matched materials, such as 6 pairs of lattice-matched materials, as shown in FIG.

[0068] The material layers of the superlattice structure 330 can have controlled thicknesses to provide substantially defect-free crystal profiles of various materials. In some embodiments, the layers of the superlattice structure 330 have a total thickness in the range of about 3 nm to about 50 nm, or about 5 nm to about 40 nm, or about 5 nm to about 30 nm, or about 5 nm to about 20 nm. In some embodiments, the layers of the superlattice structure 330 have a thickness in the range of about 3 nm to about 50 nm. For example, the plurality of first material layers 324a-f can have a thickness 325 in the range of about 1 nm to about 20 nm, or about 1 nm to about 10 nm, or about 3 nm to about 10 nm, or about 5 nm to about 7 nm, e.g., about 6 nm. The plurality of second material layers 326a-f may have a thickness 327 in the range of about 1 nm to about 20 nm, or in the range of about 5 nm to about 15 nm, or in the range of about 7 nm to about 10 nm, for example, about 8 nm.

[0069] FIG. 4 illustrates a partial device structure 400 of a memory device. The partial device structure 400 can be formed from the semiconductor device structure 300. Similar device structures can be formed from different superlattice structures. The partial device structure 400 includes a plurality of trenches 408 formed through the plurality of first material layers 324a-f and the plurality of second material layers 326a-f of the superlattice structure 330 and the first material layer 312 and the second material layer 314 or capping layer of the SRB layer 319. The trenches 408 include sidewalls 410 that are etched or treated during subsequent processing steps. The partial device structure 400 further includes a plurality of etch holes 402, which can be similar to the trenches 408. However, the etch holes 402 are filled with one or more of a poly material 404 and an oxide material 406. The poly material 404 can be a polycrystalline silicon material. The oxide material 406 can be silicon oxide or silicon nitride. In some embodiments, the oxide material 406 can instead be a silicon germanium material.

[0070] Partial device structure 400 is illustrated herein as an exemplary structure that may be formed from superlattice structure 330 and SRB layer 319. It is contemplated that a variety of device structures may be formed from superlattice structure 330 and SRB layer 319 using the methods described herein.

[0071] FIG. 5 is a plan view of a cluster tool 500 according to another embodiment described herein. The cluster tool 500 includes at least one epitaxial deposition chamber, as described above. An example of a cluster tool 500 is the CENTURA® system available from Applied Materials, Inc. of Santa Clara, California. Cluster tools manufactured by other manufacturers may be used as well. A transfer robot 504 of any convenient type is disposed within a transfer chamber 502 of the cluster tool 500. A load lock 506 including two load lock chambers 506A, 506B is coupled to the transfer chamber 502. A plurality of processing chambers 508, 510, 512, 514, and 516 are also coupled to the transfer chamber 502. The multiple processing chambers 508, 510, 512, 514, and 516 may include at least one of a pre-clean chamber, a material deposition chamber, such as an epitaxial deposition chamber, e.g., deposition chamber 100, and a thermal treatment chamber, such as an annealing chamber, a degassing chamber, or an oxidation chamber.

[0072] Processing chamber 508 may be a pre-clean chamber configured to clean a substrate prior to depositing a strain-relaxed buffer layer and / or a superlattice structure. The pre-clean chamber may be configured to perform Applied Materials' SICONI® pre-clean process. Processing chambers 510 and / or 514 may be material deposition chambers, such as epitaxial deposition chambers capable of performing epitaxial growth processes. Processing chambers 512 and / or 516 may be additional material deposition chambers or thermal treatment chambers capable of performing thermal treatment processes.

[0073] A system controller 557 communicates with the transfer robot 504 and the plurality of processing chambers 508, 510, 512, 514, and 516. The system controller 557 can be any suitable component capable of controlling the processing chambers and robots. For example, the system controller 557 can be a computer including a central processing unit (CPU) 592, memory 594, input / output 596, suitable circuitry 598, and storage.

[0074] The processes can generally be stored in the memory of the system controller 557 as software routines that, when executed by a processor, cause the process chamber to perform the processes of the present disclosure. The software routines can also be stored and / or executed by a second processor (not shown) located remotely from the hardware being controlled by the processor. Some or all of the methods of the present disclosure can also be performed in hardware. Thus, the processes can be implemented in software and executed in hardware using a computer system, for example, as an application-specific integrated circuit or other type of hardware implementation, or can be executed as a combination of software and hardware. The software routines, when executed by a processor, transform a general-purpose computer into a special-purpose computer (controller) that controls the operation of the chamber so that the processes are performed.

[0075] In some embodiments, the system controller 557 is configured to control the epitaxial growth chamber to grow a strain-relaxed buffer, such as the SRB layer 319.

[0076] Cluster tool 500 can be used to perform method 200 described above. During processing, a substrate to be processed may arrive at cluster tool 500 in a pod (not shown). The substrate is transferred from the pod to vacuum-compatible load lock chambers 506A, 506B by a factory interface robot (not shown). The substrate is then picked up by transfer robot 504 in transfer chamber 502, which is typically maintained under vacuum. Transfer robot 504 then loads the substrate into processing chamber 508 for cleaning as described in step 220. Transfer robot 504 then removes the substrate from processing chamber 508 and loads it into whichever processing chamber 510 or 514 is available for epitaxial deposition. The epitaxial strain-relaxed buffer layer described herein can be deposited on the cleaned substrate in processing chamber 510 or 514. Transfer robot 504 then removes the substrate from processing chamber 510 or 514 and transfers it into whichever available thermal processing chamber, processing chamber 512 or 516. The epitaxial buffer layer is then subjected to a rapid heating / cooling process. Transfer robot 504 then removes the substrate from processing chamber 512 or 516 and transfers it to processing chamber 514 for depositing an active material on the buffer layer, as described in step 280.

[0077] Reference has been made to specific features of the present disclosure (including method steps) in the Summary, Detailed Description, Claims, and accompanying drawings. The disclosure herein should be understood to include all possible combinations of such specific features. For example, if a particular feature is disclosed in a particular aspect or embodiment of the present disclosure, or in the context of a particular claim, that feature can also be used in combination with and / or in the context of other specific aspects and embodiments of the present disclosure, and in the disclosure generally, to the extent possible.

[0078] As used herein, when a method including two or more specified steps is referred to, the specified steps may be performed in any order or simultaneously (unless the context excludes this possibility), and the method may include one or more other steps performed before any of the specified steps, between two of the specified steps, or after all of the specified steps (unless the context excludes this possibility).

[0079] When introducing elements of the present disclosure or exemplary aspects or embodiments thereof, the articles "a," "an," "the," and "said" are intended to mean that there are one or more of the element.

[0080] The term "comprises" and its grammatical equivalents are used herein to mean that other elements, ingredients, steps, etc. are optionally present. For example, an article "comprising" elements A, B, and C can consist of elements A, B, and C (i.e., consist only of elements A, B, and C), or it can include elements A, B, and C as well as one or more other elements. In addition, whenever the transitional phrase "comprising" or its grammatical equivalent appears before a composition, element, or group of elements, it is understood that the transitional phrase "consisting essentially of," "consisting of," "selected from the group of consisting of," or "is" can also appear before the description of the same composition, element, or group of elements, and vice versa.

[0081] While the foregoing specification is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof, the scope of which is defined by the following claims.

Claims

1. 1. A method for forming a strain relaxed buffer (SRB) layer on a substrate, comprising: epitaxially depositing a first silicon germanium layer on the substrate, the first silicon germanium layer having a first surface in contact with a front surface of the substrate and a second surface opposite the first surface, the first silicon germanium layer having a first thickness and a germanium concentration gradient that increases from the first surface to the second surface; epitaxially depositing a silicon germanium capping layer on the first silicon germanium layer, the silicon germanium capping layer having a second thickness and a substantially uniform germanium concentration that is equal to, substantially equal to, or greater than a maximum germanium concentration of the germanium concentration gradient; A method comprising:

2. 2. The method of claim 1, wherein the first thickness is in a range of about 2000 nm to about 2500 nm, and the germanium concentration gradient increases from 0 at. % near the interface with the substrate to the maximum germanium concentration in a range of about 10 at. % to about 15 at. %.

3. 3. The method of claim 2, wherein the second thickness is in a range from about 1000 nm to about 1200 nm, and the substantially uniform germanium concentration is substantially equal to, equal to, or greater than the maximum germanium concentration of the first silicon germanium layer.

4. 2. The method of claim 1, wherein the germanium concentration gradient increases from a first germanium concentration in a range of about 0 at% to about 2 at% germanium to a second germanium concentration in a range of about 10 at% to about 15 at% germanium.

5. The method of claim 1 , wherein the substrate comprises silicon.

6. The method of claim 1 , further comprising polishing the silicon germanium capping layer to reduce the second thickness to a third thickness.

7. 10. The method of claim 1, wherein after polishing the silicon germanium capping layer, the silicon germanium capping layer has a top surface with a root mean square (RMS) roughness of 5 Å or less.

8. 7. The method of claim 6, further comprising subjecting the silicon germanium capping layer to a wet cleaning process after polishing the silicon germanium capping layer.

9. 2. The method of claim 1, wherein epitaxially depositing the first silicon germanium layer on the substrate comprises increasing a flow rate of a germanium source gas to form an increasing germanium concentration gradient from the first surface to the second surface.

10. 1. A device structure comprising: A substrate; a strain-relaxed buffer layer formed on the substrate, a first silicon germanium layer having a first surface in contact with the front surface of the substrate and a second surface opposite the first surface, the first silicon germanium layer having a first thickness and a germanium concentration gradient that increases from the first surface toward the second surface; and a silicon germanium capping layer contacting the second surface of the first silicon germanium layer, the silicon germanium capping layer having a second thickness and a substantially uniform germanium concentration equal to, substantially equal to, or greater than a maximum germanium concentration of the germanium concentration gradient; a strain-relaxed buffer layer comprising: a superlattice structure formed on the strain-relieved buffer layer, a silicon germanium spacer layer; and a silicon channel layer, wherein the silicon germanium spacer layer and the silicon channel layer are deposited in an alternating layer-by-layer arrangement; a superlattice structure including: A device structure comprising:

11. 11. The device structure of claim 10, wherein the first thickness is in a range of about 2000 nm to about 2500 nm, and the germanium concentration gradient increases from 0 at. % near the interface with the substrate to a maximum germanium concentration in a range of about 10 at. % to about 15 at. %.

12. 12. The device structure of claim 11, wherein the second thickness is in a range from about 1000 nm to about 1200 nm, and the substantially uniform germanium concentration is substantially equal to, equal to, or greater than the maximum germanium concentration of the first silicon germanium layer.

13. 11. The device structure of claim 10, wherein the germanium concentration gradient increases from a first germanium concentration in a range of about 0 at% to about 2 at% germanium to a second germanium concentration in a range of about 10 at% to about 15 at% germanium.

14. 11. The device structure of claim 10, wherein the device structure is a dynamic random-access memory (DRAM) device.

15. 11. The device structure of claim 10, wherein the silicon germanium capping layer has a top surface with a root mean square (RMS) roughness of 5 Å or less.

16. The device structure of claim 10 further comprising a plurality of trenches formed through said strain-relaxed buffer layer and said superlattice structure.

17. 17. The device structure of claim 16, further comprising one or more etch holes formed through said strain-relaxed buffer layer and said superlattice structure, said one or more etch holes being filled with one or more of a poly material and an oxide material.

18. 20. The device structure of claim 17, wherein said poly material is a polycrystalline silicon material and said oxide material is silicon oxide.

19. The device structure of claim 10 , wherein the substrate comprises silicon.

20. 1. A method of forming a semiconductor device, comprising: epitaxially depositing a strain-relaxed buffer layer on a substrate in a first processing chamber; epitaxially depositing a first silicon germanium layer on the substrate, the first silicon germanium layer having a first thickness and a germanium concentration gradient that increases from a first surface to a second surface of the first silicon germanium layer; and epitaxially depositing a strain-relaxed buffer layer on the substrate, the silicon germanium capping layer having a second thickness and a substantially uniform germanium concentration equal to, substantially equal to, or greater than a maximum germanium concentration of the germanium concentration gradient; transferring the substrate to a second processing chamber located ex-situ in an integrated processing system; polishing the silicon germanium capping layer in the second processing chamber to reduce the second thickness to a third thickness; transferring the substrate to a third processing chamber located ex-situ in the integrated processing system; subjecting the silicon germanium capping layer to a wet cleaning process in the third processing chamber after polishing the silicon germanium capping layer; transferring the substrate to a first processing chamber of the integrated processing system; subjecting the substrate to a dry cleaning process in the first processing chamber of the integrated processing system using a remote plasma source that generates etchant species from a fluorine-containing precursor and a hydrogen-containing precursor; transferring the substrate to a second processing chamber of the integrated processing system; epitaxially depositing a superlattice structure on the strain-relaxed buffer layer in the second processing chamber of the integrated processing system; 1. A method for forming a semiconductor device, comprising:

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