Gate driver circuit and conversion device

Abstract

1. A gate driver circuit for a half-bridge of a converter, wherein a first switching element having a first gate and a second switching element having a second gate are independently and complementarily controlled by a controller that provides gate pull-up pulse signals and gate pull-down pulse signals to the first gate driver buffer and the second gate driver buffer via a first gate driver buffer and a second gate driver buffer, respectively, the gate driver circuit including a first gate current mirroring circuit in a source branch of the first gate driver buffer, the first gate current mirroring circuit providing a first sense signal when the first gate driver buffer is turned on, and a first sense 1. A gate driver circuit for a half-bridge of a converter, comprising: a first detection circuit for processing and forwarding a signal to a second protection circuit of a second gate driver buffer configured to turn off a second switching element upon occurrence of a first detection signal; a second gate current mirroring circuit in a source branch of the second gate driver buffer for providing a second detection signal upon turn-on of the second gate driver buffer; and a second detection circuit for processing and forwarding the first detection signal to a first protection circuit of the first gate driver buffer configured to turn off the first switching element upon occurrence of the second detection signal.

Description

[Technical Field]

[0001] The present disclosure relates to a power converter comprising at least one switching half-bridge, and more precisely to protection against overlapping during switching transitions of the switches of the switching half-bridge. [Background technology]

[0002] In a power converter consisting of at least one half-bridge, the switches are controlled independently and complementary to provide on-to-off and off-to-on transitions. Between these transitions, a dead time is required during which both switches are off. The primary reason for the dead time is that multiple factors, including propagation delays, mismatches between turn-on and turn-off delays, and temperature-dependent threshold voltage drift, can cause control voltages to overlap, resulting in shoot-through currents that can damage devices.

[0003] In existing converters, there are various ways to ensure that the control signals applied to the half bridges do not overlap.

[0004] The first method is to use commercially available dedicated half-bridge gate driver ICs with overlap prevention. Typically, such devices include a logic adjustment circuit that prevents overlapping of the output signals controlling the gates of the half-bridge power devices, even if the signals coming from the controller overlap. The implemented signal adjustment is manufacturer-dependent and not known to external users. For example, the gate driver IC from Silicon Labs, known by the part number Si8273, proposes an overlap protection circuit that detects when both input levels are high and forces one of the outputs to GND, thus avoiding any short circuit on the power supply side.

[0005] The second method, which is relevant for gate driver ICs without overlap protection, involves properly sequencing the control signals supplied to the gate drivers to avoid any issues. Therefore, sufficient dead time must be provided.

[0006] As mentioned above, in a power conversion device, it is essential to control the two switches of the half-bridge quickly and accurately. However, wide bandgap elements such as SiC or GaN have high-speed switching capabilities, which increases the switching frequency and increases the constraints on the control section.

[0007] Commonly implemented half-bridge configurations require proper control timing to avoid cross-conduction and shoot-through currents, which can lead to significant additional losses or even semiconductor destruction. Summary of the Invention [Problem to be solved by the invention]

[0008] However, sometimes an incorrect control signal is applied to the gate electrode, leading to cross-conduction. There are several reasons why this can occur: a control error that pulls up one of the gate driver outputs at the wrong time, a faulty gate driver IC that shuts it off in a high state, or an EMI problem that causes an incorrect control signal. Therefore, overlap detection / protection can prevent short circuits caused by controller errors or faulty gate drivers. [Means for solving the problem]

[0009] Considering such a situation, the present disclosure proposes a simple protection system that uses a current-based gate current sensing technique to detect such erroneous control signals and proposes a circuit to avoid shorting the half-bridge in such cases.

[0010] The proposed circuit is based on current mirror technology, which senses the gate current of one of the switches while it is turning on, and allows a protection circuit to turn off the other switch if the other switch is already on.

[0011] The mirrored current is then processed and transferred across the isolation barrier to the opposite gate driver. Conditioning and / or buffering circuits can detect if a positive gate current is sensed while the second gate driver voltage is already high, so that protection can be implemented with appropriate dedicated logic.

[0012] In view of the above, the present disclosure provides a gate driver circuit for a half-bridge of a converter, in which a first switching element having a first gate and a second switching element having a second gate are independently and complementary controlled via a first gate driver buffer and a second gate driver buffer by a controller that provides a gate pull-up pulse signal and a gate pull-down pulse signal to the first gate driver buffer and the second gate driver buffer, respectively, the gate driver circuit comprising: a first gate current mirroring circuit in a source branch of the first gate driver buffer, the first gate current mirroring circuit providing a first detection signal upon turning on of the first gate driver buffer, and a first detection circuit processing and forwarding the first detection signal to a second protection circuit of the second gate driver buffer, the second protection circuit configured to turn off a second switching element upon occurrence of the first detection signal; a second gate current mirroring circuit in the source branch of the second gate driver buffer, the second gate current mirroring circuit providing a second sense signal upon turn-on of the second gate driver buffer, and a second sense circuit processing and forwarding the first sense signal to a first protection circuit of the first gate driver buffer, the first protection circuit being configured to turn-off the first switching element upon occurrence of the second sense signal; A gate driver circuit for a half bridge of a converter is proposed, which comprises an overlap protection circuit comprising:

[0013] Such gate driver circuits protect the half-bridges from overlapping through high-speed protection circuits.

[0014] To provide an isolation barrier between the upper and lower circuits, the first detection circuit can be connected to the first gate current mirroring circuit through a first isolation barrier, and the second detection circuit can be connected to the second gate current mirroring circuit through a second isolation barrier. In one implementation, such isolation barrier is a current transformer.

[0015] To improve the signal and avoid false detection, the first detection circuit and the second detection circuit may each include a conditioning circuit.

[0016] The present disclosure also relates to a gate driver circuit for a half bridge of a converter, in which the first detection circuit and the second detection circuit each include a trigger circuit and an anti-false-detection circuit that enables detection of an overlap error only when the detection signal is emitted when the positive driver command output of the opposing pre-driver is on.

[0017] In such a case, the first detection circuit and the second detection circuit may each include a latch circuit that latches the detected overlap error, transfers the detected overlap error to the controller, and triggers the protection circuit.

[0018] This provides both protection for the half-bridge and fault information at the controller level.

[0019] Each of the first and second protection circuits may be configured with a controllable switch that pulls down the gate electrode of the corresponding switching element, and the controllable switch may be configured with a diode and a MOSFET.

[0020] The controller may include a reset output to reset the detection circuit to restart the conversion.

[0021] The reset output may be connected to the reset input of the latch circuit through an isolation element.

[0022] The gate driver buffer associated with the current mirroring circuit may be driven by a pre-driver circuit that transfers control signals from the controller to the gate driver buffer and provides galvanic isolation between the controller and the gate driver buffer.

[0023] The present disclosure also relates to a half-bridge converter including a gate driver circuit as described above.

[0024] A detailed description of exemplary embodiments of the present invention is discussed below with reference to the accompanying drawings. [Brief explanation of the drawings]

[0025] [Figure 1] 1 is a schematic diagram of a conventional half bridge in a converter; [Figure 2] 1 is a schematic diagram showing a block diagram of a half-bridge command circuit with a detection / protection circuit according to the present disclosure; [Figure 3] FIG. 2 is a detailed diagram of the upper detection / protection circuit of the present disclosure. [Figure 4] FIG. 1 is a schematic diagram of a complete half-bridge command circuit including the detection / protection circuit of the present disclosure. [Figure 5] FIG. 10 is a diagram showing the switching waveforms of overlapped control signals in the absence of an overlap protection circuit. [Figure 6] FIG. 10 illustrates the switching waveforms of overlapped control signals in the presence of an overlap protection circuit. DETAILED DESCRIPTION OF THE INVENTION

[0026] Figure 1 shows the upper leg switch S H and lower leg switch S L1 is a schematic diagram of a half-bridge in a converter having a MOSFET. The upper leg switch includes a transistor Q1, in this case a MOSFET, represented by a body diode D1 and a parasitic output capacitor C1. The lower leg switch includes a transistor Q2, represented by a body diode D2 and a parasitic output capacitor C2. The reverse diodes D1 and D2 may be additional components.

[0027] In such a diagram, the MOSFET devices are considered to be in switching cells, the switch symbols include an internal body diode and an output capacitor COSS, a load 51 is connected between the midpoint of the switching cell and the high potential of the DC voltage source, and the load current is considered to be positive, i.e., current flows from the positive DC bus to the midpoint of the switching cell, and the load current is considered to be constant during the transition time scale.

[0028] Switch S H and S L are controlled via gate control circuits 50a and 50b for the upper and lower leg switches, respectively, and a DC-side capacitor 52 filters HF signals generated by the switching sequences. The gate control circuits 50a and 50b comprise push-pull output transistors, as known in the art.

[0029] Starting from this basic circuit diagram, the present disclosure relates to a detection / protection circuit that protects the half-bridges of a converter from overlapping and preventing short circuits due to controller errors or gate driver failures.

[0030] Such circuits are intended to detect overlapping gate control signals or erroneous turn-on of power devices due to faulty gate drivers, both of which can lead to a short circuit in the power stage. This overlap protection can be implemented in any kind of voltage source converter where short circuits must be avoided at all costs.

[0031] FIG. 2 provides a schematic diagram including functional blocks of the circuit of the present disclosure. The circuit begins with an upper-side current mirror circuit 32a and a lower-side current mirror circuit 32b. The circuit includes an upper-side protection circuit 34a and a lower-side protection circuit 34b, and pre-drivers 10a and 10b that receive commands from a controller 60 and provide galvanic isolation between the controller and the upper-side and lower-side driver circuits. The circuit also includes an upper-side protection circuit 34a connected to a lower-side detection circuit 33b, a lower-side protection circuit 34b connected to the upper-side detection circuit 33a, and galvanic isolation circuits 36a and 36b that send error signals from the detection circuits to the controller through an isolation barrier, such as an optocoupler or other isolation element. Galvanic isolation between the controller and the upper-side and lower-side gate buffer circuits is necessary because these portions of the half-bridge converter are powered through different voltage sources.

[0032] Galvanic isolation, also called an isolation barrier, can be achieved using optocouplers, current transformers, or voltage transformers.

[0033] In the figure, the second switching element S L The elements that drive the first switching element S are called lower elements, also called "Bot", for example "Bot.Detection" or "Bot.Detect", "Bot.Protection" or "Bot.Prot", H The elements that drive the top protection and bottom protection are called upper elements and are prefixed with "Top", such as "Top Protection" or "Top Prot.", "Top Detection" or "Top Detect."

[0034] The upper circuit ground is labeled GNDt and the lower circuit ground is labeled GNDb. The upper circuit VDD is V DDtop The lower circuit VDD is V DDbot The upper circuit VSS is V SStop The lower circuit VSS is V SSbot It is written as follows.

[0035] Both the upper and lower circuits are constructed with the same design. Figure 3 provides a more detailed view of the upper part of the half-bridge command circuit, where the upper current mirror circuit 32a is connected to the upper detection circuit 33a through a current transformer 321. Such a current transformer can be replaced with another type of isolation barrier, such as an optocoupler, a current transformer, or a voltage transformer.

[0036] Transistor T5 T and T3 T , resistor RT T and R MonT is used to replicate the gate current provided by the gate buffer to the gate driver through the isolation barrier provided here by the current transformer 321. The detection circuit has several sub-functions: a conditioning circuit C1 that conditions the signal coming from the current transformer 321; B , D1 B and R1 B For overlap detection, transistor Q2 B receives a reference voltage "Ref Bot." at its negative input and triggers comparator 331, which sets the response time of the system. In this design, MOSFET Q1 B and Q3 B The comparator is used to avoid false triggering of the protection. The comparator latches the detected error and transfers the detection result to the controller via the "FaultDetect.Bot" signal, which is necessary to trigger the protection circuit of the lower gate buffer. This protection circuit is implemented by a pull-down diode D3 between the base of gate buffer 1b and the gate electrode of the lower power device shown in Figure 4. B and MOSFET Q5 B The controllable switch function can be implemented using several other known controllable switch components, such as a JFET, a BJT, a HEMT, etc.

[0037] The lower circuit is C1, which conditions the signal coming from current transformer 322. T , D1 T and R1T and the current transformer 322 can be replaced by another type of isolation barrier, such as an optocoupler or a transformer. T triggers a comparator 332 which receives a reference voltage "RefTop" at its negative input. T and Q3 T The comparator is used to avoid false triggering of the protection. The comparator latches the detected error and transfers the detection result to the controller via the "FaultDetect.Bot" signal, which is necessary to trigger the protection circuit of the lower gate buffer using a controllable switch. The controllable switch is a pull-down diode D3 between the base of gate buffer 1a and the gate electrode of the upper power device shown in Figure 4. B and MOSFET Q5 T It consists of:

[0038] In summary, a first switching element S having a first gate H and a second switching element S having a second gate. L and a gate driver circuit of the half-bridge of the conversion device 100, which are independently and complementary controlled by a controller 60 that provides gate pull-up pulse signals and gate pull-down pulse signals to the first gate driver buffer and the second gate driver buffer via a first gate driver buffer 1a and a second gate driver buffer 1b, respectively. a first gate current mirroring circuit 32a in the source branch of the first gate driver buffer 1a, for providing a first sense signal when the first gate driver buffer is turned on, and a second switching element S L a first detection circuit 33a for transferring the signal to a second protection circuit 34b of the second gate driver buffer 1b configured to turn off the a second gate current mirroring circuit 32b in the source branch of the second gate driver buffer 1b, for providing a second sense signal when the second gate driver buffer is turned on, and a second gate current mirroring circuit 32b for processing the first sense signal and for switching on the first switching element S upon the occurrence of the second sense signal; H a second detection circuit 33b for transferring the signal to a first protection circuit 34a of the first gate driver buffer 1a configured to turn off the An overlap protection circuit is provided.

[0039] As mentioned above, since the detection circuits connected to the gate current mirroring circuits refer to the voltages of other gate driver buffers in order to trigger protection of the other gate driver buffers, isolation is required between the detection circuits and the gate current mirroring circuits of the gate driver buffers. As a result, the first detection circuit 33a, e.g., the upper detection circuit, is connected to the first gate current mirroring circuit 32a, e.g., the upper gate current mirroring circuit, via a first current transformer 321 that provides a first isolation barrier, and the second detection circuit 33b, e.g., the lower detection circuit, is connected to the second gate current mirroring circuit 32b, e.g., the lower gate current mirroring circuit, via a second current transformer 322 that provides a second isolation barrier.

[0040] Trigger circuit Q2 of the first detection circuit B and the trigger circuit Q2 of the second detection circuit T are the false detection prevention circuit Q1 B , Q1 T , Q3 B , Q3 T The false detection prevention circuit enables detection of an overlap error only when a detection signal is transmitted when the positive driver command output "vo+" of the opposite pre-driver 10a, 10b is on.

[0041] A latch circuit with comparators 331, 332 latches the detected overlap error and transfers the detected overlap error "Fault Detect." to the controller, which can trigger the opposite gate protection circuits 34a, 34b by sending an error signal "Err. To Bot. Prot." or an error signal "Err. To Top Prot.", respectively. The reset input of the comparator allows the controller to reset the MOSFET transistor Q4 of the upper detection circuit 33a. B and the MOSFET transistor Q4 of the lower detection circuit 33b. T It can be activated by having Rs1 and Rs2 outputs through

[0042] The effect of overlapping control signals is presented in FIG. 5 and explained below.

[0043] Referring to the notation in Figure 1, the initial state corresponds to the freewheeling time, and the load current flows through the upper switch S H At time t0, the control signal switches from a negative value to a positive value, and the switch S L The gate-source voltage V of Q2 GS2 At time t1, the turn-on device S L The gate-source voltage of reaches the threshold, and therefore, S L The drain current, which is the current flowing through the transistor Q2, rises to the load current value. During the Miller plateau from time t2 to time t3, the drain-source voltage V DS2 VDC drops to 0, and switch S H The drain-source voltage V of Q1 DS1 From time t3 to time t4, the gate-source voltage V of Q2 GS2continues to rise, but the power waveform remains unchanged. At time t5, a signal is sent to the gate of the second switch Q1 regarding improper operation due to one or several of the reasons listed above. At time t6, as soon as the gate voltage reaches the threshold, Q1 becomes short-circuited since it conducts simultaneously with Q2. The current through these switches rises to a limit set by the impedance of the entire switching cell. In fact, it can reach several kA, potentially destroying the power devices. After a certain time, a slight decrease in the current is observed as the on-state resistance increases due to self-heating of the power devices. Both elements share the DC bus voltage according to their transconductance.

[0044] The impact of the proposed protection method is then introduced, and updated waveforms are presented in Figure 6. When the gate driver includes overlap protection, the turn-on behavior of Q2 remains unchanged from t0 to t4. The change occurs during the erroneous turn-on of Q1. In fact, at t5, an erroneous signal is sent to the gate driver, causing the gate voltage to start rising and a positive gate current to be detected. At t6, the threshold is reached, and the current therefore begins to rise. However, after a short delay, feedback of the gate current detected by Q1 is sent to the gate driver of Q2, forcing it to turn off. Thus, the short circuit is stopped before it leads to a catastrophic failure.

[0045] The above description is based on a MOSFET application as depicted in FIG. 1, but can be extended to any unipolar transistor such as a JFET, IGFET, HEMT, or bipolar transistor BJT or IGBT by changing the electrode names, as known to those skilled in the art.

[0046] The present disclosure is not limited to the above description, and in particular the overlap protection circuit described herein can be used in a converter having two or more half bridges, each half bridge being provided with such protection circuitry for its upper and lower switches.

Claims

1. 1. A gate driver circuit for a half bridge of a converter, wherein a first switching element having a first gate and a second switching element having a second gate are independently and complementary controlled via a first gate driver buffer and a second gate driver buffer by a controller that provides gate pull-up pulse signals and gate pull-down pulse signals to the first gate driver buffer and the second gate driver buffer, respectively, the gate driver circuit comprising: a first gate current mirroring circuit in a source branch of the first gate driver buffer, the first gate current mirroring circuit providing a first detection signal when the first gate driver buffer is turned on, and a first detection circuit processing and forwarding the first detection signal to a second protection circuit of the second gate driver buffer, the second protection circuit configured to turn off the second switching element when the first detection signal occurs; a second gate current mirroring circuit in a source branch of the second gate driver buffer, the second gate current mirroring circuit providing a second detection signal when the second gate driver buffer is turned on, and a second detection circuit processing and forwarding the first detection signal to a first protection circuit of the first gate driver buffer, the first protection circuit being configured to turn off the first switching element when the second detection signal occurs; 1. A gate driver circuit for a half bridge of a converter, comprising an overlap protection circuit comprising:

2. 2. The gate driver circuit for a half bridge of a converter according to claim 1, wherein the first detection circuit is connected to the first gate current mirroring circuit through a first insulation barrier, and the second detection circuit is connected to the second gate current mirroring circuit through a second insulation barrier.

3. 3. The gate driver circuit for a half bridge of a converter device according to claim 2, wherein the first isolation barrier and the second isolation barrier are composed of a current transformer, an optocoupler, or a voltage transformer.

4. The gate driver circuit for a half bridge of a conversion device according to any one of claims 1 to 3, wherein the first detection circuit and the second detection circuit each comprise an adjustment circuit.

5. 4. The gate driver circuit for a half bridge of the conversion device according to claim 1, wherein each of the first detection circuit and the second detection circuit includes a trigger circuit and an erroneous detection prevention circuit that enables detection of an overlap error only when a detection signal is transmitted when a positive driver command output of an opposing pre-driver is on.

6. 6. The gate driver circuit for a half-bridge of a conversion device of claim 5, wherein the first detection circuit and the second detection circuit each include a latch circuit that latches a detected overlap error, transfers the detected overlap error to the controller, and triggers the protection circuit.

7. 7. The gate driver circuit for a half-bridge of a converter device according to claim 6, wherein each of the first protection circuit and the second protection circuit is composed of at least one controllable switch that pulls down a gate electrode of a corresponding switching element.

8. 8. The gate driver circuit for a half-bridge of a converter as claimed in claim 7, wherein the at least one controllable switch comprises a diode and a MOSFET.

9. 7. The gate driver circuit for a half bridge of a converter according to claim 6, wherein the controller comprises a reset output for resetting the detection circuit.

10. 10. The gate driver circuit for a half bridge of a converter according to claim 9, wherein the reset output is connected to the reset input of the latch circuit via an isolation element.

11. 4. The gate driver circuit of claim 1, wherein the gate driver buffer associated with the gate current mirroring circuit is driven by a pre-driver circuit that transfers control signals from the controller to the gate driver buffer and provides galvanic isolation between the controller and the gate driver buffer.

12. A converter comprising at least a half bridge comprising a gate driver circuit according to any one of claims 1 to 3.

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