3D Crosspoint Nonvolatile Memory

Abstract

A nonvolatile memory having a 3D cross-point architecture and double cell density is provided, in which vertically stacked word lines extend in-plane (i.e., parallel) to the substrate and bit lines extend perpendicular to the vertically stacked word lines. The vertically stacked word lines are located within a patterned dielectric material stack including alternating first dielectric material layers and recessed second dielectric material layers. The first dielectric material layers vertically separate each word line in each vertical stack of word lines, and the recessed second dielectric material layers are located laterally adjacent to the word lines. A dielectric switching material layer is located between each word line / bit line combination. Some of the bit lines are located within the dielectric material stack and some of the bit lines are located within an interlevel dielectric material layer.

Description

[Technical Field]

[0001] This application relates to semiconductor technology, and more particularly to non-volatile memories having a three-dimensional (3D) cross-point architecture and methods for forming the same.

[0002] Non-volatile memory (NVM) or non-volatile storage is a type of computer memory that can retain stored information even after power is removed. In contrast, volatile memory requires sustained power to retain data. NVM, such as resistive random access memory (ReRAM), phase change random access memory (PCRAM), and conductive bridge random access memory (CBRAM), is gaining renewed attention for its potential application to neuromorphic computing, with in-memory processing capabilities that significantly reduce power consumption and eliminate data busing time between the memory and central processing unit (CPU) of traditional complementary metal oxide semiconductor (CMOS)-based neuromorphic computing.

[0003] ReRAM (or sometimes referred to as RRAM®) is considered an electronic synaptic device or memristor for neuromorphic computing and a promising technology for high-density and high-speed NVM applications. In neuromorphic computing applications, resistive memory devices such as ReRAM devices can be used as connections (i.e., synapses) between pre-neurons and post-neurons, where the connection weights are represented in the form of device resistances.

[0004] Cross-point memory architectures, especially 3D cross-point ReRAM architectures, are particularly attractive. In cross-point memories, memory cells occur at the overlaps between word lines and bit lines. In particular, in the case of ReRAM and in such memory element materials, conductive filaments are provided between the word lines and bit lines. 3D cross-point architectures offer improved density over non-3D cross-point architectures by stacking memory cells layer by layer. Summary of the Invention

[0005] An NVM having a 3D cross-point architecture and double cell density is provided, in which vertically stacked word lines extend in-plane (i.e., parallel) to the substrate and bit lines extend perpendicular to the vertically stacked word lines. The vertically stacked word lines are located within a patterned dielectric material stack including alternating first dielectric material layers and recessed second dielectric material layers. The first dielectric material layers vertically separate each word line in each vertical stack of word lines, and the recessed second dielectric material layers are located laterally adjacent to the word lines. A dielectric switching material layer is located between each word line / bit line combination. Some of the bit lines are located within the dielectric material stack and some of the bit lines are located within an interlevel dielectric material layer.

[0006] In one aspect of the present application, an NVM cell having a 3D cross-point architecture is provided. In one embodiment, the NVM cell includes a plurality of vertically stacked word lines extending parallel to a top horizontal surface of a substrate, where each word line of the plurality of vertically stacked word lines is vertically separated by a first dielectric material layer, and each word line of the plurality of word lines has a first sidewall contacting a second dielectric material layer and a second sidewall opposite the first sidewall contacting an interlayer dielectric material layer, where the second dielectric material layer has a lateral width smaller than that of the first dielectric material layer. At least one first bit line is located within a dielectric material stack including a portion of each of the first and second dielectric material layers, and at least one second bit line is located within the interlayer dielectric material layer. According to the present application, the at least one first bit line and the at least one second bit line extend perpendicular to the plurality of vertically stacked word lines and are in direct contact with the top horizontal surface of the substrate. A dielectric switching material layer is located on the sidewalls of both the at least one first bit line and the at least one second bit line, where the dielectric switching material layer surrounding the first bit line separates the first bit line from each word line of the plurality of vertically stacked word lines, and the dielectric switching material layer surrounding the second bit line separates the second bit line from each word line of the plurality of vertically stacked word lines.

[0007] In an embodiment of the present application, the second sidewall of each wordline is vertically aligned with the outermost sidewall of each of the first dielectric material layers.

[0008] In embodiments, the first dielectric material layer is composed of a compositionally different dielectric material than the dielectric material providing the second dielectric material layer, hi one example, the first dielectric material is composed of silicon dioxide and the second dielectric material is composed of silicon nitride.

[0009] In an embodiment of the present application, a bottommost wordline of the plurality of vertically stacked wordlines is separated from the substrate by a bottommost first layer of dielectric material.

[0010] In an embodiment of the present application, each word line, the at least one first bit line and the at least one second bit line are made of an oxygen-deficient conductive material.

[0011] In an embodiment of the present application, the dielectric switching material layer is composed of a dielectric metal oxide.

[0012] In an embodiment of the present application, the substrate includes one or more selector devices.

[0013] In an embodiment of the present application, the at least one first bit line includes a plurality of first bit lines, and the at least one second bit line includes a plurality of second bit lines.

[0014] In an embodiment of the present application, the at least one first bit line and the at least one second bit line are arranged in the same row.

[0015] In an embodiment of the present application, the at least one first bit line has a top surface that is coplanar with a top surface of each of the at least one second bit line and the interlayer dielectric material layer.

[0016] In another aspect of the present application, a method for forming an NVM cell having a 3D cross-point architecture is provided. In one embodiment, the method includes providing at least one patterned dielectric material stack overlying a substrate, the at least one patterned dielectric material stack including alternating first and second dielectric material layers. Next, each second dielectric material layer of the at least one patterned dielectric material stack is recessed to provide a recessed second dielectric material layer. Word lines are then formed laterally adjacent to each recessed second dielectric material layer. An interlayer dielectric (ILD) material layer is then formed laterally adjacent to the at least one patterned dielectric material stack. Next, a first set of openings is formed in each first dielectric material layer and each recessed second dielectric material layer of the at least one patterned dielectric material stack, and a second set of openings is formed in the ILD material layer, wherein the first set of openings and the second set of openings physically expose the substrate. A dielectric switching material layer is then formed, lining the sidewalls of both the first set of openings and the second set of openings, and then a first bit line is formed in the remaining portion of each of the first set of openings and a second bit line is formed in the remaining portion of the second set of openings, wherein the first bit line and the second bit line are in direct physical contact with the substrate and are laterally surrounded by the dielectric switching material layer.

[0017] In an embodiment of the present application, each of the first dielectric material layers has a lateral width greater than a lateral width of the recessed second dielectric material layer.

[0018] In an embodiment of the present application, the recessing step comprises an isotropic lateral etch, such that a gap is formed laterally adjacent the recessed second layer of dielectric material.

[0019] In an embodiment of the present application, forming the word lines includes depositing an oxygen-deficient conductive material, laterally etching the conductive material, and cutting the conductive material formed around an edge of each recessed second dielectric material layer of the at least one patterned dielectric material stack.

[0020] In an embodiment of the present application, each word line has a first sidewall that contacts the sidewall of a laterally adjacent recessed second dielectric material layer, and a second sidewall opposite the first sidewall and vertically aligned with the outermost sidewall of each of the first dielectric material layers.

[0021] In an embodiment of the present application, forming the dielectric switching material layer comprises depositing a dielectric metal oxide in each of the first set of openings and the second set of openings by atomic layer deposition, and removing the dielectric metal oxide from a bottom of each of the first set of openings and the second set of openings to physically expose the substrate.

[0022] In an embodiment of the present application, the first dielectric layer is composed of a dielectric material that is compositionally different from the dielectric material that provides the second dielectric layer.

[0023] In an embodiment of the present application, each of the word lines extends parallel to a horizontal plane of the substrate; and the first bit line and the second bit line extend perpendicular to each word line.

[0024] In an embodiment of the present application, the step of forming the first set of openings and the second set of openings comprises lithography and etching.

[0025] In an embodiment of the present application, forming the at least one patterned dielectric material stack comprises forming a dielectric material stack of alternating blanket layers of a first dielectric material and a second dielectric material, and patterning the dielectric material stack by lithography and etching. [Brief explanation of the drawings]

[0026] [Figure 1] 3D view of an exemplary structure that may be employed in accordance with one embodiment of the present application, the exemplary structure including a dielectric material stack of alternating blanket layers of a first dielectric material and a second dielectric material positioned above a substrate.

[0027] [Figure 2] 2 is a 3D view of the exemplary structure of FIG. 1 after patterning the dielectric material stack to provide at least one patterned dielectric material stack including alternating layers of a first dielectric material and a second dielectric material.

[0028] [Figure 3] 3D view of the exemplary structure of FIG. 2 after recessing each second dielectric material layer of at least one patterned dielectric material stack to provide a recessed second dielectric material layer.

[0029] [Figure 4] 4 is a 3D view of the example structure of FIG. 3 after forming laterally adjacent word lines in each recessed second dielectric material layer.

[0030] [Figure 5] 5 is a 3D view of the example structure of FIG. 4 after forming an inter-layer dielectric (ILD) material layer laterally adjacent to at least one patterned dielectric material stack.

[0031] [Figure 6]FIG. 6 is a 3D view of the exemplary structure of FIG. 5 after forming a first set of openings in each first dielectric material layer and each recessed second dielectric material layer of at least one patterned dielectric material stack, and a second set of openings in an ILD material layer, wherein the first set of openings and the second set of openings physically expose the substrate.

[0032] [Figure 7A] 7 is a 3D view of the example structure of FIG. 6 after forming a dielectric switching material layer lining the sidewalls of both the first set of openings and the second set of openings.

[0033] [Figure 7B] 7B is a 3D view of the exemplary structure shown in FIG. 7A illustrating the dielectric switching material layer formed in both the first set of openings and the second set of openings; in this drawing, portions of each first dielectric material layer and each recessed second dielectric material layer located on the front side of the structure are not shown to expose the dielectric switching material layer.

[0034] [Figure 8A] 7B is a 3D view of the exemplary structure of FIG. 7A after forming a first bit line within the remaining portion of each of the first set of openings and a second bit line within the remaining portion of each of the second set of openings, each of the first and second bit lines being laterally surrounded by one of the dielectric switching material layers and having a bottom surface in direct contact with the surface of the substrate.

[0035] [Figure 8B] 8B is a 3D view of the exemplary structure shown in FIG. 8A illustrating the dielectric switching material layer and bit lines formed in each of the first set of openings and the second set of openings; in this drawing, portions of each first dielectric material layer and each recessed second dielectric material layer located on the front side of the structure are not shown to facilitate viewing of the dielectric switching material layer surrounding the first and second bit lines.

[0036] [Figure 9A] FIG. 1 is a top view of an NVM cell having a 3D cross-point architecture according to one embodiment of the present application; the drawing includes a cut line XX through one row of ReRAM devices and a cut line YY between two adjacent rows of ReRAM devices.

[0037] [Figure 9B] FIG. 9B is a cross-sectional view taken along the line XX shown in FIG. 9A.

[0038] [Figure 9C] FIG. 9B is a cross-sectional view taken along the line YY shown in FIG. 9A. DETAILED DESCRIPTION OF THE INVENTION

[0039] The present application will now be discussed in more detail by reference to the following description and the drawings that accompany this application. It should be noted that the drawings herein are provided for illustrative purposes only, and therefore the drawings are not drawn to scale. It should also be noted that like and corresponding elements are referred to by like reference numerals.

[0040] In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps, and techniques, to provide an understanding of various embodiments of the present application. However, it will be understood by those skilled in the art that various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail to avoid obscuring the present application.

[0041] When an element, such as a layer, region, or substrate, is referred to as being "on" or "over" another element, it will be understood that the element can be directly on the other element, or that intervening elements can be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. When an element is referred to as being "beneath" or "under" another element, it will also be understood that the element can be directly below or under the other element, or that intervening elements can be present. In contrast, when an element is referred to as being "directly beneath" or "directly under" another element, there are no intervening elements present.

[0042] In conventional 3D cross-point ReRAM architectures, integration issues and cell density penalties are common problems. The present application overcomes these problems by providing an NVM with a 3D cross-point architecture in which vertically stacked word lines extend in-plane (i.e., parallel) to the substrate and bit lines extend perpendicular to the vertically stacked word lines. In other words, the length of the word lines extends parallel to the substrate, and the length of the bit lines extends perpendicular to the word lines. The vertically stacked word lines are located within a patterned dielectric material stack including alternating first dielectric material layers and recessed second dielectric material layers. The first dielectric material layer vertically separates each word line in each vertical stack of word lines, and the recessed second dielectric material layer is located laterally adjacent to the word lines. A dielectric switching material layer is located between each word line / bit line combination. Some of the bit lines are located within the dielectric material stack, and some of the bit lines are located within the interlayer dielectric material layer.

[0043] Referring first to FIG. 1 , an exemplary structure that may be employed in accordance with one embodiment of the present application is illustrated. The exemplary structure illustrated in FIG. 1 includes a dielectric material stack 12 of alternating blanket layers of a first dielectric material and a second dielectric material positioned above a substrate 10. The term “blanket layer” refers to a layer formed entirely above the substrate 10 without undergoing a patterning process. Each blanket layer of a first dielectric material in the dielectric material stack 12 may be referred to as a first dielectric material blanket layer 14L, and each blanket layer of a second dielectric material in the dielectric material stack may be referred to as a second dielectric material blanket layer 16L. Herein, each second dielectric material blanket layer 16L is sandwiched between a bottom first dielectric material blanket layer and a top first dielectric material blanket layer. Herein, the dielectric material stack includes “n” second dielectric material blanket layers 16L and “n+1” first dielectric material blanket layers 14L, where “n” is an integer starting from 2. In the drawings, and as an example, the dielectric material stack 12 includes four first dielectric material blanket layers 14L and three second dielectric material blanket layers 16L.

[0044] The substrate 10 may be a front-end-of-the-line (FEOL) level, a middle-of-the-line (MOL) level, a lower interconnect level, or any combination thereof; each combination includes a FEOL as the lowest level of the substrate 10. In one example, the substrate 10 is a FEOL level and a MOL level. In another example, the substrate 10 is a FEOL level, a MOL level, and a lower interconnect level. The FEOL level is a level of semiconductor structure including one or more semiconductor devices, such as one or more selector devices, e.g., transistors and / or diodes, formed on or within a semiconductor substrate. The one or more selector devices typically include an array of selector devices arranged in rows and columns. The MOL level includes one or more MOL electrically conductive structures (vias and / or lines) embedded within a layer of MOL dielectric material. The lower interconnect level includes one or more interconnect structures embedded within interconnect dielectric material. The FEOL levels, MOL levels, and / or lower interconnect levels that may be used to provide substrate 10 may comprise materials known to those skilled in the art, and such levels may be formed utilizing techniques similarly known to those skilled in the art. In order not to obscure the methods herein, the materials and processing techniques used to provide the FEOL levels, MOL levels, and / or lower interconnect levels will not be described herein.

[0045] The first and second dielectric materials employed herein are electrically insulating materials, such as silicon dioxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicoboron carbonitride, or silicon carbonate, except that the first dielectric material is compositionally different from the second dielectric material. The compositional difference between the first and second dielectric materials is required to provide etch selectivity between the two different dielectric materials, such that the second dielectric material can be selectively etched relative to the first dielectric material. In one example, each first dielectric material blanket layer 14L of the dielectric material stack 12 is composed of silicon dioxide, while each second dielectric material blanket layer 16L of the dielectric material stack 12 is composed of silicon nitride.

[0046] The dielectric material stack 12, including each first dielectric material blanket layer 14L and each second dielectric material blanket layer 16L, may be formed by, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In some embodiments, the first dielectric material blanket layer 14L and the second dielectric material blanket layer 16L may be formed using the same deposition process. In one example, the first dielectric material blanket layer 14L and the second dielectric material blanket layer 16L may be formed by CVD. In other embodiments, the first dielectric material blanket layer 14L and the second dielectric material blanket layer 16L may be formed using different deposition processes. In one example, the first dielectric material blanket layer 14L may be formed by CVD, while the second dielectric material blanket layer 16L may be formed by ALD.

[0047] Each first dielectric material blanket layer 14L and each second dielectric material blanket layer 16L may have a thickness of 10 nm to 100 nm; however, other thicknesses for each first dielectric material blanket layer 14L and each second dielectric material blanket layer 16L are contemplated and may be used herein as the thicknesses of the first dielectric material blanket layer 14L and each second dielectric material blanket layer 16L. Each first dielectric material blanket layer 14L may have the same or different thickness as each other. Similarly, each second dielectric material blanket layer 16L may have the same or different thickness as each other. Each first dielectric material blanket layer 14L may have the same or different thickness as each second dielectric material blanket layer 16L.

[0048] 2, the exemplary structure of FIG. 1 is shown after patterning the dielectric material stack 12, including each first dielectric material blanket layer 14L and each second dielectric material blanket layer 16L, to provide at least one patterned dielectric material stack 12S, including alternating layers of first and second dielectric materials. Each patterned blanket layer of the first dielectric material is referred to herein as a first dielectric material layer 14, and each patterned blanket layer of the second dielectric material is referred to herein as a second dielectric material layer 16.

[0049] The number of patterned dielectric material stacks 12S formed can vary and is not limited to the two illustrated in FIG. 2 . In embodiments, a single patterned dielectric material stack 12S can be formed, while in other embodiments, two or more patterned dielectric material stacks 12S can be formed. Each patterned dielectric material stack 12S is typically square or rectangular in shape. Each patterned dielectric material stack 12S can have a length of 50 nm to 10,000 nm and a lateral width of 90 nm to 1,000 nm; however, other lengths and lateral widths are contemplated and may be used herein for each patterned dielectric material stack 12S.

[0050] Patterning to provide at least one patterned dielectric material stack 12S includes lithography and etching. Lithography includes depositing at least one photoresist material on the dielectric material stack 12S, exposing the as-deposited photoresist material to a pattern of radiation (here, forming the patterned dielectric material stack 12S shown in FIG. 2, where the pattern of radiation is a rectangular or square cell pattern), and developing the exposed as-deposited photoresist material. In embodiments, one or more photolithographic masking layers, such as a bottom antireflective coating (BARC), can be formed between the dielectric material stack 12S and the as-deposited photoresist material. In FIG. 2, the as-deposited photoresist material and the optional one or more photolithographic masking layers are not shown because both the as-deposited photoresist material and the optional one or more photolithographic masking layers are removed from the structure after the dielectric material stack 12 is patterned. The etching step used to pattern the dielectric material stack 12 includes a wet etching process or a dry etching process. The etching stops on the top horizontal surface of the substrate 10. In one example, the etching includes a fluorine-based plasma etch. Etching the dielectric material stack 12 is much simpler than etching through a material stack including alternating layers of dielectric material and electrically conductive metal-containing material, which is typically used in the prior art in forming NVMs including 3D architectures.

[0051] 3, the exemplary structure of FIG. 2 is illustrated after each second dielectric material layer 16 of the at least one patterned dielectric material stack 12S has been recessed to provide a recessed second dielectric material layer 16R. Each recessed second dielectric material layer 16R has a lateral width that is smaller than the lateral width of each second dielectric material layer 16 and each first dielectric material layer 14. In one example, each recessed second dielectric material layer 16R has a lateral width of 25 nm to 100 nm.

[0052] The recessing step provides gaps 18 laterally adjacent each recessed second dielectric material layer 16R, with each gap 18 being located between the bottom and top first dielectric material layers as shown in Figure 3. Each gap 18 represents a depression in at least one patterned dielectric material stack 12S that will subsequently accommodate a wordline.

[0053] The recessing step is performed utilizing an isotropic lateral etching process that is selective in removing the above-mentioned second dielectric material relative to the above-mentioned first dielectric material. In one example, and where the first dielectric material is comprised of silicon dioxide and the second dielectric material is comprised of silicon nitride, the isotropic lateral etching may include a high temperature phosphoric acid wet etch or a fluorine-based plasma etch, which are commercially available and widely used in the industry.

[0054] 4, the exemplary structure of FIG. 3 is illustrated after forming laterally adjacent word lines 20 in each recessed second dielectric material layer 16R. Each word line 20 has a first sidewall that contacts the sidewall of the laterally adjacent recessed second dielectric material layer 16R and a second sidewall opposite the first sidewall and vertically aligned with the outermost sidewall of the first dielectric material layer 14. Each word line 20 is comprised of an oxygen-deficient conductive material. Examples of such conductive materials that may be employed herein in providing word lines 20 include, but are not limited to, titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), ruthenium nitride (RuN), ruthenium-tantalum alloy (RuTa), RuTaN, cobalt (Co), nickel (Ni), copper (Cu), tungsten (W), tungsten nitride (WN), silver (Ag), platinum (Pt), palladium (Pd), or aluminum (Al).

[0055] Each word line 20 may be formed by first depositing a conductive material using a deposition process such as CVD, PECVD, PVD, or ALD. The deposition process fills each of the gaps 18 entirely so that the conductive material is flush with the sidewalls of the laterally adjacent recessed second dielectric material layer 16R. Following deposition of the conductive material, a lateral etching technique is used to remove the portion of the as-deposited conductive material located outside each of the gaps 18. After this lateral etching, the conductive material surrounding each end segment of each recessed second dielectric material layer 16R (connected by the conductive material on the left and right sides of each recessed second dielectric material layer 16R per patterned dielectric material stack 12S) is removed using a metal cutting process including lithography and etching. The metal cutting process ensures that the conductive material remaining in each gap 18 on the left-hand side of each patterned dielectric material stack 12S is not connected to the conductive material remaining in each gap 18 located on the right-hand side of each patterned dielectric material stack. The remaining, now separated, conductive material in gaps 18 defines word lines 20 of the present application.

[0056] Within each patterned dielectric material stack 12S, the word lines 20 are vertically stacked (in columns), and the vertically stacked word lines 20 are separated vertically by a portion of the patterned first dielectric material layer 12. Rows of word lines 20 within at least one patterned dielectric material stack 12S are laterally separated by a recessed second dielectric material layer 16R. Multiple vertically stacked word lines may be arranged in rows and columns.

[0057] 5, the exemplary structure of FIG. 4 is illustrated after forming an interlayer dielectric (ILD) material layer 22 laterally adjacent to at least one patterned dielectric material stack 12S. The ILD material layer 22 has a top surface that is coplanar with the top surface of the uppermost first dielectric material layer. In some embodiments, a seam 23 may be formed in the ILD material layer 22 located between two laterally adjacent patterned dielectric material stacks 12S. This seam is not illustrated in the remaining figures of this application.

[0058] The ILD material layer 22 is composed of a dielectric material having electrically insulating properties, including, but not limited to, silicon dioxide, silicon nitride, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), spin-on low-k dielectric materials, chemical vapor deposition (CVD) low-k dielectric materials, or any combination thereof, including multiple layers. As used throughout this application, the term "low-k" refers to a dielectric material having a dielectric constant less than 4.0. All dielectric constants referred to herein are measured in a vacuum unless otherwise specified. Exemplary low-k dielectric materials that can be used include, but are not limited to, silsesquioxanes, C-doped oxides (i.e., organosilicates) containing atoms of Si, C, O, and H, and thermosetting polyarylene ethers, or multiple layers thereof. The term "polyarylene" is used herein to denote aryl or inertly substituted aryl moieties that are linked together by bonds, fused rings, or inert linking groups such as oxygen, sulfur, sulfone, sulfoxide, carbonyl, and the like.

[0059] ILD material layer 22 may be formed using a deposition process including, for example, CVD, PECVD, ALD, evaporation, or spin-on coating. A planarization process, such as chemical mechanical polishing (CMP), may follow the deposition of the dielectric material, resulting in ILD material layer 22.

[0060] 6, the exemplary structure of FIG. 5 is illustrated after forming a first set of openings 24 in the first dielectric material layer 14 and the recessed second dielectric material layer 16R and a second set of openings 25 in the ILD material layer 22 of at least one patterned dielectric material stack 12S, with the first set of openings 24 and the second set of openings 25 extending downward to physically expose the substrate 10. Note that the first set of openings 24 passes through the first dielectric material layer 14 and the recessed second dielectric material layer 16R, but does not pass through any of the wordlines 20. However, the first set of openings 24 exposes the sidewalls of each vertically stacked wordline 20 in each patterned dielectric material stack 12S.

[0061] The first set of openings 24 and the second set of openings 25 may be formed by lithography and etching. For the lithography step, a hole pattern is formed in a photoresist material, which is transferred to the underlying structure as defined above. For the etching step, one or more etching processes may be employed, including dry etching and / or chemical wet etching. The etching process or processes used to form the first set of openings 24 and the second set of openings 25 stop on the surface of the substrate 10, and each of the first set of openings 24 and the second set of openings 25 will subsequently accommodate the dielectric switching material layer and bit lines. In some embodiments, the first set of openings 24 and the second set of openings 25 may be formed simultaneously. In other embodiments, the first set of openings 24 and the second set of openings 25 are formed at different times, for example, the first set of openings 24 may be formed first, followed by the second set of openings 25, or vice versa. If the first set of openings 24 and the second set of openings 25 are formed at different times, the etch used to form the openings 24 can be the same or different from the etch used to form the openings 25. The number of openings 24 can vary (here, at least one, more typically two or more openings 24 are formed), as can the number of openings 25 (here, at least one, more typically two or more openings 25 are formed). The number of openings providing the first set of openings 24 can be the same as or different from the number of openings providing the second set of openings 25. The first set of openings 24 and the second set of openings 25 can be formed in rows and columns, as shown in FIG.

[0062] 7A, the exemplary structure of FIG. 6 is illustrated after forming a dielectric switching material layer 26 lining the sidewalls of each of the first set of openings 24 and the second set of openings 25. FIG. 7B illustrates the exemplary structure shown in FIG. 7A illustrating the dielectric switching material layer 26 formed in each of the first set of openings 24 and the second set of openings 25; in this drawing, the first dielectric material layers 14 and the recessed second dielectric material layers 16R located on the front side of the structure are not shown to facilitate viewing of the dielectric switching material layers 26. In this application, each dielectric switching material layer 26 contacts the sidewalls of a vertically stacked wordline 20.

[0063] Each dielectric switching material layer 26 may be composed of a dielectric metal oxide material having a dielectric constant of 4.0 or greater. Each dielectric switching material layer 26 is electrically insulating at this point in the application, and during operational use, the dielectric switching material layer 26 may be converted to electrically conductive filaments. After use, the electrically conductive filaments return to their insulating state. Examples of dielectric metal oxides that may be employed as the dielectric switching material layer 26 include, but are not limited to, hafnium oxide (HfO x ), tantalum oxide (TaO x ), titanium oxide (TiO x ), aluminum oxide (AlO x), silicon dioxide (SiO2), or a combination thereof, where x is 1.5 to 3.5. The dielectric metal oxide providing each dielectric switching material layer 26 is formed by ALD, and following the ALD process, etching may be used to remove the dielectric metal oxide formed on the surface of the substrate 10 within each of the first set of openings 24 and the second set of openings 25. Each dielectric switching material layer 26 within the first set of openings 24 thus lines the first set of openings 24, and each dielectric switching material layer 26 within the second set of openings 25 thus lines the second set of openings 25. The dielectric switching material layer 26 may have a thickness of 1 nm to 30 nm; however, other thicknesses are contemplated and may be used as the thickness of the dielectric switching material layer 26, so long as the dielectric switching material layer 26 does not fill the entire volume of the openings providing the first set of openings 24 and the openings providing the second set of openings 25.

[0064] 8A , the exemplary structure of FIG. 7A is shown after forming first bit lines 28 in the remaining portions of each of the first set of openings 24 and second bit lines 29 in the second set of openings 25, with each first bit line 28 and each second bit line 29 being laterally surrounded by one of the dielectric switching material layers 28 and having a bottom surface in direct contact with the surface of the substrate 10. FIG. 8B shows the exemplary structure shown in FIG. 8A illustrating the dielectric switching material layer 26 and the first bit lines 28 formed in each of the first set of openings 24 and the second bit lines 29 formed in each of the second set of openings 25; in this drawing, the first dielectric material layers 14 and recessed second dielectric material layers 16R located on the front side of the structure are not shown to facilitate viewing the dielectric switching material layers 26 surrounding the first bit lines 28 and second bit lines 29.

[0065] Each of the first bit lines 28 and each of the second bit lines 29 is composed of one of the conductive materials mentioned above with respect to the word lines 20. The conductive material providing each of the first bit lines 28 and each of the second bit lines 29 can be compositionally the same as or compositionally different from the conductive material providing the word lines 20. The conductive material can be formed utilizing one of the deposition processes mentioned above in forming the word lines 20. After depositing the conductive material providing each of the first bit lines 28 and each of the second bit lines 29, a planarization process such as CMP can be used to provide the planar structure shown in FIGS. 8A and 8B , where the top surface of each of the first bit lines 28 and each of the second bit lines 29 is coplanar with the top surface of the ILD material layer 22 and the top surface of the uppermost first dielectric material layer 14.

[0066] As shown, each word line 20 extends in a first direction parallel to the horizontal top surface of substrate 10, while each first bit line 28 and each second bit line 29 extends in a second direction different from the first direction and perpendicular to the vertically stacked word lines 20; thus providing a cross-point memory. As further shown, each first bit line 28 and each second bit line 29 has a bottom surface in direct physical contact with substrate 10.

[0067] 9A, a top view of an NVM cell having a 3D cross-point architecture according to one embodiment of the present application is illustrated; the drawing includes a section line XX (see FIG. 9B) through one row of ReRAM devices and a section line YY (see FIG. 9C) between two adjacent rows of ReRAM devices. In the top view shown in FIG. 9A, a portion of the top patterned first material layer 14 is not shown to reveal the recessed second dielectric material underneath.

[0068] In particular, the NVM cell having a 3D cross-point architecture illustrated in Figures 8A-8B and 9A, 9B, and 9C includes a plurality of vertically stacked word lines extending parallel to the top horizontal surface of the substrate 10, wherein each word line 20 of the plurality of vertically stacked word lines is vertically separated by a first dielectric material layer 14, and each word line 20 of the plurality of word lines 20 has a first sidewall in contact with a second dielectric material layer (i.e., a recessed second dielectric material layer 16R) and a second sidewall opposite the first sidewall in contact with the interlayer dielectric material layer 22, wherein the second dielectric material layer (i.e., the recessed second dielectric material layer 16R) has a lateral width smaller than the lateral width of the first dielectric material layer 14. At least one first bit line 28 is located within the dielectric material stack including a portion of each first dielectric material layer 14 and each second dielectric material layer (i.e., recessed second dielectric material layer 16R), and at least one second bit line 29 is located within the interlevel dielectric material layer 22. In accordance with the present application, the at least one first bit line 28 and the at least one second bit line 29 extend perpendicular to the plurality of vertically stacked word lines and are in direct contact with the top horizontal surface of the substrate 10. A dielectric switching material layer 26 is located on the sidewalls of both the at least one first bit line 28 and the at least one second bit line 29, where the dielectric switching material layer 26 surrounding the at least one first bit line 28 separates the at least one first bit line 28 from each word line 20 of the multiple vertically stacked word lines, and the dielectric switching material layer 26 surrounding the at least one second bit line 29 separates the at least one second bit line 29 from each word line 20 of the multiple vertically stacked word lines. The NVM cell illustrated in Figures 8A-8B and 9A, 9B, and 9C has twice the density as a conventional NVM cell with a 3D cross-point architecture.

[0069] While the present application has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and detail may be made therein without departing from the spirit and scope of the present application. It is therefore intended that the present application not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.

Claims

1. A non-volatile memory (NVM), comprising: a plurality of vertically stacked wordlines extending parallel to a top horizontal surface of a substrate, wherein each wordline of the plurality of vertically stacked wordlines is vertically separated by a first dielectric material layer, and each wordline of the plurality of vertically stacked wordlines has a first sidewall in contact with a second dielectric material layer and a second sidewall opposite the first sidewall in contact with an interlevel dielectric material layer, wherein the second dielectric material layer has a lateral width that is smaller than a lateral width of the first dielectric material layer; at least one first bit line located within a dielectric material stack including a portion of each of the first dielectric material layers and each of the second dielectric material layers; at least one second bit line located within the interlevel dielectric material layer, wherein the at least one first bit line and the at least one second bit line extend perpendicular to the plurality of vertically stacked word lines and are in direct contact with the top horizontal surface of the substrate; and a dielectric switching material layer located on sidewalls of both the at least one first bit line and the at least one second bit line, wherein the dielectric switching material layer surrounding the at least one first bit line separates the at least one first bit line from each word line of the plurality of vertically stacked word lines, and the dielectric switching material layer surrounding the at least one second bit line separates the at least one second bit line from each word line of the plurality of vertically stacked word lines; An NVM comprising:

2. 2. The NVM of claim 1, wherein the second sidewall of each wordline is vertically aligned with an outermost sidewall of each first dielectric material layer.

3. 10. The NVM of claim 1, wherein the first dielectric material layer is composed of a dielectric material that is compositionally different from a dielectric material that provides the second dielectric material layer.

4. 2. The NVM of claim 1, wherein a bottom-most word line of the plurality of vertically stacked word lines is separated from the substrate by a bottom-most first layer of dielectric material.

5. 10. The NVM of claim 1, wherein each word line, the at least one first bit line, and the at least one second bit line are comprised of an oxygen-deficient conductive material.

6. The NVM of claim 1 , wherein the dielectric switching material layer is composed of a dielectric metal oxide.

7. The NVM of claim 1 , wherein the substrate includes one or more selector devices.

8. The NVM of claim 1 , wherein the at least one first bit line comprises a plurality of first bit lines and the at least one second bit line comprises a plurality of second bit lines.

9. The NVM of claim 1 , wherein the at least one first bit line and the at least one second bit line are arranged in the same row.

10. 2. The NVM of claim 1, wherein the at least one first bit line has a top surface that is coplanar with a top surface of each of the at least one second bit line and the layer of interlayer dielectric material.

11. 1. A method of forming a non-volatile memory, the method comprising: providing at least one patterned dielectric material stack overlying the substrate, the patterned dielectric material stack including alternating first and second dielectric material layers; recessing each second dielectric material layer of the at least one patterned dielectric material stack to provide a recessed second dielectric material layer; forming laterally adjacent word lines in each recessed second layer of dielectric material; forming an interlevel dielectric (ILD) material layer laterally adjacent the at least one patterned dielectric material stack; forming a first set of openings in each first dielectric material layer and each recessed second dielectric material layer of the at least one patterned dielectric material stack and a second set of openings in the ILD material layer, wherein the first set of openings and the second set of openings physically expose the substrate; forming a dielectric switching material layer lining a sidewall of each of the first set of openings and the second set of openings; and forming a first bit line in a remaining portion of each of the first set of openings and a second bit line in a remaining portion of the second set of openings, wherein the first bit line and the second bit line are in direct physical contact with the substrate and are laterally surrounded by the dielectric switching material layer; A method comprising:

12. 12. The method of claim 11, wherein each of the first dielectric material layers has a lateral width greater than a lateral width of each of the recessed second dielectric material layers.

13. 12. The method of claim 11, wherein the recessing step comprises an isotropic lateral etch, and gaps are formed laterally adjacent each recessed second dielectric material layer.

14. The step of forming the word lines comprises: depositing an oxygen-deficient conductive material; laterally etching the conductive material; and cutting the conductive material formed around each end of the recessed second layer of dielectric material; 14. The method of claim 13, comprising:

15. 12. The method of claim 11, wherein each word line has a first sidewall contacting a sidewall of the recessed second dielectric material layer, and a second sidewall opposite the first sidewall and vertically aligned with an outermost sidewall of the first dielectric material layer.

16. The step of forming the dielectric switching material layer comprises: depositing a dielectric metal oxide in each of the first set of openings and the second set of openings by atomic layer deposition; and removing the dielectric metal oxide from a bottom of each of the first set of openings and the second set of openings to physically expose the substrate; 12. The method of claim 11, comprising:

17. 12. The method of claim 11, wherein each of the first dielectric material layers is comprised of a dielectric material that is compositionally different from the dielectric material that provides each of the second dielectric material layers.

18. 12. The method of claim 11, wherein each of the word lines extends parallel to a horizontal plane of the substrate; and the first bit lines and the second bit lines extend perpendicular to the word lines.

19. 12. The method of claim 11, wherein forming the first set of openings and the second set of openings comprises lithography and etching.

20. The step of forming the at least one patterned dielectric material stack comprises: forming a dielectric material stack of alternating blanket layers of a first dielectric material and a second dielectric material; and patterning the dielectric material stack by lithography and etching; 12. The method of claim 11, comprising:

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