Localized annealing of ferroelectrics.

Abstract

The semiconductor device includes a ferroelectric random access memory (FeRAM) cell. The FeRAM includes a ferroelectric material that is annealed to obtain its ferroelectric phase by induced current flow and a heat treatment. The current flow is induced through a temporary wire, causing heating of the FeRAM cell. The resulting heating or annealing of the ferroelectric material may crystallize the ferroelectric material, causing it to embody or possess ferroelectric properties. The induced current flow and heat treatment are substantially localized to the FeRAM cell and the ferroelectric material therein, as opposed to a global heating or annealing process in which the entire semiconductor device or a relatively larger region of the semiconductor device is heated to the required annealing temperature of the ferroelectric material.

Description

[Technical Field]

[0001] The present disclosure relates generally to the field of semiconductor device technology, and more particularly to locally annealing ferroelectrics in ferroelectric random-access memory (FeRAM). [Background technology]

[0002] Embodiments of the present disclosure recognize that FeRAM is a non-volatile solid-state memory technology that utilizes the presence or absence of charge in a capacitor that includes a ferroelectric material between electrodes. The basic storage unit ("cell") can be programmed into at least two different states, or levels, that exhibit different charge characteristics. The programmable cell states can be used to represent different data values, allowing for the storage of information.

[0003] Embodiments of the present disclosure relate to FeRAM cells and their associated wiring and signaling transistors. Each cell typically operates in conjunction with one signaling transistor. Data can be stored as the presence or absence of charge within the ferroelectric, with the absence of charge generally representing a "0" and the presence of charge representing a "1." Writing is achieved by charging electrodes on both sides of the ferroelectric, applying an electric field across the ferroelectric, forcing the atoms within to orient "up" or "down" (depending on the polarity of the charge), thereby storing a "1" or "0." Reading a cell can be achieved by a signaling transistor forcing the cell into a particular state, e.g., a "0." If the cell holds a "0," no change occurs in the output line. If the cell holds a "1," a brief pulse of current is generated at the output as the reorientation of atoms within the film pushes electrons out of the "down" metal. The presence of this pulse indicates that the cell held a "1." Because this process overwrites the cells, reading FeRAM is a destructive process and requires the cells to be rewritten.

[0004] Embodiments of the present disclosure recognize that ferroelectrics, such as hafnium oxide (HfO), are promising materials for electronic synaptic devices, memristor devices for neuromorphic computing, and nonvolatile memory devices. To integrate a ferroelectric into an FeRAM cell, high annealing temperatures (e.g., greater than 400°C) may be required for the ferroelectric to embody or attain a ferroelectric phase having ferroelectric properties such that spontaneous electric polarization can be reversed by the application of an external electric field. Exposing an entire wafer, device, or the like to such high temperatures may damage, melt, or otherwise affect other features or materials bonded thereto. Therefore, in contrast to such global heating of an entire wafer, semiconductor device, or the like, embodiments of the present disclosure are directed to localized annealing of ferroelectrics, in which sufficient heat is applied to the ferroelectric without globally heating the entire wafer, device, or the like. Because the entire wafer, device, or the like is not exposed to the temperatures required to fully anneal the ferroelectric, damage to other features, components, or materials bonded thereto may be limited or reduced. Summary of the Invention

[0005] In one embodiment of the present disclosure, a semiconductor device manufacturing method is presented. The method includes forming a ferroelectric random access memory (FeRAM) cell comprising a ferroelectric material between a top electrode and a bottom electrode. The method further includes forming a cell vertical interconnect access (VIA) on the FeRAM cell. The method further includes forming a temporary wire on the cell VIA. The method further includes annealing the ferroelectric material to obtain a ferroelectric phase by inducing a current flow through the temporary wire. The ferroelectric material may be a hafnium oxide ferroelectric material.

[0006] In one embodiment of the present disclosure, another semiconductor device manufacturing method is presented. The method includes forming a bottom wire above a substrate. The method further includes forming a bottom heater contact on the bottom wire. The method further includes forming a ferroelectric random access memory (FeRAM) cell on the bottom heater contact. The FeRAM cell has a ferroelectric material between a top electrode and a bottom electrode. The method further includes forming a cell vertical interconnect access (VIA) on the FeRAM cell. The method further includes forming a temporary wire on the cell VIA. The method further includes annealing the ferroelectric material to obtain a ferroelectric phase by inducing a current flow through the temporary wire.

[0007] The method may further comprise removing the temporary wire after annealing the ferroelectric, which may include mechanically polishing away the temporary wire and retaining at least a portion of the cell via underneath.

[0008] In one embodiment of the present disclosure, a semiconductor device is presented, the semiconductor device comprising a bottom heater contact, the semiconductor device comprising a ferroelectric random access memory (FeRAM) cell on the bottom heater contact, the FeRAM cell having a hafnium oxide ferroelectric between a top electrode and a bottom electrode, and the semiconductor device further comprising a cell vertical interconnect access (VIA) on the FeRAM cell.

[0009] Embodiments of the present disclosure generally enable or enable the integration of ferroelectrics into FeRAM cells, which typically require ferroelectric annealing temperatures to achieve the ferroelectric phase. Exposing an entire wafer, device, or the like to such high temperatures can damage, melt, or the like, other features or materials bonded thereto. Accordingly, embodiments of the present disclosure are directed to localized annealing of ferroelectrics, in which sufficient heat is applied to the ferroelectric by inducing current flow through the FeRAM cell, without globally heating the entire wafer, device, or the like. Because the entire wafer, device, or the like is not exposed to the temperatures required to fully anneal the ferroelectric, damage to other features, components, or materials bonded thereto can be limited or reduced.

[0010] The above and other aspects, features, and advantages of various embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0011] The above and other aspects, features, and advantages of various embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings.

[0012] [Figure 1] 1A-1C are cross-sectional manufacturing views illustrating a method of fabricating a semiconductor device including an FeRAM cell with a locally annealed ferroelectric according to an embodiment of the present disclosure. [Figure 2] 1A-1C are cross-sectional manufacturing views illustrating a method of fabricating a semiconductor device including an FeRAM cell with a locally annealed ferroelectric according to an embodiment of the present disclosure. [Figure 3] 1A-1C are cross-sectional manufacturing views illustrating a method of fabricating a semiconductor device including an FeRAM cell with a locally annealed ferroelectric according to an embodiment of the present disclosure. [Figure 4]1A-1C are cross-sectional manufacturing views illustrating a method of fabricating a semiconductor device including an FeRAM cell with a locally annealed ferroelectric according to an embodiment of the present disclosure. [Figure 5] 1A-1C are cross-sectional manufacturing views illustrating a method of fabricating a semiconductor device including an FeRAM cell with a locally annealed ferroelectric according to an embodiment of the present disclosure. [Figure 6] 1A-1C are cross-sectional manufacturing views illustrating a method of fabricating a semiconductor device including an FeRAM cell with a locally annealed ferroelectric according to an embodiment of the present disclosure. [Figure 7] 1A-1C are cross-sectional manufacturing views illustrating a method of fabricating a semiconductor device including an FeRAM cell with a locally annealed ferroelectric according to an embodiment of the present disclosure. [Figure 8] 1A-1C are cross-sectional manufacturing views illustrating a method of fabricating a semiconductor device including an FeRAM cell with a locally annealed ferroelectric according to an embodiment of the present disclosure. [Figure 9] 1A-1C are cross-sectional manufacturing views illustrating a method of fabricating a semiconductor device including an FeRAM cell with a locally annealed ferroelectric according to an embodiment of the present disclosure. [Figure 10] 1A-1C are cross-sectional manufacturing views illustrating a method of fabricating a semiconductor device including an FeRAM cell with a locally annealed ferroelectric according to an embodiment of the present disclosure. [Figure 11] 1A-1C are cross-sectional manufacturing views illustrating a method of fabricating a semiconductor device including an FeRAM cell with a locally annealed ferroelectric according to an embodiment of the present disclosure. [Figure 12] 1A-1C are cross-sectional manufacturing views illustrating a method of fabricating a semiconductor device including an FeRAM cell with a locally annealed ferroelectric according to an embodiment of the present disclosure. [Figure 13] 1A-1C are cross-sectional manufacturing views illustrating a method of fabricating a semiconductor device including an FeRAM cell with a locally annealed ferroelectric according to an embodiment of the present disclosure. [Figure 14]1A-1C are cross-sectional manufacturing views illustrating a method of fabricating a semiconductor device including an FeRAM cell with a locally annealed ferroelectric according to an embodiment of the present disclosure. [Figure 15] 1A-1C are cross-sectional manufacturing views illustrating a method of fabricating a semiconductor device including an FeRAM cell with a locally annealed ferroelectric according to an embodiment of the present disclosure.

[0013] [Figure 16] 1 is a flowchart illustrating a method for fabricating a semiconductor device including an FeRAM cell with a locally annealed ferroelectric according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0014] Although a detailed description of an exemplary FeRAM architecture including a locally annealed ferroelectric is provided herein, it should be understood in advance that implementation of the teachings referred to herein is not limited to the FeRAM architecture described herein. Rather, embodiments of the present disclosure can be implemented in conjunction with any other suitable type of memory, semiconductor, or integrated circuit (IC) device now known or later developed.

[0015] Various embodiments of the present disclosure are described herein with reference to the associated drawings. Alternative embodiments may be devised without departing from the scope of this disclosure. It should be noted that in the following description and drawings, various connections and relationships (e.g., above, below, adjacent, etc.) are described between elements. These connections and / or relationships may be direct or indirect unless otherwise specified, and the present disclosure is not intended to be limited in this respect. Thus, a connection of entities may refer to either a direct or indirect connection, and a relationship between entities may be a direct or indirect relationship. As an example of an indirect relationship, a reference herein to forming layer "A" on layer "B" includes a situation in which one or more intermediate layers (e.g., layer "C") are between layer "A" and layer "B," so long as the relative properties and functions of layer "A" and layer "B" are not substantially altered by the intermediate layer(s).

[0016] Hereinafter, for purposes of explanation, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and their derivatives refer to the described structures and methods as oriented in the drawings. The terms “overlying,” “atop,” “on top,” “positioned on,” or “positioned atop” mean that a first element, such as a first structure, is on top of a second element, such as a second structure, and an intervening element, such as an interface structure, may be present between the first and second elements. “Direct contact” or similar terms mean that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediate conductive, insulating, or semiconducting layer at the boundary between the two elements. Note that the term “selective to,” e.g., “a first element selectively to a second element,” means that the first element may be etched and the second element may act as an etch stop.

[0017] The terms "about," "substantially," "approximately," and variations thereof are intended to include the degree of error associated with the measurement of a particular quantity based on equipment available at the time of filing. For example, inherent coplanarity between various materials may include appropriate manufacturing tolerances of ±8%, ±5%, ±2%, or similar differences between coplanar materials.

[0018] For the sake of brevity, conventional techniques related to semiconductor device and IC manufacturing may or may not be described in detail herein. Moreover, various tasks and process steps described herein may be incorporated into a more comprehensive procedure or process having additional steps or functions not described in detail herein. The various steps in the manufacturing of semiconductor devices and semiconductor-based ICs are well known, and therefore, for the sake of brevity, many conventional steps will be only briefly mentioned herein or will be omitted entirely without providing well-known process details.

[0019] Generally, the various processes used to form microchips that will be packaged into ICs fall into four general categories: deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition, deposition, or the like is any process that grows, coats, or otherwise transfers material onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently atomic layer deposition (ALD). Removal / etching is any process that removes material from the wafer. Examples include etching processes (either wet or dry) and chemical-mechanical planarization (CMP), and the like. Semiconductor doping is the modification of electrical properties, for example, by doping transistor sources and drains, typically by diffusion and / or ion implantation. These doping processes involve furnace annealing or rapid thermal annealing (RTA). Annealing serves to activate the implanted dopants. Both conducting (e.g., polysilicon, aluminum, copper, etc.) and insulating (e.g., various forms of silicon dioxide, silicon nitride, etc.) films are used to connect and isolate transistors and their components. Selective doping of various regions of a semiconductor substrate allows the conductivity of the substrate to be altered by applying a voltage. By creating structures for these various components, millions of transistors can be constructed and wired together to form the complex circuits of modern microelectronic devices. Semiconductor lithography is the formation of three-dimensional relief images or patterns in a semiconductor substrate for subsequent transfer of the pattern to the substrate.In semiconductor lithography, patterns are formed with a light-sensitive polymer called a photolithographic resist. The lithography and etching pattern transfer steps are repeated multiple times to build the complex structures that make up transistors and the numerous wires that connect a circuit's millions of transistors. Each pattern printed on the wafer is aligned with the previously formed pattern, and conductors, insulators, and selectively doped regions are gradually built up to form the final device.

[0020] 1-15 illustrate cross-sectional views of manufacturing stages of a manufacturing method for forming a semiconductor device 100 including one or more FeRAM cells according to various embodiments of the present disclosure. In the depicted exemplary manufacturing stages, the FeRAM cell includes a ferroelectric that has been locally annealed.

[0021] Hereinafter, for purposes of explanation, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and their derivatives refer to the described structures and methods as oriented in the drawings. The terms “overlying,” “atop,” “on top,” “positioned on,” or “positioned atop” mean that a first element, such as a first structure, is on a second element, such as a second structure, and an intervening element, such as an interface structure, may be present between the first and second elements. “Direct contact” or similar terms mean that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediate conductive, insulating, or semiconducting layer at the boundary between the two elements. Note that the term “selective to,” e.g., “a first element selectively to a second element,” means that the first element may be etched and the second element may act as an etch stop.

[0022] The terms "about," "substantially," "approximately," and variations thereof are intended to include the degree of error associated with measuring quantities based on equipment available at the time of filing. For example, inherent coplanarity between various materials may include appropriate manufacturing tolerances of ±8%, ±5%, or ±2% difference between coplanar materials.

[0023] For the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) manufacturing may or may not be described in detail herein. Moreover, various tasks and process steps described herein may be incorporated into a more comprehensive procedure or process having additional steps or functions not described in detail herein. The various steps in the manufacturing of semiconductor devices and semiconductor-based ICs are well known, and thus, for the sake of brevity, many conventional steps may be briefly described herein or omitted entirely without providing well-known process details.

[0024] Films of both conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) can be used to connect components. Selective doping of various regions of a semiconductor device allows the conductivity of the semiconductor device to be altered by applying a voltage. By creating structures of these various components, millions of semiconductor microdevices, such as FeRAM cells, can be built and wired together to form the complex circuits of modern microelectronic devices. Semiconductor lithography is the formation of three-dimensional relief images or patterns on a semiconductor substrate for subsequent transfer of the pattern to the substrate. In semiconductor lithography, the pattern is formed by a photosensitive polymer called a photolithography resist. Lithography and etching pattern transfer steps are repeated multiple times to build the complex structures that make up the microdevice and the numerous wires that connect the millions of transistors in the circuit. Each pattern printed on a semiconductor device layer is aligned with the previously formed pattern, gradually building up conductors, insulators, and selectively doped regions to form the final semiconductor device, IC package, or the like.

[0025] 1 illustrates a cross-sectional view of a manufacturing stage for forming a semiconductor device 100 according to various embodiments of the present disclosure. After this manufacturing stage, the semiconductor device 100 includes a substrate 102 and one or more bottom wires 104.

[0026] The substrate 102 is generally formed from a semiconductor or a dielectric. In a preferred implementation, the substrate 102 may be formed from a low-k dielectric material (i.e., a material with a dielectric constant smaller than that of silicon dioxide, such as SiCOH). In some implementations, the substrate 102 may be an inter-layer dielectric (ILD) layer, such that additional layers of the semiconductor device 100 have been pre-fabricated below it. In these implementations, electrical microdevices such as transistors, diodes, capacitors, resistors, or the like may be formed in the additional layers of the semiconductor device 100 by any suitable formation method.

[0027] The substrate 102 and / or additional layers of the semiconductor device 100 may include semiconductor materials such as germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used.

[0028] In some implementations, the bottom wire 104 may be part of or below a metallization layer of the semiconductor device 100. The metallization layers may be described as Mx, where x = 0, 1, 2, ..., where M0 refers to the bottom (e.g., closest to the substrate 102) metallization layer, and the index x increases by 1 for each additional metallization layer. In some implementations, conductive features such as conductive lines, contacts, and / or vias provide electrical connection from the bottom wire 104 to features above and / or below the bottom wire 104, such as a microdevice below it or a wiring feature above it. In some implementations, the bottom wires 104 may also each be referred to as a pad, plug, plane, trace, or the like.

[0029] In some implementations, bottom wire 104 includes an interior conductive region and a conductive barrier layer (not shown) lining the sidewalls and bottom surface of the interior conductive region. The conductive barrier layer may be formed of titanium, titanium nitride, tantalum, tantalum nitride, cobalt, combinations thereof, or the like. The interior conductive region may be formed of a metal such as copper, aluminum, tungsten, cobalt, alloys thereof, or the like. For example, one or more electrical paths may connect bottom wire 104 with a FeRAM memory controller to sense the resistance across a coupled FeRAM cell or the like.

[0030] Forming the bottom wire 104 may include etching a portion of the substrate 102 to form an opening, forming a blanket conductive barrier layer extending into the opening, depositing metal over the blanket conductive barrier layer, and performing a planarization process, such as a CMP process or a mechanical polishing process, to remove excess portions of the blanket conductive barrier layer and excess portions of the inner conductive region so that the top surfaces of the substrate 102 and the bottom wire 104 are coplanar.

[0031] 2 illustrates a cross-sectional view of a manufacturing stage for forming the semiconductor device 100 according to various embodiments of the present disclosure, in which a heater layer 106 is formed on the substrate 102 and on one or more bottom wires 104.

[0032] The heater layer 106 may be, for example, a silicon layer or a silicon-based layer, such as a silicon nitride layer. The heater layer 106 may be formed by depositing a blanket dielectric layer to a thickness between 1 nm and 100 nm. In a preferred implementation, the heater layer 106 may be formed to a thickness between 5 nm and 20 nm. The heater layer 106 may be the dielectric layer in which the bottom heater, bottom contact, or the like of the FeRAM cell is formed.

[0033] 3 illustrates a cross-sectional view of a manufacturing stage for forming the semiconductor device 100 according to various embodiments of the present disclosure, in which the heater layer 106 is patterned by forming one or more bottom contact trenches 108 therein.

[0034] The bottom contact trench 108 may be formed by photolithography techniques. For example, a photolithography resist (not shown) may be formed on the heater layer 106. The photolithography resist may be applied as a liquid onto the heater layer 106, which may be dried and patterned to form trenches entirely within the photolithography resist. The photolithography resist may be semi-solid film coated, laminated, or otherwise formed on the heater layer 106. For example, the photolithography resist may have a thickness ranging from about 10 μm to about 500 μm, although thicknesses of less than 40 μm or greater than 500 μm are also contemplated. In one implementation, the photolithography resist may be about 150 μm to 175 μm thick.

[0035] A pattern may be formed in the photolithography resist by removing portions of the photolithography resist. For example, the portions of the photolithography resist may be exposed to radiation, such as deep ultraviolet light, or an electron beam. Once patterning of the photolithography resist is complete, the portions of the photolithography resist may be retained and the portions of the photolithography resist may be etched away with an etchant that removes the photolithography resist. The retained portions of the photolithography resist may form patterned photolithography resist. The etched-away portions of the retained photolithography resist may form resist trenches, exposing the underlying heater layer 106. Using the patterned photolithography resist as a mask, portions of the underlying heater layer 106 are either exposed or protected, and the exposed or unprotected portions of the underlying heater layer 106 may be etched or removed. This patterning or removal of a portion of the heater layer 106 may effectively form one or more bottom contact trenches 108. Each of the one or more bottom contact trenches 108 may expose a portion of the associated bottom wire 104 underneath.

[0036] 4 illustrates a cross-sectional view of a manufacturing stage for forming the semiconductor device 100 according to various embodiments of the present disclosure, in which a bottom contact 110 is formed in the bottom contact trench 108.

[0037] The bottom contact 110 may be formed by depositing a conductive material on the heater layer 106 and on the bottom wire 104 to fill the contact trench 108. Excess bottom contact 110 material may be removed by CMP or other polishing techniques. This planarization may result in the top surface of the heater layer 106 being flush with the top surface of one or more bottom contacts 110. The bottom contact 110 material may be any common conductive material used as an electrode, such as, for example, tungsten, platinum, titanium nitride, tantalum nitride, titanium aluminum nitride, alloys thereof, or the like.

[0038] In some implementations, bottom contact 110 includes an inner conductive region and a conductive barrier layer (not shown) lining the sidewalls and bottom surface of the inner conductive region. The conductive barrier layer may be formed of titanium, titanium nitride, tantalum, tantalum nitride, cobalt, combinations thereof, or the like. The inner conductive region may be formed of a metal such as copper, aluminum, tungsten, cobalt, tungsten, platinum, titanium nitride, tantalum nitride, titanium aluminum nitride, alloys thereof, or the like.

[0039] Forming the bottom contact 110 may include forming a blanket conductive barrier layer that extends into the bottom contact trench 108, depositing metal over the blanket conductive barrier layer, and performing a planarization process, such as a CMP process polishing process, to remove excess portions of the blanket conductive barrier layer and excess portions of the interior conductive region so that the top surfaces of the heater layer 106 and the bottom contact 110 are coplanar.

[0040] 5 illustrates a cross-sectional view of a manufacturing stage for forming the semiconductor device 100 according to various embodiments of the present disclosure, in which the FeRAM cell build-up layer 120 is formed on the heater layer 106 and the bottom contact 110.

[0041] The FeRAM cell build-up layer 120 may be formed by first depositing a bottom electrode layer 112 on the heater layer 106 and the bottom contact 110, depositing a ferroelectric layer 114 on the bottom electrode layer 112, depositing a top electrode layer 116 on the ferroelectric layer 114, and depositing a resistor layer 118 on the top electrode layer 116.

[0042] The bottom electrode layer 112 may be formed on the heater layer 106 by depositing a conductive electrode material, such as titanium nitride, tantalum nitride, tungsten, or the like, onto the heater layer 106 and onto the bottom contact 110. The bottom electrode layer 112 may be formed to a thickness between 5 nm and 75 nm. In particular implementations, the bottom electrode layer 112 may be formed to a thickness between 20 nm and 30 nm. The bottom electrode layer 112 may be formed by any suitable process or any suitable combination of processes, including, but not limited to, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, plating, evaporation, ion beam deposition, electron beam deposition, laser-assisted deposition, chemical solution deposition, etc.

[0043] The bottom electrode layer 112 may be made of, but is not limited to, metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), hafnium (Hf), zirconium (Zr), cobalt (Co), nickel (Ni), copper (Cu), aluminum (Al), platinum (Pt), tin (Sn), silver (Ag), gold (Au)), conductive metal compound materials (e.g., tantalum nitride (TaN), titanium nitride (TiN), titanium carbide (TiC), etc.). The conductive material may comprise any suitable conductive material, including talc (TaC), titanium carbide (TiC), titanium aluminum carbide (TiAlC), tungsten silicide (WSi), tungsten nitride (WN), ruthenium oxide (RuO), cobalt silicide (CoSi), nickel silicide (NiSi), transition metal aluminides (e.g., TiAl, ZrAl), TaC, TaMgC, suitable combinations or alloys of these metals, or the like.

[0044] The ferroelectric layer 114 may be formed on the bottom electrode layer 112 by depositing a ferroelectric material, such as, but not limited to, HfO2, TaO, TaNO3, HfNO4, TiO3, TiNO3, WO3, WNO3, ZrO3, ZrNO3, CeO3, CeNO3, and mixtures thereof, such as HfZnO, onto the bottom electrode layer 112. The ferroelectric layer 114 may be formed to a thickness between 10 nm and 100 nm. In a particular implementation, the ferroelectric layer 114 may be formed to a thickness between 40 nm and 50 nm. The ferroelectric layer 114 may be an undoped material layer, or alternatively, a doped material layer. For example, the ferroelectric layer 114 may be a ferroelectric layer doped with silicon (Si), aluminum (Al), zirconium (Zr), nitrogen (N), yttrium (Y), lanthanum (La), or the like.

[0045] The top electrode layer 116 may be formed on the ferroelectric layer 114 by depositing a conductive electrode material thereon. The top electrode layer 116 may be formed to a thickness between 5 nm and 75 nm. In one implementation, the top electrode layer 116 may be formed to a thickness between 15 nm and 25 nm. The top electrode layer 116 may be formed by any suitable process or any suitable combination of processes, including, but not limited to, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, plating, evaporation, ion beam deposition, electron beam deposition, laser-assisted deposition, chemical solution deposition, etc. The top electrode layer 116 is typically, but not necessarily, formed from the same material as the bottom electrode material layer 112.

[0046] The resistor layer 118 may be formed on the top electrode layer 116 by depositing a dielectric, such as aluminum gallium nitride (AlGaN), nitrogen-rich tantalum nitride, or the like, onto the top electrode layer 116. The resistor layer 118 may be formed to a thickness between 1 nm and 20 nm. In particular implementations, the resistor layer 118 may be formed to a thickness between 2 nm and 10 nm. In some implementations, the resistor layer 118 may act as a resistor to current flow to and / or from the FeRAM cell.

[0047] 6 illustrates a cross-sectional view of a manufacturing stage for forming semiconductor device 100 according to various embodiments of the present disclosure, in which FeRAM cell build-up layer 120 is patterned to form one or more FeRAM cells 122.

[0048] Photolithography techniques can be used to develop or pattern the FeRAM cell build-up layer 120. For example, photolithography resist can be formed on the resist layer 118, and a pattern can be formed in the photolithography resist by removing portions of the photolithography resist. In a particular implementation, the portions of the photolithography resist can be exposed to radiation, such as deep ultraviolet light, or an electron beam. Once the patterning of the photolithography resist is complete, the portions of the photolithography resist can be retained, and the portions of the photolithography resist can be etched away with an etchant that removes the photolithography resist. The retained portions of the photolithography resist can form patterned photolithography resist. The etched-away portions of the photolithography resist form resist trenches that can reveal the underlying FeRAM cell build-up layer 120. Using the patterned photolithographic resist as a mask, portions of the underlying FeRAM cell build-up layer 120 are either exposed or protected, and the exposed or unprotected portions of the underlying FeRAM cell build-up layer 120 can be etched or removed. Patterning or removing portions of the FeRAM cell build-up layer 120 effectively forms one or more FeRAM cells 122, exposes the top surface of one or more portions of the heater layer 106, and may also expose the top surface of one or more bottom contacts 110.

[0049] The etching technique utilized in removing the FeRAM cell build-up layer 120 may be a physical or dry etching technique or a chemical wet etching. In a preferred implementation, the etching is a physical dry etching, which poses a lower risk of damage to one or more FeRAM cells 122 (e.g., due to the lack of a chemical etchant, lateral etching of the FeRAM cell build-up layer 120 may be limited).

[0050] After formation, the FeRAM cell 122 may include a bottom electrode 124 formed from the retained portion of the bottom electrode layer 112, may include a ferroelectric 126 formed from the retained portion of the ferroelectric layer 114, may include a top electrode 128 formed from the retained portion of the top electrode layer 116, and may include a resistor 130 formed from the retained portion of the resistor layer 118.

[0051] 7 illustrates a cross-sectional view of a manufacturing stage for forming semiconductor device 100 according to various embodiments of the present disclosure. At this manufacturing stage, encapsulation layer 132 is formed over and around FeRAM cell 122, and over heater layer 106 and bottom contact 110.

[0052] The encapsulation layer 132 may be a silicon layer or a silicon-based layer, such as a silicon nitride layer. The encapsulation layer 132 may be formed by depositing a blanket dielectric layer to a thickness between 5 nm and 200 nm. In certain implementations, the encapsulation layer 132 may be formed to a thickness between 3 nm and 50 nm. In some implementations, portions of the encapsulation layer 132 located on the top surface of the FeRAM cell 122 and / or on the top surface of the bottom heater 110 and / or on the top surface of the heater layer 106 may be removed, while portions of the encapsulation layer 132 located on the sidewalls of the FeRAM cell 122 may be retained. In other words, the encapsulation layer 132 may be formed as spacers on the sidewalls of the FeRAM cell 122.

[0053] 8 illustrates a cross-sectional view of a manufacturing stage for forming semiconductor device 100 according to various embodiments of the present disclosure, in which an inter-layer dielectric (ILD) 134 is formed on encapsulation layer 132 above FeRAM cell 122.

[0054] If the encapsulation layer 132 takes the form of spacers on the sidewalls of the FeRAM cells 122, the ILD 134 may be formed over the FeRAM cells 122, around the encapsulation layer 132 spacers, and on the upper surface and / or top of the bottom heater 110.

[0055] The ILDs 134 may be formed by depositing a blanket layer of dielectric, such as a low-k dielectric material, above the heating layer 106 and above the bottom contact 110, as appropriate or desirable, on the encapsulation layer 132. The ILDs 132 may be formed to a thickness generally greater than or generally above the height of the top surfaces of the FeRAM cells 122 and / or the top surface of the encapsulation layer 132 above the top surface of the FeRAM cells 122.

[0056] 9 illustrates a cross-sectional view of a manufacturing stage for forming a semiconductor device 100 according to various embodiments of the present disclosure, in which cell vertical interconnect accesses (VIAs) 142 and temporary wires 144 are formed in the ILD 134.

[0057] The cell via 142 and temporary wire 144 may be formed simultaneously by dual damascene techniques. For example, a selective removal technique may remove an unwanted portion of the ILD 134 generally above a portion of the FeRAM cell 122 to form a via trench, and a temporary wire trench may be formed generally above the via trench. The via trench may expose at least a portion of the resistor 130 of the FeRAM cell 122. The temporary wire trench may form a well or trench and may intersect or be associated with one or more via trenches.

[0058] Etching techniques can be used to form wiring trenches with right-angled sidewalls (i.e., parallel to the sidewalls of the FeRAM cells) or with sloped sidewalls as depicted. In one implementation, the resistor 130 is used as an etch stop layer. The etching technique can be a physical or dry etching technique or a chemical wet etching. In a preferred implementation, the etching technique can be a chemical wet etching, and the resistor 130 can be configured as a wet etchant stop.

[0059] Subsequently, cell vias 142 are formed in the via trenches, and temporary wires 144 are formed in the temporary wire trenches. In this implementation, the cell vias 142 and temporary wires 144 may be formed simultaneously by dual damascene techniques. For example, the cell vias 142 and temporary wires 144 may be formed simultaneously by depositing a conductive material, such as copper or the like, in the via trenches and temporary wire trenches, respectively.

[0060] The cell via 142 may directly contact the resistor 130 of the FeRAM cell 122. For example, the cell via 142 contacts the entire top surface or a portion of the top surface of the resistor 130. Because the cell via 142 contacts or connects with the resistor 130 of the FeRAM cell 122 instead of directly contacting the top electrode 128, the amount of current to the FeRAM cell 122 may be limited by the resistance of the resistor 130 (which may be adjustable based on the selection of the material and / or dimensions of the resistor 130). By using the resistor 130 to limit the current entering the FeRAM cell 122, the durability of the FeRAM cell 122 may be improved and adverse effects on components in the vicinity of the FeRAM cell 122 may be limited. The temporary wire 144 may be electrically connected to or otherwise coupled to one or more underlying cell vias 142 such that current may flow through the temporary wire 144 and through the associated cell via 142 to the FeRAM cell 122.

[0061] For clarity, the temporary wires 144 are considered temporary or sacrificial because they are subsequently removed. Because the temporary wires 144 are removed, the geometry of the temporary wires 144 may be specifically selected to achieve a sufficient amount of current through the FeRAM cells 122. For example, a replacement wire or other conductive feature subsequently formed above the FeRAM cells 122 and / or cell vias 142 may not achieve a sufficient amount of current through the FeRAM cells 122, and a temporary wire 144 may be fabricated that is larger (i.e., has a lower impedance) than the replacement wire or other conductive feature. Furthermore, space requirements may not allow for such a large replacement wire or other conductive feature to achieve a sufficient amount of current through the FeRAM cells 122 to anneal the ferroelectric 126. Therefore, the temporary wires 144 may be specifically fabricated to achieve such a sufficient amount of current through the FeRAM cells 122, and then later removed to apply a relatively smaller replacement wire or other conductive feature that conforms to the space requirements.

[0062] 10 illustrates a cross-sectional view of a manufacturing stage for forming the semiconductor device 100 according to various embodiments of the present disclosure, in which the ferroelectric material 126 is annealed by the flow of an induced current and a heat treatment 150 to obtain its ferroelectric phase.

[0063] The induced current flow and heating process 150 occurs when current flow is induced through the temporary wires 144 and the associated cell vias 142, which causes heating of the FeRAM cells 122. The resulting heating or annealing of the ferroelectric 126 may crystallize the ferroelectric 126 such that the ferroelectric 126 embodies or has ferroelectric properties (e.g., the spontaneous polarization of the ferroelectric 126 can be reversed by the application of an external electric field, etc.).

[0064] The induced current flow and heating process 150 is a localized annealing technique in which heating is substantially confined to the FeRAM cell 122 and the ferroelectric 126 therein by the flow of induced current through the temporary wire 144, as opposed to a global heating or annealing process in which the entire semiconductor device 100 or a relatively larger region of the semiconductor device 100 is heated to the required annealing temperature of the ferroelectric 126. The induced current flow and heating process 150 may be referred to as an electron charging process, whereby the temporary wire 144 is exposed to an electron charge, resulting in the flow of an induced current through the temporary wire 144.

[0065] In a particular implementation, the induced current flow and heating process 150 may be a technique or process in which an external device or system induces a current flow across the temporary wires 144 and the associated cell vias 142 into the FeRAM cells 122. For example, a plasma generating tool or an electron beam generating tool may be utilized to induce a current flow across the temporary wires 144 and the associated cell vias 142 into the FeRAM cells 122, thereby heating the ferroelectric 126. The plasma generating tool may be an inductively coupled plasma (ICP) tool, a capacitively coupled plasma (CCP) tool, a microwave-generated plasma tool, or the like. The electron beam generating tool may be a field emission-based electron beam generating tool, a plasma-based electron beam tool, or the like.

[0066] In a particular implementation in which the FeRAM cell 122 has a prismatic geometry with a width between 10 nm and 1000 nm and a height between 1 nm and 500 nm, the induced current flow and heating process 150 can generate a current of 100 μA to 500 μA across the temporary wire 144 and the associated cell via 142 into the FeRAM cell 122 to achieve a temperature sufficient to anneal the HfO2 ferroelectric 126.

[0067] The geometry and materials of the cell vias 142 and temporary wires 144 may be selected to achieve or allow a predetermined required amount of induced current therethrough to generate a required annealing temperature of the ferroelectric material 126 while staying below a predetermined maximum temperature of the cell vias 142 and temporary wires 144. By staying below a predetermined maximum temperature of the cell vias 142 and temporary wires 144, temperature-based damage to semiconductor device 100 components or materials in the vicinity or substantially near the cell vias 142 and temporary wires 144 may be limited, and the induced current flow and heat treatment 150 may be well localized. In particular implementations, the predetermined maximum temperature of the cell vias 142 and temporary wires 144 may be between 100° C. and 1000° C., and the predetermined required amount of induced current may be between 100 μA and 1 mA.

[0068] 11 illustrates a cross-sectional view of a manufacturing stage for forming semiconductor device 100 according to various embodiments of the present disclosure, in which temporary wires 144 are removed and the top surfaces of ILD 134 and one or more cell vias 142 are planarized.

[0069] The temporary wires 144 may be removed by a planarization process, such as a CMP process or a mechanical polishing process, to remove the temporary wires 144 and achieve coplanarity of the top ILD 134 and the top surface of each of the one or more cell vias 142 .

[0070] 12 through 15 show cross-sectional views of alternative manufacturing stages of semiconductor device 100, including sequential fabrication of cell vias 142 and temporary wires 144. The manufacturing stages depicted in FIGS. 12 through 15 may occur after the manufacturing stage shown in FIG.

[0071] 12 illustrates a cross-sectional view of a manufacturing stage for forming semiconductor device 100 according to various embodiments of the present disclosure. During this manufacturing stage, one or more cell vias 142 are formed in ILD 134.

[0072] The cell via 142 may be formed by damascene techniques. For example, an unwanted portion of the ILD 134 generally above a portion of the FeRAM cell 122 may be removed by selective removal or etching techniques to form a via trench 152. The via trench 152 may expose at least a portion of the resistor 130 of the FeRAM cell 122.

[0073] Etching techniques can be used to form via trenches 152 with right-angled sidewalls (i.e., parallel to the sidewalls of the FeRAM cells 122) or with sloped sidewalls as shown. In one implementation, the resistor 130 is used as an etch stop layer. The etching technique can be a physical or dry etching technique or a chemical wet etching. In a preferred implementation, the etching technique can be a chemical wet etching, and the resistor 130 is configured as a wet etchant stop.

[0074] Subsequently, the cell via 142 is formed in the via trench 152. For example, the cell via 142 may be formed by depositing a conductive material, such as copper, or the like, in the via trench 152.

[0075] The cell via 142 may directly contact the resistor 130 of the FeRAM cell 122. For example, the cell via 142 may contact the entire top surface or a portion of the top surface of the resistor 130. Because the cell via 142 contacts or connects with the resistor 130 of the FeRAM cell 122 instead of directly contacting the top electrode 128, the amount of current to the FeRAM cell 122 may be limited by the resistance of the resistor 130. By using the resistor 130 to limit the current entering the FeRAM cell 122, the durability of the FeRAM cell 122 may be improved and adverse effects on components near the FeRAM cell 122 may be limited.

[0076] 13 illustrates a cross-sectional view of a manufacturing stage for forming a semiconductor device 100 according to various embodiments of the present disclosure. During this manufacturing stage, one or more cell temporary wires 144 are formed on the ILD 134 and on the cell vias 142.

[0077] The formation of one or more temporary wires 144 may be formed by photolithography techniques. For example, a photolithography resist (not shown) may be formed on the ILD 134 and the cell vias 142. The photolithography resist may be applied as a liquid onto the ILD 134 and the cell vias 142, dried, and patterned to form trenches in the photolithography resist. The photolithography resist may be semi-solid film coated, laminated, or otherwise formed onto the ILD 134 and the cell vias 142.

[0078] A pattern can be formed in the photolithography resist by removing portions of the photolithography resist. For example, the portions of the photolithography resist can be exposed to radiation, such as deep ultraviolet light, or an electron beam. Once patterning of the photolithography resist is complete, the portions of the photolithography resist can be retained and etched away with an etchant that removes the photolithography resist. The retained portions of the photolithography resist can form the patterned photolithography resist. The portions of the photolithography resist that are etched away form temporary wire trenches that can reveal or expose portions of the underlying ILD 134 and the underlying cell vias 142.

[0079] The formation of one or more temporary wires 144 may be further formed by depositing metal within the temporary wire trenches and on the exposed portions of the underlying ILD 134 and the underlying cell VIA 142, performing a planarization process such as a CMP process or a mechanical polishing process to remove excess portions of the temporary wires 144, and removing the photolithography resist.

[0080] 14 shows a cross-sectional view of a manufacturing stage for forming semiconductor device 100 according to various embodiments of the present disclosure. At this manufacturing stage, ferroelectric material 126 is annealed to obtain its ferroelectric phase by the flow of induced current and a heat treatment 150. Details of the flow of induced current and the heat treatment 150 are disclosed above and therefore will not be repeated.

[0081] 15 illustrates a cross-sectional view of a manufacturing stage for forming semiconductor device 100 according to various embodiments of the present disclosure, in which temporary wires 144 are removed and the top surfaces of ILD 134 and one or more cell vias 142 are planarized.

[0082] The temporary wires 144 may be removed by a planarization process, such as a CMP process or a mechanical polishing process, to remove the temporary wires 144 and achieve coplanarity of the top ILD 134 and the top surface of each of the one or more cell vias 142 .

[0083] For clarity, semiconductor device 100 may undergo further fabrication stages to produce a final semiconductor device, IC device, IC chip, or the like. For example, semiconductor device 100 may undergo back-end of the line (BEOL) fabrication stages to produce one or more M0-Mx wiring levels, which may include one or more wires, potential planes, or the like, which may be electrically connected to cell vias 142 and / or bottom wires 104.

[0084] FIG. 16 illustrates a method 200 for fabricating a semiconductor device 100 including an FeRAM cell 122 having a locally annealed ferroelectric 126 according to an embodiment of the present disclosure.

[0085] The method 200 may include forming one or more bottom wires 104 on or within the substrate 102 (block 202), followed by forming a heating layer 106 on the one or more bottom wires 104 and on the substrate 102 (block 204).

[0086] The method 200 may further include forming one or more bottom heaters 110 in the heating layer 106. For example, one or more bottom contact trenches 108 are formed in the heating layer 106. Each of the one or more bottom contact trenches 108 may expose a portion of the top surface of a respective one or more bottom wires 104. Subsequently, a bottom heater 110 is formed in each of the one or more bottom contact trenches 108, and a planarization process may make the top surface of each of the bottom heaters 110 flush with the top surface of the heating layer 106.

[0087] The method 200 may further include forming (block 208) an FeRAM build-up layer 120 on the heating layer 106 and the one or more bottom heaters 110. The FeRAM cell build-up layer 120 may be formed by depositing a bottom electrode layer 112 on the heater layer 106 and the bottom contacts 110, depositing a ferroelectric layer 114 on the bottom electrode layer 112, depositing a top electrode layer 116 on the ferroelectric layer 114, and depositing a resistor layer 118 on the top electrode layer 116.

[0088] The method 200 may further include forming FeRAM cells 122 from the FeRAM build-up layer 120 (block 210). The FeRAM cells 122 may be formed by retaining one or more portions of the FeRAM build-up layer 120 and removing one or more portions of the FeRAM build-up layer 120 that are not needed. Each of the one or more retained portions of the FeRAM build-up layer 120 may be arranged in a stack of FeRAM build-up layer 120 portions having coplanar sidewalls. Each FeRAM cell 122 may be located directly above one bottom heater 110.

[0089] The formed FeRAM cell 122 includes a bottom electrode 124 formed from the retained portion of the bottom electrode layer 112, a ferroelectric 126 formed from the retained portion of the ferroelectric layer 114, a top electrode 128 formed from the retained portion of the top electrode layer 116, and a resistor 130 formed from the retained portion of the resistor layer 118.

[0090] The method 200 may further include forming (block 212) an encapsulation layer 132 on at least the sidewalls of the one or more FeRAM cells 122. The encapsulation layer 132 may further be formed on a top surface of the one or more FeRAM cells 122. An encapsulation layer may further be formed on a top surface of each of the one or more bottom heaters 110 and on a top surface of at least a portion of the heating layer 106.

[0091] Method 200 may further include forming an ILD 134 on encapsulation layer 132 (block 214). If encapsulation layer 132 is not fabricated on the top surface of FeRAM cell 122, ILD 134 may be further formed on the top surface of FeRAM cell 122. If encapsulation layer 132 is not formed on the top surface of each of one or more bottom heaters 110 and is not formed on the top surface of at least a portion of heating layer 106, ILD 134 may be further formed thereon.

[0092] Method 200 may further include forming vias 142 in ILD 134 and over FeRAM cells 122 (block 216), and may further include forming temporary wires 144 in or on ILD 134 and over vias 142 (block 218). Formation of vias 142 and temporary wires 144 may occur simultaneously (i.e., in the same dual damascene manufacturing process) or sequentially (i.e., in separate, consecutive single damascene manufacturing processes), as described herein.

[0093] The method 200 may further include exposing the temporary wire 144 to an induced current flow and heating process 150 to induce a current through the temporary wire 144 and across the associated FeRAM cell 122 (block 220) and locally heat or anneal (block 222) the ferroelectric 126. The resulting heating or annealing of the ferroelectric 126 may crystallize the ferroelectric 126 such that the ferroelectric 126 embodies or has ferroelectric properties. The geometry and materials of the cell via 142 and temporary wire 144 may be selected to achieve or allow a predetermined required amount of induced current therethrough to generate the required annealing temperature of the ferroelectric 126 while remaining below a predetermined maximum temperature of the cell via 142 and temporary wire 144. By staying below a predetermined maximum temperature of the cell VIA 142 and temporary wire 144, temperature-based damage to semiconductor device 100 components or materials in the vicinity or substantially near the cell VIA 142 and temporary wire 144 can be limited, and induced current flow and heat treatment 150 can be well localized.

[0094] The method 200 may continue with removing (block 224) the temporary wires 144. For example, by mechanical polishing or a CMP process, the temporary wires 144 may be removed, and the top surface of the one or more vias 142 may be flush with the top surface of the ILD 134.

[0095] The descriptions of various embodiments of the present disclosure have been presented for illustrative purposes, but are not intended to be exhaustive or limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been selected to best explain the principles of the embodiments, practical applications, or technical improvements over commercially available technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. forming a ferroelectric random access memory (FeRAM) cell comprising a ferroelectric material between a top electrode and a bottom electrode; forming a cell vertical interconnect access (VIA) on the FeRAM cell; forming a temporary wire over the cell via; and annealing the ferroelectric material to obtain a ferroelectric phase by inducing a current flow through the temporary wire. A semiconductor device manufacturing method comprising:

2. 2. The semiconductor device manufacturing method of claim 1, wherein the ferroelectric material is formed from hafnium oxide.

3. removing the temporary wire after annealing the ferroelectric. The semiconductor device manufacturing method of claim 1 , further comprising:

4. 10. The semiconductor device manufacturing method of claim 1, wherein the cell via and the temporary wire are formed simultaneously by a dual damascene process.

5. Inducing a flow of electrical current through the temporary wire includes: Inducing current flow from the temporary wire to the cell via and into the FeRAM cell.

10. The semiconductor device manufacturing method of claim 1, comprising:

6. The semiconductor device manufacturing method of claim 1 , wherein annealing the ferroelectric material comprises crystallizing the ferroelectric material to obtain a ferroelectric phase.

7. 7. The method of claim 6, wherein the ferroelectric material achieves the ferroelectric phase in which the electric polarization of the ferroelectric material is reversible upon the application of an electric field to the ferroelectric material.

8. 4. The semiconductor device manufacturing method of claim 3, wherein removing the temporary wire comprises mechanically polishing away the temporary wire and retaining at least a portion of the cell via.

9. 10. The semiconductor device manufacturing method of claim 1, wherein inducing a flow of electrical current through the temporary wire comprises electronically charging the temporary wire.

10. forming a bottom wire above the substrate; forming a bottom heater contact on the bottom wire; forming a ferroelectric random access memory (FeRAM) cell on the bottom heater contact, wherein the FeRAM cell has a ferroelectric between a top electrode and a bottom electrode; forming a cell vertical interconnect access (VIA) on the FeRAM cell; forming a temporary wire over the cell via; and annealing the ferroelectric material to obtain a ferroelectric phase by inducing a current flow through the temporary wire. A semiconductor device manufacturing method comprising:

11. The semiconductor device manufacturing method of claim 10 , wherein the ferroelectric material is formed from hafnium oxide.

12. removing the temporary wire after annealing the ferroelectric. The semiconductor device manufacturing method of claim 10 further comprising:

13. 11. The semiconductor device manufacturing method of claim 10, wherein the cell via and the temporary wire are formed simultaneously by a dual damascene process.

14. Inducing a flow of electrical current through the temporary wire includes: Inducing current flow from the temporary wire through the cell via into the FeRAM cell. The semiconductor device manufacturing method of claim 10, comprising:

15. The semiconductor device manufacturing method of claim 10 , wherein annealing the ferroelectric material comprises crystallizing the ferroelectric material to obtain a ferroelectric phase.

16. 16. The semiconductor device manufacturing method of claim 15, wherein the ferroelectric material achieves the ferroelectric phase in which the electric polarization of the ferroelectric material is reversible upon the application of an electric field to the ferroelectric material.

17. 13. The semiconductor device manufacturing method of claim 12, wherein removing the temporary wire comprises mechanically polishing away the temporary wire and retaining at least a portion of the cell via.

18. The semiconductor device manufacturing method of claim 10 , wherein inducing a flow of electrical current through the temporary wire comprises electronically charging the temporary wire.

19. The semiconductor device manufacturing method of claim 10 , wherein the FeRAM cell further comprises a resistor on the top electrode.

20. Bottom heater contact; a ferroelectric random access memory (FeRAM) cell on the bottom heater contact, the FeRAM cell having a hafnium oxide ferroelectric between a top electrode and a bottom electrode; and Cell Vertical Interconnect Access (VIA) on the FeRAM Cell A semiconductor device comprising:

21. 21. The semiconductor of claim 20, wherein the FeRAM cell further comprises a resistor on the top electrode.

22. 22. The semiconductor of claim 21, wherein the cell via directly contacts a top surface of the resistor.

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