SFQ-based pulse-conserving logic gates

Abstract

Josephson junction-based logic devices and methods of use are described. An example of a Josephson junction-based logic device is a two-input OR / AND (OA2) gate. The OA2 gate includes a first input node inductively coupled to a first input source and a second input node inductively coupled to a second input source. The first and second input sources are configured to provide single flux quantum (SFQ) pulses. The OA2 gate also includes a first plurality of inductors coupled between the first input node and one of the first output node or the second output node. The OA2 gate further includes a second plurality of inductors coupled between the second input node and one of the first output node or the second output node. The OA2 gate also includes a Josephson junction coupled between a common node and either the first or second input node or the first or second output node.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Patent Application No. 17 / 815,368, filed July 27, 2022, the contents of which are incorporated herein by reference. [Technical Field]

[0002] This application relates to superconducting circuits. In particular, this application discloses various Josephson junction-based logic devices and methods for their use. [Background technology]

[0003] Superconducting digital systems are capable of performing computations at clock speeds exceeding 100 GHz. In these systems, circuits contain superconducting wires and Josephson junctions that together form superconducting loops in which information in the form of single flux quantum (SFQ) is encoded and stored.

[0004] Superconducting circuits can be configured to implement conventional logic gates such as AND gates, OR gates, flip-flops, etc. These gates can be further configured to implement more complex logic such as shift registers, counters, and processors.

[0005] SFQ pulse-based logic devices operate by propagating, storing, generating, and destroying pulses. Although the scalability and combinatorial behavior of the various logic families has improved over time (i.e., RSFQ, QFP, RQL), the efficiency of logic gate implementation remains a challenge. Inversion is particularly costly, in contrast to CMOS. Summary of the Invention

[0006] This disclosure solves the inversion problem of SFQ logic and, more generally, 1) replicates all functions of a standard CMOS gate library using pulse-saving gates and dual-rail data encoding. For completeness, this disclosure describes gate implementations of 2) a D-latch device configured to remove signal dither, and 3) a single-ended to dual-rail data conversion device configured for implementation without the need for a transformer.

[0007] In a first aspect, a Josephson junction-based logic device is provided. The Josephson junction-based logic device includes a two-input OR / AND (OA2) gate. The OA2 gate includes a first input node inductively coupled to a first input source and a second input node inductively coupled to a second input source. The first input source and the second input source are configured to provide single flux quantum (SFQ) pulses. The OA2 gate also includes a first plurality of inductors coupled between the first input node and one of the first output node or the second output node. The OA2 gate further includes a second plurality of inductors coupled between the second input node and one of the first output node or the second output node. The OA2 gate also includes a plurality of Josephson junctions. Each Josephson junction is coupled between a common node and one of the first input node, the second input node, the first output node, or the second output node.

[0008] In a second aspect, a Josephson junction-based logic device is provided. The Josephson junction-based logic device includes a three-input OR / MAJ / AND (OMA3) gate. The OMA3 gate includes a first input node inductively coupled to a first input source, a second input node inductively coupled to a second input source, and a third input node inductively coupled to a third input source. The first input source, the second input source, and the third input source are configured to provide single flux quantum (SFQ) pulses. The OMA3 gate includes a first plurality of inductors coupled between the first input node and one of a first output node, a second output node, or a third output node, a second plurality of inductors coupled between the second input node and one of the first output node, the second output node, or a third output node, and a third plurality of inductors coupled between the third input node and one of the first output node, the second output node, or the third output node. The OMA3 gate further includes a plurality of Josephson junctions. Each Josephson junction is coupled between the common node and one of the first input node, the second input node, the third input node, the first output node, the second output node, or the third output node.

[0009] In a third aspect, a method is provided. The method includes providing single flux quantum (SFQ)-based inputs to a first input source and a second input source of a Josephson junction-based logic device. The Josephson junction-based logic device includes a first input node inductively coupled to the first input source and a second input node inductively coupled to the second input source. The Josephson junction-based logic device further includes a first plurality of inductors coupled between the first input node and one of the first output node or the second output node. The Josephson junction-based logic device further includes a second plurality of inductors coupled between the second input node and one of the first output node or the second output node. The Josephson junction-based logic device further includes a plurality of Josephson junctions. Each Josephson junction is coupled between a common node and one of the first input node, the second input node, the first output node, or the second output node. The method also includes providing an OR2 output at the first output node in response to the input, the OR2 output being a result of a logical OR function based on the input, and providing an AND2 output at the second output node, the AND2 output configured to provide a result of a logical AND function based on the input. [Brief explanation of the drawings]

[0010] The above and additional features will be better understood from the following detailed description of illustrative and non-limiting exemplary embodiments, taken in conjunction with the accompanying drawings, in which:

[0011] [Figure 1] 1 illustrates a block diagram of a Josephson junction-based two-input OR / AND (OA2) gate, according to an example embodiment. [Figure 2A] 1 illustrates a circuit diagram of a Josephson junction-based two-input OR / AND (OA2) gate, according to an exemplary embodiment. [Figure 2B] 1 illustrates a circuit diagram of a Josephson junction-based two-input OR / AND (OA2) gate, according to an exemplary embodiment. [Figure 3A] FIG. 1 illustrates a schematic logical block diagram of an OA2 gate arrangement, according to an exemplary embodiment. [Figure 3B] FIG. 1 illustrates a schematic logical block diagram of an OA2 gate arrangement, according to an exemplary embodiment. [Figure 3C] 3B shows a table of Boolean logic functions possible with the arrangement of OA2 gates of FIG. 3A, according to an example embodiment. [Figure 4A] 1 illustrates a dual-rail waveform according to an exemplary embodiment. [Figure 4B] 1 illustrates a dual-rail waveform according to an exemplary embodiment. [Figure 5] 1 illustrates a block diagram of a Josephson junction-based 3-input OR / MAJ / AND (OMA3) gate, in accordance with an example embodiment. [Figure 6A] 1 illustrates a circuit diagram of a Josephson junction-based 3-input OR / MAJ / AND (OMA3) gate, according to an example embodiment. [Figure 6B] 6B illustrates a waveform diagram of the OMA3 gate of FIG. 6A in accordance with an exemplary embodiment. [Figure 7A] 1 illustrates a schematic logical block diagram of an arrangement of OMA3 gates, according to an exemplary embodiment. [Figure 7B] 1 illustrates a schematic logical block diagram of an arrangement of OMA3 and OA2 gates according to an exemplary embodiment. [Figure 7C] 1 illustrates a schematic logical block diagram of an arrangement of OMA3 and OA2 gates according to an exemplary embodiment. [Figure 7D] 1 illustrates a schematic logical block diagram of an arrangement of OMA3 and OA2 gates according to an exemplary embodiment. [Figure 7E] 10 shows a table of possible logic functions and outputs corresponding to placement of OMA3 gates, according to an example embodiment. [Figure 8] FIG. 1 illustrates a schematic logical block diagram of an OA2 gate arrangement, according to an exemplary embodiment. [Figure 9] FIG. 1 illustrates a circuit diagram of a Josephson junction-based circuit configured to provide strobed logic inversion, according to an example embodiment. [Figure 10] 10 shows waveform diagrams corresponding to the operation of the circuit of FIG. 9 in accordance with an exemplary embodiment. [Figure 11] FIG. 1 illustrates a circuit diagram of a Josephson junction-based circuit configured to provide strobed logic inversion, according to an example embodiment. [Figure 12A] FIG. 1 illustrates a circuit diagram of a Josephson junction-based circuit configured to provide strobed logic inversion, according to an example embodiment. [Figure 12B] FIG. 1 illustrates a circuit diagram of a Josephson junction-based circuit configured to provide strobed logic inversion, according to an example embodiment. [Figure 12C] FIG. 1 illustrates a circuit diagram of a Josephson junction-based circuit configured to provide strobed logic inversion, according to an example embodiment. [Figure 13] FIG. 1 illustrates a circuit diagram of a Josephson junction-based circuit configured to convert a single-ended input to a strobed dual-rail signal, according to an exemplary embodiment. [Figure 14] 1 illustrates a logic diagram of a Josephson junction-based circuit configured to remove dither from return-to-zero (RZ) data, according to an example embodiment. [Figure 15] 15 shows waveform diagrams corresponding to the operation of the circuit of FIG. 14 in accordance with an exemplary embodiment. [Figure 16] 1 illustrates a method according to an exemplary embodiment. [Figure 17] 1 illustrates a method according to an exemplary embodiment.

[0012] All figures are schematic, not necessarily to scale, and generally show only parts necessary to explain the exemplary embodiments; other parts may be omitted or merely suggested. DETAILED DESCRIPTION OF THE INVENTION

[0013] Various example systems, devices, and / or methods are described herein with reference to the accompanying drawings. Any embodiment, implementation, and / or feature described herein as illustrative is not necessarily to be construed as preferred or advantageous over any other embodiment, implementation, and / or feature, unless so described. Accordingly, other embodiments, implementations, and / or features may be utilized, and other changes may be made, without departing from the scope of the subject matter presented herein.

[0014] Accordingly, the examples set forth herein are not intended to be limiting, and it will be readily understood that the aspects of the present disclosure, as generally described herein and illustrated in the Figures, can be arranged, substituted, combined, separated, and designed in a wide variety of different configurations.

[0015] Furthermore, unless the context suggests otherwise, features shown in each figure can be used in combination with one another. Thus, the figures should generally be understood as component aspects of one or more overall embodiments, with the understanding that not all of the illustrated features are required for each embodiment.

[0016] Furthermore, any recitation of elements, blocks, or steps in the specification or claims is for purposes of clarity and, therefore, such recitation should not be construed as requiring or implying that these elements, blocks, or steps follow a particular arrangement or be performed in a particular order.

[0017] Furthermore, terms such as "substantially" and "about" that may be used herein mean that the stated property, parameter, or value need not be achieved exactly, but that deviations and variations, including, for example, tolerances, measurement errors, limits of measurement accuracy, and other factors known to those skilled in the art, may occur to an extent that the property does not interfere with its intended effect.

[0018] Furthermore, terms such as "A is coupled to B" or "A is electrically coupled to B" do not necessarily mean that items A and B are directly coupled to one another. For example, if a first component is electrically coupled to a second component, this is interpreted to mean that the components are directly coupled (e.g., via conductors) or are coupled to one another via one or more resistors, capacitors, inductors, and / or other active or passive components.

[0019] As mentioned above, superconducting circuits include superconducting wires and Josephson junctions that combine to form superconducting loops in which information in the form of single flux quantum (SFQ) is encoded and stored. Examples of AC-powered single flux quantum (AC-SFQ) superconducting circuits correspond to reciprocal quantum logic (RQL) circuits and quantum flux parametron (QFP) circuits that are both powered and clocked by multiphase alternating current signals.

[0020] Superconducting wire is made from materials that can conduct direct current (DC) electrical current in the absence of an electric field. Such materials have near-zero resistance below a critical temperature. Niobium, an example of a superconductor, has a critical temperature (Tc) of 9.3 Kelvin. At temperatures below the critical temperature, niobium is in a superconducting state. However, above the critical temperature, niobium behaves like a normal metal with electrical resistance.

[0021] A Josephson junction contains two superconductors coupled through a region that prevents current flow. Examples of this region include or correspond to a physical constriction of the superconductor itself, a metallic region, or a thin insulating barrier. An example of a Josephson junction is a niobium superconductor sandwiched between two Al2O3 barriers. When the potential difference between the two superconductors is integrated with respect to time over one cycle of phase change, the magnetic flux through the loop changes by an integer number of magnetic flux quanta. The voltage pulse associated with the magnetic flux quantum corresponds to the aforementioned SFQ pulse. As an example, an overdamped Josephson junction can generate individual SFQ pulses. In an AC SFQ circuit, each Josephson junction may be part of one or more superconducting loops. The phase difference across the junction may be modulated by the magnetic flux applied to the loop.

[0022] This disclosure relates to an SFQ-based pulse-storing logic gate with the same number of outputs as inputs that converts inputs into thermometer codes. A two-output implementation is described as an improvement over previous designs, and is generalized to entirely new gates with multiple outputs. These gates are suitable for efficient implementation of all standard logic functions when using dual-rail data encoding. Implementations of exclusive-or and full adders are particularly efficient. This disclosure solves the "inversion problem" of pulse-based SFQ logic. This gate avoids physically large components such as transformers, resulting in a 400 MJJ / cm2 output at a 30 GHz clock rate with 12 levels of logic per pipeline stage. 2 These performance indices achieve computational density equivalent to that of state-of-the-art CMOS.

[0023] Examples of logic devices based on Josephson junctions This disclosure describes an SFQ gate library constructed from several logic elements: Josephson transmission lines (JTLs), OA2 gates, and OMA3 gates. In some examples, LC shunt junctions can be used to generate resonant clock-powered networks. The logic operates on an AC power supply, and the gates transmit positive and negative SFQ pulses on opposite half-periods of the clock cycle.

[0024] Advantages over conventional implementations include the elimination of transformers and the elimination of auxiliary inductors connecting the output junctions to each other or to ground, which is achieved by directly flux biasing the interconnecting inductors.

[0025] 1 shows a block diagram of a Josephson junction-based two-input OR / AND (OA2) gate 100, according to an example embodiment. OA2 gate 100 includes a first input node 110 that is inductively coupled to a first input source 120. OA2 gate 100 also includes a second input node 112 that is inductively coupled to a second input source 122. First input source 120 and second input source 122 are configured to provide single flux quantum (SFQ) pulses 102.

[0026] The OA2 gate 100 also includes a first plurality of inductors 130 coupled between the first input node 110 and one of the first output node 140 or the second output node 142 .

[0027] The OA2 gate 100 further includes a second plurality of inductors 132 coupled between the second input node 112 and one of the first output node 140 or the second output node 142 .

[0028] The OA2 gate 100 further includes a plurality of Josephson junctions 150. Each Josephson junction of the plurality of Josephson junctions 150 is coupled between a common node (e.g., ground) and one of the first input node 110, the second input node 112, the first output node 140, or the second output node 142.

[0029] In an exemplary embodiment, first output node 140 may be configured to provide OR2 output 160. In such a scenario, OR2 output 160 is configured to provide the result of a logical OR function based on the signals provided by first input source 120 and second input source 122.

[0030] In a further example, the second output node 142 may be configured to provide an AND2 output 162. In such a scenario, the AND2 output 162 is configured to provide the result of a logical AND function based on the signals provided by the first input source 120 and the second input source 122.

[0031] In some embodiments, the OA2 gate 100 may be configured to generate one output pulse at each output node (e.g., the first output node 140 and the second output node 142) in response to each input pulse provided at the input nodes (e.g., the first input node 110 and the second input node 112).

[0032] In various embodiments, the first plurality of inductors 130 may be biased with a flux bias equal to 1 / 2 SFQ, although it will be understood that other flux bias values are possible and contemplated.

[0033] In some embodiments, the OA2 gate 100 may additionally or alternatively include a global clock input 180 configured to provide a global clock signal 182. In such a scenario, the Josephson junction-based OA2 gate 100 may be configured to operate based on the global clock signal 182. As an exemplary embodiment, the global clock signal 182 has a clock frequency of at least 30 GHz.

[0034] In some examples, the OA2 gate 100 includes a flux bias initialization system 170, which may be configured to initialize one or more inductors with a flux bias. The flux bias initialization system 170 may include one or more current sources configured to supply current to one or more primary inductors. The primary inductors may be inductively coupled to one or more secondary loops of the OMA3 gate.

[0035] In exemplary embodiments, the inputs and outputs of OA2 gate 100 are typically connected to other gates via JTLs (not shown for clarity). All Josephson junctions are supplied with AC power (not shown for clarity), either directly or via leakage current from adjacent junctions. In various exemplary embodiments, all inputs are inductively connected to all outputs.

[0036] In some embodiments, a magnetic flux bias applied to the interconnect inductor can preferentially bias the output without disturbing the input and without requiring additional interconnects. After a positive SFQ on the input generates a positive event on the OR2 output, the addition of magnetic flux in the inductive loop transfers the preferential bias to AND2. In such a scenario, a subsequent positive input generates a positive output on AND2. Alternatively, a subsequent negative input generates a negative output of OR2.

[0037] 2A shows a circuit diagram of a Josephson junction-based two-input OR / AND (OA2) gate 200, according to an example embodiment. In such a scenario, the flux bias applied to the first plurality of inductors 130 is equal to one-half of the SFQ.

[0038] 2B shows a circuit diagram of a Josephson junction-based two-input OR / AND (OA2) gate 220 according to an example embodiment. In some examples, the first plurality of inductors 130 may include a first inductor pair 222 coupled in parallel between the first input node 110 and the first output node 140 and a second inductor pair 224 coupled in parallel between the first input node 110 and the second output node 142. In such a scenario, full SFQ can be applied to one of the two parallel inductors of the first inductor pair 222 and the second inductor pair 224.

[0039] 3A shows a schematic logic block diagram of an arrangement 300 of OA2 gates (e.g., OA2 gates 100a, 100b, 100c, and 100d) according to an example embodiment. Illustratively, the logic block may include multiple OA2 gates coupled within the logic block configured to accept two dual-rail inputs and provide multiple logic outputs including OR2, NOR2, AND2, NAND2, XOR2, and XNOR2.

[0040] As an exemplary embodiment, applying dual-rail data encoding to the OA2 gate arrangement 300 allows the logic functions OR2, NOR2, AND2, and NAND2 to be generated in one stage, and XOR2 and XNOR2 to be generated in two stages.

[0041] 3B shows a schematic logical block diagram of an OA2 gate arrangement 320 according to an exemplary embodiment. Illustratively, dual-rail data encoding applied to OA2 gate arrangement 320 can generate two stages of XOR2 and XNOR2 with different intermediate values compared to arrangement 300.

[0042] FIG. 3C shows a table 330 of Boolean logic functions possible with the OA2 gate arrangement 300 of FIG. 3A, according to an exemplary embodiment. The JTL, OA2, and OMA3 gates described herein are all pulse-preserving, meaning that each input pulse produces one output pulse. Additionally, these gates have degenerate inputs, meaning that the inputs are not distinguishable; only the total number of inputs that are high or low is important. The degenerate two-input logic functions are listed in FIG. 3C. The number of inputs that must be high (true) to create a true output is shown for each logic function. An "input code" numbers the logic functions.

[0043] Tie Low and Tie High are simple functions that correspond to constant outputs without using input values. The remaining two-input logic functions are generated using dual-rail data encoding and the OA2 gate 100.

[0044] 4A shows a dual-rail waveform 400 according to an example embodiment. This dual-rail data encoding technique is energy efficient because the dual-rail waveform can swing from low to high every clock cycle, but can also remain low or high for any number of clock cycles, minimizing transitions. In some implementations, both rails can exhibit a low state with inactive circuitry.

[0045] 4B shows a dual-rail waveform 420 according to an example embodiment. Waveforms 400 and 420 have different numbers of transitions, but are logically equivalent because logically valid states are read during the positive half clock cycle.

[0046] 5 shows a block diagram of a Josephson junction-based 3-input OR / MAJ / AND (OMA3) gate 500 according to an example embodiment. Illustratively, OMA3 gate 500 can be configured to generate logical OR3, MAJ3, and AND3 based on three inputs.

[0047] In an exemplary embodiment, OMA3 gate 500 includes a first input node 510 inductively coupled to a first input source 520, a second input node 512 inductively coupled to a second input source 522, and a third input node 514 inductively coupled to a third input source 524. In such a scenario, first input source 520, second input source 522, and third input source 524 are configured to provide single flux quantum (SFQ) pulses.

[0048] OMA3 gate 500 also includes a first plurality of inductors 530 coupled between first input node 510 and one of first output node 540, second output node 542, or third output node 544. OMA3 gate 500 further includes a second plurality of inductors 532 coupled between second input node 512 and one of first output node 540, second output node 542, or third output node 544. OMA3 gate 500 further includes a third plurality of inductors 534 coupled between third input node 514 and one of first output node 540, second output node 542, or third output node 544.

[0049] The OMA3 gate 500 further includes a plurality of Josephson junctions 550. Each Josephson junction of the plurality of Josephson junctions 550 is coupled between a common node (e.g., ground) and one of a first input node 510, a second input node 512, a third input node 514, a first output node 540, a second output node 542, or a third output node 544.

[0050] In an exemplary embodiment, first output node 540 may provide OR3 output 560. In such a scenario, OR3 output 560 is configured to provide the result of a logical OR function based on signals provided by first input source 520, second input source 522, and third input source 524.

[0051] In some examples, the second output node 542 may provide a MAJ3 output 562. In such a scenario, the MAJ3 output 562 is configured to provide the result of a logical majority function based on the signals provided by the first input source 520, the second input source 522, and the third input source 524.

[0052] In various other embodiments, the third output node 544 may provide an AND3 output 564. The AND3 output 564 is configured to provide the result of a logical AND function based on the signals provided by the first input source 520, the second input source 522, and the third input source 524.

[0053] In some embodiments, OMA3 gate 500 may be configured to generate one output pulse at each output node in response to each input pulse provided at the input node.

[0054] In various embodiments, OMA3 gate 500 may include a global clock input 580 configured to provide a global clock signal 582. In such a scenario, Josephson junction-based logic devices may be configured to operate based on global clock signal 582. Furthermore, in some examples, global clock signal 582 may have a clock frequency of at least 30 GHz.

[0055] In some embodiments, OMA3 gate 500 includes a flux bias initialization system 570, which may be configured to initialize one or more inductors with a flux bias. Flux bias initialization system 570 may include one or more current sources configured to supply current to one or more primary inductors, which may be inductively coupled to one or more secondary loops of the OMA3 gate.

[0056] FIG. 6A shows a circuit diagram of a three-input OR / MAJ / AND (OMA3) gate 600 based on Josephson junctions, according to an example embodiment. In various examples, the inputs and outputs are typically connected to other gates via JTLs (not shown for clarity). Additionally, in some embodiments, the Josephson junctions are driven with AC power (not shown for clarity), either directly or via leakage current from adjacent junctions. In various examples, the inputs are inductively connected to all outputs. Additionally, a magnetic flux bias can preferentially bias the outputs without disturbing the inputs or requiring additional interconnections. In some embodiments, after a positive SFQ on the input generates a positive event on the OR3 output, the addition of magnetic flux in the inductive loop rotates the preferential bias forward on the MAJ3 output. Furthermore, a subsequent positive input generates a positive output on MAJ3, rotating the preferential bias to AND3. Furthermore, a negative input generates a negative output, rotating the preferential bias in the opposite direction.

[0057] In various exemplary embodiments, at least a portion of the first plurality of inductors 530 (e.g., inductor 602 and inductor 606) are biased with a flux bias equal to one complete SFQ. In such a scenario, some of the first plurality of inductors 530 (e.g., inductor 604) may be configured with no bias. It will be understood that a flux bias may be applied to at least some of the first plurality of inductors 530, the second plurality of inductors 532, and / or other inductors of the third plurality of inductors 534.

[0058] 6B shows a waveform diagram 620 of the OMA3 gate 600 of FIG. 6A according to an example embodiment. In some embodiments, a positive polarity SFQ event causes a positive transition in the junction phase, and a negative polarity event causes a negative transition. Every input SFQ pulse generates a corresponding output pulse. The positive and negative transitions occur on opposite halves of the clock cycle, but may be separated by any number of cycles.

[0059] 7A illustrates a schematic logic block diagram of an arrangement 700 of OMA3 gates (e.g., OMA3 gates 500a, 500b, 500c, and 500d) according to an example embodiment. In some examples, arrangement 700 may include multiple OMA3 gates coupled to a logic block configured to accept three dual-rail inputs and provide multiple logic outputs including NOR3, XS3, NMAJ3, XD3, XNOR3, XNE3, NAND3, OR3, XNS3, MAJ3, XND3, XOR3, XE3, and AND3. It will be understood that other logic functions are possible and contemplated within the scope of this disclosure.

[0060] In an exemplary embodiment, all standard three-input logic functions can be generated in one or two stages using various combinations of OA2 and OMA3 gates. Specifically, arrangements 700, 720, 730, and 740, described with reference to Figures 7A, 7B, 7C, and 7D, are used. As shown in Figure 7A and arrangement 700, the MAJ3 function from the first stage and the XOR3 function from the second stage generate the logic of a full adder. Note that the OMA3 gate primitive in the second stage never has three true inputs, allowing for a more efficient implementation.

[0061] Additionally or alternatively, various logic blocks can include various combinations of OMA3 and OA2 gates, as shown in Figures 7B, 7C, and 7D. In such scenarios, several non-standard logic functions are possible and are considered, such as exclusive single-input, XS, exclusive double-input, XD, and exclusive equal-input, XE.

[0062] FIG. 7B illustrates a schematic logical block diagram of an arrangement 720 of OMA3 gates (eg, OMA3 gate 500) and OA2 gates (eg, OA2 gate 100) according to an example embodiment.

[0063] FIG. 7C illustrates a schematic logical block diagram of an arrangement 730 of OMA3 gates (eg, OMA3 gate 500) and OA2 gates (eg, OA2 gate 100) according to an example embodiment.

[0064] FIG. 7D illustrates a schematic logical block diagram of an arrangement 740 of OMA3 gates (eg, OMA3 gate 500) and OA2 gates (eg, OA2 gate 100) according to an example embodiment.

[0065] FIG. 7E shows a table 750 of Boolean logic functions possible with an OMA3 gate arrangement 700, such as the arrangement shown and described in connection with FIG. 7A, according to an exemplary embodiment. Degenerate three-input logic functions are listed in FIG. 7E. The number of inputs that must be high (true) to produce a true output is shown for each logic function. An "input code" numbers the logic functions accordingly.

[0066] Ty-low and ty-high are simple functions that correspond to constant outputs without using input values. The remaining three-input logic functions are generated using dual-rail data encoding, OA2 gates 100, and OMA3 gates 500.

[0067] It will be appreciated that four-input logic functions can be implemented with various logic blocks as contemplated herein. For example, FIG. 8 shows a schematic logic block diagram of an arrangement 800 of eight OA2 gates in accordance with an exemplary embodiment. In such an example, the eight OA2 gates can be arranged in two stages to perform logic functions such as AND4, NAND4, OR4, NOR4, etc.

[0068] Several other auxiliary operations are possible and contemplated herein. For example, a first auxiliary operation includes converting a single-ended coded signal to a dual-rail coded signal with logic inversion. Figure 9 shows a circuit diagram of a Josephson junction-based circuit 900 configured to provide strobed logic inversion in accordance with an exemplary embodiment.

[0069] Logic inversion is implemented as a polarity inversion, converting A to A', after which a logic inverter strobed with signal S generates the output !AS. Note that A and !AS are logically valid dual-rail signals only when S is active; otherwise, both rails are logically "zero," resulting in an inactive logic cycle. Note that in some embodiments, Josephson junction-based circuit 900 can be configured to provide strobed logic inversion without the need for a transformer (e.g., one that changes AC voltage levels by energy transfer involving a varying magnetic flux and primary and secondary loops / coils).

[0070] FIG. 10 shows a waveform diagram 1000 corresponding to the operation of the circuit of FIG. 9, in accordance with an exemplary embodiment.

[0071] 11 illustrates a circuit diagram of a Josephson junction-based circuit configured to provide polarity inversion 1100. It will be understood that other circuits configured to provide polarity inversion are possible and are contemplated within the scope of the present disclosure.

[0072] 12A, 12B, and 12C illustrate variations of circuits configured to provide a logic inversion function. FIG. 12A illustrates a circuit diagram of a Josephson junction-based circuit 1200 configured to provide a strobed logic inversion according to an exemplary embodiment. In such a scenario, a first loop 1202 may be initially biased with a flux bias equal to one full SFQ having a first polarity, and a second loop 1204 may be initially biased with a flux bias equal to one full SFQ having a first polarity.

[0073] In an exemplary embodiment, Josephson junction-based circuit 1200 may include an input node 1206 inductively coupled to an input source 1208. In such a scenario, input node 1206 may be inductively coupled to a common ground node via a first loop inductor 1210. Circuit 1200 may include an output node 1212 inductively coupled to the common ground node via a second loop inductor 1214. In some examples, output node 1212 may be coupled to a strobe source 1216 via a strobe resistor 1219 and a strobe inductor 1218. Circuit 1200 includes a bridge inductor 1201 coupled between input node 1206 and output node 1212.

[0074] Circuit 1200 further includes a first Josephson junction 1203 coupled between input node 1206 and a common ground node. Circuit 1200 also includes a second Josephson junction 1205 coupled between output node 1212 and the common ground node. In such a scenario, Josephson junction-based circuit 1200 is configured to provide a strobe logic inversion function at output node 1212 with respect to a logic input provided by input source 1208.

[0075] 12B shows a circuit diagram of a Josephson junction-based circuit 1220 configured to provide strobed logic inversion according to an example embodiment. In such a scenario, loop 1222 may initially be biased with a flux bias equal to one full SFQ and having a predetermined polarity.

[0076] 12C shows a circuit diagram of a Josephson junction-based circuit 1230 configured to provide strobed logic inversion according to an example embodiment. In such a scenario, loop 1232 may be initially biased with a flux bias equal to one full SFQ and having a predetermined polarity.

[0077] FIG. 13 shows a circuit diagram of a Josephson junction-based circuit 1300 configured to convert a single-ended input to a strobed dual-rail signal, according to an exemplary embodiment. The single-ended to dual-rail converter can accept return-to-zero (RZ) data encoding at the input. This means that the input must transition low for half a cycle after every high transition. This produces RZ encoding at the output.

[0078] A second auxiliary operation includes removing unwanted dither from the waveform, thereby improving power efficiency. FIG. 14 illustrates a simplified logic diagram of a Josephson junction-based circuit 1400 configured to remove dither from RZ data according to an example embodiment. In some implementations, an OR gate with non-standard input and output phases can be used to remove dither from the signal. In some implementations, the Josephson junction-based circuit 1400 includes an input node 1402 configured to receive an input signal 1404 from an input source 1406. The circuit 1400 also includes a Josephson junction transmission line 1408 configured to accept the input signal 1404 from the input source 1406 and provide a delayed signal 1410. In this situation, the delayed signal 1410 is a version of the input signal 1404 delayed by 180°.

[0079] The circuit 1400 also includes an OR2 gate 1412 configured to accept the input signal 1404 and the delayed signal 1410 and provide an output signal 1414 that includes a version of the input signal 1404 delayed by 225° and that does not include signal dithering.

[0080] Optionally, the circuit 1400 may include a Josephson junction transmission line 1416 coupled to the OR2 gate 1412 and configured to output an output signal 1414 .

[0081] Figure 15 shows a waveform diagram 1500 corresponding to the operation of the circuit 1400 of Figure 14, in accordance with an exemplary embodiment. Note that removing dither requires a latency of half a clock cycle based solely on causality; otherwise, the desired operation would require knowledge of signal transitions half a cycle ahead.

[0082] Exemplary Methods 16 illustrates a method 1600 according to an exemplary embodiment. It will be understood that the method 1600 may include fewer or more steps or blocks than those explicitly illustrated or disclosed herein. Furthermore, each step or block of the method 1600 may be performed in any order, and each step or block may be performed one or more times. In some embodiments, some or all of the blocks or steps of the method 1600 may be associated with the OA2 gate 100 and / or the OMA3 gate 500, as described in connection with FIGS. 1 and 5.

[0083] Block 1602 includes providing a single flux quantum (SFQ)-based input to a first input source (e.g., first input source 120) and a second input source (e.g., second input source 122) of a Josephson junction-based logic device (e.g., OA2 gate 100). In such a scenario, the Josephson junction-based logic device includes a first input node (e.g., first input node 110) inductively coupled to the first input source and a second input node (e.g., second input node 112) inductively coupled to the second input source. The logic device further includes a first plurality of inductors (e.g., first plurality of inductors 130) coupled between the first input node and one of a first output node (e.g., first output node 140) or a second output node (e.g., second output node 142). The logic device also includes a second plurality of inductors (e.g., second plurality of inductors 132), which are coupled between a second input node and one of the first output node or the second output node. The logic device includes a plurality of Josephson junctions (e.g., multiple Josephson junctions 150). In such a scenario, each Josephson junction of the multiple Josephson junctions may be coupled between a common node (e.g., ground) and one of the first input node, the second input node, the first output node, or the second output node.

[0084] In response to the input, block 1604 provides an OR2 output (e.g., OR2 output 160) at a first output node. In such a scenario, the OR2 output is a result of a logical OR function based on the input. Further, in response to the input, block 1604 includes providing an AND2 output (e.g., AND2 output 162) at a second output node. In such a scenario, the AND2 output is configured to provide a result of a logical AND function based on the input.

[0085] In some demonstrative embodiments, method 1600 may include providing an initialization signal to generate a desired magnetic flux bias in the first plurality of inductors while cooling the Josephson junction-based logic device. In such a scenario, method 1600 may also turn off the initialization signal once a superconducting critical temperature of the Josephson junction-based logic device is reached, such that the desired magnetic flux bias in the first plurality of inductors persists.

[0086] 17 illustrates a method 1700 according to an exemplary embodiment. It will be understood that the method 1700 may include fewer or more steps or blocks than those explicitly illustrated or disclosed herein. Furthermore, each step or block of the method 1700 may be performed in any order, and each step or block may be performed one or more times. In some embodiments, some or all of the blocks or steps of the method 1700 may be associated with the OA2 gate 100 and / or the OMA3 gate 500, as described in connection with FIGS. 1 and 5.

[0087] Method 1700 relates to initializing a flux bias in one or more inductors of a plurality of inductors in a Josephson junction-based logic device (e.g., OA2 gate 100 and / or OMA3 gate 500). In some embodiments, one or more primary inductors may be inductively coupled to one or more secondary loops configured to store at least a portion of the magnetic flux quanta. In some embodiments, method 1700 may be implemented to initialize a flux bias in one or more secondary loops in a given logic device.

[0088] Illustratively, method 1700 may be performed, at least in part, by flux bias initialization system 170 and / or flux bias initialization system 570.

[0089] Block 1702 includes applying a negative polarity current to the primary inductor such that approximately one magnetic flux quantum is induced in the secondary loop.

[0090] Block 1704 includes cooling the circuit below the superconducting transition temperature of the secondary loop, which is initialized to a low energy, low flux state.

[0091] Block 1706 includes turning off the current to the primary inductor to subtract exactly one negative flux quantum from the zero flux state, thereby achieving a quantum-accurate flux quantum in the secondary loop.

[0092] Upon initialization, various logic functions and operations may be performed by the logic devices described herein.

[0093] Enumerated exemplary embodiments Accordingly, embodiments of the present disclosure may relate to any of the following listed exemplary embodiments (EEE):

[0094] EEE1 includes Josephson junction-based logic devices including:

[0095] A two-input OR / AND (OA2) gate, the OA2 gate including:

[0096] a first input node inductively coupled to the first input source;

[0097] a second input node inductively coupled to a second input source, the first input source and the second input source configured to provide single flux quantum (SFQ) pulses;

[0098] a first plurality of inductors coupled between the first input node and one of the first output node or the second output node;

[0099] a second plurality of inductors coupled between the second input node and one of the first output node or the second output node; and

[0100] a plurality of Josephson junctions, each Josephson junction coupled between a common node and one of the first input node, the second input node, the first output node, or the second output node;

[0101] EEE2 includes the Josephson junction-based logic device of EEE1, with the first output node configuring the OR2 output, the OR2 output configured to provide a result of a logical OR function based on signals provided by the first input source and the second input source.

[0102] EEE3 includes the Josephson junction-based logic device of EEE1, and the second output node comprises an AND2 output, the AND2 output configured to provide a result of a logical AND function based on signals provided by the first input source and the second input source.

[0103] EEE4 includes the Josephson junction-based logic devices of EEE1, where the Josephson junction-based logic devices are configured to generate one output pulse at each output node in response to each input pulse provided at the input node.

[0104] EEE5 includes the Josephson junction-based logic device of EEE1, where the first plurality of inductors is biased with a flux bias equal to one-half of the SFQ.

[0105] EEE6 includes the Josephson junction-based logic device of EEE1, wherein the first plurality of inductors are:

[0106] a first inductor pair coupled in parallel between the first input node and the first output node; and

[0107] a second inductor pair coupled in parallel between the first input node and the second output node;

[0108] EEE7 includes the Josephson junction-based logic device of EEE6, wherein at least a portion of the first plurality of inductors are biased with a flux bias equal to one complete SFQ.

[0109] EEE8 includes the Josephson junction-based logic device of EEE1 and further includes a global clock input configured to provide a global clock signal, the Josephson junction-based logic device being configured to operate based on the global clock signal.

[0110] The EEE9 includes the Josephson junction-based logic devices of the EEE8, and the global clock signal has a clock frequency of at least 30 GHz.

[0111] EEE10 includes the Josephson junction-based logic device of EEE1 and further includes a plurality of OA2 gates coupled in a logic block configured to accept two dual-rail inputs and provide a plurality of logic outputs including OR2, NOR2, AND2, NAND2, XOR2, and XNOR2.

[0112] EEE11 includes Josephson junction-based logic devices including:

[0113] It includes a 3-input OR / MAJ / AND (OMA3) gate, and the OMA3 gate is

[0114] a first input node inductively coupled to the first input source;

[0115] a second input node inductively coupled to a second input source;

[0116] a third input node inductively coupled to a third input source, the third input node being configured to provide single flux quantum (SFQ) pulses with the first input source, the second input source, and the third input source;

[0117] a first plurality of inductors coupled between the first input node and one of the first output node, the second output node, or the third output node;

[0118] a second plurality of inductors coupled between the second input node and one of the first output node, the second output node, or the third output node;

[0119] a third plurality of inductors coupled between the third input node and one of the first output node, the second output node, or the third output node; and

[0120] The Josephson junction includes a plurality of Josephson junctions, each Josephson junction coupled between a common node and one of a first input node, a second input node, a third input node, a first output node, a second output node, or a third output node.

[0121] EEE12 includes the Josephson junction-based logic device of EEE11, and the first output node includes an OR3 output, the OR3 output configured to provide a result of a logical OR function based on signals provided by the first input source, the second input source, and the third input source.

[0122] EEE13 includes the Josephson junction-based logic device of EEE11, and the second output node includes the MAJ3 output, the MAJ3 output configured to provide a logical majority function result based on signals provided by the first input source, the second input source, and the third input source.

[0123] EEE14 includes the Josephson junction-based logic device of EEE11, and the third output node includes an AND3 output, the AND3 output configured to provide a result of a logical AND function based on signals provided by the first input source, the second input source, and the third input source.

[0124] EEE15 includes the Josephson junction-based logic device of EEE11, the Josephson junction-based logic device configured to generate one output pulse at each output node in response to each input pulse provided at the input node.

[0125] EEE16 includes the Josephson junction-based logic device of EEE11, wherein at least a portion of the first plurality of inductors are biased with a flux bias equal to one complete SFQ.

[0126] EEE17 includes the Josephson junction-based logic device of EEE11 and further includes a global clock input configured to provide a global clock signal, the Josephson junction-based logic device configured to operate based on the global clock signal, the global clock signal having a clock frequency of at least 30 GHz.

[0127] EEE18 includes the Josephson junction-based logic device of EEE11 and further includes a plurality of OMA3 gates coupled in a logic block configured to accept three dual-rail inputs and provide a plurality of logic outputs including NOR3, XS3, NMAJ3, XD3, XNOR3, XNE3, NAND3, OR3, XNS3, MAJ3, XND3, XOR3, XE3, and AND3.

[0128] EEE19 includes a method that includes:

[0129] providing single flux quantum (SFQ) based inputs to a first input source and a second input source of a Josephson junction based logic device, wherein the Josephson junction based logic device:

[0130] a first input node inductively coupled to the first input source;

[0131] a second input node inductively coupled to a second input source;

[0132] a first plurality of inductors coupled between the first input node and one of the first output node or the second output node;

[0133] a second plurality of inductors coupled between the second input node and one of the first output node or the second output node; and

[0134] a plurality of Josephson junctions, each Josephson junction coupled between a common node and one of the first input node, the second input node, the first output node, or the second output node;

[0135] In response to the input, the input is configured to provide an OR2 output at a first output node, the OR2 output being a result of a logical OR function based on the input, and to provide an AND2 output at a second output node, the AND2 output being a result of a logical AND function based on the input.

[0136] EEE20 includes the methods of EEE19 and further comprises:

[0137] providing an initialization signal to induce a desired flux bias in at least a portion of the first plurality of inductors while cooling the Josephson junction-based logic device; and

[0138] turning off the initialization signal when the superconducting critical temperature of the Josephson junction-based logic device is reached, so that a desired magnetic flux bias persists in the first plurality of inductors.

[0139] EEE21 describes a method including the following steps:

[0140] providing single flux quantum (SFQ) based inputs to a first input source, a second input source, and a third input source of a Josephson junction-based logic device, the Josephson junction-based logic device comprising:

[0141] a first input node inductively coupled to the first input source;

[0142] a second input node inductively coupled to a second input source;

[0143] a third input node inductively coupled to a third input source, the first input source, the second input source, and the third input source configured to provide single flux quantum (SFQ) pulses;

[0144] a first plurality of inductors coupled between the first input node and one of the first output node, the second output node, or the third output node;

[0145] a second plurality of inductors coupled between the second input node and one of the first output node, the second output node, or the third output node;

[0146] a third plurality of inductors coupled between the third input node and one of the first output node, the second output node, or the third output node; and

[0147] a plurality of Josephson junctions, each Josephson junction coupled between a common node and one of the first input node, the second input node, the third input node, the first output node, the second output node, or the third output node;

[0148] In response to the input, the input is configured to provide an OR3 output at a first output node, the OR3 output providing a result of a logical OR function based on the input, a MAJ3 output at a second output node, the MAJ3 output providing a result of a logical MAJ function based on the input, and an AND3 output at a third output node, the AND3 output being configured to provide a result of a logical AND function based on the input.

[0149] EEE22 includes the methods of EEE21 and further includes:

[0150] providing an initialization signal to induce a desired flux bias in at least a portion of the first plurality of inductors while cooling the Josephson junction-based logic device; and

[0151] Upon reaching the superconducting critical temperature of the Josephson junction-based logic device, turning off the initialization signal so that a desired magnetic flux bias persists in the first plurality of inductors.

[0152] EEE23 includes an arrangement of Josephson junction-based logic gates, the arrangement of which is as follows:

[0153] a plurality of Josephson junction-based logic devices, each logic device of the plurality of Josephson junction-based logic devices comprising at least two inputs, configured to accept single flux quantum (SFQ) input pulses, and configured to provide a logic function output via at least two outputs in response to each input pulse;

[0154] EEE24 includes the logic gate arrangement of EEE23, wherein the plurality of Josephson junction-based logic devices includes at least two two-input OR / AND (OA2) gates, the OA2 gates being:

[0155] a first input node inductively coupled to the first input source;

[0156] a second input node inductively coupled to a second input source, the first input source and the second input source configured to provide single flux quantum (SFQ) pulses;

[0157] a first plurality of inductors coupled between the first input node and one of the first output node or the second output node;

[0158] a second plurality of inductors coupled between the second input node and one of the first output node or the second output node;

[0159] a plurality of Josephson junctions, each Josephson junction coupled between a common node and one of the first input node, the second input node, the first output node, or the second output node;

[0160] EEE25 includes the logic gate arrangement of EEE23, wherein the multiple Josephson junction based logic device is comprised of at least two 3-input OR / MAJ / AND (OMA3) gates, the OMA3 gates being:

[0161] a first input node inductively coupled to the first input source;

[0162] a second input node inductively coupled to a second input source;

[0163] a third input node inductively coupled to a third input source, the third input source being configured to provide single flux quantum (SFQ) pulses;

[0164] a first plurality of inductors coupled between the first input node and one of the first output node, the second output node, or the third output node;

[0165] a second plurality of inductors coupled between the second input node and one of the first output node, the second output node, or the third output node;

[0166] a third plurality of inductors coupled between the third input node and one of the first output node, the second output node, or the third output node;

[0167] a plurality of Josephson junctions, each Josephson junction coupled between a common node and one of the first input node, the second input node, the third input node, the first output node, the second output node, or the third output node;

[0168] EEE26 includes the logic gate arrangement of EEE23, wherein the plurality of Josephson junction-based logic devices comprises at least two two-input OR / AND (OA2) gates and two three-input OR / MAJ / AND (OMA3) gates, wherein the OA2 gates are:

[0169] a first OA2 input node inductively coupled to the first OA2 input source;

[0170] a second OA2 input node inductively coupled to a second OA2 input source, the first OA2 input source and the second OA2 input source configured to provide single flux quantum (SFQ) pulses;

[0171] a first plurality of OA2 inductors coupled between the first OA2 input node and one of the first OA2 output node or the second OA2 output node;

[0172] a second plurality of OA2 inductors coupled between the second OA2 input node and one of the first OA2 output node or the second OA2 output node; and

[0173] a plurality of OA2 Josephson junctions, each Josephson junction coupled between a common node and one of the first OA2 input node, the second OA2 input node, the first OA2 output node, or the second OA2 output node, and an OMA3 gate configured to:

[0174] a first OMA3 input node inductively coupled to the first OMA3 input source;

[0175] a second OMA3 input node inductively coupled to a second OMA3 input source;

[0176] a third OMA3 input node inductively coupled to the third OMA3 input source, the first OMA3 input source, the second OMA3 input source, and the third OMA3 input source configured to provide single flux quantum (SFQ) pulses;

[0177] a first plurality of OMA3 inductors coupled between the first OMA3 input node and one of the first OMA3 output node, the second OMA3 output node, or the third OMA3 output node;

[0178] a second plurality of OMA3 inductors coupled between the second OMA3 input node and one of the first OMA3 output node, the OMA3 second output node, or the OMA3 third output node;

[0179] a third plurality of OMA3 inductors coupled between the third OMA3 input node and one of the first OMA3 output node, the second OMA3 output node, or the third OMA3 output node; and

[0180] The OMA3 Josephson junctions include a plurality of OMA3 Josephson junctions, each coupled between a common node and one of a first OMA3 input node, a second OMA3 input node, a third OMA3 input node, a first OMA3 output node, an OMA3 second output node, or a third OMA3 output node.

[0181] EEE27 includes the arrangement of logic gates of EEE23, where the logic function outputs include at least one of the following: OR2, NOR2, AND2, NAND2, XOR2, XNOR2, NOR3, XS3, NMAJ3, XD3, XNOR3, XNE3, NAND3, OR3, XNS3, MAJ3, XND3, XOR3, XE3, or AND3.

[0182] EEE28 includes logic devices based on Josephson junctions, including:

[0183] an input node inductively coupled to the input source, the input node being inductively coupled to a common ground node via a first loop inductor;

[0184] an output node inductively coupled to the common ground node via a second loop inductor, the output node being coupled to a strobe source via a strobe resistor and a strobe inductor;

[0185] a bridge inductor coupled between the input node and the output node;

[0186] a first Josephson junction coupled between the input node and a common ground node; and

[0187] a second Josephson junction coupled between the output node and a common ground node, the second Josephson junction being configured to provide a strobed logic inversion function at the output node with respect to a logic input provided by the input source;

[0188] The EEE29 includes a single-ended-to-dual-rail converter, the single-ended-to-dual-rail converter configured to accept a return-to-zero (RZ) input signal, and the single-ended-to-dual-rail converter configured to output the RZ input signal and a strobed complement of the RZ input signal.

[0189] EEE30 includes a Josephson junction-based logic device, the logic device being

[0190] an input node configured to receive an input signal from an input source;

[0191] a Josephson junction transmission line configured to receive an input signal from an input source and to provide a delayed signal, the delayed signal comprising a version of the input signal delayed by 180°;

[0192] an OR2 gate configured to accept an input signal and a delayed signal and to provide an output signal comprising a version of the input signal without signal dithering; and

[0193] an optional Josephson junction transmission line coupled to the OR2 gate and configured to output an output signal;

[0194] While several embodiments have been illustrated and described in detail in the accompanying drawings and the foregoing description, such illustration and description should be considered exemplary and not restrictive. Other variations to the disclosed embodiments can be understood and realized in practicing the claims, from a study of the drawings, the disclosure, and the appended claims. The mere fact that certain measures or features are recited in mutually different dependent claims does not indicate that a combination of these measures or features cannot be used. Reference signs in the claims should not be construed as limiting the scope.

Claims

1. 1. A Josephson junction-based logic device, comprising: It includes a two-input OR / AND (OA2) gate, where the OA2 gate is: a first input node inductively coupled to the first input source; a second input node inductively coupled to a second input source, the first input source and the second input source configured to provide single flux quantum (SFQ) pulses; a first plurality of inductors coupled between the first input node and one of the first output node or the second output node; a second plurality of inductors coupled between the second input node and one of the first output node or the second output node; and a plurality of Josephson junctions, each Josephson junction coupled between a common node and one of the first input node, the second input node, the first output node, or the second output node; Josephson junction-based logic devices, including:

2. 10. The Josephson junction-based logic device of claim 1, wherein the first output node comprises an OR2 output configured to provide a result of a logical OR function based on signals provided by the first input source and the second input source, and the second output node comprises an AND2 output configured to provide a result of a logical AND function based on signals provided by the first input source and the second input source.

3. 10. The Josephson junction-based logic device of claim 1, wherein the Josephson junction-based logic device is configured to generate one output pulse at each output node in response to each input pulse provided at the input node.

4. 10. The Josephson junction-based logic device of claim 1, wherein the first plurality of inductors are biased with a flux bias equal to one-half of the SFQ.

5. The first plurality of inductors includes: a first inductor pair coupled in parallel between the first input node and the first output node; and a second inductor pair coupled in parallel between the first input node and the second output node; 10. The Josephson junction-based logic device of claim 1, comprising:

6. 6. The Josephson junction-based logic device of claim 5, wherein at least a portion of the first plurality of inductors are biased with a flux bias equal to one complete SFQ.

7. 10. The Josephson junction-based logic device of claim 1, further comprising a global clock input configured to provide a global clock signal, wherein the Josephson junction-based logic device is configured to operate based on the global clock signal.

8. 8. The Josephson junction-based logic device of claim 7, wherein the global clock signal has a clock frequency of at least 30 GHz.

9. 10. The Josephson junction-based logic device of claim 1, further comprising a plurality of OA2 gates coupled in a logic block configured to accept two dual-rail inputs and provide a plurality of logic outputs including OR2, NOR2, AND2, NAND2, XOR2, and XNOR2.

10. 1. A Josephson junction-based logic device, comprising: It contains a 3-input OR / MAJ / AND (OMA3) gate, where the OMA3 gate is: a first input node inductively coupled to the first input source; a second input node inductively coupled to a second input source; a third input node inductively coupled to a third input source, the third input node being configured to provide single flux quantum (SFQ) pulses; a first plurality of inductors coupled between the first input node and one of the first output node, the second output node, or the third output node; a second plurality of inductors coupled between the second input node and one of the first output node, the second output node, or the third output node; a third plurality of inductors coupled between the third input node and one of the first output node, the second output node, or the third output node; and a plurality of Josephson junctions, each Josephson junction coupled between a common node and one of the first input node, the second input node, the third input node, the first output node, the second output node, or the third output node; Josephson junction-based logic devices, including:

11. 11. The Josephson junction-based logic device of claim 10, wherein the first output node comprises an OR3 output configured to provide a result of a logical OR function based on signals provided by the first input source, the second input source, and the third input source; the second output node comprises a MAJ3 output configured to provide a result of a logical majority function based on signals provided by the first input source, the second input source, and the third input source; and the third output node comprises an AND3 output configured to provide a result of a logical AND function based on signals provided by the first input source, the second input source, and the third input source.

12. 11. The Josephson junction-based logic device of claim 10 configured to generate one output pulse at each output node in response to each input pulse provided at an input node.

13. 11. The Josephson junction-based logic device of claim 10, wherein at least a portion of the first plurality of inductors are biased with a flux bias equal to one complete SFQ.

14. 11. The Josephson junction-based logic device of claim 10, further comprising a global clock input configured to provide a global clock signal, the Josephson junction-based logic device being configured to operate based on the global clock signal, the global clock signal having a clock frequency of at least 30 GHz.

15. 11. The Josephson junction-based logic device of claim 10, further comprising a plurality of OMA3 gates coupled in a logic block configured to accept three dual-rail inputs and provide a plurality of logic outputs including NOR3, XS3, NMAJ3, XD3, XNOR3, XNE3, NAND3, OR3, XNS3, MAJ3, XND3, XOR3, XE3, and AND3.

16. providing a single flux quantum (SFQ) based input to a Josephson junction based logic device, the Josephson junction based logic device including at least one of an OA2 gate or an OMA3 gate; Gate OA2 is as follows: a first OA2 input node inductively coupled to the first OA2 input source; a second OA2 input node inductively coupled to a second OA2 input source; a first plurality of OA2 inductors coupled between the first OA2 input node and one of the first OA2 output node or the second OA2 output node; a second plurality of OA2 inductors coupled between the second OA2 input node and one of the first OA2 output node or the second OA2 output node; and a plurality of OA2 Josephson junctions, each including a plurality of OA2 Josephson junctions coupled between a common node and one of the first OA2 input node, the second OA2 input node, the first OA2 output node, or the second OA2 output node; The OMA3 gates are: a first OMA3 input node inductively coupled to the first OMA3 input source; a second OMA3 input node inductively coupled to the second OMA3 input source; a third OMA3 input node inductively coupled to a third OMA3 input source, the first OMA3 input source, the second OMA3 input source, and the third OMA3 input source configured to provide single flux quantum (SFQ) pulses; a first plurality of OMA3 inductors coupled between the first OMA3 input node and one of the first OMA3 output node, the second OMA3 output node, or the third OMA3 output node; a second plurality of OMA3 inductors coupled between the second OMA3 input node and one of the first OMA3 output node, the second OMA3 output node, or the third OMA3 output node; a third plurality of OMA3 inductors coupled between the third OMA3 input node and one of the first OMA3 output node, the second OMA3 output node, or the third OMA3 output node; and comprising a plurality of OMA3 Josephson junctions, each OMA3 Josephson junction coupled between a common node and one of a first OMA3 input node, a second OMA3 input node, a third OMA3 input node, a first OMA3 output node, a second OMA3 output node, or a third OMA3 output node; in response to the input, providing at an output node a logic function based on the input, the logic function including at least one of OR2, NOR2, AND2, NAND2, XOR2, XNOR2, NOR3, XS3, NMAJ3, XD3, XNOR3, XNE3, NAND3, OR3, XNS3, MAJ3, XND3, XOR3, XE3, or AND3; A method comprising:

17. providing an initialization signal to induce a desired flux bias in at least a portion of the first plurality of OA2 inductors or the first plurality of OMA3 inductors while cooling the Josephson junction-based logic device; and turning off the initialization signal when the superconducting critical temperature of the Josephson junction-based logic device is reached, and a desired magnetic flux bias persists in the first plurality of OA2 inductors or the first plurality of OMA3 inductors; 17. The method of claim 16 further comprising:

18. 17. The method of claim 16, further comprising converting the single-ended encoded signal to a dual-rail encoded signal, wherein the converting is performed by an SFQ-based strobe logic inverter, and the logic inverter includes a polarity inverter and a logic inverter.

19. 20. The method of claim 18, wherein the SFQ-based input comprises a dual-rail encoded signal.

20. 20. The method of claim 18, further comprising removing dither from at least a portion of the dual-rail data signal, wherein the removing is performed by a Josephson junction-based circuit, the Josephson junction-based circuit including at least one Josephson junction transmission line, at least one delay element, and at least one OR2 gate.

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