An efficient Muller C-element implementation for wide-bit-width asynchronous applications.

Abstract

The system comprises an nMOS active resistor, an nMOS transistor, a pMOS active resistor, and a pMOS transistor, where a portion of the nMOS transistors and a portion of the pMOS transistors are respectively coupled together according to a parallel OR configuration, with a source terminal of the nMOS active resistor coupled to a respective drain terminal of the nMOS transistors, and a source terminal of the pMOS active resistor coupled to a respective drain terminal of the pMOS transistors. The transistor level delay based circuit further comprises a write partial circuit component comprising one of the nMOS transistors coupled to at least one of the pMOS transistors, where the write partial circuit is controlled by an inverse logic signal, and a gating component comprising an additional portion of a plurality of nMOS transistors coupled to an additional portion of the pMOS transistors, where the gating component corresponds to a semi-static cross-coupled inverter circuit.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Patent Application No. 63 / 122,073, filed December 7, 2020, the entire disclosure of which is incorporated herein by reference.

[0002]

[0002] The embodiments described herein relate generally to systems suitable for digital asynchronous applications, and more particularly to systems with Muller C-elements, such as null convention logic-based applications with wide input bit widths. STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0003] This invention was made with government support under award CNS-1916722 from the National Science Foundation. The government has certain rights in this invention. [Background technology]

[0003]

[0004] Synchronous circuits or clocked integrated circuits are susceptible to side-channel attacks (SCAs). For example, Trojan circuits may be incorporated as part of an untrusted foundry and various applications, such as electromagnetic radiation, temperature fluctuations, and operating characteristics, or as part of the manufacturing process, to compromise the operation of synchronous circuits and facilitate the theft of confidential information. Extra hardware, such as Trojan horse circuits, is incorporated as part of the design and manufacturing process of synchronous circuits to compromise and extract information from synchronous circuits during thermal spikes or temperature rises on rising or falling clock edges during operation of clocked integrated circuits, decrypting secret keys, etc. Trojan horse circuits can capture power and dissipated heat on rising and falling clock edges to decrypt confidential information. Techniques to address and overcome SCAs may include the use of clockless asynchronous digital designs, such as speed-independent circuits and delay-independent circuits. However, each of these circuits has limitations. Specifically, they cannot completely eliminate clocks and are space-inefficient. Summary of the Invention [Problem to be solved by the invention]

[0004]

[0005] Therefore, a need exists for an asynchronous null convention logic-based system that is compactly designed and configured to address and overcome the adverse effects of various Trojan horse circuits such as those described above. [Means for solving the problem]

[0005]

[0006] In one embodiment, a system is provided that is suitable for null convention logic (NCL) based applications that benefit from having fast switching speeds and wide input bit widths. The system includes: a two-transistor level delay-based circuit comprising an nMOS active resistor, a plurality of nMOS transistors, a pMOS active resistor, and a plurality of pMOS transistors, wherein at least a portion of the plurality of nMOS transistors are coupled according to a parallel OR configuration and at least a portion of the plurality of pMOS transistors are coupled according to a parallel OR configuration, a source terminal of the nMOS active resistor coupled to respective drain terminals of the plurality of nMOS transistors and a source terminal of the pMOS active resistor coupled to respective drain terminals of the plurality of pMOS transistors; a write sub-circuit component comprising at least one of the plurality of nMOS transistors coupled to at least one of the plurality of pMOS transistors, wherein the write sub-circuit component is controlled by an inverse logic signal; and a gating component comprising an additional portion of the plurality of nMOS transistors coupled to an additional portion of the plurality of pMOS transistors, wherein the gating component corresponds to a semi-static cross-coupled inverter circuit.

[0006]

[0007] In another embodiment, another system is provided that is suitable for null convention logic based applications with wide input bit widths. The system includes: a two-transistor level delay-based circuit comprising an nMOS active resistor, a plurality of nMOS transistors, a pMOS active resistor, and a plurality of pMOS transistors, the two-transistor level delay-based circuit having a fixed delay value independent of an input bit width, wherein at least a portion of the plurality of nMOS transistors are coupled according to a parallel OR configuration and at least a portion of the plurality of pMOS transistors are coupled according to a parallel OR configuration, a source terminal of the nMOS active resistor coupled to respective drain terminals of the plurality of nMOS transistors and a source terminal of the pMOS active resistor coupled to respective drain terminals of the plurality of pMOS transistors; a write partial circuit component comprising at least one of the plurality of nMOS transistors coupled to at least one of the plurality of pMOS transistors, the write partial circuit component being controlled by an inverse logic signal; and a gating component comprising an additional portion of the plurality of nMOS transistors coupled to an additional portion of the plurality of pMOS transistors, the gating component corresponding to a semi-static cross-coupled inverter circuit.

[0007]

[0008] These and additional features offered by the embodiments described herein will be more fully understood from consideration of the following detailed description in conjunction with the drawings.

[0008]

[0009] The embodiments set forth in the drawings are illustrative and exemplary in nature and are not intended to limit the subject matter defined by the claims. The following detailed description of illustrative embodiments can be understood to be read in conjunction with the following drawings, in which like structure is indicated with like reference numerals and in which: [Brief explanation of the drawings]

[0009] [Figure 1]

[0010] FIG. 1 illustrates a synchronous sequential data flow circuit according to one or more embodiments described and illustrated herein. [Figure 2]

[0011] FIG. 1 illustrates an NCL asynchronous dataflow circuit with asynchronous registers according to one or more embodiments described and illustrated herein. [Figure 3A]

[0012] FIG. 1 illustrates a conventional complementary metal oxide semiconductor (“CMOS”) based implementation of a conventional semi-static TH44 according to one or more embodiments described and illustrated herein. [Figure 3B]

[0013] FIG. 2 illustrates an exemplary 16 T mm Muller C-element implementation of a five-stage TH44 gate circuit according to one or more embodiments described and illustrated herein. [Figure 4A]

[0014] FIG. 4 illustrates an exemplary Muller C-element circuit implementation 400 with certain constraints and limitations, according to one or more embodiments described and illustrated herein. [Figure 4B]

[0015] FIG. 2 illustrates an example voltage divider-based feedback circuit according to one or more embodiments described and illustrated herein. [Figure 5A]

[0016] FIG. 1 illustrates a modified EMC inverse logic-based partial circuit that is part of a two-transistor level delay-based circuit of the present disclosure, in accordance with one or more embodiments described and illustrated herein. [Figure 5B]

[0017] FIG. 2 illustrates a write partial circuit that is part of a two-transistor level delay-based circuit of the present disclosure, in accordance with one or more embodiments described and illustrated herein. [Figure 5C]

[0018] FIG. 2 illustrates an EMC Muller C-element gate component that may be included as part of a two-transistor level delay-based circuit of the present disclosure, in accordance with one or more embodiments described and illustrated herein. [Figure 5D]

[0019] FIG. 5B illustrates a two-transistor level delay-based circuit of the present disclosure, comprising a modified EMC inverse logic-based partial circuit shown in FIG. 5A, a write partial circuit shown in FIG. 5B, and an EMC Muller C-element gate component shown in FIG. 5C, each coupled together in accordance with one or more embodiments described and illustrated herein. [Figure 5E]

[0020] FIG. 10 illustrates another implementation of an EMC Muller C-element gate component that may be included as part of a two-transistor level delay-based circuit of the present disclosure, in accordance with one or more embodiments described and illustrated herein. [Figure 5F]

[0021] FIG. 5F illustrates a two-transistor level delay-based circuit of the present disclosure, comprising a modified EMC inverse logic-based partial circuit shown in FIG. 5A, a write partial circuit shown in FIG. 5B, and another implementation of an EMC Muller C-element gate component shown in FIG. 5F, each coupled together in accordance with one or more embodiments described and illustrated herein. [Figure 6]

[0022] FIG. 10 is a graphical waveform diagram corresponding to test waveform results of a conventional TH6464 circuit with an increased stage, in accordance with one or more embodiments described and illustrated herein. [Figure 7]

[0023] FIG. 10 is another graphical waveform diagram, also corresponding to test waveform results, of a conventional TH6464 circuit with an increased stage, in accordance with one or more embodiments described and illustrated herein. [Figure 8]

[0024] FIG. 10 is a graphical waveform diagram including functional and power simulation waveforms of a two-transistor level delay based circuit according to one or more embodiments described and illustrated herein. [Figure 9]

[0025] FIG. 5C is another graphical waveform diagram showing functional and power simulation waveforms of another implementation of a two-transistor level delay based circuit according to one or more embodiments described and illustrated herein, namely, an implementation with a semi-static cross-coupled inverter output stage or circuit, as shown in FIGS. 5E and 5F. [Figure 10]

[0026] FIG. 12 is a graph including relative average power consumption and delay during transitions as a function of active resistor channel length multiplier for a two-transistor level delay-based circuit according to one or more embodiments described and illustrated herein. [Figure 11A]

[0027] FIG. 11A illustrates a CMOS design equivalent to the transistor diagram of a data pass gate according to one or more embodiments described and illustrated herein. [Figure 11B] FIG. 11B illustrates a CMOS design equivalent to the transistor diagram of a data pass gate according to one or more embodiments described and illustrated herein. [Figure 12A]

[0028] FIG. 10 illustrates waveform simulation results for a datapath equivalent of a two-input “AND” gate design, according to one or more embodiments described and illustrated herein. [Figure 12B] FIG. 10 illustrates waveform simulation results for a datapath equivalent of a two-input “OR” gate design in accordance with one or more embodiments described and illustrated herein. DETAILED DESCRIPTION OF THE INVENTION

[0010]

[0029] As mentioned above, synchronous circuits are susceptible to side-channel attacks (SCAs). Techniques to address and overcome SCAs may include the use of clock-free asynchronous digital designs, such as speed-independent and delay-independent circuits, but these techniques cannot completely eliminate clocks and are space-inefficient.

[0011]

[0030] The two-transistor level delay-based circuit as described in the present disclosure addresses and overcomes the drawbacks described above. In one embodiment, the two-transistor level delay-based circuit specifically comprises an nMOS active resistor, a plurality of nMOS transistors, a pMOS active resistor, and a plurality of pMOS transistors, whereby at least a portion of the plurality of nMOS transistors are coupled according to a parallel OR configuration and at least a portion of the plurality of pMOS transistors are coupled according to a parallel OR configuration. Furthermore, a source terminal of the nMOS active resistor is coupled to a drain terminal of each of the plurality of nMOS transistors, a source terminal of the pMOS active resistor is coupled to a drain terminal of each of the plurality of pMOS transistors, a write partial circuit component comprises at least one of the plurality of nMOS transistors coupled to at least one of the plurality of pMOS transistors, the write partial circuit is controlled by an inverse logic signal, and a gate component comprises an additional portion of the plurality of nMOS transistors coupled to an additional portion of the plurality of pMOS transistors, the gate component corresponding to a semi-static cross-coupled inverter circuit.

[0012]

[0031] It should be noted that in an embodiment, a two-level null convention logic ("NCL")-based threshold gate, referred to as a "THmn" gate, has n inputs ("n" represents the total number of inputs of such a gate) and a threshold value m. It should also be noted that a portion of an NCL-based threshold gate, where the total number of inputs to the NCL-based threshold gate ("n") is equal to the threshold value (m), is represented as a Muller C-element. The two-transistor level delay-based circuit of the present disclosure can be used for and operates on a portion of an NCL-based threshold gate, where the input (n) is equal to the threshold value (m). It should further be noted that Muller C-elements are used in a variety of different types of asynchronous circuits in addition to circuits used in NCL-based or NCL-specific applications.

[0013]

[0032] FIG. 1 illustrates a synchronous sequential data flow circuit 100 according to one or more embodiments described and illustrated herein. Note that a synchronous sequential circuit is a digital circuit in which feedback to an input is controlled by a clock signal to generate a specific output. The operation of such circuits is predictable and easy to design. However, synchronous sequential circuits operate slower than asynchronous circuits due to the propagation delay associated with the clock signal reaching all elements of the circuit. Synchronous sequential circuits are typically used in counters, shift registers, memory units, etc. The synchronous sequential data flow circuit 100 uses a register bit width of four signal registers as shown in FIG. 1. Note also that combinational logic circuits may be utilized to generate a specific output, as shown in FIG. 1.

[0014]

[0033] FIG. 2 illustrates an NCL asynchronous dataflow circuit 200 with asynchronous registers according to one or more embodiments described and illustrated herein. A key component of the NCL asynchronous dataflow circuit 200 for handshaking or establishing a communication connection is a traditional feedback circuit (TFBC), indicated by a circular dotted line. The traditional feedback circuit includes a TH44 gate with an inverter placed at the output of the TH44 gate. The notation "THmm" represents a Muller C-element, where "mm" can represent a number (related to the input bit). Note that the "THmm" gate corresponds to the Muller C-element, which is classified as part of the NCL-based threshold gate "THmn," described above. Note that the Muller C-element also operates in and can be used for a variety of different types of asynchronous circuits, in addition to circuits specifically used in NCL-based or NCL-specific applications, as discussed above. In an embodiment, for input bits of 5 or more, a conventional feedback circuit may be implemented during operation of NCL asynchronous dataflow circuit 200 by combining or staging up smaller gates, such as the TH44 gate shown in FIG. 2. Note that in an embodiment, the size and delay of the conventional feedback circuit may be based on a function of the number of inputs of the TFBC, represented by "N," and a single "THmm" Muller C-element may be utilized if the register bit width is equal to a particular number of input bits.

[0015]

[0034] 3A illustrates a conventional complementary metal-oxide semiconductor ("CMOS")-based implementation of conventional semi-static TH44 300 according to one or more embodiments described and illustrated herein. Note that in an embodiment, a constraint of the CMOS-based implementation of conventional semi-static TH44 300 is that the number of transistors connected in series to a significant number of technology nodes is limited to an input bit width of four. Note that the conventional CMOS-based implementation of conventional semi-static TH44 300 comprises a 12-transistor-based dual or two-level delay semi-static TH44 threshold gate.

[0016]

[0035] FIG. 3B illustrates an exemplary 16-T hmm Muller C-element implementation of a five-stage TH44 gating circuit 302 according to one or more embodiments described and illustrated herein. The 16-T hmm Muller C-element implementation of the five-stage TH44 gating circuit 302 is specifically designed for a 16-signal NCL TFBC register, as shown. The gating circuit 302 utilizes five TH44 cells, totaling four transistor delays and 60 transistors. As shown in FIG. 3B, smaller THmm Muller C-elements are arranged or combined in stages to form larger THmm Muller C-elements, which may be static or semi-static. Note that smaller Muller C-elements are arranged or combined in stages to form larger Muller C-elements, as shown in FIG. 3B.

[0017]

[0036] 4A illustrates an exemplary Muller C-element circuit implementation 400 with certain limitations and constraints in accordance with one or more embodiments described and illustrated herein. The exemplary Muller C-element circuit implementation is based on careful and specific sizing of a set of weak transistors, as shown. In an embodiment, a constraint of the exemplary Muller C-element circuit implementation 400 is that the operation of the Muller C-element circuit depends on the sequence or order in which the circuit's inputs switch. As noted above, Muller C-elements are classified as part of NCL-based threshold gates "THmn" and can operate in and be used for a variety of different types of asynchronous circuits, in addition to circuits used specifically for NCL-based or NCL-specific applications.

[0018]

[0037] 4B illustrates an exemplary voltage divider-based feedback circuit 402 according to one or more embodiments described and illustrated herein. In an embodiment, for the exemplary voltage divider-based feedback circuit 402, the only time during operation when the quiescent power can be zero is when all inputs are at "0." This is a limitation of the circuit. Additionally, in an embodiment, another limitation of the voltage divider-based feedback circuit 402 is that the circuit consumes a large amount of power, e.g., twice the amount typically consumed by other circuits.

[0019]

[0038] As described in this disclosure, a system for null convention logic based applications with wide bit widths comprising two-transistor level delay based circuits addresses and overcomes the circuit design constraints described above.

[0020]

[0039] FIG. 5A illustrates a modified EMC inverse logic-based partial circuit 500 that is part of a two-transistor level delay-based circuit of the present disclosure, according to one or more embodiments described and illustrated herein. Note that partial circuit 500 is the result of modifying a particular transistor resistor circuit implementation in which the partial circuit combination is always in the active or on position, resulting in quiescent power always being drawn through the active resistor. Consistently drawing power through the active resistor in quiescent state reduces the operating efficiency of conventional circuits. Partial circuit 500 illustrated in FIG. 5A addresses and overcomes this drawback. Specifically, the design of partial circuit 500 ensures that neither the top circuit within partial circuit 500 (e.g., a set circuit) nor the bottom circuit of partial circuit 500 (e.g., a reset circuit) draws or removes power when all inputs are “0” or “1.” The design of partial circuit 500 also ensures that only one of the resistive transistors is active during an input transition from "0" to "1" or "1" to "0".

[0021]

[0040] In an embodiment, the inverted output “Z b " is sent or fed back to the control gates of the nMOS and pMOS active resistors, respectively. Note that the central portion of partial circuit 500 shows the nMOS and pMOS active resistors. The inverted output Z bWith such routing of the outputs, and depending on the state of the outputs, only one of the two active resistors will be in the "on" state at any given time. In this way, the power draw or fetching constraints when the input is "0" or "1" are addressed or overcome. Note that, as shown in FIG. 5A, the source terminal of the pMOS active resistor is moved or positioned to correspond to the drain terminal of the pMOS input transistor. Note further that the pMOS transistors, which are transistors located in the top portion of the partial circuit 500, are connected or coupled to each other according to a parallel OR configuration. Note further that the source terminal of the nMOS active resistor may be moved or positioned to correspond to the drain terminal of the nMOS input transistor. Note further that the nMOS transistors, which are transistors located in the bottom portion of the partial circuit 500, are connected or coupled to each other according to a parallel OR configuration. The pMOS and nMOS active resistors are located in the center portion of the partial circuit 500, i.e., where the inverting outputs are Z b The output is shown in the circuit. b to the control gates of the nMOS and pMOS active resistors, and by placing the source terminals of the nMOS and pMOS active resistors at the drain terminals of the nMOS and pMOS input transistors, respectively, V DD From V SS There is definitely no path to . Thus, power is saved when the partial circuit is in a quiescent state, i.e., all inputs are "0" or all inputs are "1", or when the partial circuit is transitioning between states, i.e., some inputs are "0" and some inputs are "1".

[0022]

[0041] FIG. 5B illustrates a write partial circuit 502, which is part of a two-transistor level delay-based circuit of the present disclosure, according to one or more embodiments described and illustrated herein. The write partial circuit 502, as illustrated, comprises at least one of a plurality of nMOS transistors coupled to at least one of a plurality of pMOS transistors and is controlled by an inverse logic signal. Note also that the write partial circuit 502 is based on a modified t-gate design. In operation, with respect to node Y, when all inputs are reset from “1” to “0,” the transistor will be in the “on” position and correct the value of “Z” to the reset value “0.” The rest of the time, node Y may be “off,” thus not affecting the value of “Z.” Furthermore, with respect to node X, when all inputs are set to the value “1,” transistor X may be in the “on” position and correct the value of “Z” to the reset value “0.” Transistor X may be in the “off” state the rest of the time.

[0023]

[0042] It should be noted that the widths of the nMOS and pMOS transistors in write subcircuit 502 are based on the particular type of output stage. The width of the transistors, for example, if a conventional semi-static cross-coupled inverter is selected, is determined so that when the transistors are "on," their resistance is small enough to drive the output labeled "Z" (and "Z" as shown in FIG. 5A). b "), designed and sized to disable the cross-coupled inverters. In other embodiments, when a particular amplifier output stage (e.g., a sense amplifier output stage) is selected, the widths of the nMOS and pMOS transistors in the write sub-circuit may be designed to be smaller in size, resulting in space and area savings.

[0024]

[0043] 5C illustrates an EMC Muller C-element gate component 504 that may be included as part of a two-transistor level delay-based circuit of the present disclosure, according to one or more embodiments described and illustrated herein. The EMC Muller C-element gate component 504 is shown to implement digital hysteresis when the output "Z" is set and reset (e.g., from "1" to "0"), minimizing the load on the write partial circuit 502, as shown in FIG. 5B. The gate component comprises an additional portion of multiple nMOS transistors coupled to an additional portion of multiple pMOS transistors, corresponding to the output stage of a semi-static cross-coupled inverter (or semi-static cross-coupled inverter circuit).

[0025]

[0044] 5D illustrates a two-transistor level delay-based circuit 506 of the present disclosure, comprising the modified EMC inverse logic-based partial circuit 500 shown in FIG. 5A, the write partial circuit 502 shown in FIG. 5B, and the EMC Muller C-element gate component 504 shown in FIG. 5C, coupled together in accordance with one or more embodiments described and illustrated herein. As detailed above, the two-transistor level delay-based circuit 506 is designed and operates to reduce delay and can be utilized to reduce or remove constraints on the number of inputs to the two-transistor level delay-based circuit 506. It is further noted that the quiescent power drawn by the two-transistor level delay-based circuit 506 is zero when all of the inputs to the two-transistor level delay-based circuit 506 are "0" and when all of the inputs to the two-transistor level delay-based circuit 506 are "1." The two-transistor level delay-based circuit 506 again ensures that only one active resistor is in the "on" position at any given time. In an embodiment, in a situation where all inputs are either "0" or "1", both active resistors will be in the "off" position.

[0026]

[0045] 5E illustrates another implementation of an EMC Muller C-element gate component 508 that may be included as part of a two-transistor level delay-based circuit of the present disclosure, according to one or more embodiments described and illustrated herein. The alternative implementation corresponds to a sense amplifier output stage or circuit. As illustrated, the EMC Muller C-element gate component 508 is designed to include an additional nMOS transistor compared to the EMC Muller C-element gate component 504 illustrated in FIG. 5C. The alternative implementation of the EMC Muller C-element gate component 508 is further configured to perform a digital hysteresis function and maintain the output value (e.g., "Z") of the two-transistor level delay-based circuit until a specific condition for modifying the value of the output is met.

[0027]

[0046] 5F illustrates a two-transistor level delay-based circuit 510 of the present disclosure, comprising the modified EMC inverse logic-based partial circuit 500 shown in FIG. 5A , the write partial circuit 502 shown in FIG. 5B , and another implementation of an EMC Muller C-element gate component 508 shown in FIG. 5F , each coupled together in accordance with one or more embodiments described and illustrated herein. As detailed above, the two-transistor level delay-based circuit 510 is also designed and operates to reduce delay and can be utilized to reduce or remove constraints on the number of inputs to the two-transistor level delay-based circuit 510. It is further noted that the quiescent power drawn by the two-transistor level delay-based circuit 506 is zero when all of the inputs to the two-transistor level delay-based circuit 506 are “0” and when all of the inputs to the two-transistor level delay-based circuit 506 are “1.” The two-transistor level delay-based circuit 510 again ensures that only one active resistor is in the "on" position at any given time. In an embodiment, in a situation where all inputs are either "0" or "1", both active resistors will be in the "off" position.

[0028]

[0047] As described in this disclosure, a two-level null convention logic ("NCL")-based threshold gate, referred to as a "THmn" gate, has n inputs and a threshold value m. In embodiments, a portion of an NCL-based threshold gate, where the total number of inputs to the NCL-based threshold gate ("n") equals the threshold value (m), is represented as a Muller C-element. The two-transistor level delay-based circuit of the present disclosure can be used for and operates on a portion of an NCL-based threshold gate, where the inputs (n) equal the threshold value (m). It should also be noted that Muller C-elements are used in a variety of different types of asynchronous circuits in addition to NCL-based or NCL-specific applications.

[0029]

[0048] FIG. 6 illustrates a conventional staged TH filter according to one or more embodiments described and illustrated herein. 6464 6 shows a graphical waveform diagram 600 corresponding to the results of a test waveform of the circuit. In an embodiment, a conventional TH 6464 Muller's C-element circuit is a new EMC TH with a semi-static cross-coupled inverter output stage or circuit. 6464 Comparisons were made with Muller's C element. As part of the simulation, all circuit inputs were reset to the value "0". Then, all inputs were individually set to "1" and then reset to "0" again. The input signals thus went through multiple set and reset cycles, and the same input sequence was used in multiple test cases. Tests were performed successfully for input bit-width values ​​where m was 1024.

[0030]

[0049] The graphical waveform diagram 600 shows the first input transitioning from “0” to “1” and the last input changing from “1” to “0.” Specifically, the x-axis 602 corresponds to time values, and the y-axis 604 corresponds to bit width values. As part of the testing process, all inputs were driven with identically sized buffers and outputs, and identically sized loads. Note further that as part of the testing, the lengths of all transistors were selected and designed to be as short as possible, and the widths of all transistors were also designed to be as short as possible. The delay values ​​for all circuits were calculated by averaging the difference between the time when the last input changing reached 50% of its stable value and the time when the output “Z” reached 50% of its stable value. Additionally, the average power was calculated by averaging the numerical data used in the plot over the appropriate test period. The average power consumption, shown at the bottom of the graph, shows spikes during the transition periods, i.e., when the output changes from “0” to “1” and when the output changes from “1” to “0” again.

[0031]

[0050] FIG. 7 also illustrates a conventional TH system with increased stages according to one or more embodiments described and illustrated herein. 6464 Another graphical waveform diagram 700 is shown corresponding to the results of the test waveform for the circuit. Graphical waveform diagram 700 shows an output transition when an input (e.g., the last input) is set to a value of "1" to satisfy the threshold input and set the output value of "Z" to "1", and another output transition when the last input is reset to "0" to reset the output Z back to "0", as shown.

[0032]

[0051] 8 shows a graphical waveform diagram 800 including functional and power simulation waveforms of a two-transistor level delay based circuit according to one or more embodiments described and illustrated herein. Comparing the graphical waveform diagram 800 with the graphical waveform diagrams 600 and 700, the TH 64648 shows a discernible delay during operation of the gate. In contrast, in the graphical waveform diagram 800 of the two-transistor level delay based circuit of the present disclosure, there is a minimal or negligible delay at the output as a result of the input changing, for example, from "0" to "1," and there is another minimal or negligible delay at the other output as a result of resetting the input from "1" to "0." The two-transistor level delay based circuit of the present disclosure is different from the conventional stage-added TH 6464 Compared to the operation of the circuit, the power consumption in the quiescent state when both circuits are quiescent (e.g., when all inputs are reset to the same value "0" or set to the same value "1") is ensured to be low or minimal. It should be noted that an advantage of the two-transistor level delay based circuit is that it allows for faster switching times between two gates, for example, when an input switches from "0" to "1" and from "1" to "0". Additionally, another advantage of the two-transistor level delay based circuit of the present disclosure is that the total number of transistors used for proper operation of the two-transistor level delay based circuit is reduced compared to the conventional stage-increased TH 6464 It is further noted that the size of the nMOS and pMOS active resistors in the two-transistor level delay-based circuits of the present disclosure acts to directly control the delay and power consumption of the two-transistor level delay-based circuits.

[0033]

[0052] FIG. 9 shows another graphical waveform diagram 900 illustrating functional and power simulation waveforms of another implementation of a two-transistor level delay-based circuit according to one or more embodiments described and illustrated herein, namely, an implementation with a semi-static cross-coupled inverter output stage or circuit, as shown in FIGS. 5E and 5F . The graphical waveform diagram 900 includes an x-axis 902 corresponding to time and a y-axis 904 corresponding to input bit width. Specifically, the graphical waveform diagram 900 illustrates output transitions from “0” to “1” and “1” to “0” as a result of input “0” to “1” and “1” to “0” transitions, respectively. As shown, the delay between the input and output during the transitions is minimal or negligible. Furthermore, the quiescent power consumption levels or spikes during the input and output transitions are significantly lower than those of the conventional multi-stage TH1100 described above. 6464 It is small compared to the power consumption level of the circuit.

[0034]

[0053] 10 illustrates a graphical representation 1000 including relative average power consumption and delay during transitions as a function of the channel length multiplier of the active resistor for a two-transistor level delay-based circuit according to one or more embodiments described and illustrated herein. The graphical representation 1000 includes an x-axis 1002 corresponding to channel lengths ranging from 1 to 8 and a y-axis 1004 corresponding to power consumption. An additional y-axis is included, corresponding to delay. As shown, as channel length increases, delay 1008 also increases and power consumption 1006 decreases. The curves, or graphs, for delay 1008 and power consumption 1006 are approximately inversely related.

[0035]

[0054] Table 1, presented below, shows the results of a conventional stepped TH according to one or more embodiments described and illustrated herein. 6464 Included are comparisons of various elements of the circuit with the two-transistor level delay based circuit of the present disclosure.

[0036] [Table 1]

[0037]

[0055] As shown in the table, the total number of transistors, the number of transistor delays, the simulated delay, and the average quiescent power for the two-transistor level delay-based circuit of the present disclosure are significantly higher than the conventional stage-increasing TH described above. 6464 For at least these reasons, the two-transistor level delay-based circuits of the present disclosure are significantly smaller than, for example, the conventional stage-augmented TH circuits described above. 6464 The shortcomings of the circuit are addressed and overcome.

[0038]

[0056] 11A and 11B show CMOS designs 1100 and 1102, respectively, corresponding to transistor diagrams of data pass gates according to one or more embodiments described and illustrated herein. In embodiments, the data pass gate designs shown in FIGS. 11A and 11B are specific or custom complementary metal-oxide-semiconductor gate designs configured to simultaneously receive both asynchronous and synchronous signals while maintaining a specific Boolean function. Such designs also allow for the conversion of synchronous netlists into hybrid (i.e., synchronous and asynchronous) netlists. Such designs offer many advantages, namely, additional security against side-channel attacks that target and expose sensitive data.

[0039]

[0057] In embodiments, the conversion method can be based on timing critical path data of the design and is configured to preserve all functionality of the original netlist. Such designs include data pass gates that receive both synchronous and asynchronous signals and can perform an execution operation only if a value is set for the asynchronous input. It should also be noted that data pass gates can be utilized to convert a portion of a synchronous netlist into a hybrid netlist based on one or more timing critical paths. This hybrid netlist minimizes circuit area while providing additional security benefits, namely, security against side-channel attacks. It should also be noted that such designs maintain a return-to-zero (RTZ) property, such that a circuit based on such a design will not perform an execution operation until an asynchronous input is set, regardless of whether the input arrives at the gate synchronously. It should also be noted that the data paths described above can be included as part of such a design to replace one or more timing critical paths while ensuring that area is not compromised, without increasing beyond a certain threshold.

[0040]

[0058] The design methodology for designing the CMOS designs 1100 and 1102 is based on a five-step process, detailed in Table 1 presented below.

[0041] [Table 2]

[0042]

[0059] Table 1 above shows the evolved Boolean equations representing the pull-down network (PDN) and pull-up network (PUN) of the CMOS design described above. In an embodiment, the A signal may be an asynchronous input, and the B signal is a synchronous input. Note that it is an important design feature of the CMOS design that the gates contained within the CMOS design only need to perform an execute operation if the value of A is set. As part of step 1, the minterm of the Boolean equation may be changed from A to A1, which will serve as the logic high wire of the data pass gate. Steps 2 and 3 then provide a Boolean equivalent to the PDN of the F0 output. In an embodiment, to achieve an inverted input, the input would first need to be parsed through a NOT gate before reaching the data pass gate, by adding another level of gate delay. To address and overcome this issue, all inverted synchronous input signals in the PDN path of the data pass gate will be sent to pMOS gates rather than the usual nMOS gates. All asynchronous inputs can then be connected to a series of p-channel metal-oxide semiconductor (pMOS) gates to design a PUN of data pass gates.

[0043]

[0060] This ensures that only asynchronous input signals are set and remain static along with the output data path signals. Furthermore, a key step in designing the data pass gates involves determining the appropriate size of each transistor. In an embodiment, the transistor sizes were designed so that the width of the transistors was modified while keeping all lengths uniform. Furthermore, as shown in CMOS designs 1100 and 1102, the backward inverter G2 was designed to have the minimum size for all data pass gates, and the forward inverter G1 was designed to have twice the size of the minimum-sized inverter. This design was applied uniformly to all data pass gate designs. The PDNs for all designs were sized according to the longest existing path from GND to the input of the forward inverter in a particular design. Note also that the pMOS transistors were designed to have sizes according to the path of the two transistors in a similar manner to that used in the design of the PDNs, since all PUNs were designed identically.

[0044]

[0061] 12A and 12B show waveform simulation results 1200 and 1202, respectively, for the datapath equivalents of a two-input "AND" gate design and a two-input "OR" gate design, according to one or more embodiments described and illustrated herein. These simulation results illustrate the important results that, in essence, outputs are never set during a "NULL" waveform, and that both a logic high output and a logic low output are never set to have a high value simultaneously. Such important results enable circuit operation and preserve circuit functionality while maintaining the RTZ characteristics of asynchronous circuits.

[0045] List of Aspects

[0062] Aspect 1. A system for null convention logic based applications having a wide bit width, comprising: a two-transistor level delay-based circuit comprising an nMOS active resistor, a plurality of nMOS transistors, a pMOS active resistor, and a plurality of pMOS transistors, wherein at least a portion of the plurality of nMOS transistors are coupled according to a parallel OR configuration and at least a portion of the plurality of pMOS transistors are coupled according to a parallel OR configuration, a source terminal of the nMOS active resistor coupled to respective drain terminals of the plurality of nMOS transistors and a source terminal of the pMOS active resistor coupled to respective drain terminals of the plurality of pMOS transistors; a write partial circuit component comprising at least one of the plurality of nMOS transistors coupled to at least one of the plurality of pMOS transistors, wherein the write partial circuit component is controlled by an inverse logic signal; and a gating component comprising an additional portion of the plurality of nMOS transistors coupled to an additional portion of the plurality of pMOS transistors, wherein the gating component corresponds to a semi-static cross-coupled inverter circuit.

[0046]

[0063] Embodiment 2. The system of embodiment 1, wherein the two-transistor level delay based circuit is a Muller C-element based electromagnetic compatibility circuit.

[0064] Embodiment 3. The system of embodiment 1 or embodiment 2, wherein the write partial circuit is based on a modified t-gate.

[0047]

[0065] Embodiment 4. The system of any of embodiments 1 to 3, wherein a source terminal of the nMOS active resistor coupled to the respective drain terminal of the plurality of nMOS transistors and a source terminal of the pMOS active resistor coupled to the respective drain terminal of the plurality of pMOS transistors block a path from a drain voltage of the two-transistor level delay based circuit to a source voltage of the two-transistor level delay based circuit when an input associated with the two-transistor level delay based circuit is associated with a value equal to zero when the input associated with the two-transistor level delay based circuit is associated with a different value, one.

[0048]

[0066] Embodiment 5. The system of any of embodiments 1-4, wherein the gate component further comprises an additional nMOS transistor of the plurality of nMOS transistors connected to an additional portion of the plurality of nMOS transistors, the additional portion being coupled to an additional portion of the plurality of pMOS transistors.

[0049]

[0067] Embodiment 6. The system of embodiment 5, wherein the gating component further comprising an additional nMOS transistor corresponds to a sense amplifier circuit.

[0068] Embodiment 7. The system of embodiment 6, wherein the sense amplifier circuitry implements digital hysteresis.

[0050]

[0069] Embodiment 8. The system of embodiment 7, wherein implementing digital hysteresis enables maintaining an output value of two transistor level delays until the plurality of inputs are reset from a first value to a second value.

[0051]

[0070] Embodiment 9. The system of embodiment 8, wherein the first value corresponds to one and the second value corresponds to zero.

[0071] Embodiment 10. The system of embodiment 10, wherein the two-transistor level delay based circuit has a fixed delay value that is independent of the input bit width.

[0052]

[0072] Embodiment 11. The system of embodiment 7, wherein the sense amplifier circuitry offloads the write subcircuitry.

[0073] Aspect 12. A system for null convention logic-based applications with a wide input bit width, comprising: a two-transistor level delay-based circuit comprising an nMOS active resistor, a plurality of nMOS transistors, a pMOS active resistor, and a plurality of pMOS transistors, wherein the two-transistor level delay-based circuit has a fixed delay value independent of the input bit width, at least a portion of the plurality of nMOS transistors are coupled according to a parallel OR configuration, at least a portion of the plurality of pMOS transistors are coupled according to a parallel OR configuration, and a source terminal of the nMOS active resistor is coupled to each drain terminal of the plurality of nMOS transistors. a two-transistor level delay-based circuit, wherein a source terminal of the pMOS active resistor is coupled to each drain terminal of a plurality of pMOS transistors; a write partial circuit component comprising at least one of a plurality of nMOS transistors coupled to at least one of the plurality of pMOS transistors, the write partial circuit being controlled by an inverse logic signal; and a gate component comprising an additional portion of a plurality of nMOS transistors coupled to an additional portion of the plurality of pMOS transistors, the gate component corresponding to a semi-static cross-coupled inverter circuit.

[0053]

[0074] Embodiment 13. The system of embodiment 12, wherein the two-transistor level delay based circuit is a Muller C-element based electromagnetic compatibility circuit.

[0075] Embodiment 14. The system of embodiment 12, wherein the write sub-circuit is based on a modified t-gate.

[0054]

[0076] Embodiment 15. The system of embodiment 12, wherein a source terminal of the nMOS active resistor coupled to the respective drain terminals of the plurality of nMOS transistors and a source terminal of the pMOS active resistor coupled to the respective drain terminals of the plurality of pMOS transistors block a path from a drain voltage of the two-transistor level delay based circuit to a source voltage of the two-transistor level delay based circuit when an input associated with the two-transistor level delay based circuit is associated with a value equal to zero, different from when the input associated with the two-transistor level delay based circuit is associated with a value equal to one.

[0055]

[0077] Embodiment 16. The system of embodiment 12, wherein the gate component further comprises an additional nMOS transistor of the plurality of nMOS transistors connected to an additional portion of the plurality of nMOS transistors coupled to an additional portion of the plurality of pMOS transistors.

[0056]

[0078] Embodiment 17. The system of embodiment 16, wherein the gating component further comprising an additional nMOS transistor corresponds to a sense amplifier circuit.

[0079] Embodiment 18. The system of embodiment 17, wherein the sense amplifier circuitry implements digital hysteresis.

[0057]

[0080] Embodiment 19. The system of embodiment 18, wherein implementing digital hysteresis enables maintaining an output value of the two-transistor level delay based circuit until the plurality of inputs are reset from a first value to a second value.

[0058]

[0081] Embodiment 20. The system of embodiment 17, wherein the sense amplifier circuitry reduces the load on the write subcircuitry.

[0059]

[0082] The terminology used herein is for the purpose of describing particular aspects only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include plural forms, including "at least one," unless the content clearly dictates otherwise. "Or" means "and / or." As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. As used herein, it will be further understood that the terms "comprises (third person singular present)" and / or "comprises (present participle)," or "includes (third person singular present)" and / or "includes (present participle)," specify the presence of stated features, regions, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof. The term "or combinations thereof" means combinations including at least one of the aforementioned elements.

[0060]

[0083] It should be noted that the terms "approximately" and "about" may be used herein to express the inherent degree of uncertainty that may exist with any quantitative comparison, value, measurement, or other representation. These terms are also used herein to express the degree to which a quantitative representation may vary from the stated standard without resulting in a change in the basic functionality of the subject matter at issue.

[0061]

[0084] While particular embodiments have been illustrated and described herein, it should be understood that various other changes and modifications can be made without departing from the spirit and scope of the claimed subject matter. Moreover, although various aspects of the claimed subject matter have been described herein, such aspects need not be utilized in combination. It is therefore intended that the appended claims cover all such changes and modifications that are within the scope of the claimed subject matter.

Claims

1. 1. A system for null convention logic based applications with wide input bit widths, comprising: A two-transistor level delay based circuit comprising an nMOS active resistor, a plurality of nMOS transistors, a pMOS active resistor, and a plurality of pMOS transistors; at least a portion of the plurality of nMOS transistors are coupled according to a parallel OR configuration, and at least a portion of the plurality of pMOS transistors are coupled according to the parallel OR configuration; a source terminal of the nMOS active resistor coupled to a drain terminal of each of the plurality of nMOS transistors; a source terminal of the pMOS active resistor coupled to a drain terminal of each of the plurality of pMOS transistors; a two-transistor level delay based circuit; a write subcircuit component comprising at least one of the plurality of nMOS transistors coupled to at least one of the plurality of pMOS transistors, the write subcircuit component being controlled by an inverse logic signal; a gate component comprising an additional portion of the plurality of nMOS transistors coupled to an additional portion of the plurality of pMOS transistors, the gate component corresponding to a semi-static cross-coupled inverter circuit; A system comprising:

2. 2. The system of claim 1, wherein the two-transistor level delay based circuit is a Muller C-element based electromagnetic compatibility circuit.

3. 2. The system of claim 1, wherein the write sub-circuit is based on a modified t-gate.

4. 2. The system of claim 1, wherein the source terminal of the nMOS active resistor coupled to the respective drain terminals of the plurality of nMOS transistors and the source terminal of the pMOS active resistor coupled to the respective drain terminals of the plurality of pMOS transistors block a path from a drain voltage of the two-transistor level delay based circuit to a source voltage of the two-transistor level delay based circuit when an input associated with the two-transistor level delay based circuit is associated with a value equal to zero when the input associated with the two-transistor level delay based circuit is associated with a different value, one.

5. 2. The system of claim 1, wherein the gate component further comprises an additional nMOS transistor of the plurality of nMOS transistors connected to the additional portion of the plurality of nMOS transistors coupled to the additional portion of the plurality of pMOS transistors.

6. 6. The system of claim 5, wherein the gating component further comprising the additional nMOS transistor corresponds to a sense amplifier circuit.

7. The system of claim 6 , wherein the sense amplifier circuitry implements digital hysteresis.

8. 8. The system of claim 7, wherein the implementing the digital hysteresis enables maintaining an output value of the two-transistor level delay based circuit until a plurality of inputs are reset from a first value to a second value.

9. The system of claim 8 , wherein the first value corresponds to one and the second value corresponds to zero.

10. 2. The system of claim 1, wherein the two-transistor level delay based circuit has a fixed delay value that is independent of the input bit width.

11. 8. The system of claim 7, wherein the sense amplifier circuitry offloads the write subcircuitry.

12. 1. A system for null convention logic based applications with wide input bit widths, comprising: A two-transistor level delay based circuit comprising an nMOS active resistor, a plurality of nMOS transistors, a pMOS active resistor, and a plurality of pMOS transistors, wherein the two-transistor level delay based circuit has a fixed delay value independent of an input bit width; at least a portion of the plurality of nMOS transistors are coupled according to a parallel OR configuration, and at least a portion of the plurality of pMOS transistors are coupled according to the parallel OR configuration; a source terminal of the nMOS active resistor coupled to a drain terminal of each of the plurality of nMOS transistors; a source terminal of the pMOS active resistor coupled to a drain terminal of each of the plurality of pMOS transistors; a two-transistor level delay based circuit; a write subcircuit component comprising at least one of the plurality of nMOS transistors coupled to at least one of the plurality of pMOS transistors, the write subcircuit component being controlled by an inverse logic signal; a gate component comprising an additional portion of the plurality of nMOS transistors coupled to an additional portion of the plurality of pMOS transistors, the gate component corresponding to a semi-static cross-coupled inverter circuit; A system comprising:

13. 13. The system of claim 12, wherein the two-transistor level delay based circuit is a Muller C-element based electromagnetic compatibility circuit.

14. 13. The system of claim 12, wherein the write sub-circuit is based on a modified t-gate.

15. 13. The system of claim 12, wherein the source terminal of the nMOS active resistor coupled to the respective drain terminals of the plurality of nMOS transistors and the source terminal of the pMOS active resistor coupled to the respective drain terminals of the plurality of pMOS transistors block a path from a drain voltage of the two-transistor level delay based circuit to a source voltage of the two-transistor level delay based circuit when an input associated with the two-transistor level delay based circuit is associated with a value equal to zero when the input associated with the two-transistor level delay based circuit is associated with a different value, one.

16. 13. The system of claim 12, wherein the gate component further comprises an additional nMOS transistor of the plurality of nMOS transistors connected to the additional portion of the plurality of nMOS transistors coupled to the additional portion of the plurality of pMOS transistors.

17. 17. The system of claim 16, wherein the gating component further comprising the additional nMOS transistor corresponds to a sense amplifier circuit.

18. 20. The system of claim 17, wherein the sense amplifier circuitry implements digital hysteresis.

19. 20. The system of claim 18, wherein the implementing the digital hysteresis enables maintaining an output value of the two-transistor level delay based circuit until a plurality of inputs are reset from a first value to a second value.

20. 20. The system of claim 17, wherein the sense amplifier circuitry reduces the load on the write subcircuitry.

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