Peak voltage amplitude detector tolerant to process variations and device mismatches and related methods

Abstract

The peak detector includes multiple small-sized amplitude detection circuits coupled in parallel to a signal input receiving a signal from a VCO. Each amplitude detection circuit generates a voltage at its output (specifically, the differential output of the VCO) indicative of the voltage peak or amplitude of the first and second signal inputs. At a given time, only one small-sized amplitude detection circuit is active to load the VCO, thereby reducing its impact on the LC resonant frequency. The multiple small-sized detection circuits function sequentially, and automatic averaging of their outputs can significantly improve the peak detector's variability (caused by process variations and device mismatches) compared to each single small-sized amplitude detection circuit.

Description

[Technical Field]

[0001] The techniques of this disclosure relate generally to phase-locked loops (PLLs), and more particularly to maintaining a stable amplitude of a PLL output signal. [Background technology]

[0002] Wireless communications are utilized by smartphones and other mobile devices for voice communications and many other applications. To support growing needs in this area, fifth-generation new radio (5G-NR) technology provides high-speed cellular communications and the Internet of Things across several different frequency bands over a wide range of frequencies. Wired transmission media also support multiple simultaneous transmissions using frequency division techniques. To avoid interference between signals transmitted simultaneously over the same wired and wireless transmission media, the transmitted signals must remain at frequencies within their assigned frequency bands.

[0003] In this regard, the transmitter includes a phase-locked loop (PLL) circuit to maintain the frequency of the transmitted signal within a specified frequency range. The PLL provides a control signal to a voltage-controlled oscillator (VCO) to generate a signal having a desired amplitude and frequency. A peak detector is used to monitor the amplitude of the generated signal. The peak detector detects the amplitude of the generated signal's voltage oscillation and provides feedback to the PLL to adjust the control signal to the VCO to correct when the amplitude deviates from the desired amplitude range. As technology advances and voltage levels are reduced to reduce power consumption, the peak amplitude of the desired range of signal voltage decreases, making the accuracy of the peak detector more important. Additionally, the accuracy of circuits, including peak detectors, tends to vary across manufacturing process corners, resulting in inconsistent device operating characteristics. Summary of the Invention

[0004] Exemplary embodiments disclosed herein include a peak voltage amplitude detector that is tolerant to process variations and device mismatches. A method for detecting peak voltage amplitude is also disclosed. A peak voltage amplitude detector ("peak detector") in an integrated circuit (IC) is utilized in a phase-locked loop (PLL) to monitor the peak amplitude of a signal generated by a voltage-controlled oscillator (VCO). While the transistors used in peak detectors in different devices or ICs will inevitably be from various manufacturing process corners, resulting in differences in operating characteristics, output variations between such devices (or ICs) are significantly reduced when a higher alternating current (AC) input amplitude is applied to the input signal to the peak detector. The AC input amplitude depends on the ratio of the coupling capacitance to the load capacitance of the peak detector circuit. Using smaller transistors with smaller load capacitances can increase the AC input amplitude, but device mismatch can lead to greater variations from IC to IC. In this regard, exemplary embodiments provide a peak detector comprising multiple amplitude detection circuits coupled in parallel to a signal input at which a signal is received from a VCO. Each amplitude detection circuit generates a voltage at its output that indicates a voltage difference between the first signal input and the second signal input. The amplitude detection circuits are activated one by one (e.g., sequentially in a rotational manner), for example, to capture peak voltages of the received signal at different times. The amplitude detection circuits include an averaging circuit for generating an average voltage based on an average of the voltages captured by the multiple amplitude detection circuits. The amplitude detection circuit of the peak detector can utilize smaller transistors to maintain higher AC input amplitudes, and the averaging circuit that averages the voltages of the multiple amplitude detection circuits reduces performance variation between ICs compared to peak detectors with a single amplitude detection circuit.

[0005] In one exemplary embodiment, a peak detector is disclosed that includes a plurality of amplitude detection circuits coupled in parallel to a first signal input and a second signal input, each of the amplitude detection circuits configured to generate a peak voltage on an output indicative of the amplitude of an input signal received on the first signal input and the second signal input, and an averaging circuit coupled to the output of each of the plurality of amplitude detection circuits, the averaging circuit configured to generate an average voltage on the peak detector output that includes an average of the peak voltages on the outputs of the plurality of amplitude detection circuits.

[0006] In another exemplary aspect, an IC is disclosed that includes a transmitter configured to generate a transmission signal and a PLL including a voltage-controlled oscillator (VCO). The VCO is configured to generate an output signal having an amplitude based on a control voltage, and the PLL is configured to control the frequency of the transmission signal. The PLL further includes a peak detector including multiple amplitude detection circuits coupled in parallel to a first signal input and a second signal input. Each of the multiple amplitude detection circuits is configured to generate a voltage on its output indicative of a voltage difference between the first signal input and the second signal input. The peak detector further includes an averaging circuit coupled to the output of each of the multiple amplitude detection circuits, the averaging circuit configured to generate an average voltage on the peak detector output that includes an average of the voltages generated on the outputs of the multiple amplitude detection circuits. The PLL further includes a range sensor configured to determine whether the average voltage on the peak detector output is outside a voltage range and to adjust the control voltage in response to determining that the average voltage on the peak detector output is outside the voltage range.

[0007] In another exemplary aspect, a method of detecting amplitude in a peak detector is disclosed that includes a plurality of amplitude detection circuits coupled in parallel to a first signal input and a second signal input, each of the plurality of amplitude detection circuits including an output, an averaging circuit coupled to the output of each of the plurality of amplitude detection circuits, and a peak detector output. The method includes generating a peak voltage on the output of each of the plurality of amplitude detection circuits indicative of the amplitude of an input signal received on the first signal input and the second signal input, and generating an average voltage on the peak detector output that includes an average of the peak voltages on the outputs of the plurality of amplitude detection circuits.

[0008] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several aspects of the present disclosure and, together with the description, serve to explain the principles of the disclosure. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram of a phase-locked loop (PLL) including a voltage-controlled oscillator (VCO). [Figure 2] FIG. 1 is a block diagram of a VCO circuit including a regulated voltage source and an exemplary peak detector for determining whether the output signal of the VCO circuit is within a desired range. [Figure 3] FIG. 1 shows a schematic diagram of a source follower circuit including a capacitor for capturing the peak voltage of an input signal, and a diagram comparing the output signal with the input signal. [Figure 4] FIG. 1 is a schematic diagram of a source follower circuit including a coupling capacitor circuit to illustrate the ratio required for high amplitude AC inputs to reduce output variation across process corners. [Figure 5] FIG. 2 is a block diagram of an example of an exemplary peak detector in which each of the amplitude detection circuits includes a capacitive coupling circuit. [Figure 6] FIG. 10 is a block diagram of another example of an exemplary peak detector and a timing diagram illustrating sequential sharing of one capacitive coupling circuit between each of the amplitude detection circuits. [Figure 7]7 is a block diagram of the example peak detector of FIG. 6 coupled to a first example of an averaging circuit for averaging the voltages generated in each of the amplitude detection circuits. [Figure 8] 8 is a block diagram illustrating another view of the example peak detector of FIG. 6 coupled to another example averaging circuit that utilizes fewer capacitors between the amplitude detection circuits than the example of FIG. 7. [Figure 9] 9A to 9D are a series of configuration diagrams showing the operation of the averaging circuit of FIG. [Figure 10] 10 is a flow chart illustrating a method for detecting peak amplitudes in a peak detector having multiple parallel amplitude detection circuits. [Figure 11] FIG. 1 is a block diagram of an exemplary processor-based system including multiple devices coupled together through a system bus, the processor-based system comprising at least one integrated circuit (IC) including a VCO having a peak detector including multiple amplitude detection circuits to provide immunity to process variations and device mismatches. DETAILED DESCRIPTION OF THE INVENTION

[0010] Several exemplary aspects of the present disclosure are described with reference to the drawings. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0011] Exemplary embodiments disclosed herein include a process and a mismatch-tolerant peak voltage amplitude detector. A method for detecting peak voltage amplitude is also disclosed. A peak voltage amplitude detector ("peak detector") within an integrated circuit (IC) is utilized in a phase-locked loop (PLL) to monitor the peak amplitude of a signal generated by a voltage-controlled oscillator (VCO). While the transistors used within peak detectors within different devices or ICs will necessarily be from different manufacturing process corners, resulting in differences in operating characteristics, output variations between such devices (or ICs) are significantly reduced when the input signal to the peak detector provides a higher alternating current (AC) input amplitude. The AC input amplitude depends on the ratio of the coupling capacitance to the load capacitance of the peak detector circuit. Using smaller transistors with smaller load capacitances can increase the AC input amplitude, but device mismatch can lead to greater variations between ICs. In this regard, exemplary embodiments provide a peak detector comprising multiple amplitude detection circuits coupled in parallel to a signal input at which a signal is received from a VCO. Each amplitude detection circuit generates a voltage on its output that indicates a voltage difference between the first signal input and the second signal input. The amplitude detection circuits are activated one by one (e.g., sequentially in a rotational manner), for example, to capture peak voltages of the received signal at different times. The amplitude detection circuits include an averaging circuit for generating an average voltage based on an average of the voltages captured at the multiple amplitude detection circuits. The amplitude detection circuit of the peak detector can utilize smaller transistors to maintain higher AC input amplitudes, and the averaging circuit that averages the voltages of the multiple amplitude detection circuits reduces performance variation between ICs compared to peak detectors with a single amplitude detection circuit.

[0012] Before describing an example of an exemplary peak detector according to the present disclosure with reference to Figures 5-8, an example of a phase-locked loop (PLL) 100 will be briefly described with reference to Figure 1. An example of a voltage-controlled oscillator (VCO) 200 is shown in Figure 2, and an example of a peak detector circuit will be discussed with reference to Figures 3 and 4.

[0013] 1 is a block diagram of a PLL 100, including conventional components as well as an exemplary VCO 102. A crystal oscillator 104 provides a signal SCO oscillating at a stable frequency. The signal SCO is provided to a phase detector 106, which detects the frequency F of the signal SCO. SCO The frequency of the feedback signal SFB is F SFB Compared with frequency F SCO and F SFB Based on the phase / frequency difference between the voltage signal V PD Generates a voltage signal V PD is provided to a low pass filter 108, which filters the voltage signal V PD The low-pass filter 108 removes noise and high frequency components from the voltage signal V LP produces a voltage signal V LP is the output signal V OUT The frequency F VCO to the desired frequency F OUT The output signal V OUT may be used to determine the frequency of a wired or wireless signal transmitted by a transmitter (not shown). OUT is also the frequency F of the signal SCO SCO is too fast or too slow, and the output signal V OUT is fed back to the phase detector 106 to determine whether the output signal V is out of phase with the signal SCO. Typically, as in the PLL 100, OUT is the frequency F of the signal SCO SCO Since it is a multiple (for example, N times) of OUT is first divided (e.g., by N) in divider 110 before being provided to phase detector 106 as feedback signal SFB. Although not shown in FIG. 1, PLL 100 also adjusts output signal V OUT The present invention includes circuitry for monitoring and adjusting the amplitude of the

[0014] 2 is a diagram of an exemplary VCO top circuit 200, which may be VCO 102 in FIG. 1 and is provided as an example of a circuit in which an exemplary peak detector 202 may be utilized. VCO top circuit 200 generates an output signal V OUT a VCO core circuit 204 for generating an output signal V OUT 1 may be an output signal of the PLL 100 in FIG. 1 that is provided to a transmitter (not shown) for wired or wireless communication. In some examples, the VCO core circuit 204 may be an LC tank circuit including an inductive element (L) and a capacitive element (C), as known in the art. The output V of the VCO core circuit 204 OUT The amplitude of V is strongly influenced by the regulated supply voltage VDD_VCO generated by the low-drop output regulator (LDO) circuit 224. A higher VDD_VCO within the range / level allowed by the process will increase V OUT The amplitude is increased and the VCO output noise is correspondingly lower. Other types of VCO circuits may be used in PLL 100 of Figure 1, and such VCO circuits may also utilize a peak detector as disclosed herein.

[0015] The power device 206 in the LDO regulator circuit 224 isolates the VCO core circuit 204 from noise that may be present in the external power supply VDD. In this example, the power device 206 includes multiple power circuit "slices" 208(1)-208(X) coupled in parallel with one another. Each of the slices 208(1)-208(X) in FIG. 2 receives a control signal S that controls a transistor 212. SLC A capacitor 210 is included to reduce noise in the slices 208(1)-208(X). Depending on the power requirements, a sufficient number of slices 208(1)-208(X) are enabled to provide the required level of power in parallel to the VCO circuit 204. The supply voltage VDD_VCO is proportional to the feedback signal S generated by the peak detector 202. ADJThe gate control signal S for the power device 206 is generated by the slices 208(1)-208(X) under the influence of a feedback circuit 214 that receives the reference voltage VREF. SLC helps to create.

[0016] The VCO core circuit 204 generates the output signal VCO+ as a differential signal on outputs VCO-. OUT In the example transmitter including the PLL 100 of FIG. OUT is provided to peak detector 202 at a maximum sustainable amplitude (i.e., voltage) that will not cause damage to the circuitry therein. The maximum sustainable amplitude is determined to be a point that is at the high end of the transistor's voltage range, but low enough to avoid long-term device damage that would reduce the device's life expectancy. Thus, the output signal V OUT is preferably as close as possible to the maximum sustainable amplitude to maximize power and efficiency.

[0017] In this regard, the VCO top circuit 200 generates an output signal V OUT The peak detector 202 is included to keep the amplitude of the output signal V within a small range close to the maximum sustainable amplitude. OUT The peak voltage V indicates the maximum amplitude detected PK The range detector 218 holds (e.g., captures) and generates the peak voltage V PK is outside the desired range and provides a feedback signal S to the feedback circuit 214. ADJ In response, feedback circuit 214 causes VCO core circuit 204 to generate an amplitude V OUT The range detector 218 adjusts the peak voltage V PK , the output signal V OUT The upper and lower limits of the desired voltage range for the high reference voltage V REFH and low reference voltage V REFL The comparators 220H and 220L include comparators 220H and 220L for comparing VOUT It can provide a +1 (220L sends a "1" and 220H sends a "0"), a 0 (220L and 220H both send a "0"), or a -1 (220L sends a "0" and 220H sends a "1") to indicate that the amplitude is above, within, or below the desired range, respectively. Accumulator circuit 222 provides a feedback signal S that indicates the direction of the adjustment needed (i.e., increase or decrease the peak amplitude). ADJ It is useful to accumulate the comparator results after scaling to generate

[0018] However, peak detectors also include circuitry that can be affected by process corners, which can result in significant performance mismatches between different peak detectors. In exemplary embodiments disclosed below, peak detector 202 is tolerant to manufacturing process variations and device mismatches.

[0019] First, examples of circuits that may be utilized within peak detector 202 will be described with reference to Figures 3 and 4. Figure 3 shows an example of a peak detector 202 for an input signal V IN 1 is a block diagram of a peak detector 300 used to capture the peak of each oscillation of a signal. In the context of this description, the term "peak" refers to the maximum voltage or amount of amplitude of the oscillation of a signal. The term "peak" may be used interchangeably with "peak voltage," "amplitude," "maximum voltage," and other related terms.

[0020] The peak detector 300 includes a transistor 302 having a drain terminal DRN, a gate terminal GT, and a source terminal SRC. The transistor 302 may be, for example, a field effect transistor (FET) such as a metal-oxide semiconductor (MOS) FET (MOSFET). In FIG. 3, the transistor 302 is an N-type MOSFET (NFET), but may alternatively be a P-type FET. The drain terminal DRN receives a supply voltage VDD. The source terminal SRC is coupled to an output node 304, on which the peak signal V PKThe source terminal SRC is also coupled to a current source 306 and a capacitor 308. The current source 306 and the capacitor 308 are also coupled to a reference voltage VSS (e.g., ground). An alternating current (AC) signal, or an oscillating signal, is generated by the input signal V IN is provided to the gate terminal GT as

[0021] In this configuration, peak detector 300 detects whether the voltage at source terminal SRC of transistor 302 is greater than the voltage V of the input signal. IN to the gate-source voltage V of the transistor 302 GS This is sometimes called a source follower circuit, as it follows the voltage obtained by subtracting the input signal V IN As the voltage increases, the source terminal SRC increases to the gate-source voltage V GS Because source terminal SRC is coupled to capacitor 308, capacitor 308 charges to the highest voltage level (i.e., peak) reached by source terminal SRC. Thus, output node 304 also follows the voltage difference between input signal V IN to the gate-source voltage V GS Peak voltage V minus PK The input signal V IN , source terminal SRC, and peak signal V PK The relationship between the input signal V and the source terminal SRC is also shown in Figure 3. As shown, the source terminal SRC is connected to the input signal V IN corresponds to the gate-source voltage V between the gate terminal GT and the source terminal SRC. GS The input signal V IN The voltage V of the source terminal SRC is lower than SRC is the gate-source voltage V GS The input signal V on the gate terminal IN As shown here, the peak signal V on output node 304 PK is the input signal V IN As the signal V falls, it slowly decreases. PKThe slow decay of V is caused by current source 306 draining charge from capacitor 308. Without current source 306, capacitor 308 would remain charged to the maximum applied voltage. IN If the amplitude of V decreases in successive oscillations, the peak signal V PK will continue to indicate the voltage to which capacitor 308 is charged and should not correspond to lower peak voltages in subsequent oscillations.

[0022] Although the operating characteristics of transistor 302 may vary from chip to chip due to manufacturing process corners, devices from different process corners have been found to exhibit similar output characteristics in response to sufficiently large AC input amplitudes. AC and the load capacitance C of the transistor 302 G It is determined by the ratio of

[0023] Figure 4 shows the coupling capacitor C AC 4 is a block diagram of a peak detector 400, which includes the peak detector 300 of FIG. 3 with the addition of a load capacitance C G is based on, for example, the capacitance between the gate terminal GT and drain terminal DRN of transistor 302, the source terminal SRC, and the body (not shown).

[0024] As stated, the AC input amplitude is AC , pair, coupling capacitor C AC Plus load capacity C G The sum of, the ratio of (e.g., C AC / (C AC +C G )) which results in a smaller size and a smaller load capacity C GA transistor having a .DELTA..times ...

[0025] 5A includes a plurality of amplitude detection circuits 502(1)-502(N). The amplitude detection circuits 502(1)-502(N) may be referred to herein as a group as "amplitude detection circuits 502." Additionally, unless a specific one of the ranges (1)-(N) is discussed, any individual amplitude detection circuit of the amplitude detection circuits 502 may be referred to generally as "amplitude detection circuit 502." This naming convention is also used herein for other features having numbered ranges below.

[0026] The amplitude detection circuits 502 vary in performance such that there is a distribution (e.g., random distribution) of performance characteristics among the multiple amplitude detection circuits 502. In an IC in which the voltages of multiple amplitude detection circuits are averaged together, the results will vary much less from the results of another IC of this type than would occur when comparing the results of the peak detectors in two ICs, each containing a single amplitude detection circuit. This improvement can be measured as a much lower standard deviation in the average of multiple amplitude detection devices than from a single amplitude detection circuit. In the example of FIG. 5A, there are N amplitude detection circuits. The number N can be any number, for example, in the range of 2 to 100 or more. The operation of the amplitude detection circuit 502 is also described below in accordance with the circuit description.

[0027] 5A , amplitude detection circuits 502 are coupled in parallel to signal inputs 506N and 506P. Each amplitude detection circuit 502 includes a first sense circuit 508N coupled to the signal input 506N and a second sense circuit 508P coupled to the signal input 506P. In this example, the first and second sense circuits 508N and 508P are transistors coupled between a supply voltage source 510 (e.g., a power rail) that provides a supply voltage VDD and an output 512. The output 512 is also coupled to a capacitor 514 and a current source 516. The outputs 512 of the amplitude detection circuits 502(1) through 502(N) are also referred to as outputs 512(1) through 512(N). Within each amplitude detection circuit 502, the capacitor 514 and the current source 516 are also coupled to a reference voltage source 518 that provides a reference voltage VSS (e.g., ground). In this example, signal inputs 506N and 506P are coupled to outputs 520N and 520P of VCO 522. Outputs 520N and 520P are coupled to outputs VCO 522 as the voltage difference between voltage signals VCO− and VCO+. OUT Thus, signal inputs 506N and 506P provide output V OUT The input signal V IN Receive as.

[0028] The amplitude detection circuits 502(1) to 502(N) detect the input signals V received at the signal inputs 506N and 506P. IN Based on the amplitude of PK (1)~V PK 7 and 8, individual amplitude detection circuits of amplitude detection circuits 502(1)-502(N) are activated one by one under the control of control circuit 528. Thus, one activated amplitude detection circuit 502 generates a peak voltage V on its output 512. PK , while all but one of the amplitude detection circuits 502 may be inactive. The amplitude detection circuits 502 may each capture a peak voltage V PKAlternatively, the average voltage may be less than the peak voltage V of the amplitude detection circuit of all of the amplitude detection circuits 502(1) to 502(N). PK may be based on

[0029] To individually activate the amplitude detection circuits 502, each includes a first input switch 530N coupled to the first signal input 506N and a second input switch 530P coupled to the second signal input 506P. The first and second input switches 530N, 530P are controlled by a control circuit 528 to close when the amplitude detection circuit 502 is active and open when it is inactive. The control circuit 528 closes both the first input switch 530N and the second input switch 530P in each of the multiple amplitude detection circuits 502, sequentially, one by one. The control circuit 528 may include hardware logic and storage elements for sequential control of the multiple amplitude detection circuits 502.

[0030] For example, the first and second input switches 530N and 530P of the amplitude detection circuit 502(1) receive the input signal V IN When the first and second input switches 530N, 530P of the amplitude detection circuit 502(1) are opened, the peak voltage V PK is held on capacitor 514 and may be detected on output 512. The first and second input switches 530N, 530P of amplitude detection circuit 502(2) may then be closed to activate amplitude detection circuit 502(2), and so on, up to amplitude detection circuit 502(N). Alternatively, the amplitude detection circuits 502 may be activated in any order, and / or less than all of the amplitude detection circuits 502 may be activated sequentially.

[0031] The amplitude detection circuit 502 includes a first resistor-capacitor (RC) circuit 532N coupled to the first signal input 506N when the first input switch 530N is closed, and a second RC circuit 532P coupled to the second signal input 506P when the second input switch 530P is closed. The first and second RC circuits 532N, 532P couple to the load capacitance C of the first and second sense circuits 508N and 508P. G and the coupling capacitance C that determines the AC input amplitude to 508N and 508P. AC Variations between peak detectors 500 in different devices (e.g., VCOs, PLLs, transmitters) can be reduced by keeping the AC input amplitude to sense circuits 508N and 508P at a high level.

[0032] Further with respect to the amplitude detection circuit 502, the first sense circuit 508N includes a first transistor 534N, such as a field effect transistor (FET), which may be a metal-oxide semiconductor (MOS) FET (MOSFET). The first transistor 534N includes a gate G1 coupled to the first signal input 506N, a first source / drain D1 coupled to the supply voltage source 510, and a second source / drain S1 coupled to the output 512. The second sense circuit 508P includes a second transistor 534P, which includes a gate G2 coupled to the second signal input 506P, a first source / drain D2 coupled to the supply voltage source 510, and a second source / drain S2 coupled to the output 512. As described above, the capacitor 514 is coupled to the output 512 and the reference voltage source 518, and the current source 516 is coupled to the output 512 and the reference voltage source 518. The amplitude detection circuit 502 configured in this manner detects the voltage V provided to the capacitor 514 and the output 512. PK is the voltage drop between the gate G1 and the second source / drain S1 or between the gate G2 and the second source / drain S2 (for example, the gate-source voltage V GS ) minus the voltage at the output.

[0033] It should be noted that the term "coupled" as used herein refers to an electrical coupling, which may include an indirect or direct electrical conductive coupling, which may include an electrical conductive coupling, and may also include a mechanical interlock.

[0034] 6 is a block diagram of another example peak detector, peak detector 600, that is tolerant to process variations and mismatches and includes multiple (e.g., multiple) amplitude detection circuits 602(1)-602(N) to reduce the standard deviation of peak detector 600. The operation of peak detector 600 is the same as peak detector 500 of FIG. 5 and will not be described again here. The structure of peak detector 600 differs from peak detector 500 only in the following aspects.

[0035] 5, each of the amplitude detection circuits 602 includes two RC coupling circuits. Rather than this, the peak detector 600 includes only a first RC coupling circuit 604N and a second RC coupling circuit 604P that can be used by each of the amplitude detection circuits 602(1)-(N) because the amplitude detection circuits 602(1)-(N) are activated one at a time. The RC coupling circuit 604N is coupled to a first signal input 606N and a first input switch 608N of each of the amplitude detection circuits 602. The RC coupling circuit 604P is coupled to a second signal input 606P and a second input switch 608P of each of the amplitude detection circuits 602. The first signal input 606N and the second signal input 606P are coupled to a signal generation circuit 620, which may be a VCO of a PLL. First and second RC coupled circuits 604N and 604P are utilized when the first and second input switches 608N, 608P are closed to activate (e.g., sequentially) one of the amplitude detection circuits 602. By utilizing RC coupled circuits 604N and 604P in this manner, one for each of the amplitude detection circuits 602, the total number of RC coupled circuits in the peak detector 600 is reduced from 2×N to two (2). Each amplitude detection circuit includes a first sense circuit 610N, a second sense circuit 610P, a current source 612, and a capacitor 614.

[0036] 6 also includes a timing diagram 622 illustrating the states of control signals SEL1, SEL2, SEL3, and SELN generated by a control circuit, such as control circuit 528, to control input switches 608N, 608P to sequentially activate amplitude detection circuits 602(1), 602(2), 602(3), and 602(N) (amplitude detection circuits 602(2) and 602(3) are not shown). After activating amplitude detection circuits 602(1)-(N), the process resumes with amplitude detection circuit 602(1) after the averaging process described below with respect to FIGS. 7 and 8. Both FIGS. 7 and 8 include a peak detector corresponding to peak detector 600, but show the peak voltage V captured by amplitude detection circuit 602. PK The following examples illustrate different averaging circuits that may be utilized to generate an average voltage that is an average of the

[0037] 7 is a block diagram of a peak detector 700 that may be coupled to a VCO (not shown) at signal inputs 701N and 701P. As shown, peak detector 700 includes all the features of peak detector 600 and further includes multiple amplitude detection circuits 702. Peak detector 700 detects an average voltage V AVG The amplitude detector circuit 702 also includes an averaging circuit 704 with which the average voltage V can be generated by the averaged output 706 of the amplitude detector circuit 702. AVG is generated by the multiple amplitude detection circuits 702 of the peak detector 700, the peak voltage V generated by a peak detector having only one amplitude detection circuit PK has a lower standard deviation than

[0038] The amplitude detection circuits 702(1) to 702(N) detect the peak voltage V PK is the input signal V received on the signal inputs 701N, 701P. INThe averaging circuit 704 has corresponding outputs 706(1)-706(N) generated thereon based on the maximum voltage of the V detected on the input signal when the amplitude detection circuit 702(1) is activated by closing its input switches 712N and 712P and output switch 710(1) via SEL1. IN to the gate-source voltage V GS Peak voltage V minus PK (V PK =V IN -V GS )

[0039] The averaging circuit 704 also includes averaging switches 714(1) through 702(N) each coupled to the output 706 of two of the amplitude detection circuits 702(1) through 702(N). For example, averaging switch 714(1) is coupled between output 706(1) and output 706(2), averaging switch 714(2) is coupled between output 706(2) and output 706(3), and so on. Thus, the averaging switches 714(1) through 714(N) are coupled in series to couple each of the outputs 706(1) through 706(N) of the amplitude detection circuits 702(1) through 702(N) to the peak detector output 716. Peak detector output 716 is coupled to output 706(N) in the example of FIG. 7, but may be coupled to any of outputs 706(1)-706(N).

[0040] During the charging phase, as shown in timing diagram 720, each amplitude detection circuit 702 is activated one by one as switch select signals SEL1-SELN are sequentially activated to charge its corresponding capacitor 708(1)-708(N). For example, switch select signal SEL1 is activated to close input switches 712N, 712P and output switch 710(1) of amplitude detection circuit 702(1). The input signal V IN After a predetermined time, which may correspond to one or more cycles of, switch select signal SEL1 is deactivated, opening input switches 712N, 712P and output switch 710(1) of amplitude detection circuit 702(1), and switch signal SEL2 is activated, closing input switches 712N, 712P and output switch 710(2) of amplitude detection circuit 702(2).

[0041] During the charging phase, the averaging switches 714(1) through 714(N-1) remain open to electrically isolate the capacitors 708(1) through 708(N) from each other. After the charging phase, when all of the capacitors 708(1) through 708(N) have been charged, the output switches 710(1) through 710(N) remain open when the averaging switches 714(1) through 714(N-1) are closed. A pulse signal AVG is generated (e.g., by control circuitry not shown here) to briefly close the averaging switches 714(1) through 714(N-1), coupling the capacitors 708(1) through 708(N) to each other and to the peak detector output 716. By closing all averaging switches 714(1) through 714(N-1), all capacitors 708(1) through 708(N) are coupled in parallel, thus redistributing their charges and reducing all sustained peak voltages V PK The average voltage V AVG is created. The average voltage V AVG may be detected on the peak detector output 716.

[0042] Assuming that each amplitude detection circuit 702 has some error due to process variations, each error may be random. Therefore, the effect of each individual error is reduced because the individual errors cancel each other out when averaged overall. V AVG The theoretical RMS error of each V PK compared to

[0043]

number

[0044] Figure 8 is a block diagram of a peak detector 800 that includes peak detector 600 of Figure 6 coupled to an alternative averaging circuit that utilizes approximately half the capacitors of peak detector 700 of Figure 7. Peak detector 800 includes amplitude detection circuits 802(1) through 802(N), where N is an even number. Amplitude detection circuits 802(1) through 802(N) include odd amplitude detection circuits 802(1), 802(3), 802(5), ... 802(N-1) ("odd amplitude detection circuit 802O") and even amplitude detection circuits 802(2), 802(4), 802(6), ... 802(N) ("even amplitude detection circuit 802E").

[0045] The peak detector 800 includes an averaging circuit 804 coupled to the outputs 806(1) through 806(N) of the amplitude detection circuits 802(1) through 802(N). Like the averaging circuit 704 of FIG. 7, the averaging circuit 804 is also utilized to average the charge captured by each amplitude detection circuit 802(1) through 802(N). However, rather than having N capacitors, the averaging circuit 804 includes only N / 2+1 capacitors, which are odd capacitors 808O(1) through 808O(N / 2) and even capacitors 808E, as follows: Each of the odd capacitors 808O(1) through 808O(N / 2) is coupled to the output 806 of one of the amplitude detection circuits 802O. The even capacitor 808E may be coupled to the output 806 of any one of the even amplitude detection circuits 802E.

[0046] Again for clarity, outputs 806 of every odd amplitude detector circuit 802O are coupled to respective odd capacitors 808O(1) through 808O(N / 2). Outputs 806 of every even amplitude detector circuit 802E are coupled to even capacitor 808E. Thus, averaging circuit 804 includes approximately half (i.e., N / 2-1 fewer) the number of capacitors used in averaging circuit 704 of FIG. 7.

[0047] Averaging circuit 804 also includes averaging switches 810(1) through 810(N / 2), which are each coupled to an output 806 of one odd amplitude detection circuit among odd amplitude detection circuits 802O and an output 806 of a corresponding even amplitude detection circuit among even amplitude detection circuits 802E. For example, averaging switch 810(1) is coupled to output 806(1) of amplitude detection circuit 802(1) and output 806(2) of amplitude detection circuit 802(2), averaging switch 810(2) is coupled to outputs 806(3) through 806(4) of amplitude detection circuits 802(3) and 802(4), and averaging switch 810(N / 2) is coupled to outputs 806(N-1) through 806(N) of amplitude detection circuits 802(N-1) and 802(N).

[0048] Input signal VIN Each amplitude detection circuit 802 includes input switches 814N, 814P, which correspond to input switches 712N, 712P in FIG. 7, for coupling the amplitude detection circuit 802 to signal inputs 812N, 812P to receive the signal. The averaging circuit 804 includes output switches 816(1)-816(N) for selectively coupling to the output 806 of the amplitude detection circuit 802. During the charging phase of the peak detector 800, the input switches 814N, 814P and output switch 816 operate in the same manner as the input switches 712N, 712P and output 710 during the charging phase of the peak detector 700 described previously. In addition, the averaging circuit 804 is also controlled during the charging phase, as in the following example.

[0049] Referring to timing diagram 820, voltage averaging is performed in pairs of odd and even amplitude detector circuits 808O, 808E, starting with amplitude detector circuits 802(1)-802(2). Control circuit 818 activates switch signal SEL1 to close input switches 814N, 814P and output switch 816(1), charging capacitor 808(1) to voltage V (as described above). PK During this time, the averaging switch 810(1) is open. The input switches 814N, 814P and output switches 816(2) through 816(N) of all other amplitude detection circuits 802 are also open.

[0050] Next, control circuit 818 deactivates switch signal SEL1 to open input switches 814N, 814P and output switch 816(1) and activates switch signal SEL2 to close input switches 814N, 814P and output switch 816(2) of amplitude detection circuit 802(2). Because amplitude detection circuit 802(2) is one of the even amplitude detection circuits, output switch 816(2) couples output 806 to capacitor 808E, which couples input signal V detected at signal inputs 812N, 812P. IN The peak voltage V PK The input signal V INAfter a predetermined time, which may include several cycles of, the control circuit 818 deactivates the switch signal SEL2, opening the input switches 814N, 814P and the output switch 816(2) of the amplitude detection circuit 802(2).

[0051] The control circuit 818 then activates the switch signal SEL3, thereby closing the averaging switch 810(1), thereby coupling the odd capacitor 808O(1) to the even capacitor 808E. In this manner, charge is distributed between the odd capacitor 808O(1) and the even capacitor 808E, resulting in the respective peak voltages V detected by the amplitude detection circuits 802(1)-802(2). PK The average voltage V1 of is held on odd capacitor 808O(1). Switch signal SEL3 is then deactivated to open averaging switch 810(1).

[0052] The process moves to the next pair of odd and even amplitude detector circuits 802(3) and 802(4). As described above, the input switches 814N, 814P and output switch 816 of amplitude detector circuit 802(3) are closed to apply the peak voltage V PK The amplitude detection circuit 802(4) detects the peak voltage V on the even capacitor 808E. PK Averaging switch 810(2) is then closed to hold the peak voltage V across odd capacitor 808O(2) and even capacitor 808E, respectively. PK The average voltage V2 of

[0053] This process is performed by activating the selection signals SELN-1 and SELN to control the amplitude detection circuits 802(N-1) to 802(N) to detect the peak voltage V PK The odd and even pairs of amplitude detector circuits 802 continue until the odd capacitor 808O(N / 2) holds the average voltage V N / 2 Responds to the average voltage V N / 2 is the peak voltage V held on odd capacitor 808O(N / 2) by amplitude detection circuit 802(N-1).PK and the peak voltage V held on the even capacitor 808E by the amplitude detection circuit 802(N). PK is the average of

[0054] When the control circuit 818 activates the switch signal AVG, all the peak voltages V detected by all the amplitude detection circuits 802 are PK The average voltage V AVG is coupled to the peak detector output 822. The switch signal AVG couples all of the odd capacitors 808O(1) through 808O(N / 2) to the even capacitor 808E, thereby providing an average voltage V AVG Peak detector 800 produces the same RMS error improvement over VAVG as peak detector 700 (i.e.,

[0055]

number

[0056] It should be understood that peak detectors including odd numbered amplitude detection circuits may be utilized with obvious modifications of the circuits described above. The operation of averaging circuit 804 can be more clearly understood with reference to Figures 9A-9D. In Figure 9A, amplitude detection circuit 802(1) is coupled to odd capacitor 808O(1) by closing output switch 816(1) while averaging switch 810(1) is open. During this state, the peak voltage V detected by amplitude detection circuit 802(1) is PK 9B, amplitude detection circuit 802(1) is decoupled from odd capacitor 808O(1) by opening output switch 816(1), and amplitude detection circuit 802(2) is coupled to even capacitor 808E by closing output switch 816(2), producing a peak voltage V PK The averaging switch 810(1) remains open.

[0057] In FIG. 9C, amplitude detection circuit 802(2) is decoupled from even capacitor 808E by opening output switch 816(2), and averaging switch 810(1) is closed to hold the average voltage V1 on odd capacitor 808O(1).

[0058] Thus, for each of odd amplitude detection circuits 802O(1) through 802O(N / 2), control circuit 818 closes averaging switch 810 coupled to odd capacitor 808O.

[0059] As shown in FIG. 9D, the remaining odd capacitors 808O(2) to 808O(N / 2) are similarly operated to generate average voltages V2 to V N / 2 After holding, the output switches 816(1) to 816(N) of all amplitude detection circuits 802 remain open, while all averaging switches 810(1) to 810(N / 2) are closed, and the average voltage V of all amplitude detection circuits 802 is output on the peak detector output 822. AVG to provide.

[0060] 10 is a flow chart illustrating a method 1000 of detecting a peak voltage of an input signal utilizing the peak detectors 700 and 800 of Figures 7 and 8. The method includes detecting a peak voltage of an input signal V received on the first signal input 701N, 812N and the second signal input 701P, 812P on the output 706, 806 of each of the plurality of amplitude detection circuits 702, 802 in a peak detector 700, 800 having a plurality of amplitude detection circuits 702, 802 coupled in parallel to a first signal input 701N, 812N and a second signal input 701P, 812P, each of the plurality of amplitude detection circuits 702, 802 having an output 706, 806, an averaging circuit 704, 804 coupled to the output 706, 806 of each of the plurality of amplitude detection circuits 702, 802, and a peak detector output 716, 822. IN The amplitude of the peak voltage V PK on the output 706, 806 of each of the amplitude detection circuits 702, 802. PKThe step of generating a peak voltage V on the outputs 706, 806 of the plurality of amplitude detection circuits 702, 802 may include coupling each of the plurality of amplitude detection circuits 702, 802 sequentially, one at a time, to the first signal input 701N, 812N and the second signal input 701P, 812P (block 1004). The method may further include coupling a peak voltage V on the outputs 706, 806 of the plurality of amplitude detection circuits 702, 802 to the peak detector outputs 716, 822. PK The average voltage V AVG , which may further include combining (1008) the outputs 706, 806 of the plurality of amplitude detection circuits 702, 802 to the peak detector output.

[0061] FIG. 11 is a block diagram of an exemplary processor-based system 1100 including a processor 1102 (e.g., a microprocessor) that includes an instruction processing circuit 1104. The processor-based system 1100 may be one or more circuits included in an electronic board card such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing pad, a mobile device, or any other device, and may correspond to, for example, a server or a user's computer. In this example, the processor-based system 1100 includes the processor 1102. The processor 1102 corresponds to one or more general-purpose processing circuits, such as a microprocessor or central processing unit. More specifically, the processor 1102 may be an EDGE instruction set microprocessor or other processor that implements an instruction set that supports unambiguous consumer naming for communicating produced values ​​resulting from the execution of producer instructions. The processor 1102 is configured to execute the processing logic of instructions to perform the operations and steps discussed herein. In this example, processor 1102 includes a temporary instruction cache 1106 that is a fast-access memory storage of instructions accessible by instruction processing circuits 1104. Instructions fetched or prefetched from a memory, such as main memory 1108, via a system bus 1110 are stored in instruction cache 1106. Data may also be stored in a cache memory 1112 coupled to system bus 1110 for low-latency access by processor 1102. Instruction processing circuits 1104 are configured to process instructions fetched into instruction cache 1106 and process the instructions for execution.

[0062] The processor 1102 and main memory 1108 are coupled to a system bus 1110, which may interconnect peripheral devices included in the processor-based system 1100. As is well known, the processor 1102 communicates with these other devices by exchanging address, control, and data information via the system bus 1110. For example, the processor 1102, as an example of a slave device, may communicate bus transaction requests to a memory controller 1114 in the main memory 1108. Although not shown in FIG. 11 , multiple system buses 1110 may be provided, with each system bus 1110 having a different structure. In this example, the memory controller 1114 is configured to make memory access requests to a memory array 1116 in the main memory 1108. The memory array 1116 is comprised of an array of storage bit cells for storing data. The main memory 1108 may be, by way of non-limiting example, read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), and / or static memory (e.g., flash memory, SRAM, etc.).

[0063] Other devices may be connected to the system bus 1110. As shown in FIG. 11, these devices may include, by way of example, a main memory 1108, one or more input devices 1118, one or more output devices 1120, a modem 1122, and one or more display controllers 1124. The input device(s) 1118 may include any type of input device, including but not limited to input keys, switches, audio processors, etc. The output device(s) 1120 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. The modem 1122 may be any device configured to enable the exchange of data with a network 1126. The network 1126 may be any type of network, including but not limited to a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The modem 1122 may be configured to support any type of communication protocol desired. The processor 1102 may also be configured to access display controller(s) 1124 via the system bus 1110 to control information sent to one or more displays 1128. The display(s) 1128 may include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc.

[0064] 11 may include an instruction set 1130 to be executed by the processor 1102 for any desired application according to the instructions 1130. The instructions 1130 may be stored in main memory 1108, processor 1102, and / or instruction cache 1106 as examples of non-transitory computer-readable medium 1132. The instructions 1130 may also reside, completely or at least partially, in main memory 1108 and / or within the processor 1102 during their execution. The instructions 1130 may also be transmitted or received via modem 1122 over a network 1126 that includes the computer-readable medium 1132.

[0065] Any of the circuits within the processor-based system 1100, and particularly the modem 1122 and the output device 1120, may include a peak detector 700, 800 that includes multiple amplitude detection circuits coupled in parallel to produce an average voltage with a lower standard deviation, as shown in Figures 7 and 8. Any of the circuits within the processor-based system 1100, such as the modem 1122, may include a phase-locked loop (PLL) that includes a voltage-controlled oscillator with a peak detector 700, 800.

[0066] While the computer-readable medium 1132 is shown to be a single medium in the exemplary embodiment, the term "computer-readable medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) that store one or more sets of instructions. The term "computer-readable medium" should also be understood to include any medium that can store, encode, or carry a set of instructions for execution by a processing device, causing the processing device to perform any one or more of the methodologies of the embodiments disclosed herein. Thus, the term "computer-readable medium" should be understood to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0067] The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be formed by hardware components or embodied in machine-executable instructions that can be used to cause a general-purpose or special-purpose processor programmed with the machine-executable instructions to perform the steps. Alternatively, the steps may be performed by a combination of hardware and software.

[0068] The embodiments disclosed herein may be provided as a computer program product or software that may include a machine-readable medium (or computer-readable medium) having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes a machine-readable storage medium (e.g., ROM, random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices, etc.), etc.

[0069] Unless otherwise specifically stated, as is evident from the preceding discussion, throughout this description, discussions utilizing terms such as "processing," "calculating," "determining," or "displaying" will be understood to relate to the operations and processes of a computer system, or similar electronic computing device, and which operations and processes manipulate and convert data and memory represented as physical (electronic) quantities in the computer system's registers into other data similarly represented as physical quantities in the computer system's memory or registers, or other such information storage, transmission, or display device.

[0070] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will be apparent from the above description. Additionally, the embodiments described herein are not described with reference to any particular programming language. It will be understood that a variety of programming languages ​​can be used to implement the teachings of the embodiments described herein.

[0071] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein may be implemented as electronic hardware, as instructions stored in a memory or another computer-readable medium, and executed by a processor or other processing device, or a combination of both. The components of the systems described herein may be utilized in, for example, any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present embodiments.

[0072] The various illustrative logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed by a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Further, a controller may be a processor. A processor may be a microprocessor, but alternatively, a processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0073] The embodiments disclosed herein may be embodied in hardware and with instructions stored in the hardware and that may reside in, for example, RAM, flash memory, ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disk, removable disk, CD-ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. Alternatively, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

[0074] It should also be noted that the operational steps described in any of the exemplary embodiments herein are described to provide examples and discussion. The described operations may be performed in many different sequences that differ from the illustrated sequence. Furthermore, operations described in a single operational step may actually be performed in many different steps. Furthermore, one or more operational steps discussed in an exemplary embodiment may be combined. Those skilled in the art will also understand that information and signals may be represented using any of a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields, light fields, or particles, or any combination thereof.

[0075] Unless expressly stated otherwise, in no way should any method set forth herein be construed as requiring that its steps be performed in a particular order. Thus, method claims herein do not in fact recite the order in which their steps should be followed, nor is there otherwise any specific statement in the claims or description that the steps should be limited to a particular order, and in no way should any particular order be inferred.

[0076] It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit and scope of the present invention. Modifications, combinations, subcombinations, and variations of the disclosed embodiments that incorporate the spirit and content of the present invention may occur to those skilled in the art, and the present invention should be construed as including all that come within the scope of the appended claims and their equivalents.

Claims

1. a plurality of amplitude detection circuits coupled in parallel to a first signal input and a second signal input, each of the plurality of amplitude detection circuits configured to generate a peak voltage on an output indicative of the amplitude of an input signal received on the first signal input and the second signal input; an averaging circuit coupled to the output of each of the plurality of amplitude detection circuits, the averaging circuit configured to generate an average voltage on a peak detector output comprising an average of the peak voltages on the outputs of the plurality of amplitude detection circuits; A peak detector including

2. 2. The peak detector of claim 1, wherein each of the plurality of amplitude detection circuits comprises: a first sense circuit configured to generate the peak voltage on the output based on the input signal received on the first input signal; a second sense circuit configured to generate the peak voltage on the output based on the input signal received on the second input signal; a peak detector,

3. 3. A peak detector according to claim 2, The first sense circuit includes: a gate coupled to the first signal input; a first source / drain coupled to a supply voltage source; a second source / drain coupled to the output; and a first transistor including The second sense circuit includes: a gate coupled to the second signal input; a first source / drain coupled to the supply voltage source; a second source / drain coupled to the output; and a second transistor including Each of the plurality of amplitude detection circuits a capacitor coupled to the output and to a reference voltage source; a current source coupled to the output and the reference voltage source; further comprising: Peak detector.

4. 2. The peak detector of claim 1, wherein each of the plurality of amplitude detection circuits comprises: a first input switch coupled to the first signal input; a second input switch coupled to the second signal input; an output switch coupled to the output; The peak detector further includes:

5. 5. The peak detector of claim 4, further comprising a control circuit configured to close both the first input switch and the second input switch of each of the plurality of amplitude detection circuits, one amplitude detection circuit at a time.

6. 5. The peak detector of claim 4, wherein each of the plurality of amplitude detection circuits comprises: a first resistor-capacitor (RC) circuit coupled to the first signal input by the first input switch; a second RC circuit coupled to the second signal input by the second input switch; The peak detector further includes:

7. 7. A peak detector as claimed in claim 6, wherein the averaging circuit comprises: a plurality of capacitors each coupled to the output of a corresponding one of the plurality of amplitude detection circuits; a plurality of averaging switches each coupled to the output of two amplitude detection circuits of the plurality of amplitude detection circuits; Including, The plurality of averaging switches are coupled in series to couple each of the outputs of each of the plurality of amplitude detection circuits to the peak detector output.

8. 8. The peak detector of claim 7, further comprising a control circuit configured to close the plurality of averaging switches to couple the plurality of capacitors to the peak detector output.

9. 5. A peak detector according to claim 4, a first resistor-capacitor (RC) circuit coupled to the first signal input and to the first input switch of each of the plurality of amplitude detection circuits; a second RC circuit coupled to the second signal input and to the second input switch of each of the plurality of amplitude detection circuits; The peak detector further comprises:

10. 5. A peak detector according to claim 4, the plurality of amplitude detection circuits include a plurality of odd amplitude detection circuits and a plurality of even amplitude detection circuits; The averaging circuit A plurality of capacitors, a first capacitor coupled to the output of a first even amplitude detection circuit of the plurality of even amplitude detection circuits; a plurality of second capacitors each coupled to the output of one odd amplitude detection circuit of the plurality of odd amplitude detection circuits; a plurality of capacitors including a plurality of averaging switches respectively coupled to the outputs of a corresponding one of the plurality of odd amplitude detection circuits and a corresponding one of the plurality of even amplitude detection circuits; Including, the output of the first even amplitude detection circuit is coupled to the outputs of the plurality of odd amplitude detection circuits and to the peak detector output; Peak detector.

11. 11. The peak detector of claim 10, wherein the control circuit is configured to close, for each of the plurality of odd amplitude detection circuits, an averaging switch of the plurality of averaging switches that couples the one second capacitor of the plurality of second capacitors corresponding to the odd amplitude detection circuit to the first capacitor.

12. 12. The peak detector of claim 11, wherein the control circuit is further configured to close the plurality of averaging switches to couple the capacitor of each of the plurality of even amplitude detection circuits to the peak detector output.

13. a transmitter configured to generate a transmission signal; a PLL including a voltage controlled oscillator (VCO) configured to generate an output signal having an amplitude based on a control voltage, the PLL configured to control the frequency of the transmission signal; a peak detector, a plurality of amplitude detection circuits coupled in parallel to a first signal input and a second signal input, each of the plurality of amplitude detection circuits configured to generate a voltage on an output indicative of a voltage difference between the first signal input and the second signal input; an averaging circuit coupled to the output of each of the plurality of amplitude detection circuits, the averaging circuit configured to generate an average voltage on a peak detector output comprising an average of the voltages generated on the outputs of the plurality of amplitude detection circuits; a peak detector including: A range sensor comprising: determining whether the average voltage on the peak detector output is outside a voltage range; adjusting the control voltage in response to determining that the average voltage on the peak detector output is outside a voltage range; a range sensor configured to An integrated circuit (IC) comprising:

14. 14. The IC of claim 13, wherein each of the plurality of amplitude detection circuits of the peak detector comprises: a source follower circuit configured to generate the voltage on the output based on a higher voltage on one of the first input and the second signal input; The IC further comprises:

15. 14. The IC of claim 13, wherein each of the plurality of amplitude detection circuits of the peak detector comprises: a first input switch coupled to the first signal input; a second input switch coupled to the second signal input; The IC further includes:

Images