Multi-bit voltage-delay conversion in data conversion circuit elements

Abstract

The analog-to-digital conversion circuit (100) incorporates a multi-bit input buffer (110) having a differential input and configured to generate, at a plurality of differential outputs, a plurality of residues (VP / M9, ...) of a differential input sample (VIN) relative to a corresponding plurality of zero-crossing references. The chopping stage chops the residues using, for example, a pseudo-random binary sequence. The circuit further includes zero-crossing comparators (120), each having a differential input coupled to receive one of the chopped residues. The zero-crossing comparators are an ordered sequence of zone thresholds within the input range of the circuit. A folding logic circuit element (130) has an input coupled to the comparator output and outputs a delay-domain signal (FOLDP, FOLDM) indicative of the magnitude of one of the residues relative to the nearest zone threshold. A digital stage circuit element (160) generates a digital output word representing the received input sample in response to the comparator output and the delay-domain signal.

Description

[Technical Field]

[0001] This application relates to data conversion circuitry, and more particularly to delay-domain analog-to-digital converters.

[0002] Advances in wireless communication technology have enabled widespread deployment and new applications of wireless communications in recent years. Wireless communications are now commonplace in short-range communications (e.g., "personal area networks"), wireless local area networks (e.g., home or office "WiFi" networks), and long-range communications (e.g., cellular networks). Performance requirements across these network types range from low data rate and delay-tolerant applications (e.g., machine-to-machine communications in the so-called "Internet of Things" or "IoT") to high data rate, real-time applications at gigahertz frequencies.

[0003] In any of these wireless communication applications, the conversion of analog signal levels to digital data and vice versa is a critical function performed in each network node or device. The performance requirements for high data rate communication devices, particularly in mobile and battery-powered devices such as "5G" cellular communication-enabled user equipment, are reflected in the performance requirements for data conversion circuitry within these devices. In these applications (especially for mobile devices), data converters must provide high performance (e.g., low error rate) conversion at high data rates, wide input bandwidths, and low power consumption levels. Power constraints on data converters become particularly stringent in multiple-input, multiple-output (MIMO) network devices, such as integrated transceivers, which typically have eight or sixteen transmitters and receivers (e.g., 8T8R, 16T16R).

[0004] A common type of analog-to-digital converter (ADC) can be referred to as a "pipelined" ADC. This architecture includes a first flash converter that resolves one or more most significant bits (MSBs) of an output word from an input analog signal. A digital-to-analog converter converts those MSBs back to analog levels and subtracts them from the original input levels to generate a residue value, which is then applied to another flash converter to resolve one or more next-higher MSBs, and so on. The performance of this ADC architecture is limited by the time required for the flash conversion, residue generation, and residual amplification (e.g., to match the input range of the next flash converter). Increasing the number of pipeline stages, for example to achieve higher resolution, can further increase the overall processing time required by this architecture. An example of a pipelined ADC circuit is provided in co-pending U.S. patent application (T101840), entitled "Method and Apparatus for Reducing Inter-Stage Gain Error in Analog-to-Digital Converters," invented by K. Prasanth and S. Rahul of Texas Instruments, Incorporated, and incorporated herein by reference in its entirety. [Patent Document 1] U.S. Patent Application No. 17 / 899,149

[0005] Recently, ADCs operating in the "delay domain" have been proposed for high-performance applications. A delay-domain ADC may include a voltage-to-delay (V2D) converter that operates to convert an input voltage level into the delay between two pulses. For example, a V2D converter may include multiple conversion circuits, each receiving an analog input level and a reference level, where the reference level varies among the multiple converters. Folding interpolation logic generates a signal from the converter output with a delay interval that indicates the proximity of the reference level to the input signal. A time-to-digital converter (TDC) encodes the delay interval output from the V2D converter into a digital output word. Because the delay-domain signal at the output of the V2D converter is a nonlinear function of the voltage difference between the input level and the reference level, this nonlinearity in the time-to-digital transfer function is typically corrected, for example, by using a look-up table (LUT). In some architectures, the LUT can be calibrated during operation, for example, by periodically comparing the output data word with the conversion results from known input levels, such as a known linear DAC, to identify the ideal input and therefore any adjustments to the LUT contents.

[0006] Several sources of error have been observed in some delay-domain analog-to-digital (A / D) conversions. In the V2D stage, inherent differences exist between the calibration and signal paths, affecting the common-mode rejection ratio (CMRR) and power-supply rejection ratio (PSRR). Flicker noise also exists in some delay-domain ADCs, particularly those implemented in complementary metal-oxide semiconductor (CMOS) technology. This flicker noise can vary between calibration occurrences and affect the nonlinearity of the TDC stage, thereby changing the spurious-free dynamic range (SFDR) over time. Also, in some implementations, when the analog input level is approximately equidistant between two levels, two parallel TDC paths are required to resolve the closest of the two reference levels, doubling the cost of the TDC stage in terms of chip area and power consumption.

[0007] Some delay-domain ADCs use separate dual differential pairs to generate each of the multiple reference levels applied to the V2D stage. However, variations in the transfer function between the differential pairs, and therefore between input range zones, can degrade the converter's CMRR and be difficult to correct through calibration. Also, mismatches in flicker noise between these differential reference pairs can result in time-dependent degradation of SFDR performance. These dual differential structures are also prone to excessive noise. Examples of various V2D architectures are described in U.S. Patent Nos. 10,284,188 and 10,673,453, and U.S. Patent Applications 17 / 126,157, 17 / 182,339, 17 / 129,180, 17 / 131,981, 17 / 158,526, 17 / 133,745, 17 / 467,561, 17 / 568,972, and 17 / 588,493, all of which are incorporated herein by reference in their entirety. [Patent Document 2] U.S. Patent No. 10,284,188 [Patent Document 3] U.S. Patent No. 10,673,453 [Patent Document 4] U.S. Patent Application No. 17 / 126,157 [Patent Document 5] U.S. Patent Application No. 17 / 182,339 [Patent Document 6] U.S. Patent Application No. 17 / 129,180 [Patent Document 7] U.S. Patent Application No. 17 / 131,981 [Patent Document 8] U.S. Patent Application No. 17 / 158,526 [Patent Document 9] U.S. Patent Application No. 17 / 133,745 [Patent Document 10] U.S. Patent Application No. 17 / 467,561 [Patent Document 11] U.S. Patent Application No. 17 / 568,972 [Patent Document 12] U.S. Patent Application No. 17 / 588,493

[0008] The examples described herein arise within this context. Summary of the Invention

[0009] According to one aspect, an analog-to-digital conversion circuit includes a multi-bit input buffer having a differential input and configured to generate, at a plurality of differential outputs, a plurality of residuals of a differential input sample relative to a corresponding plurality of zero-crossing references. The circuit further includes zero-crossing comparators, each having a differential input coupled to receive one of the residuals. The zero-crossing comparators are within an ordered sequence of zone thresholds within an input range of the circuit. A folding logic circuit element has an input coupled to the output of the comparator and outputs a delay-domain signal indicative of the magnitude of one of the residuals relative to the nearest zone threshold. Digital stage circuitry is provided in response to the comparator output and the delay-domain signal to generate a digital output word representing the received input sample.

[0010] According to another aspect, a method for converting an analog signal level to a digital word includes sampling a differential input signal and generating from the input samples a plurality of differential residual signals relative to a plurality of zero-crossing references. The residuals are applied to corresponding ones of a plurality of zero-crossing comparators in an ordered sequence according to zone thresholds. Input range zones for the sampled input signal between zone thresholds of adjacent comparators in the ordered sequence having a change in polarity at their outputs are identified, and delays between logic transitions at adjacent comparators are identified. The method further includes encoding a digital output word indicative of the identified input range zones and the identified delays.

[0011] Technical advantages enabled by one or more of these aspects include efficient implementation of the ADC in terms of chip area and reduced power consumption. These aspects may also enable chopping the zero-crossing residual rather than the input signal, thereby reducing the effects of additive or flicker noise in the time-to-delay domain conversion. The zero-crossing comparators may be identical to each other, producing a single-ended output, simplifying the folding logic, and eliminating the need for parallel TDC circuitry to accurately identify input range zones.

[0012] Other technical advantages enabled by the described aspects will become apparent to those skilled in the art upon review of the following specification in conjunction with its drawings. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is an electrical diagram in block form of an analog-to-digital converter according to some examples.

[0014] [Figure 2] 2 is a schematic electrical diagram of a multi-bit input buffer in the analog-to-digital converter of FIG. 1, according to some examples.

[0015] [Figure 3A] 2 is an electrical diagram in block form of a voltage-to-delay converter stage in the analog-to-digital converter of FIG. 1, according to some examples.

[0016] [Figure 3B] 3B is an electrical diagram in block form illustrating an example of frequency chopping in the voltage-to-delay converter stage of FIG. 3A, according to some examples. [Figure 3C] 3B is an electrical diagram in block form illustrating an example of frequency chopping in the voltage-to-delay converter stage of FIG. 3A, according to some examples.

[0017] [Figure 4A]2 is a schematic electrical diagram of folding logic in the analog-to-digital converter of FIG. 1, according to some examples.

[0018] [Figure 4B] 4B is an electrical schematic diagram illustrating an example of the operation of the folding logic of FIG. 4A, according to some examples.

[0019] [Figure 4C] FIG. 4C is a timing diagram illustrating delay domain signals from the example shown in FIG. 4B.

[0020] [Figure 5] 2 is a flowchart illustrating the operation of the analog-to-digital converter of FIG. 1, according to some examples.

[0021] In the drawings, the same reference numbers or other reference identifiers are used to denote the same or similar (functional and / or structural) features. DETAILED DESCRIPTION OF THE INVENTION

[0022] One or more examples described herein are implemented in an analog-to-digital converter (ADC) such as may be used in direct sampling radio frequency (RF) communications receivers and transceivers, as such implementations are believed to be particularly advantageous in that context. However, it is contemplated that aspects of these examples may also be beneficially applied in other applications incorporating analog-to-digital conversion. Accordingly, the following description is provided by way of example only and is not intended to limit the true scope of the invention as claimed.

[0023] FIG. 1 illustrates the architecture of an analog-to-digital converter (ADC) 100 according to some examples. As described hereinafter, the ADC 100 performs analog-to-digital conversion by converting an analog voltage or current level received at its input into a delay-domain signal represented as the time interval between a pair of signal transitions, and then converting the delay-domain signal into a digital output word. This approach to delay-domain conversion is suitable for high-speed applications such as direct-sampling RF receivers. Examples of delay-domain ADC architectures and their applications are described in U.S. Pat. Nos. 10,673,452 and 10,673,456, which are commonly assigned and incorporated herein by reference. [Patent Document 13] U.S. Patent No. 10,673,452 and [Patent Document 14] U.S. Patent No. 10,673,456

[0024] 1 includes a sample-and-hold circuit 102 having an input AIN that receives an analog input signal for conversion to a digital data word DOUT. Generally, the analog input signal received at input AIN may be a time-varying voltage or current and may be in the form of a single-ended signal (e.g., communicated over a single conductor) or a differential signal (e.g., communicated over a pair of conductors or lines).

[0025] For purposes of this description and by way of example, the received analog input signal will be considered to be in the form of a differential voltage communicated over a pair of conductors, such that the input A,N corresponds to a pair of input terminals. The sample-and-hold (S / H) circuit 102 may be constructed in a conventional manner depending on the particular application of the ADC 100. Generally, the S / H circuit 102 is represented by a switch 104, as shown in FIG. 1, with one side coupled to the differential input A,N and the other side coupled to a capacitor 106 at the output V,V, of the S / H circuit 102. (In a differential implementation such as FIG. 1, each switch 104 and capacitor 106 are paired.) The capacitor 106 is coupled between the output V and a common potential (e.g., circuit ground). The switch 104 is controlled by appropriate clock circuitry (not shown) to periodically open and close at a desired sampling frequency, with each sampled voltage being held by the capacitor 106 and presented at the output V. In this differential example, the output VIN of the S / H circuit 102 comprises a differential pair of signal lines (eg, INP, INM in FIG. 2) that are coupled to the differential inputs of the multi-bit input buffer 110.

[0026] According to some examples, multi-bit input buffer 110 of ADC 100 has an input coupled to output V of S / H circuit 102 and applies each input sample received from output V to multiple zero-crossing reference levels. In the example of FIG. 1, input buffer 110 has nine output pairs VP1, VM1 through VP9, ​​and VM9 (represented as outputs VP / M1 through VP / M9, respectively). Each of outputs VP / M1 through VP / M9 communicates a differential signal corresponding to the residual of the input sample relative to a corresponding zero-crossing reference level. For example, if the input signal range of ADC 100 is 500 mV p-p, output pairs VP / M1 through VP / M9 may represent the residual of the input sample relative to zero-crossing reference levels ranging from −250 mV to +250 mV in 62.5 mV steps. Output pairs VP / M1 through VP / M9 of input buffer 110 are coupled to corresponding inputs of voltage-to-delay (V2D) comparator stage 120 in the architecture of Figure 1. Input buffer 110 may provide more or fewer output pairs than the nine shown in Figure 1, as desired for a particular application of ADC 100.

[0027] V2D comparator stage 120, as will be described in more detail hereinafter, includes a set of comparators, each of which receives one of output pairs VP / M1 through VP / M9 from input buffer 110 and generates an output logic signal based on a comparison of the levels at its inputs. In the illustrated embodiment of FIG. 1, each comparator in V2D comparator stage 120 outputs a complementary single-ended signal. V2D comparator stage 120 therefore has nine output pairs OUTP / M1 through OUTP / M9, each output pair presented by a corresponding comparator in response to the differential residual received on output pair VP / M1 through VP / M9 from input buffer 110.

[0028] The logic states at output pairs OUTP / M1 through OUTP / M9 may indicate the "zone" of the input signal range within which the differential amplitude of the sampled input signal lies. For example, in the case where the zero-crossing reference levels applied by input buffer 110 are 62.5 mV apart within a 500 mV p-p input range, the logic levels of complementary outputs OUTP / M1 through OUTP / M9 indicate the zones of the input range, e.g., in thermometer code. The zero-crossing references applied by input buffer 110 thus define the zone thresholds of corresponding comparators in V2D comparator stage 120. Outputs OUTP / M1 through OUTP / M9 are coupled via signal line 125 to digital encoder 150 within digital stage 160, which encodes m bits of the digital output word DOUT according to the indicated zones.

[0029] In addition to indicating the zone in which the input differential voltage lies, each comparator in V2D comparator stage 120 provides an indication, in the delay domain, of the proximity of the input sample to the corresponding zone threshold based on the response time of that comparator to the magnitude of the residual error at the input. A residual error with a relatively large differential magnitude, indicating that the input sample has a large difference from the associated zero-crossing reference (or zone threshold), is reflected in a rapid switch in the comparator output. Conversely, the comparator output responds slowly to a small residual error, indicating that the input sample is close to the corresponding zero-crossing reference level (or zone threshold).

[0030] 1, some of the outputs OUTP / M1-OUTP / M9 of V2D comparator stage 120 are coupled to inputs of folding logic 130. As will be described in detail hereinafter, folding logic 130 includes digital logic gates arranged to generate logic transitions at outputs FOLDP, FOLDM having relative delays corresponding to the amplitude difference between the input sample and the nearest zone threshold. The outputs FOLDP, FOLDM of folding logic 130 are coupled to a time-to-digital converter (TDC) 140 within digital stage 160, which operates to encode n bits of a digital output word DOUT in response to the delays between the logic transitions at the folded logic outputs FOLDP, FOLDM and which transition precedes the other (i.e., the polarity of the delay). A look-up table (LUT) 145 may be included within or with digital stage 160 to receive a digital address from TDC 140 based on the delay observed at outputs FOLDP, FOLDM, and either forward corrected digital data back to TDC 140 or forward the corrected digital data directly as n bits of word DOUT. In either example, nonlinearities in the voltage-to-digital conversion are corrected. LUT 145 may be constructed as an addressable memory, such as a random access memory (RAM) or another type of writable memory, with an address input coupled to receive the digital address from TDC 140 and a data output representing the corrected digital data.

[0031] For example, the most significant bit (MSB) of digital output word DOUT may be m bits encoded by digital encoder 150 to indicate the input range zone of the input sample, and the n least significant bits of digital word DOUT may be those output by TDC 140 in response to relative delays in the folded logic outputs FOLDP, FOLDM. Alternatively, digital stage 160 may encode digital output word DOUT according to a different coding scheme suitable for the application.

[0032] 2 illustrates the configuration of a multi-bit input buffer 110 according to an example embodiment. In this example, a differential input sample is received at inputs INP, INM, and the input buffer 110 includes a pair of resistor ladders 200, 210, each biased between a power supply node Vdd and circuit ground, that receive the differential inputs INP, INM, respectively, from the output VIN of the S / H circuit 102.

[0033] Resistor ladder 200 includes an n-channel metal-oxide semiconductor (NMOS) transistor 202, whose drain is at power supply node Vdd and whose source is coupled to resistor 205 at node VP1. Resistor ladder 200 also includes a p-channel MOS (PMOS) transistor 204, whose drain is at circuit ground and whose source is coupled to resistor 205 at node VP9. In this example, eight resistors 205 are connected in series between the source of NMOS transistor 202 at node VP1 and the source of PMOS transistor 204 at node VP9. Having resistors 205 with the same resistance value is convenient for defining equally sized differential voltage intervals or "zones" of the ADC input range. However, in other examples, some or all of resistors 205 may have different resistances. In resistor ladder 200, the junctions between each resistor 205 represent corresponding nodes VP2-VP8 (from top to bottom in FIG. 2). Input INP is coupled to the gates of transistors 202 and 204.

[0034] Resistor ladder 210 is configured similarly to resistor ladder 200, with NMOS transistor 212 having a drain at power supply node Vdd and a source coupled to resistor 215 at node VM9, and PMOS transistor 214 having a drain at circuit ground and a source coupled to resistor 215 at node VM1. Eight resistors 215 are connected in series between the source of NMOS transistor 212 at node VM9 and the source of PMOS transistor 214 at node VM1. Resistors 215 may have the same resistance as each other and as resistor 205 in resistor ladder 200 to again define equal-sized differential voltage zones. Nodes VM8-VM2 are located at the junctions between resistors 215 in resistor ladder 210, in the reverse order of resistor ladder 200 (top to bottom in FIG. 2). Input INM is coupled to the gates of transistors 212 and 214.

[0035] Resistors 205, 215 may be configured as diffused resistors, polysilicon resistors, or other patterned resistors, depending on the integrated circuit technology used to fabricate the integrated circuit containing ADC 100. Alternatively, resistors 205, 215 may be configured as MOS with gates biased into the ohmic region at the desired resistance level. Also, more or fewer resistors 205, 215 than the eight in this example may be provided in resistor ladders 200, 210, respectively, to define more or fewer node pairs.

[0036] The current conducted between power supply node Vdd and circuit ground through resistor ladders 200 and 210 remains relatively constant regardless of the differential voltage at inputs INP and INM, as long as the voltage at each input is sufficient to bias transistors 202, 204, 212, and 214 into their linear regions. As the differential voltage at inputs INP and INM changes, voltage nodes VP1-VP9 and VM1-VM9 change accordingly. Referring first to resistor ladder 200, a higher voltage at input INP tends to turn on transistor 202 more strongly, lowering its drain-source resistance, and turn on transistor 204 more weakly, increasing its drain-source resistance. Thus, the voltage at nodes VP1-VP9 increases as the voltage at input INP increases. Resistor ladder 210 operates similarly to resistor ladder 200, except that the order of nodes VM9-VM1 is reversed from the top-to-bottom order of resistor ladder 200 (FIG. 2).

[0037] Thus, input buffer 110 operates in response to a differential voltage at inputs INP and INM (input samples) to present a set of differential output voltages at pairs of nodes: VP1 and VM1 (referred to as VP / M1), VP2 and VM2 (VP / M2), ..., and VP9 and VM9 (VP / M9). Each of node pairs VP / M1 through VP / M9 presents a differential voltage based on the input sample at a different offset. For example, when the input sample is at zero differential voltage across inputs INP and INM, the differential voltage across nodes VP5 and VM5 is approximately zero because these two nodes VP5 and VM5 are in the center of their respective resistor ladders 200 and 210. At this zero input differential voltage, the on-resistances of resistors 202 and 212 are matched to each other, and the on-resistances of resistors 204 and 214 are matched to each other. In other words, the zero-crossing reference applied to nodes VP5 and VM5 is 0 mV.

[0038] Meanwhile, zero differential voltage at inputs INP and INM results in a positive differential voltage across nodes VP4 and VM4 according to the offset voltages defined by their different positions within the respective resistor ladders 200 and 210 (node ​​VP4 is two resistor values ​​closer to Vdd than node VM4). Positive offset voltages appear similarly across node pairs VP / M3, VP / M2, and VP / M1, increasing in magnitude in that order. Similarly, because node VP6 is two resistor values ​​closer to circuit ground than node VM6, a negative differential voltage appears across nodes VP6 and VM6 for zero input differential voltage. Negative offset voltages appear similarly across node pairs VP / M7, VP / M8, and VP / M9, increasing in magnitude in that order. Thus, in this example, the offsets applied to node pairs VP / M1 through VP / M9 are ordered from positive to negative.

[0039] Conversely, a non-zero differential input sample at inputs INP, INM causes one of the node pairs other than center node VP / M5 to exhibit the lowest output differential voltage. For example, when a positive differential voltage exists across inputs INP, INM, NMOS transistor 202 has a lower on-resistance than NMOS transistor 212 (and PMOS transistor 204 has a higher on-resistance than PMOS transistor 214), resulting in higher voltages at nodes VP1-VP9 than opposite nodes VM9-VM1, respectively. In this example, one of node pairs VP / M1-VP / M4 may exhibit the smallest output differential voltage according to the magnitude of the input sample differential voltage.

[0040] Thus, the differential offset voltages at node pairs VP / M1 through VP / M9 of input buffer 110 act as zero-crossing references for comparing the input differential voltages. The differential voltage appearing at each node pair VP / M1 through VP / M9 is therefore the residual of the input sample received at inputs INP, INM relative to the corresponding zero-crossing reference at that node pair.

[0041] An example of this operation of input buffer 110 may be helpful. Consider a differential voltage at input AIN, received by ADC 100 and sampled by S / H circuit 102, with a peak-to-peak differential swing of 500 mV. Thus, a sample of the differential voltage across inputs INP, INM may vary between −250 mV and +250 mV. To convert such a 500 mV analog differential signal, input buffer 110 (according to one example) includes resistor ladders 200, 210, each with eight resistors 205, 215 whose resistances are selected to apply zero-crossing criteria at each of node pairs VP / M1 through VP / M9, as set forth in Table 1. According to Table 1, input buffer 110 generates residuals of the differential sampled signals at inputs INP and INM for nine zero-crossing references ranging from -250 mV to +250 mV in 62.5 mV steps. For example, if the sampled differential voltage at inputs INP and INM is +62 mV, node VP / M9 will exhibit a differential residual of -188 mV, node VP / M8 will exhibit a differential residual of -125.5 mV, node VP / M7 will exhibit a differential residual of -63 mV, and so on, with node VP / M1 exhibiting a differential residual of +312 mV. In this example, the smallest magnitude residual of the set will be -0.5 mV at nodes VP6 and VM6.

[0042] According to this example, the polarity of the differential voltage at nodes VP / M1 through VP / M9 of input buffer 110 can identify the input range zone in which the differential voltage at inputs INP and INM lies. Specifically, adjacent pairs of nodes exhibiting opposite polarity residuals indicate the zone of the input sample. In the above example where the input differential voltage is +62 mV, the output voltage at node VP / M6 is −0.5 mV as described above, while the output voltage at node VP / M5 is +62 mV (the zero-crossing reference at node VP / M5 is 0 mV). Therefore, the input differential voltage lies in the zone between 0 mV (VP / M5) and +62.5 mV (VP / M6).

[0043] Returning to Figure 1, the output differential voltages at node pairs VP / M1 through VP / M9 of input buffer 110 are applied to corresponding inputs of V2D comparator stage 120. Figure 3A illustrates the architecture of V2D comparator stage 120 according to this example embodiment, which is described below. According to this example embodiment, V2D comparator stage 120 includes, for each node pair of input buffer 110, a chopping stage followed by a comparator stage.

[0044] Chopping a signal refers to mixing an input signal with a time-varying signal to shift the frequency of the input signal, for example, to a frequency that is less susceptible to noise. In certain applications, in high-speed data conversion such as that performed by ADC 100, the effects of flicker noise can reduce the resolution and accuracy of the conversion and reduce the effectiveness of calibration for the nonlinearities inherent in delay-domain conversion. In the case of flicker noise with a 1 / f frequency characteristic, such as is common in MOS circuit elements such as comparator circuits, chopping a baseband signal can shift its bandwidth to a higher frequency, thereby reducing the effect of the flicker noise on the processed signal.

[0045] According to this exemplary embodiment as shown in FIG. 3A, each node pair VP / M1 through VP / M9 is coupled to a corresponding input of chopping stages 310(1) through 310(9), respectively (collectively referred to herein as chopping stages 310). Chopping stages 310 may be constructed as passive mixers, active mixers, or other conventional techniques for mixing the residue with a chopping signal. In this implementation, pseudorandom binary sequence (PRBS) logic 325 generates a chopping signal CHOP that is applied to each of chopping stages 310 in the form of a pseudorandom binary sequence (e.g., multiplication with a random sequence of binary values ​​+1 and −1) at a frequency at or below half the sampling frequency fs of S / H circuit 102 (i.e., at or below the Nyquist frequency of the signal being converted). It has been observed that using a PRBS sequence as chopping signal CHOP prevents “spurious” signals from appearing in the signal spectrum. To apply the PRBS as a chopping signal, chopping stage 310 may be configured with logic or other circuitry for selectively inverting the differential residue as chopping signal CHOP according to the PRBS value generated by PRBS logic 325 and presenting it at a corresponding output. The differential outputs of chopping stages 310(1)-310(9) are coupled to the differential inputs of comparators 320(1)-320(9), respectively, as shown in FIG. 3A.

[0046] V2D comparator stage 120 also includes comparators 320(1) through 320(9) (collectively or collectively referred to herein as comparators 320), each having a differential input coupled to receive the residual error at a corresponding node pair VP / M1 through VP / M9 from input buffer 110, which has been chopped by chopping stages 310(1) through 310(9), respectively. Comparators 320 may be considered to be in an ordered sequence in V2D comparator stage 120 according to a zero-crossing criteria for the residual error received at the comparator input. In this example, comparators 320 are constructed and configured as zero-crossing comparators, each with complementary single-ended outputs. For example, as shown in FIG. 3A, comparator 320(1) has a positive output OUTP1 and a negative output OUTM1, comparator 320(2) has a positive output OUTP2 and a negative output OUTM2, and so on. Alternatively, each comparator 320 may have only a single output (e.g., a positive output OUTP1 for comparator 320(1)), with another inverter or other downstream logic, if necessary, to generate the logical complement of the level at the single output. Also in this example, comparators 320 each have an input that receives chopping signal CHOP from PRBS logic 325, and in response, comparators 320 selectively invert their results according to the PRBS value generated by PRBS logic 325 as chopping signal CHOP. In this manner, any inversion applied to chopping stage 310 is inverted in comparators 320, so that the outputs of comparators 320 reflect the polarity of the differential residual from input buffer 110 at their corresponding inputs.

[0047] Thus, in this example, each comparator 320 generates a logic high level at its positive output (e.g., OUTP1 for comparator 320(1)) and a logic low level at its negative output (e.g., OUTM1) in response to the corresponding differential residual from input buffer 110 having a positive polarity, and generates a logic low level at its positive output and a logic high level at its negative input in response to the corresponding differential residual having a negative polarity. The logic state at the output of comparator 320 provides an indication of the input range zone in which the input sample lies.

[0048] For the example input differential voltage of +62 mV described above, resulting in a differential residual of +62 mV at node VP / M5 and −0.5 mV at node VP / M6, comparator 320(5) drives a high level at its output OUTP5 and a low level at its output OUTM5, and comparator 320(6) drives a low level at its output OUTP6 and a high level at its output OUTM6. Due to the change in output polarity between comparator 320(5) and its neighboring comparator 320(6), comparators 320(5) and 320(6) identify the zone in which the input sample resides and may be considered the “critical” comparators in this example. In this example, comparators 320(1) through 320(4) below comparator 320(5) in the ordered sequence of comparators 320 all drive a high logic level at their positive output and a low logic level at their negative output because the corresponding residuals from input buffer 110 applied to them are all positive in polarity. Conversely, comparators 320(7) through 320(9) above comparator 320(6) in the ordered sequence of comparators 320 all drive a low logic level at their positive output and a high logic level at their negative output because the corresponding residuals from input buffer 110 applied to them are all negative in polarity. The outputs of comparators 320, considered as an ordered sequence, therefore provide a thermometer-coded digital value indicative of the voltage zone within which the differential voltage at inputs INP and INM lies. 1, the output of comparator 320 is transferred via signal line 125 to digital encoder 150 in digital stage 160. Digital encoder 150, in response to the output of comparator 320, encodes m bits of a digital output word DOUT to indicate voltage zones of the sampled input signal, for example, as the m most significant bits of the output digital word DOUT.

[0049] In addition to the logic levels output at the complementary single-ended outputs of comparators 320, comparators 320 also operate to convert the magnitude of the differential signals at their inputs into the delay domain. As is typical for zero-crossing comparators, comparators 320 respond more quickly to larger differential input voltages than to smaller differential input voltages. The delay-domain response of a zero-crossing comparator, such as comparator 320 in this example, to the difference between two input voltages Vin+, Vm− can be characterized as follows: t delay =τ In(V in+ -V in- ) (1) where t delay is the response time of a logic transition at the comparator output, and τ is a proportionality constant defined by the circuit parameters. In the example embodiment of FIG. 3A, the input voltage difference [(V in+ )-(V in- )] corresponds to the differential residual received at the input of each comparator 320. This differential voltage to each comparator 320 is the differential residual from the corresponding node of the resistor ladder 200, 210 of the input buffer 110 (as chopped by the associated chopping stage 310). Smaller residuals result in slower responses by the comparators 320, so the delay at the output of each comparator 320 is a measure of the magnitude of the differential residual at its input.

[0050] As shown in FIG. 3A and described above, chopping stage 310 applies chopping signal CHOP to the residual at each of node pairs VP / M1 through VP / M9 from input buffer 110. In connection with these examples, it has been observed that this chopping of the residual applied by V2D comparator stage 120 as shown in FIG. 3A substantially reduces flicker noise and other additive noise compared to conventional chopping of the input signal itself. Chopping of the residual according to this exemplary embodiment also reduces errors in the conversion result due to differences between comparators 320, as described in connection with FIGS. 3B-3E.

[0051] 3B and 3C illustrate example operations of input buffer 110 and V2D comparator stage 120 according to the example of FIG. 3A for a sampled input differential voltage V of +62 mV. As shown in Table 1, node pairs VP / M6, VP / M5, and VP / M4 are most relevant to this example, producing residuals of the input sample V relative to zero-crossing references of −62.5 mV, 0 mV, and +62.5 mV, respectively. Thus, the resulting differential residuals applied to V2D comparator stage 120 from node pairs VP / M6, VP / M5, and VP / M4 are −0.5 mV, +62 mV, and +124.5 mV, respectively.

[0052] FIG. 3B illustrates the operation of chopping stages 310(6), 310(5), and 310(4), with a +1 value of chopping signal CHOP applied to the differential residual received from node pairs VP / M6, VP / M5, and VP / M4, respectively. The +1 level of chopping signal CHOP in chopping stage 310 operates to pass the residual unchanged to the differential inputs of corresponding comparators 320. In this example, comparators 320 present single-ended signals (complementary levels in this example) indicative of the polarity of the differential voltage at their inputs after a delay corresponding to the magnitude of that differential voltage, as described above. Comparators 320 apply the current level of chopping signal CHOP by either inverting or not inverting the result of the comparison at their outputs. For the +1 level of chopping signal CHOP in the example of FIG. 3B, the output of comparator 320 is not inverted. Thus, in this example, comparator 320(6) issues a negative polarity output at a delay corresponding to a differential voltage of −0.5 mV, and comparators 320(5) and 320(4) issue positive polarity outputs at delays corresponding to differential voltages of +62 mV and +124.5 mV, respectively. For purposes of identifying the input range zone in which the input voltage V lies, a negative result from comparator 320(6) and a positive result from its neighboring comparator 320(5) (e.g., the critical comparator in this example) indicate that the input voltage V lies in the input range zone between 0 mV and +62.5 mV, which are the zone thresholds corresponding to comparators 320(5) and 320(6), respectively.

[0053] Figure 3C illustrates the same operation for the case where chopping signal CHOP is at a -1 level. Thus, the differential residuals of -0.5 mV, +62 mV, and +124.5 mV at node pairs VP / M6, VP / M5, and VP / M4 are inverted by respective chopping stages 310(6), 310(5), and 310(4). Thus, comparator 320(6) receives the +0.5 mV differential voltage at its input from chopping stage 310(6), comparator 320(5) receives -62 mV at its input from chopping stage 310(5), and comparator 320(4) receives -124.5 mV at its input from chopping stage 310(4). Comparators 320 operate similarly to the example of Figure 3B, but invert their results in response to chopping signal CHOP being at a -1 level. As shown in FIG. 3C, the resulting signals output from comparators 320(6), 320(5), and 320(4) are the same for both the −1 and +1 chopping levels, and comparators 320(5) and 320(6) are critical comparators that identify input range zones of input samples between the 0 mV and 62.5 mV zone thresholds.

[0054] As is evident from the examples shown in Figures 3B and 3C, the same two comparators 320(6) and 320(5) are the critical comparators 320 for both chopping signal levels. Therefore, flicker and additive noise in comparators 320 tend to cancel over time because the noise present at the +1 chopping level is inverted in polarity at the -1 chopping level. This cancellation effect occurs because chopping stage 310 operates on each of the residues from input buffer 110, rather than being applied to input signal V before input buffer 110 prior to comparing the input signal to the generated reference voltage, as is done in conventional delay-domain ADCs. It has been observed from conventional architectures that applying chopping to the input signal rather than the residue, as in the examples of Figures 3A-3C, can result in different critical comparators for different chopping levels. That is, one input range zone may be indicated for a chopping signal level of +1, and a different input range zone may be indicated (e.g., by at least one critical comparator) for a chopping signal level of −1. The correct zone may be determined by downstream logic circuitry, but the different critical comparators involved in zone identification inherently have differences that may affect flicker noise, and the effects of those differences do not cancel out between the two chopping signal levels.

[0055] Therefore, according to some examples, chopping the residual rather than the input signal improves conversion accuracy and makes ADC 100 more robust to flicker noise.

[0056] Also, in this example, by configuring the input buffer 110 as described above to generate residuals at node pairs VP / M1 through VP / M9, the V2D comparator stage 120 can be configured as a set of identically constructed zero-crossing comparators 320. By using identical comparators 320 to convert the residuals to the delay domain, mismatches due to design differences in comparator circuit parameters are avoided, thereby achieving superior common-mode rejection ratio (CMRR) performance. Furthermore, the resistor ladders 200, 210 in the input buffer 110 ensure that the bandwidths at each zone threshold (zero-crossing reference) are similar, at least to first order. As a result, an improvement in overall bandwidth and, therefore, performance of the ADC 100 can be achieved. The resistor structure configuration of the input buffer 110 can also reduce flicker at the threshold because current noise tends to leak primarily into the fundamental frequency of the signal.

[0057] Returning to FIG. 1 , output pairs OUTP / M1 (e.g., output pairs OUTP1 and OUTM1) through OUTP / M9 (e.g., output pairs OUTP9 and OUTM9) may be transferred via signal lines 125 to digital encoder 150 to encode m bits of digital output word DOUT. As described above in this example, the logic states of output pairs OUTP / M1 through OUTP / M9 provide a thermometer-coded indication of the input range zone in which the sampled input differential voltage lies. The zone indication may be made from only the positive comparator outputs OUTP1 through OUTP9, or similarly, from only the negative comparator outputs OUTM1 through OUTM9.

[0058] According to this exemplary embodiment, some or all of the comparator outputs OUTP1-OUTP9 and OUTM1-OUTM9 are also forwarded to folding logic 130 to generate a delay-domain signal corresponding to the residual of the input sample relative to the nearest zone threshold. More specifically, folding logic 130 (according to this implementation) is configured to present logic transitions at two outputs FOLDP, FOLDM, the delay intervals between which constitute a delay-domain signal indicative of the differential residual from the nearest zone threshold.

[0059] 4A illustrates an example of a configuration of folding logic 130 according to this illustrative embodiment. NAND gate 400 within folding logic 130 has an input coupled to output OUTM8 of comparator 320(8) of V2D stage 120 and an input coupled to output OUTP6 of comparator 320(6). Similarly, NAND gate 402 has an input coupled to output OUTM6 of comparator 320(6) and an input coupled to output OUTP4 of comparator 320(6), and NAND gate 404 has an input coupled to output OUTM4 of comparator 320(4) and an input coupled to output OUTP2 of comparator 320(2). NAND gate 406 has an input coupled to output OUTM2 of comparator 320(2) and an input coupled to a voltage corresponding to a logic high or “1” level (e.g., at the Vdd power supply). NAND gates 400, 402, 404, and 406 each have an output coupled to a corresponding input of NAND gate 410, which has an output FOLDP.

[0060] NAND gate 411 has an input coupled to output OUTM9 of comparator 320(9) and an input coupled to output OUTP7 of comparator 320(7) of V2D stage 120, NAND gate 413 has an input coupled to output OUTM7 of comparator 320(7) and an input coupled to output OUTP5 of comparator 320(5), NAND gate 415 has an input coupled to output OUTM5 of comparator 320(5) and an input coupled to output OUTP3 of comparator 320(3), NAND gate 417 has an input coupled to output OUTM3 of comparator 320(3) and an input coupled to output OUTP1 of comparator 320(1), and NAND gate 419 has an input coupled to output OUTM1 of comparator 320(1) and a voltage corresponding to a logic “1” level. NAND gates 411, 413, 415, 417, and 419 each have an output that is coupled to a corresponding input of NAND gate 420, which has output FOLDM.

[0061] The folding logic 130 according to this example is implemented using NAND logic, however, other types of logic and logic gates may alternatively be used to equivalently perform the same logical operations as the NAND logic in this example, with the appropriate polarity of the input signals being selected accordingly.

[0062] Thus, NAND gates 400, 402, 404, and 406 in this example are arranged to receive a negative input (e.g., OUTM8) from one of the even-numbered comparators 320 and a positive input (e.g., OUTP6) from the next lower even-numbered comparator 320, two zone thresholds away, in sequence in the V2D comparator stage 120. In this arrangement, a fixed “1” level at the input of NAND gate 406 essentially corresponds to the lowest amplitude within the input range of ADC 100, above which the sampled input differential voltage V necessarily lies. According to this arrangement of NAND gates 400, 402, 404, 406, the output of the even-numbered critical comparator 320 for a given input sample is delayed relative to the other outputs because the residual error received at that comparator is the smallest among the even-numbered comparators.

[0063] For the example described above in connection with Table 1, if the sampled input differential voltage is between the zone threshold of comparator 320(8) (e.g., +187.5 mV) and the zone threshold of comparator 320(6) (e.g., +62.5 mV), NAND gate 400 will present a logic “0” level at its output. This is because, in that condition, both outputs OUTM8 and OUTP6 will be at a “1” level. NAND gates 402, 404, and 406 similarly respond to whether the sampled input differential voltage V is between the thresholds of the comparators 320 that drive their inputs. It is clear that the output of only one of NAND gates 400, 402, 404, and 406 coupled to an even-numbered critical comparator 320 will be at a “0” level for a given input sample. Also, the delay of the output logic transition of one of the NAND gates 400 , 402 , 404 , 406 to a “0” level inversely indicates the difference between the residue voltage and the closest zone threshold of the even-numbered comparator 320 .

[0064] NAND gate 410 has inputs coupled to the outputs of NAND gates 400, 402, 404, and 406, as shown in FIG. 4A, and operates to generate a single output signal at output FOLDP for the smallest even-numbered residual. For a given input sample, the output of only one of NAND gates 400, 402, 404, and 406 transitions from a “1” level to a “0” level, while the others maintain a “1” output level for that sample, so that output FOLDP of NAND gate 410 transitions from “0” to “1” in response to the “1” to “0” transition of that one NAND gate. The delay of the output logic transition to “1” at output FOLDP inversely indicates the difference between the residual voltage and the closest zone threshold of the even-numbered comparators 320 in V2D comparator stage 120.

[0065] Similarly, NAND gates 411, 413, 415, 417, and 419 in this example are arranged to receive a negative input (e.g., OUTM9) from one odd-numbered comparator 320 and a positive input (e.g., OUTP7) from the next lower odd-numbered comparator 320 that is two zone thresholds away in the V2D comparator stage 120. In this arrangement, the fixed “1” level at the input of NAND gate 419 corresponds to the lowest amplitude voltage in the input range of ADC 100, above which the sampled input differential voltage V necessarily lies. According to this arrangement of NAND gates 411, 413, 415, 417, the output of the critical odd-numbered comparator 320 for a given input sample is delayed relative to the other outputs because the residual error received at that comparator is the smallest of the odd-numbered comparators.

[0066] In the example described above in connection with Table 1, when the sampled input differential voltage is between the zone threshold for comparator 320(7) (e.g., +125 mV) and the zone threshold for comparator 320(5) (e.g., 0 mV), NAND gate 413 presents a logic “0” level at its output because, in that condition, both outputs OUTM7 and OUTP5 are at a “1” level. NAND gates 411, 415, 417, and 419 similarly respond to whether the sampled input differential voltage V is between the zone thresholds of the comparators 320 driving their inputs. It is clear that the output of only one of NAND gates 411, 413, 415, 417, and 419 coupled to odd-numbered critical comparators 320 will be at a “0” level for a given input sample. Also, the delay in the output logic transition to a “0” level of that one of the NAND gates 411 , 413 , 415 , 417 , 419 inversely indicates the difference between the residue voltage and the nearest zone threshold of the odd-numbered comparator 320 .

[0067] NAND gate 420 has inputs coupled to the outputs of NAND gates 411, 413, 415, 417, and 419 and operates to generate a single output signal at output FOLDM for the smallest odd-numbered residual. For a given input sample, the output of only one of NAND gates 411, 413, 415, 417, and 419 transitions from a “1” level to a “0” level, while the others maintain a “1” output level for that sample, so that output FOLDM of NAND gate 420 transitions from “0” to “1” in response to the “1” to “0” transition of that one NAND gate. The delay of the output logic transition to “1” at output FOLDM inversely indicates the difference between the residual voltage and the nearest zone threshold of the odd-numbered comparators 320 in V2D comparator stage 120.

[0068] In addition to the delay of the transitions at the outputs FOLDP, FOLDM of the folding logic 130 indicating the magnitude of the residual error relative to the associated zone threshold, the order in which the outputs FOLDP, FOLDM make their transitions from a "0" level to a "1" level indicates whether the residual error is closer to the zone threshold of an even-numbered comparator 320 or an odd-numbered comparator 320. More specifically, the folding logic 130 shown in FIG. 4A is arranged so that the NAND gates receive the outputs of comparators 320 that are two locations apart in the ordered sequence of comparators 320 (and node pairs VP / M1 through VP / M9). This arrangement of the folding logic 130 facilitates translation of input differential voltages at or near the midpoint of the input range zone.

[0069] An example of the operation of the folding logic 130 according to this illustrative embodiment is illustrated in Figures 4B and 4C for the case where the input differential voltage V is +62mV. For this input voltage of +62mV, the differential residual at each node pair VP / M9 to VP / M1 is shown in Table 2 relative to the zero-crossing criterion for each of these pairs. TIFF2025527845000003.tif132143As described above, the +62 mV input sample differential voltage is thermometer coded into a codeword by V2D comparator stage 120, with positive outputs OUTP5 and below in the ordered sequence from comparator 320 being at "1" levels and outputs OUTP6 and above in the ordered sequence being at "0" levels. Negative outputs OUTM9-OUTM1 have the opposite state to their corresponding positive outputs.

[0070] 4B illustrates folding logic 130, where the logic levels of the NAND gate inputs shown are based on the results of comparators 320 shown in the right column of Table 2. In this example, only NAND gate 402 in the group of NAND gates 400, 402, 404, 406 and NAND gate 413 in the group of NAND gates 411, 413, 415, 417, 419 exhibit a "0" output logic level, and the +62 mV input differential voltage is between the zone thresholds of comparators 320(5) and 320(6). Thus, NAND gate 410 drives a “0” to “1” transition at its output FOLDP in response to the output of NAND gate 402 driving a “1” to “0” transition at its output, and NAND gate 420 drives a “0” to “1” transition at its output FOLDM in response to the output of NAND gate 413 driving a “1” to “0” transition at its output. The order in which outputs FOLDP, FOLDM make their transitions indicates, in this example, whether input differential voltage V is closer to the zone threshold of comparator 320(6) (e.g., FOLDM transitions before FOLDP) or closer to the zone threshold of comparator 320(5) (e.g., FOLDP transitions before FOLDM).

[0071] Referring to Table 2, the differential residual at node pair VP / M5 is +62 mV, while the residual at node pair VP / M6 is −0.5 mV. Therefore, because the magnitude of the differential residual relative to the zone threshold at comparator 320(6) is much smaller than that at comparator 320(5), the logic “1” level driven by comparator 320(6) at output OUTM6 is delayed from the logic “1” level driven by comparator 320(5) at output OUTP5. Therefore, NAND gate 420 receives a logic “0” level from NAND gate 413 and responsively drives a “1” level at its output FOLDM earlier than NAND gate 410 receives a logic “0” level from NAND gate 402 and responsively drives a “1” level at its output FOLDP. In this example, output FOLDM switching before output FOLDP indicates that the input sample differential voltage is closer to the +62.5 mV zone threshold at comparator 320(6) than to the 0 mV zone threshold at comparator 320(5).

[0072] 4C illustrates the relative timing between transitions at output FOLDM of NAND gate 420 and transitions at output FOLDP of NAND gate 410 in this example. The delay tD between transitions at output FOLDM and transitions at output FOLDP corresponds to the relative difference between the residual error at node pair P / M6, represented by the timing of the transitions at the output of NAND gate 413, and the residual error at node pair P / M5, represented by the timing of the transitions at the output of NAND gate 402. In this example, an input sample differential voltage of +62 mV has a residual error of +62 mV at node pair P / M5 relative to the 0 mV zone threshold of comparator 320(5) and a residual error of −0.5 mV at node pair P / M6 relative to the +62.5 mV zone threshold of comparator 320(6).

[0073] 1, the outputs FOLDP, FOLDM from the folding logic 130 are coupled to a time-to-digital (TDC) converter 140 for encoding into n bits of a digital output word DOUT. The TDC converter 140 according to this implementation may be constructed according to any of several conventional approaches, including a delay-line-based TDC architecture, a digital counter-based architecture, an interpolation-based architecture such as that described in the above-incorporated U.S. Pat. No. 10,673,452, etc.

[0074] As described above, the conversion of voltage to the delay domain may be based on a nonlinear relationship, such that the delay signal varies nonlinearly (e.g., logarithmically) with the magnitude of the input voltage. Accordingly, digital stage 160 may further include LUT 145 to correct for such nonlinearity. For example, TDC converter 140 may present a digital value resulting from the conversion of the delay between transitions in outputs FOLDP and FOLDM as an address to LUT 145, in response to which LUT 145 returns a corresponding digital value corrected for the nonlinear relationship. The result output by LUT 145 may, in some implementations, be output directly as n bits of output digital word DOUT.

[0075] 5 illustrates how ADC 100 operates in converting an analog input differential voltage to a digital data word via delay-domain conversion, according to some examples. This method can be applied to a wide range of applications, including, for example, in direct sampling RF receivers for multiple-in-multiple-out (MIMO) wireless networks and communication systems.

[0076] This method involves sampling the received analog signal at a preselected sampling frequency f s5 is applied to each of the samples obtained in process 500 to generate a stream of digital output data corresponding to the received signal for processing in the digital domain. Although the method of FIG. 5 is described for a single sample, each sample obtained for the signal is similarly converted to digital at the desired data rate.

[0077] In process 502, the sampled input signal is applied in the form of a differential voltage to a multi-bit input buffer 110 to generate a set of residuals of the input differential voltage relative to multiple zero-crossing references. In some implementations, chopping of the residuals generated in process 502 is performed at a sampling frequency f s This may be accomplished in process 504 by mixing the residue with a chopping signal, such as a PRBS sequence, at a frequency equal to or less than half the frequency of the residual. Chopping process 504 reduces the effects of flicker noise and may be omitted if the effects of flicker noise are tolerable in ADC 100.

[0078] In process 506, the differential residual generated in process 502 is applied to a corresponding zero-crossing comparator 320 in V2D comparator stage 120. If chopping process 504 is performed, the same chopping signal is also applied to the comparator used in process 502. In some examples, each comparator 320 used in process 506 produces a single-ended output signal (or a complementary single-ended signal) in response to the differential residual at its input, with a delay in the output signal inversely proportional to the magnitude of the residual. The result output by each comparator 320 indicates a comparison of the input differential voltage with a zone threshold corresponding to a zero-crossing criterion for the residual at its input.

[0079] In process 508, an input range zone in which the input sample lies is identified from the single-ended output signal from comparators 320. If we consider comparators 320 as an ordered sequence according to the associated zero-crossing criteria of their input residuals, an input range zone is indicated by adjacent pairs of comparators 320 having output signals of opposite polarity (i.e., "critical" comparators). For example, the logic level of the comparator 302 output from process 508 may indicate a thermometer-coded indication of the input range zone in which the input sample lies. In process 510, n bits of the output digital word are encoded from the zone identified in process 508.

[0080] In process 512, some or all of the outputs of comparators 320 from process 508 are applied to folding logic 130 to generate a delay-domain signal indicative of the magnitude of the residual relative to the closest zone threshold. In this implementation, the delay-domain signal is generated in process 512 by folding logic 130, which emits a pair of output signal transitions (e.g., at outputs FOLDP and FOLDM, as described above) with relative delays corresponding to the magnitude of the residual relative to the closest zone threshold. As described above, folding logic 130 is configured to generate output signals based on outputs from critical comparators 320 having zone thresholds on either side of the input range zone, with the output signal indicating which zone threshold is closer by the later transition. In the example of FIG. 4B described above, if the transition at output FOLDP from NAND gate 410 lags the transition at output FOLDM from NAND gate 420, then the even-numbered one of the critical comparators 320 (comparator 320(6) in this example) corresponds to the closer zone threshold. Conversely, if the transition at output FOLDM from NAND gate 420 lags the transition at output FOLDP from NAND gate 410, the odd-numbered critical comparator 320 (in this example, comparator 320(5)) corresponds to the closer zone threshold.

[0081] In process 520, TDC 140 in digital stage 160 of ADC 100 encodes n bits of digital output word DOUT from the delay-domain signals generated in process 512. In this example, encoding process 520 is based on the relative delay of the output signal transitions generated in process 512 and the polarity of that delay (e.g., whether outputs FOLDP, FOLDM are delayed relative to the other). As described above, process 520 may include generating address data in response to the delay-domain signals from process 512 and applying the address data to LUT 145 to retrieve a corresponding digital value (e.g., n output bits) corrected for nonlinearities resulting from the analog-to-delay-domain conversion performed in processes 506-512.

[0082] The digital output word DOUT, which includes the m bits encoded in process 510 and the n bits encoded in process 520, represents the sampled input differential voltage obtained in process 500 and may then be forwarded to appropriate downstream circuitry for processing according to the application in which ADC 100 is being used. The method of Figure 5 is, of course, repeated for each of the samples in the sample stream obtained in process 500 to produce a digital data stream representative of the received input signal.

[0083] Important advantages result from the examples described herein. The configuration of multi-bit input buffers to generate zero-crossing residuals allows chopping to be applied to those residuals rather than the input signal, which may eliminate additional flicker from T2D conversion. The same zero-crossing comparator producing a single-ended output, according to some examples, may simplify folding logic and eliminate the need for parallel TDC circuitry to accurately identify input range zones. The substantially digital architecture of the ADC allows for efficient implementation of the ADC in terms of chip area and reduced power consumption.

[0084] As used herein, the terms "terminal," "node," "interconnect," and "pin" are used interchangeably. Unless otherwise specified to the contrary, these terms are used generally to refer to an interconnection or termination between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0085] While some elements of the illustrated examples are included in an integrated circuit and other elements are external to the integrated circuit, in other embodiments, additional or fewer features may be incorporated into the integrated circuit. Also, some or all of the features shown as being external to the integrated circuit may be included in the integrated circuit, and / or some features shown as being internal to the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits (1) incorporated within / on a semiconductor substrate, (2) incorporated within a single semiconductor package, (3) incorporated within the same module, and / or (4) incorporated within / on the same printed circuit board.

[0086] Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means + / - 10 percent of the stated value, or if the value is zero, a reasonable range around the zero value. Variations in the described embodiments are possible, and other embodiments are possible, within the scope of the claims.

[0087] A device that is "configured" to perform a certain task or function may be configured (e.g., programmed and / or hardwired) to perform that function by a manufacturer at the time of manufacture, or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be through firmware and / or software programming of the device, or through the configuration and / or layout of hardware components, device interconnections, or a combination thereof.

[0088] A circuit or device described as including certain components may instead be adapted to be coupled to those components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and be adapted to be coupled to at least some of the passive elements and / or sources, thereby forming the described structure, either at the time of manufacture or at a later time, e.g., by an end user and / or a third party. In some instances, certain elements may be included in an integrated circuit and other elements may be external to the integrated circuit, while in other instances, additional or fewer features may be incorporated into the integrated circuit. Also, some or all of the features shown to be external to the integrated circuit may be included in the integrated circuit, and / or some features shown to be internal to the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits (1) integrated in / on a semiconductor substrate, (2) integrated in a single semiconductor package, (3) integrated in the same module, and / or (4) integrated in / on the same printed circuit board.

[0089] Circuits described herein are reconfigurable to include replaced components to provide functionality at least partially similar to that available prior to the component replacement. Unless otherwise noted, a component depicted as a resistor generally represents any one or more elements coupled in series or parallel to provide the amount of impedance represented by the depicted resistor. For example, a resistor described herein as a single component may instead be multiple resistors or capacitors, each of which may be multiple resistors coupled in parallel between the same nodes. For example, a resistor or capacitor depicted and described herein as a single component may instead be multiple resistors or capacitors, each of which may be coupled in parallel between the same nodes, as a single resistor or capacitor. For example, a resistor or capacitor depicted and described herein as a single component may instead be multiple resistors or capacitors, each of which may be coupled in series between the same two nodes, as a single resistor or capacitor.

[0090] Use of the term "ground" in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other type of ground connection applicable or suitable to the teachings herein.

[0091] While one or more embodiments have been described herein, it is understood that modifications and alternatives to those embodiments, modifications and alternatives which may achieve one or more of the technical advantages of those embodiments, will be apparent to those skilled in the art having reference to this specification and its drawings. Such modifications and alternatives are intended to be within the scope of the claims presented herein.

Claims

1. An analog-to-digital conversion circuit, a multi-bit input buffer having differential inputs coupled to receive the differential input samples; a plurality of zero-crossing comparators; a folded logic circuit element; digital stage circuitry; Including, the multi-bit input buffer is configured to output, at a plurality of differential outputs, a plurality of residuals of the differential input samples relative to a corresponding plurality of zero-crossing references; each of the plurality of zero-crossing comparators having a differential input coupled to receive one of the plurality of residuals from one of the plurality of differential outputs of the multi-bit input buffer; and an output, each zero-crossing comparator being associated with a zone threshold according to an ordered sequence of zone thresholds; each of the folding logic circuit elements having a plurality of inputs coupled to the output of one of the plurality of zero-crossing comparators, the folding logic circuit elements configured to output a delay-domain signal indicative of a magnitude of the one of the residuals associated with a nearest zone threshold; the digital stage circuitry is coupled to an output of the zero-crossing comparator and to an output of the folding logic circuitry and configured to generate a digital output word corresponding to the received differential input sample. Analog-to-digital conversion circuit.

2. 2. The analog-to-digital converter circuit of claim 1, wherein the multi-bit input buffer comprises: first and second resistor ladders, each including a plurality of series-connected resistors; first and second transistors; third and fourth transistors; Including, the first transistor has a conduction path between a power supply node and the first resistor ladder, the second transistor has a conduction path between the first resistor ladder and a ground node, and the first and second transistors each have a control terminal coupled to a first input of the differential input; the third transistor has a conductive path between the power supply node and the second resistor ladder, the fourth transistor has a conductive path between the first resistor ladder and the ground node, and the third and fourth transistors each have a control terminal coupled to a second input of the differential input; each of the plurality of differential outputs includes a node in the first resistor ladder and a corresponding opposite node in the second resistor ladder; Analog-to-digital conversion circuit.

3. 2. The analog-to-digital conversion circuit of claim 1, further comprising a plurality of chopping stages, each of the plurality of chopping stages coupled between the output of the multi-bit input buffer and the differential input of a corresponding comparator, the chopping stages having an input coupled to receive a chopping signal. Analog-to-digital conversion circuit.

4. 4. The circuit of claim 3, further comprising a sequence generator configured to generate the chopping signal in the form of a pseudo-random binary sequence at a chopping frequency.

5. 2. The analog-to-digital conversion circuit of claim 1, the digital stage circuitry includes a digital encoder having an input coupled to the output of the comparator and configured to encode one or more bits of the digital output word to indicate an input range zone of the differential input sample between the zone thresholds associated with adjacent comparators in the ordered sequence having different polarities at their outputs; Analog-to-digital conversion circuit.

6. 2. The analog-to-digital converter circuit of claim 1, wherein the outputs of each of the comparators comprise complementary single-ended outputs.

7. 7. The analog-to-digital converter circuit of claim 6, wherein the folding logic circuit element comprises: a first plurality of logic functions; a first output logic function; a second plurality of logic functions; a second output logic function; and Including, each of the first plurality of logic functions having a first input coupled to a negative output of one of the comparators, a second input coupled to a positive output of another of the comparators that is two positions away from the one of the comparators in the sequence, and an output; the first output logic function having a plurality of inputs each coupled to an output of one of the first plurality of logic functions and configured to present a logic transition at its output in response to receiving a most recent logic transition at its input; each of the second plurality of logic functions having a first input coupled to a negative output of one of the comparators, a second input coupled to a positive output of another of the comparators that is two positions away from the one of the comparators in the sequence, and an output; the second output logic function having a plurality of inputs, each coupled to an output of a logic function of the second plurality of logic functions, and configured to present a logic transition at an output in response to receiving a most recent logic transition at an input; Analog-to-digital conversion circuit.

8. 8. The analog-to-digital conversion circuit of claim 7, wherein the inputs of the first plurality of logic functions are coupled to odd-numbered comparators in the sequence, and the inputs of the second plurality of logic functions are coupled to even-numbered comparators in the sequence.

9. 8. The analog-to-digital conversion circuit of claim 7, wherein the digital stage circuitry comprises: a digital encoder having an input coupled to the output of the comparator; a time-to-digital converter having a first input coupled to the output of the first output logic function, a second input coupled to the output of the second output logic function, and an output; Including, the digital encoder is configured to encode one or more bits of the digital output word to indicate an input range zone of the input sample between the zone thresholds associated with adjacent comparators in the ordered sequence having different polarities at their outputs; the time-to-digital converter is configured to present at its output one or more bits of the digital output word in response to a delay time between a logic transition at the output of the first output logic function and a logic transition at the output of the second output logic function; Analog-to-digital conversion circuit.

10. 10. The analog-to-digital conversion circuit of claim 9, the digital stage circuitry further comprises addressable memory; the addressable memory stores a look-up table, has an address input coupled to the output of the time-to-digital converter, and has a data output for presenting the one or more bits of the digital output word; Analog-to-digital conversion circuit.

11. 1. A method for converting an analog signal level into a digital word, comprising: sampling a differential input signal; generating a plurality of differential residual signals from the sampled differential input signal relative to a plurality of zero-crossing references; applying each differential residual signal to a corresponding one of a plurality of zero-crossing comparators in an ordered sequence of zone thresholds; identifying an input range zone for the sampled differential input signal between the zone thresholds of adjacent comparators in the ordered sequence having a change in polarity at their outputs; identifying a delay between logic transitions in adjacent comparators; encoding a digital output word indicative of the identified input range zone and the identified delay; A method comprising:

12. 12. The method of claim 11, wherein the step of generating the plurality of differential residual signals comprises: applying a first signal line from the sampled differential input signal to a first resistor ladder, the first resistor ladder having a first plurality of nodes of the resistors in the first resistor ladder, each of the first plurality of nodes being coupled to a first input of a corresponding zero-crossing comparator; applying a second signal line from the sampled differential input signal to a second resistor ladder, the second resistor ladder having a second plurality of nodes of the resistors in the second resistor ladder, each of the second plurality of nodes being coupled to a second input of a corresponding zero-crossing comparator; A method comprising:

13. 13. The method of claim 12, wherein the step of identifying the delay comprises: generating a first signal in response to a most recent logic transition at the output of an even-numbered comparator in the sequence; generating a second signal in response to a most recent logic transition at the output of an odd-numbered comparator in the sequence, one of the first and second signals being delayed from the other; applying the first and second signals to a time-to-digital conversion circuit; A method comprising:

14. 12. The method of claim 11, further comprising chopping each of the differential residues at a frequency equal to or less than half the frequency of the sampling step; the applying step applies the chopped differential residue to an input of the zero-crossing comparator. method.

15. A voltage-to-delay conversion circuit, a multi-bit input buffer having differential inputs coupled to receive the differential input samples; a plurality of zero-crossing comparators; a folded logic circuit element; Including, the multi-bit input buffer is configured to generate, at a plurality of differential outputs, a plurality of residues of the differential input samples relative to a corresponding plurality of zero-crossing references; each of the zero-crossing comparators has a differential input coupled to receive one of the residuals from one of the differential outputs of the multi-bit input buffer, and has an output, each zero-crossing comparator associated with a zone threshold according to an ordered sequence of zone thresholds such that the output of a zero-crossing comparator indicates an input range zone of the input sample between the zone thresholds associated with adjacent comparators in the ordered sequence having different polarities at their outputs; the folding logic circuit element has a plurality of inputs each coupled to one of the outputs of one of the zero-crossing comparators, the folding logic circuit element being configured to output a delay-domain signal indicative of the magnitude of one of the residuals relative to a nearest zone threshold. circuit.

16. 16. The circuit of claim 15, wherein the multi-bit input buffer comprises: first and second resistor ladders, each including a plurality of series-connected resistors; first and second transistors; third and fourth transistors; Including, the first transistor has a conduction path between a power supply node and the first resistor ladder, the second transistor has a conduction path between the first resistor ladder and a ground node, and the first and second transistors each have a control terminal coupled to a first input of the differential input; the third transistor has a conductive path between the power supply node and the second resistor ladder, the fourth transistor has a conductive path between the first resistor ladder and the ground node, and the third and fourth transistors each have a control terminal coupled to a second input of the differential input; each of the plurality of differential outputs includes a node in the first resistor ladder and a corresponding opposite node in the second resistor ladder; circuit.

17. 16. The circuit of claim 15, further comprising a plurality of chopping stages, each of the plurality of chopping stages having an input coupled between the output of the input stage and the differential input of a corresponding comparator, the input coupled to receive a chopping signal; circuit.

18. 20. The circuit of claim 17, further comprising a sequence generator configured to generate the chopping signal in the form of a pseudo-random binary sequence at a chopping frequency.

19. 16. The circuit of claim 15, wherein the outputs of each of the comparators comprise complementary single-ended outputs; the folding logic circuit element: a first plurality of logic functions; a first output logic function; a second plurality of logic functions; a second output logic function; and Including, each of the first plurality of logic functions having a first input coupled to a negative output of one of the odd-numbered comparators in the sequence, a second input coupled to a positive output of another of the odd-numbered comparators two positions away from the one of the comparators in the sequence, and an output; the first output logic function has a plurality of inputs, each of the plurality of inputs coupled to an output of a logic function of the first plurality of logic functions and configured to present a logic transition at its output in response to receiving a most recent logic transition at its input; each of the second plurality of logic functions having a first input coupled to a negative output of an even-numbered one of the comparators, a second input coupled to a positive output of another of the even-numbered comparators that is two places away from said one of the comparators in the sequence, and an output; the second output logic function having a plurality of inputs, each of the plurality of inputs coupled to an output of a logic function of the second plurality of logic functions, and configured to present a logic transition at its output in response to receiving a most recent logic transition at its input; circuit.

20. 1. An analog to digital converter having an analog input operable to receive an analog input signal and having an output operable to output a digital signal comprising a most significant bit (MSB) and a least significant bit (LSB), said analog to digital converter comprising: a multi-bit input buffer having a buffer input coupled to the analog input and having a plurality of buffer outputs; a V2D comparator stage having a plurality of V2D inputs, each V2D input coupled to a different one of the plurality of buffer outputs, and having a plurality of V2D outputs; a folding circuit including a plurality of mixers and a plurality of comparators; Including, each of the plurality of mixers having a mixer input, a mixer output, and a mixer chopper input, each mixer input coupled to one of the plurality of V2D inputs, and each mixer chopper input coupled to chopper circuitry operable to generate a pseudo-random binary sequence; each of the plurality of comparators having a comparator input, a comparator output, and a comparator-chopper input, each comparator input coupled to a corresponding mixer output and each comparator-chopper input coupled to the chopper circuitry, the plurality of comparators operable to output the MSB of the digital signal; the folding circuit having a plurality of folding circuit inputs, a plurality of folding circuit outputs, and a plurality of logic gates coupled therebetween, each folding circuit input coupled to a respective comparator output, the folding circuit operable to output the least significant bit of the digital signal; Analog-to-digital converter.

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