Topology structure used in IP cores and IP cores

Abstract

An embodiment of the present disclosure discloses a topology structure used in an IP core, which includes a first topology structure and a second topology structure. The first topology structure includes a driver chip, multiple stages of first signal lines, and at least two first loads. A signal output terminal of one first signal line in a front stage is connected to signal input terminals of two first signal lines in a rear stage connected in parallel. The signal input terminal of the first signal line in the first stage is connected to a signal output terminal of the driving signal. An output terminal of each first signal line in the last stage is connected to one first load. The second topology structure includes multiple branch structures, each branch structure including at least one second load. The signal input terminal of each branch structure is connected to a signal output terminal of one first signal line in the last stage of the first topology structure. This provides a new topology structure for the IP core and realizes diversified IP core topology structures to meet different needs.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to a Chinese patent application filed on July 29, 2022, bearing application number 202210904304.5 and entitled "Topology structure and IP core used in IP core," the entire text of which is incorporated herein by reference.

[0002] The present disclosure relates to the field of integrated circuit technology, and more particularly to a topology structure used in IP cores and IP cores. [Background technology]

[0003] As integrated circuits become larger, their designs become more and more complex. To design and manufacture integrated circuits that achieve various functions faster, integrated circuit modules with appropriate functions may be designed as reusable IP cores. In integrated circuit design, an IP core refers to an integrated circuit design module with some appropriate function that has been verified and can be reused.

[0004] A memory integrated circuit module with high-speed data read / write capabilities can be reused across different integrated circuits by using a driver chip and double data rate synchronous dynamic random access memory (DDR) as an IP core. Summary of the Invention

[0005] This Summary is provided to introduce concepts in a simplified form that are described in detail later in the Detailed Description. This Summary is not intended to identify key features or required features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0006] The embodiments of the present disclosure provide a topology structure for use in an IP core and the IP core.

[0007] According to a first aspect, an embodiment of the present disclosure provides a topology structure used in an IP core, the topology structure including a first topology structure and a second topology structure, the first topology structure including a driver chip, multiple stages of first signal lines, and at least two first loads, a signal output end of one first signal line of a front stage connected to signal input ends of two first signal lines of a rear stage connected in parallel, a signal input end of the first signal line of the first stage connected to a signal output end of the driving signal, and an output end of each first signal line of a last stage connected to one first load, the second topology structure including multiple branch structures, each branch structure including at least one second load, and a signal input end of each branch structure connected to a signal output end of one first signal line of a last stage of the first topology structure.

[0008] According to a second aspect, an embodiment of the present disclosure provides an IP core, comprising: a substrate; a driver chip provided on the substrate; a plurality of loads; and a connection structure between the plurality of loads and the driver chip; wherein the topology structure connected between the plurality of loads and the driver chip comprises a first topology structure and a second topology structure; the first topology structure comprises a driver chip, a plurality of first signal lines, and at least two first loads; a signal output end of one first signal line of a preceding stage is connected to signal input ends of two first signal lines of a subsequent stage connected in parallel; a signal input end of the first signal line of the first stage is connected to a signal output end of the driving signal; and an output end of each first signal line of a final stage is connected to one first load; and the second topology structure comprises a plurality of branch structures, each branch structure comprising at least one second load, and a signal input end of each branch structure is connected to a signal output end of one first signal line of a final stage of the first topology structure.

[0009] In the topology structure used in the IP core and the IP core according to the embodiments of the present disclosure, the topology structure includes a first topology structure and a second topology structure, the first topology structure includes a driver chip, a plurality of first signal lines, and at least two first loads, the signal output terminal of one first signal line in a preceding stage is connected to the signal input terminals of two first signal lines in a succeeding stage connected in parallel, the signal input terminal of the first signal line in the first stage is connected to the signal output terminal of the driving signal, and the output terminal of each first signal line in the last stage is connected to one first load, the second topology structure includes a plurality of branch structures, each branch structure includes at least one second load, and the signal input terminal of each branch structure is connected to the signal output terminal of one first signal line in the last stage of the first topology structure, thereby realizing the combination of the first topology structure and the second topology structure to form the topology structure used in the IP core, providing new topology structures for the IP core and realizing diversified IP core topology structures to meet different needs. [Brief explanation of the drawings]

[0010] These and other features, advantages, and aspects of the embodiments of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. In all of the accompanying drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the accompanying drawings are schematic, and that the objects and elements are not necessarily drawn to scale. [Figure 1] FIG. 1 is a schematic diagram of a topology structure used in an IP core according to the present disclosure. [Figure 2] FIG. 10 is another schematic diagram of a topology structure used in an IP core according to the present disclosure. [Figure 3] FIG. 1 is a schematic eye diagram of an IP core according to the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0011] The following describes in more detail the embodiments of the present disclosure with reference to the accompanying drawings. Although several embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be realized in various forms and should not be construed as being limited to the embodiments described herein. On the contrary, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the accompanying drawings and embodiments of the present disclosure are merely illustrative and do not limit the scope of protection of the present disclosure.

[0012] It should be understood that the steps described in the method embodiments of the present disclosure may be performed in different orders and / or in parallel. Furthermore, method embodiments may include additional steps and / or omit the performance of steps shown. The scope of the present disclosure is not limited in this respect.

[0013] As used herein, the term "comprises" and variations thereof are open-ended, meaning "including, but not limited to." The term "based on" means "based at least in part on." The term "in one embodiment" means "at least one embodiment," the term "in another embodiment" means "at least one other embodiment," and the term "in some embodiments" means "at least some embodiments." Relevant definitions of other terms are provided below.

[0014] It should be noted that the concepts of "first," "second," etc. described in this disclosure are merely intended to distinguish between different devices, modules, or units, and are not intended to limit the order or interdependence of functions performed by these devices, modules, or units.

[0015] It should be understood by those skilled in the art that the modifications "one" and "multiple" described in this disclosure are illustrative and not limiting, and should be understood as "one or more" unless otherwise specified.

[0016] The names of messages or information exchanged between devices in the embodiments of the present disclosure are merely descriptive and do not limit the scope of these messages or information.

[0017] It should be noted that, unless contradictory, the embodiments and features in the embodiments of the present disclosure can be combined with each other.

[0018] Referring to FIG. 1, a schematic diagram of a topology structure used in an IP core according to the present disclosure is shown. As shown in FIG. 1, the topology structure used in the IP core includes a first topology structure 11 and a second topology structure 12. The first topology structure 11 includes a driver chip D, multiple stages of first signal lines S11, S2, ..., S1M, and at least two first loads B1. The driver chip D here may include various chips for generating operating signals, including, but not limited to, a field-programmable gate array (FPGA), a system-on-chip (SoC), etc. The driver chip D can generate a clock signal. The clock signal here may be a control signal for controlling the load. The control signal here may be, for example, a control address signal (CA).

[0019] In the first topology structure, the number of stages of the first signal lines S11, S2, ..., S1M may be set according to a specific application scenario. Here, the output terminal of one first signal line in the preceding stage is connected to the signal input terminals of two first signal lines in the following stage connected in parallel. The input terminal of the first signal line in the first stage is connected to the output terminal of the driver chip. The output terminal of each first signal line in the final stage is connected to one first load B1.

[0020] That is, the signal input terminals of the two first signal lines in the latter stage are connected in parallel, and then connected to the signal output terminal of one first signal line in the former stage.

[0021] The first signal line of the first stage includes one first signal line. The signal input terminal of the first signal line of the first stage is connected to the signal output terminal of the driver chip D.

[0022] The output terminal of the first signal line S1M in the last stage is connected to a first load.

[0023] When there are two stages of first signal lines in the multiple stages, the first signal line in the second stage includes two first signal lines and the first signal line in the first stage includes one first signal line. When there are three stages of first signal lines in the multiple stages, of the first signal lines in the three stages, the first signal line in the first stage includes one first signal line, the first signal line in the second stage includes two first signal lines, and the first signal line in the third stage includes four first signal lines. When there are four stages of first signal lines in the multiple stages, of the first signal lines in the four stages, the first signal line in the first stage includes one first signal line, the first signal line in the second stage includes two first signal lines, the first signal line in the third stage includes four first signal lines, and the first signal line in the fourth stage includes eight first signal lines, and so on.

[0024] The output end of the first signal line of the last stage is connected to a first load B1.

[0025] In the first topology structure, the number of first loads B1 may be equal to or less than the number of first signal lines in the last stage. A control signal generated by the driver chip D may be transmitted through the first signal lines of each stage to the output end of the first signal line in the last stage, and then transmitted to the first loads B1 to control the operation of the first loads B1.

[0026] The first topology structure may be a T-shaped topology structure.

[0027] The second topology structure 12 includes a plurality of branching structures 121, each of which includes at least one second load B2. A signal input terminal of each branching structure 121 is connected to an output terminal of one first signal line at the last stage of the first topology structure 11.

[0028] At least one second load B2 in each branch structure 121 may be connected in series. The second loads B2 in one branch structure 121 may be connected to each other via a second signal line S22.

[0029] Since the signal input terminal of each branching structure 121 is connected to the output terminal of one first signal line S1M of the last stage of the first topology structure 11, the control signal issued by the driver chip D can be transmitted to the second load B2 via the first signal line and the second signal line S22 of each stage.

[0030] The number of branching structures 121 in the second topology structure 12 may be equal to or less than the number of first signal lines at the last stage in the first topology structure.

[0031] The output end of the first signal line in the last stage of the first topology structure 11 is connected to the input end of one second signal line in the branching structure 121. The output end of the second signal line is connected to one second load B2. In some application scenarios, one branching structure includes two second loads. The branching structure may include multiple second signal lines. The input end of the first second signal line in the branching structure is connected to the output end of one of the first signal lines in the last stage of the first topology structure. The output end of the first second signal line is connected to one second load. Furthermore, the output end of the first second signal line S22 is further connected to the input end of the second second signal line S22. The output end of the second second signal line S22 is connected to one second load.

[0032] The second topology structure 12 may be a fly_by structure.

[0033] The number of second loads in the branch structure in the second topology structure 12 may be determined according to the driving capability of the driver chip.

[0034] The first load B1 and the second load B2 may be electronic components that complete the same function, for example, electronic components that complete a data storage function. Specifically, the first load B1 and the second load B2 may be double data rate synchronous dynamic random access memory (DDR), low power double data rate synchronous dynamic random access memory (LPDR), etc. Synchronous Dynamic Random Access Memory (LPDDR), etc.

[0035] The topology structure used in the IP core according to this embodiment combines the first topology structure and the second topology structure to form the topology structure used in the IP core, thereby providing a new topology structure for the IP core and realizing a diversified IP core topology structure to meet different needs.

[0036] In some application scenarios, in the first topology structure 11, the equivalent impedance formed by two first signal lines connected in parallel in the subsequent stage is equal to the impedance of one first signal line in the previous stage connected to it.

[0037] The impedance of each of the two first signal lines connected in parallel at the subsequent stage may be equal.

[0038] For example, the magnitude of the equivalent impedance formed by two second-stage first signal lines connected in parallel among the second-stage first signal lines is equal to the impedance of the first-stage first signal line connected to the two second-stage first signal lines connected in parallel.

[0039] For example, if the impedance of the first signal line of the first stage is 10 ohms, the impedance of each first signal line of the second stage connected to the first signal line of the first stage may be 20 ohms, and the equivalent impedance after the first signal lines of the second stage are connected in parallel may be 10 ohms, which is equal to the impedance of the first signal line of the first stage.

[0040] In these application scenarios, the equivalent impedance formed by the two first signal lines connected in parallel in the subsequent stage is equal to the impedance of the single first signal line in the previous stage connected to it, and the impedances of the two first signal lines connected in parallel in the subsequent stage are set equal, so that it is possible to ensure that the impedance of the first signal lines in each stage has good continuity.

[0041] In some alternative implementations, the branch structure of the second topology structure 12 includes at least one second signal line connected to a second load, which may include a second signal line S22 connected to the first signal line of the last stage in the first topology structure and a second signal line S22 between each second load B2.

[0042] In these selective implementation forms, the impedance of the second signal line at each stage in the branch structure 121 of the second topology structure 12 is also set to be equal to the impedance of the first signal line connected to the branch structure, thereby improving the continuity of the impedance of the signal line throughout the entire topology structure.

[0043] In some alternative implementations, the above first topology structure 11 includes two stages of first signal lines and two first loads.

[0044] That is, the first topology structure 11 includes one first-stage first signal line and two second-stage first signal lines. The two second-stage first signal lines are connected in parallel and then connected to the output terminal of the first-stage first signal line. The output terminals of the two second-stage first signal lines are each connected to a first load.

[0045] In some alternative implementations, the second topology structure 12 may include two branch structures 121. Each branch structure 121 includes one second load.

[0046] In this way, the second topology structure 12 may include a total of two second loads B2.

[0047] In some application scenarios, refer to Fig. 2, which shows a schematic diagram of a topology structure used in an IP core according to the present disclosure. As shown in Fig. 2, a first topology structure 11' may include two stages of first signal lines S11 and S12.

[0048] The second topology structure 12′ may include two branch structures 121′, and the input end of the second signal line S22′ of each branch structure may be connected to the output end of the first signal line S12 of the second stage of the first topology structure 11′. The output end of the second signal line S22′ of the branch structure 121′ is connected to one second load B2.

[0049] In these alternative implementations, the first topology structure 11′ includes two stages of first signal lines S11 and S12, the first topology structure 11′ includes two first loads B1, and the second topology structure 12′ includes two branch structures 121′. Each branch structure 121′ includes one second load B2. The output terminal of the first topology structure 11′ is connected to the input terminal of one branch structure 121′ of the second topology structure 12′. This allows the entire topology structure to accommodate four loads. This topology structure is applicable when a driver chip needs to interface with four loads, which is difficult to achieve using the first topology structure or the second topology structure alone.

[0050] An embodiment of the present disclosure further provides an IP core, the IP core including: a substrate; a driver chip provided on the substrate; a plurality of loads; and a connection structure between the plurality of loads and the driver chip, wherein a topology structure formed by connection between the plurality of loads and the driver chip includes a first topology structure and a second topology structure, the first topology structure including the driver chip, a plurality of first signal lines, and at least two first loads, wherein a signal output terminal of one first signal line of a preceding stage is connected to signal input terminals of two first signal lines of a succeeding stage connected in parallel, a signal input terminal of the first signal line of the first stage is connected to a signal output terminal of the driving signal, and an output terminal of each first signal line of a last stage is connected to one first load, and the second topology structure including a plurality of branch structures, each branch structure including at least one second load, and a signal input terminal of each branch structure connected to a signal output terminal of one first signal line of a last stage of the first topology structure.

[0051] The driver chip may be various chips capable of generating clock signals, such as a Field Programmable Gate Array (FPGA), a System on Chip (SoC), a Microcontroller Unit (MCU), etc. The load may be an electronic component that realizes one or more functions. In some application scenarios, the load may be an electronic component that realizes a data storage function. For example, the load may be a DDR, an LPDDR, etc.

[0052] The driver chip, the first load and the second load may be connected to the substrate by soldering, gluing or the like.

[0053] The first signal line of each stage above may be made of the substrate material.

[0054] The branch structure may also include a second signal line. Each of the first signal line and the second signal line may be made of a conductive material on the substrate.

[0055] The branch structure of the second topology structure may include a second signal line, and the second signal line may include a second signal line connected between an output end of the first signal line of the last stage of the first topology structure and a second load, or may include a second signal line connected between different second loads.

[0056] In this example, the substrate may be any substrate that utilizes it as a driver chip, a load carrier, and in which signal lines in a second topology structure are fabricated relative to the first signal line.

[0057] In one implementation, the substrate may be a printed circuit board (PCB), also called a printed circuit board, which includes a copper cladding layer and an insulating layer, and connection leads and pads can be created on the copper cladding layer by processes such as printing and etching.

[0058] The first topology structure includes a plurality of first signal lines, and the second topology structure includes a plurality of branch structures, each of which includes at least one second signal line. The first signal line and the second signal line are formed on a printed circuit board. A pad may connect a signal output terminal of the driver chip to an input terminal of the first signal line in the first stage. An output terminal of the first signal line in the last stage of the first topology structure may be connected to an input terminal of the first load. An output terminal of one second signal line in the second topology structure may be connected to a signal input terminal of the second load.

[0059] If the PCB board is a multilayer board, the first signal line and the second signal line may include a signal line provided within a horizontal plane of at least one copper clad layer, or may include a signal line that spans different copper clad layers via a hole.

[0060] When fabricating the first signal lines of each stage using a PCB board, the continuity of the impedance of the first signal lines of each stage may be ensured by controlling the impedance of the first signal lines of each stage so that the equivalent impedance of the two first signal lines connected in parallel in the latter stage is equal to the impedance of the first signal line of the former stage connected to the two first signal lines connected in parallel.

[0061] Similarly, when fabricating the second signal lines of each branch structure using a PCB board, it is necessary to control the impedance of the second signal lines of each branch structure. For each branch structure, the impedance of each second signal line on the branch structure may be controlled to be equal. Furthermore, it is necessary to control the impedance of the second signal line in the branch structure to be equal to the impedance of the first signal line connected to the branch structure.

[0062] It should be noted that, when a signal line formed across different copper clad layers by a hole is a first signal line, the impedance of the first signal line needs to be controlled based on the relationship between the impedance of the first signal line and the impedance of the previous stage connected to it. When a signal line formed across different copper clad layers by a hole is a second signal line, the impedance of the second signal line may be controlled based on the impedance of the first signal line connected to the branch structure in which the second signal line is located. Specifically, the value of an antipad may be optimized to adjust the impedance of the first signal line or the impedance of the second signal line, thereby ensuring good continuity in the impedance of each node of the IP core.

[0063] Various signal lines may be provided on the PCB board to connect the driver chip and the load. The printed wiring board in the PCB board is composed of an insulating base plate, connecting lead wires, and pads for soldering electronic components, and can serve as both a conductive line and an insulating base plate. This can realize electrical connections between each element in the circuit instead of complex wiring.

[0064] A PCB substrate can be selected according to the impedance requirements of the first signal line. For example, a PCB substrate that can achieve the impedance of the final first signal line can be selected to fabricate the signal line. When the load supports a high-speed transmission rate, the lower the Dk of the PCB board material, the better the quality and speed of the high-speed transmitted signal. Dk is an index that measures the material's ability to store electricity. The lower the Dk, the faster the signal transmission speed in the medium and the stronger the capacity.

[0065] Dk is the dielectric constant (Dk) or relative permittivity of a PCB wiring board material. Dk is not a fixed constant. For example, the Dk of a material changes with frequency. In this disclosure, an IP core is fabricated by selecting a PCB substrate whose Dk value is smaller than a predetermined threshold. The predetermined threshold can be set according to a specific application scenario and is not limited here.

[0066] The first topology structure may be a T-type topology structure. When the first signal lines of each stage of the first topology structure are provided on the PCB board so that the impedance of the first topology structure has good continuity, the equivalent impedance of each of the two parallel-connected first signal lines of the subsequent stage is equal to twice the impedance of the first signal line of the previous stage connected to the two first signal lines. Thus, the equivalent impedance of the two parallel-connected first signal lines of the subsequent stage after being connected in parallel is equal to the impedance of the first signal line of the previous stage connected to the two first signal lines.

[0067] The IP core of this example combines a first topology structure and a second topology structure on a substrate, thereby realizing an IP core that enables a driver chip to drive multiple loads at low manufacturing costs.

[0068] In some embodiments, the first load and the second load may be memory components having high-speed data read / write capabilities. The first topology structure provided on the substrate includes two stages of first signal lines and two first loads, and the second topology structure includes two branch structures, each including one second load. Accordingly, the IP core may include one driver chip and four loads. The driver chip may be soldered or glued onto the substrate. Accordingly, the first signal lines formed on the substrate based on the topology structure include two stages. An input end of the first signal line of the first stage is connected to an output end of the driver chip. The first signal line of the first stage includes one first signal line. The second signal line of the second stage includes two first signal lines connected in parallel. The impedance of the first signal line of the second stage may be twice the impedance of the first signal line of the first stage. The branch structure provided on the substrate may include two branch structures. Each branch structure may include one second load. Each branch structure may include one second signal line. The impedance of the second signal line in each branch structure may be equal to the impedance of one second-stage first signal line connected to the branch structure.

[0069] In these alternative implementations, the first topology corresponds to a T-type topology, and the second topology corresponds to a fly_by topology. The substrate may be a PCB. By creating an IP core using a topology composed of the first topology and the second topology, a driver chip in the IP core can smoothly drive four loads.

[0070] If the load is a high-speed read / write memory component, such as a 64-bit LPDDR5, the driver chip is an SoC. To achieve four loads with one driver chip using a conventional T-type topology, a double-T-type topology is required. Because the number of branching structures is one more than in a single-T-type topology, and the number of loads is one-fold greater, if the IP core is to achieve good eye diagram results, the driver chip requires stronger driving capabilities and strictly satisfies the proportional relationship that a single signal line in the subsequent stage is twice as large as the signal line in the previous stage connected to it. However, in actual construction, when fabricating the first signal line on a PCB, the greater the number of first signal line stages in the T-type topology, the greater the impedance of the first signal line in that stage. However, since there is an upper limit to the impedance of signal lines that can be realized on a PCB board and it cannot be infinite, the impedance designed into the T-type structure may not be realized on the PCB board. For this reason, signal lines in a T-type topology with a large number of stages are difficult to implement. On the other hand, due to variations in the manufacturing process, there is a large variation in the impedance values ​​actually realized on the PCB board. The variation in impedance values ​​is related to the magnitude of the impedance value. The greater the number of stages in the T-shaped structure, the greater the variation due to issues in the manufacturing process. Therefore, the continuity of the impedance of the first signal line of each stage becomes poor, causing a phenomenon in which the eye diagram effect becomes poor.

[0071] In these alternative implementations, a method of combining a first topology structure and a second topology structure is adopted, where the first topology structure is a T-shaped topology structure and the second topology structure is a fly_by topology structure. Two-stage first signal lines in the first topology structure are fabricated on a PCB board by a process such as printing or etching, and second signal lines in the second topology structure are fabricated.

[0072] Of the two-stage first signal lines fabricated on the PCB board, the signal input terminal of the first-stage signal line may be connected to the signal output terminal of the driver chip. The output terminal of the second-stage first signal line may be connected to two first loads. Two branch structures may be fabricated on the PCB board, each branch structure corresponding to one second signal line. The signal input terminal of each second signal line may be connected to the output terminal of one second-stage first signal line. The output terminal of the second signal line is connected to one second load.

[0073] Thus, in the implementation of the lead wires corresponding to the first topology structure described above, the signal wire with the largest impedance is the first signal wire in the second stage, and its impedance is twice that of the first signal wire in the first stage. If the median impedance of the first signal wire in the first stage is 30 ohms, the median impedance of the first signal wire in the second stage is 60 ohms. A lead wire impedance of 60 ohms can be realized using existing PCB board materials and fabrication processes. The magnitude of the impedance of the second signal wire in the branch structure corresponding to the second topology structure may be equal to the impedance of the first signal wire in the second stage. Therefore, the impedance of the second signal wire can also be realized using existing PCB board materials and fabrication processes. Therefore, when driving four loads, each signal wire for the topology structure of the embodiment shown in FIG. 2 can be implemented on a PCB board, reducing the requirements for the PCB board and the cost of the IP core.

[0074] In these alternative implementations, the matching of the impedance of the driver chip, the impedance of the first load and the second load, and the first signal line and the second signal line may be set to achieve a better eye diagram effect.

[0075] Taking the example of a first signal line in the first stage having an impedance of 30 ohms, the equivalent impedance of the driver chip may be selected to be close to the impedance of the first signal line in the first stage, 30 ohms, for example, 35 ohms may be selected as the equivalent impedance of the driver chip. The equivalent impedance of the first load may be close to the impedance of a single first signal line in the second stage, 60 ohms, for example, 55 ohms may be selected as the impedance of the first load. The equivalent impedance of the second load may be close to the impedance of the second signal line connected thereto, 60 ohms, for example, 55 ohms may be selected as the impedance of the second load. This achieves impedance continuity and ensures good signal integrity.

[0076] To achieve better signal integrity, the length of the second signal line may be set based on the signal integrity.

[0077] In some implementations, the length of the second signal line is determined according to the maximum signal transmission rate corresponding to the load and the period of the control signal issued by the driver chip. Referring to FIG. 3, in the eye diagram shown in FIG. UI is the period of the control signal. The eye diagram shown in Figure 3 is an integrated diagram of the waveform of the control signal and the data transmission signal corresponding to the load.

[0078] In one implementation, the ratio of the length of the second signal line to the maximum transmission rate of the data transmission signal corresponding to the load is equal to an integer multiple of half the period of the control signal. In other words, the transmission delay of the signal corresponding to the load on the second signal line is an integer multiple of half the period of the control signal. The above relationship may be expressed by the following equation (1).

[0079]

number

[0080] where L is the length of the second signal line, and V maxis the maximum data transmission rate of the signal corresponding to the load. K is a positive integer, and T UI is the periodic time length of the control signal.

[0081] By setting the length of the second signal line in this manner, the reflection position Ed of the second load in the branch structure relative to the first load corresponding to the first topology structure can be forced exactly to the rising or falling position of the eye diagram of the first load, so that the eye height in the eye diagram is not affected, and furthermore, the sampling judgment is not affected.

[0082] In addition, a low-speed section is required during the process of adjusting the synchronization between the control signal and the data transmission signal on the load. During the process of adjusting the synchronization between the control signal and the data transmission signal on the load, the transmission rate of the load is set to 1 / 4 or 3 / 4 of the maximum transmission rate of the load to ensure that the eye height of the control signal meets the appropriate requirements.

[0083] The above is merely a description of the preferred embodiments and the technical principles applied in the present disclosure. It should be understood by those skilled in the art that the scope of the present disclosure is not limited to the technical solution based on the specific combination of the above technical features, but also includes other technical solutions formed by any combination of the above technical features or features equivalent thereto without departing from the concept of the above disclosure. For example, it also includes technical solutions formed by mutually replacing the above features with technical features having similar functions disclosed in the present disclosure (but not limited to those).

[0084] Also, although operations are described in a particular order, this should not be understood as requiring that these operations be performed in the particular order shown, or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, although certain specific implementation details are included in the above description, these should not be construed as limiting the scope of the present disclosure. Certain features that are described in the context of a single embodiment can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination.

[0085] Although the present subject matter has been described in language specific to structural features and / or methodological operations, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or operations described above. Rather, the specific features and operations described above are merely example forms of implementing the claims.

Claims

1. A topology structure used in an IP core, comprising a first topology structure and a second topology structure, the first topology structure comprising a driver chip, first signal lines of a plurality of stages, and at least two first loads, a signal output terminal of one first signal line of a front stage being connected to signal input terminals of two first signal lines of a rear stage connected in parallel, a signal input terminal of the first signal line of the first stage being connected to a signal output terminal of the drive signal, and an output terminal of each first signal line of a last stage being connected to one first load; A topology structure, wherein the second topology structure includes a plurality of branch structures, each of which includes at least one second load, and the signal input end of each branch structure is connected to the signal output end of one first signal line at the last stage of the first topology structure.

2. 2. The topology structure according to claim 1, wherein in the first topology structure, an equivalent impedance of two signal lines connected in parallel in a subsequent stage is equal to an impedance of one signal line in a previous stage connected thereto.

3. 2. The topology structure of claim 1, wherein the branch structure includes at least one second signal line connected to a second load, the impedance of the second signal line being equal to the impedance of a first signal line connected to the branch structure.

4. The topology structure according to claim 1 , wherein the first topology structure includes two stages of first signal lines and two first loads.

5. The topology structure of claim 1 or 4, wherein the second topology structure includes two branch structures, each branch structure including one second load.

6. An IP core including: a substrate; a driver chip provided on the substrate; a plurality of loads; and a connection structure between the plurality of loads and the driver chip, wherein the topology structure connected between the plurality of loads and the driver chip includes a first topology structure and a second topology structure; The first topology structure includes the driver chip, first signal lines of multiple stages, and at least two first loads, a signal output terminal of one first signal line of a front stage is connected to signal input terminals of two first signal lines of a rear stage connected in parallel, a signal input terminal of the first signal line of the first stage is connected to a signal output terminal of the driving signal, and an output terminal of each first signal line of the last stage is connected to one first load; An IP core, wherein the second topology structure includes a plurality of branching structures, each of which includes at least one second load, and the signal input end of each branching structure is connected to the signal output end of one first signal line at the last stage of the first topology structure.

7. The IP core of claim 6 , wherein the second topology structure includes a second signal line, and the first signal line and the second signal line are disposed on a PCB board.

8. 8. The IP core according to claim 7, wherein in the IP core, an equivalent impedance of two first signal lines connected in parallel in a subsequent stage is equal to an impedance of one first signal line in a previous stage connected thereto.

9. 8. The IP core of claim 7, wherein in the IP core, an impedance of at least one second signal line connected to a second load included in the branch structure is equal to an impedance of a first signal line connected to the branch structure.

10. the first signal line provided on the substrate has two stages and two first loads; The IP core of claim 6 , wherein there are two branch structures, each branch structure including one second load.

11. The IP core of claim 6 , wherein the Dk value of the substrate is less than a predetermined threshold.

12. 8. The IP core according to claim 7, wherein the length of the second signal line is determined according to a maximum signal transmission rate corresponding to a load and a period of a control signal issued by the driver chip.

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