Display panel and manufacturing method thereof

Abstract

The present application provides a display panel and a manufacturing method thereof, the manufacturing method including the steps of: providing a first substrate having a plurality of Micro-LED chips spaced apart on one side; providing a second substrate having a plurality of conductive layers on one surface; forming an insulating layer on the second substrate, the insulating layer having a plurality of opening groups, each opening group including a first opening and a second opening exposing the surface of the conductive layer, the width of the first opening being greater than the width of the P-type electrode, and the width of the second opening being greater than the width of the N-type electrode; forming a first bonding layer in the first opening and a second bonding layer in the second opening; supporting the chip body with the insulating layer, bonding the P-type electrode to the first bonding layer and bonding the N-type electrode to the second bonding layer, so that the P-type electrode is embedded in the first bonding layer and the N-type electrode is embedded in the second bonding layer.

Description

[Technical Field]

[0001] This application claims priority to a Chinese patent application filed with the China Patent Office on August 29, 2022, bearing application number 202211043484.9 and entitled "Display panel and manufacturing method thereof," the entire contents of which are incorporated herein by reference.

[0002] This application relates to the field of display technology, and more particularly to display panels and methods for manufacturing the same. [Background technology]

[0003] Light-emitting diodes (LEDs) are important optoelectronic semiconductor components. Light-emitting diodes (LEDs) are widely used as light sources due to their advantages of low power consumption, small size, high brightness, easy integration with integrated circuits, and high reliability. With technological developments, micro-LEDs have found relevant applications in display, optical communications, indoor positioning, biology, and medicine. They are expected to further expand into various fields, such as wearable / implantable devices, augmented reality / virtual reality, in-vehicle displays, ultra-large displays, optical communications / optical interconnects, medical detection, smart car lighting, and spatial imaging, demonstrating significant market prospects. When using micro-LED chips in display technology, millions or even tens of millions of micro-LED chips must be precisely and efficiently transferred onto the display panel. For example, a 4K TV requires 24 million micro-LED chips (calculated as 4000 x 2000 x R / G / B three colors). To transfer 10,000 micro-LED chips at a time, 2,400 transfers are required.

[0004] However, in the conventional technology, the accuracy of the bonding position between the micro-LED chip and the substrate is low, resulting in bonding failure between the micro-LED chip and the bonding layer. Summary of the Invention [Problem to be solved by the invention]

[0005] Therefore, the technical problem to be solved by the present application is to overcome the problem of poor bonding between the Micro-LED chip and the bonding layer in the prior art, and to provide a display panel and a manufacturing method thereof. [Means for solving the problem]

[0006] The present application provides a method for manufacturing a first substrate having a plurality of Micro-LED chips spaced apart on one side thereof, the Micro-LED chips including a chip body and a P-type electrode and an N-type electrode located on a portion of a surface of the chip body; a second substrate having a plurality of conductive layers on a surface of one side thereof; and forming an insulating layer on the second substrate, the insulating layer having a plurality of opening groups, each opening group including a first opening and a second opening spaced apart from each other, the first opening and the second opening exposing a surface of the conductive layer, The present invention provides a method for manufacturing a display panel, the method including the steps of: forming a first bonding layer in the first opening and a second bonding layer in the second opening; and supporting the chip body with the insulating layer, bonding the P-type electrode to the first bonding layer and bonding the N-type electrode to the second bonding layer, so that the P-type electrode is embedded in the first bonding layer and the N-type electrode is embedded in the second bonding layer.

[0007] Optionally, the chip body includes an N-type semiconductor layer, an active layer located on a portion of one surface of the N-type semiconductor layer, and a P-type semiconductor layer located on a surface of the active layer away from the N-type semiconductor layer, the P-type electrode being located on a portion of the surface of the P-type semiconductor layer away from the active layer, and the N-type electrode being located on a portion of the surface of the N-type semiconductor layer on a side of the active layer, the P-type semiconductor layer, and the P-type electrode, and the insulating layer supports the P-type semiconductor layer around the P-type electrode during the process of bonding the P-type electrode to a first bonding layer and bonding the N-type electrode to a second bonding layer.

[0008] Optionally, the method further includes forming a first inclined surface near the boundary between the sidewall of the first opening and the top surface of the insulating layer surrounding the first opening before forming the first bonding layer in the first opening, and forming a second inclined surface near the boundary between the sidewall of the second opening and the top surface of the insulating layer surrounding the second opening before forming the second bonding layer in the second opening.

[0009] Optionally, there is a first included angle between a top surface of the insulating layer connected to the first inclined surface and the first inclined surface, and tan(180°-θ1)>μ1, where θ1 is the first included angle and μ1 is a coefficient of friction of the first inclined surface.

[0010] Optionally, there is a second included angle between the top surface of the insulating layer connected to the second inclined surface and the second inclined surface, and tan(180°-θ2)>μ2, where θ2 is the second included angle and μ2 is the coefficient of friction of the second inclined surface.

[0011] Optionally, before bonding the P-type electrode to the first bonding layer and the N-type electrode to the second bonding layer, the method further includes forming a barrier layer on the insulating layer around the opening group, wherein the barrier layer has a third opening, and the width of the third opening is greater than the width of the Micro-LED chip.

[0012] Optionally, the width of the third opening is less than or equal to 1.5 times the width of the Micro-LED chip.

[0013] Optionally, the barrier layer is a light-blocking barrier layer.

[0014] Optionally, the material of the light-shielding barrier layer is a light-shielding resin.

[0015] Optionally, after bonding the P-type electrode to the first bonding layer and the N-type electrode to the second bonding layer, the height of the top surface of the barrier layer away from the second substrate is greater than the height of the top surface of the Micro-LED chip away from the second substrate.

[0016] Optionally, in the process of bonding the P-type electrode to the first bonding layer and the N-type electrode to the second bonding layer, a binding device employed has a specific alignment accuracy, and the width of the first opening is greater than or equal to the sum of the width of the P-type electrode and twice the specific alignment accuracy, and the width of the second opening is greater than or equal to the sum of the width of the N-type electrode and twice the specific alignment accuracy.

[0017] Optionally, in the step of forming a first bonding layer in the first opening and a second bonding layer in the second opening, the thickness of the first bonding layer is greater than or equal to 80% of the depth of the first opening and less than or equal to the depth of the first opening, and the thickness of the second bonding layer is greater than or equal to 80% of the depth of the second opening and less than or equal to the depth of the second opening.

[0018] Optionally, the thickness of the insulating layer is no more than 50% of the difference in thickness between the N-type electrode and the P-type electrode.

[0019] Optionally, the insulating layer has a thickness of 500 nm to 1000 nm.

[0020] Optionally, the material of said first bonding layer and said second bonding layer is solder, and the material of said first bonding layer and said second bonding layer is a conductive adhesive.

[0021] The present application further provides a display panel including: a first substrate having a plurality of Micro-LED chips spaced apart on one side thereof, the Micro-LED chips including a chip body and a P-type electrode and an N-type electrode located on a portion of a surface of the chip body; a second substrate having a plurality of conductive layers on a surface of one side thereof; an insulating layer located on one side of the second substrate, the insulating layer having a plurality of opening groups in the insulating layer, each opening group including a first opening and a second opening spaced apart, the first openings and the second openings being located in the conductive layer, respectively, the width of the first openings being greater than the width of the P-type electrode, and the width of the second openings being greater than the width of the N-type electrode; a first bonding layer located in the first openings and a second bonding layer located in the second opening, the P-type electrode being embedded in the first bonding layer and the N-type electrode being embedded in the second bonding layer, and the chip body contacting a top surface of a portion of the insulating layer.

[0022] Optionally, the chip body includes an N-type semiconductor layer, an active layer located on a portion of one surface of the N-type semiconductor layer, and a P-type semiconductor layer located on a surface of the active layer away from the N-type semiconductor layer, the P-type electrode located on a portion of the surface of the P-type semiconductor layer away from the active layer, the N-type electrode located on a portion of the surface of the N-type semiconductor layer on a side of the active layer, the P-type semiconductor layer, and the P-type electrode, and the P-type semiconductor layer around the P-type electrode contacts a top surface of the insulating layer around the first opening.

[0023] Optionally, there is a first sloping surface between a sidewall of the first opening and a top surface of the insulating layer around the first opening, and there is a second sloping surface between a sidewall of the second opening and a top surface of the insulating layer around the second opening.

[0024] Optionally, there is a first included angle between a top surface of the insulating layer connected to the first inclined surface and the first inclined surface, and tan(180°-θ1)>μ1, where θ1 is the first included angle and μ1 is a coefficient of friction of the first inclined surface.

[0025] Optionally, there is a second included angle between the top surface of the insulating layer connected to the second inclined surface and the second inclined surface, and tan(180°-θ2)>μ2, where θ2 is the second included angle and μ2 is the coefficient of friction of the second inclined surface.

[0026] Optionally, the device further includes a barrier layer located on the insulating layer around the openings, wherein the barrier layer has a third opening, the width of the third opening being greater than the width of the Micro-LED chip.

[0027] Optionally, the width of the third opening is less than or equal to 1.5 times the width of the Micro-LED chip.

[0028] Optionally, the barrier layer is a light-blocking barrier layer.

[0029] Optionally, the material of the light-shielding barrier layer is a light-shielding resin.

[0030] Optionally, after bonding the P-type electrode to the first bonding layer and the N-type electrode to the second bonding layer, the height of the top surface of the barrier layer facing away from the second substrate is greater than the height of the top surface of the Micro-LED chip facing away from the second substrate.

[0031] Optionally, the width of the first opening is greater than or equal to the sum of the width of the P-type electrode and twice a specific alignment accuracy, and the width of the second opening is greater than or equal to the sum of the width of the N-type electrode and twice a specific alignment accuracy, and the specific alignment accuracy is between 0.5 μm and 2 μm.

[0032] Optionally, the thickness of the first bonding layer is greater than or equal to 80% of the depth of the first opening and less than or equal to the depth of the first opening, and the thickness of the second bonding layer is greater than or equal to 80% of the depth of the second opening and less than or equal to the depth of the second opening.

[0033] Optionally, the thickness of the insulating layer is no more than 50% of the difference in thickness between the N-type electrode and the P-type electrode.

[0034] Optionally, the insulating layer has a thickness of 500 nm to 1000 nm.

[0035] Optionally, the material of said first bonding layer and said second bonding layer is solder, and the material of said first bonding layer and said second bonding layer is a conductive adhesive. [Effects of the Invention]

[0036] The technical solution of the present application has the following beneficial effects:

[0037] The display panel manufacturing method according to the present technical solution includes supporting the chip body with the insulating layer, bonding the P-type electrode to the first bonding layer, and bonding the N-type electrode to the second bonding layer, such that the P-type electrode is embedded in the first bonding layer and the N-type electrode is embedded in the second bonding layer. The P-type electrode enters the first opening, the N-type electrode enters the second opening, and the insulating layer supports the chip body around the P-type electrode, enhancing self-alignment and limiting the lateral offset of the micro-LED chip to the sidewalls of the first opening and the second opening, ensuring bonding stability. The material of the first bonding layer can be confined within the first opening, and the material of the second bonding layer can be confined within the second opening, reducing the lateral offset of the materials of the first and second bonding layers during bonding and avoiding short-circuiting between the first and second bonding layers. As a result, bonding failure between the Micro-LED chip and the first and second bonding layers is avoided.

[0038] In order to more clearly describe the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly describe the drawings used to describe the specific embodiments or the prior art. Obviously, the drawings described below are some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative efforts. [Brief explanation of the drawings]

[0039] [Figure 1] FIG. 1 is a schematic diagram of the manufacturing process of a display panel. [Figure 2] FIG. 2 is a schematic diagram of the manufacturing process of a display panel. [Figure 3] FIG. 3 is a schematic diagram of a manufacturing process for another display panel. [Figure 4] FIG. 4 is a schematic diagram of a manufacturing process for another display panel. [Figure 5] FIG. 5 is a schematic diagram of a manufacturing process for a display panel according to an embodiment of the present application. [Figure 6] FIG. 6 is a schematic diagram of a manufacturing process for a display panel according to an embodiment of the present application. [Figure 7] FIG. 7 is a schematic diagram of a manufacturing process for a display panel according to an embodiment of the present application. [Figure 8] FIG. 8 is a schematic diagram of a manufacturing process for a display panel according to an embodiment of the present application. [Figure 9] FIG. 9 is a schematic diagram of a manufacturing process for a display panel according to an embodiment of the present application. [Figure 10] FIG. 10 is a schematic diagram of a manufacturing process for a display panel according to an embodiment of the present application. [Figure 11] FIG. 11 is a schematic diagram of a manufacturing process for a display panel according to another embodiment of the present application. [Figure 12] FIG. 12 is a schematic diagram of a manufacturing process for a display panel according to another embodiment of the present application. [Figure 13] FIG. 13 is a schematic diagram of a manufacturing process for a display panel according to another embodiment of the present application. [Figure 14] FIG. 14 is a schematic diagram of a manufacturing process for a display panel according to another embodiment of the present application. [Figure 15] FIG. 15 is a schematic diagram of a manufacturing process for a display panel according to another embodiment of the present application. [Figure 16] FIG. 16 is a schematic diagram of a manufacturing process for a display panel according to another embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0040] As described in the background art, the prior art has a problem in that the bonding position between the micro-LED chip and the substrate is not accurate, resulting in bonding failure.

[0041] A method for manufacturing a display panel includes, as shown in FIG. 1, providing a first substrate 101 having conductive posts 102, wherein solder 103 is attached to a surface of the conductive posts 102 facing away from the first substrate 101; providing a second substrate 105 having a plurality of Micro-LED chips 104 spaced apart on one surface; placing the second substrate 105 and the first substrate 101 opposite each other so that the electrodes of the Micro-LED chips 104 face the solder 103; and as shown in FIG. 2, welding the electrodes of the Micro-LED chips 104 to the solder 103.

[0042] However, during the process of welding the electrodes of the Micro-LED chip 104 and the solder 103 together, a certain amount of misalignment may occur between the electrodes of the Micro-LED chip 104 and the solder 103, resulting in cold solder connections and even short circuits. Research has revealed that the reasons for this are as follows: 1. The process of aligning the electrodes of the Micro-LED chip 104 and the solder 103 is limited by the alignment accuracy of the alignment device. 2. The electrodes of the Micro-LED chip 104 and the solder 103 are welded by reflow soldering, and during the reflow soldering process, the solder 103 melts, causing an offset in the position of the electrodes of the Micro-LED chip 104 relative to the solder 103. 3. The eutectic vacuum furnace used to weld the electrodes of the Micro-LED chip 104 and the solder 103 together does not have a pressure system, so it is not possible to ensure that the relative positions of the Micro-LED chip 104 and the solder 103 do not change.

[0043] Another method for manufacturing a display panel includes, referring to FIG. 3, a step of providing a first substrate 101a having a plurality of electrodes (not shown) on a surface thereof, where conductive colloids 102a are formed on the surface of the electrodes and conductive particles 106 are formed inside the conductive colloids 102a; referring to FIG. 3, a step of providing a second substrate 105 having a plurality of Micro-LED chips 104 spaced apart on a surface of one side of the second substrate 105, where the Micro-LED chips 104 include a P-type electrode and an N-type electrode; and referring to FIG. 4, a step of placing the second substrate 105 and the first substrate 101a opposite each other, and integrally bonding the P-type electrode of the Micro-LED chip 104 to a portion of the conductive colloids 102a and integrally bonding the N-type electrode of the Micro-LED chip 104 to a portion of the conductive colloids 102a.

[0044] However, in the process of integrally bonding the N-type electrode of the Micro-LED chip 104 and a portion of the conductive colloid 102a, if the pitch between the N-type electrode and the P-type electrode is small, it is easy to cause a short circuit between the N-type electrode and the P-type electrode.

[0045] In the above method, there is a high risk of bonding failure occurring between the electrode of the Micro-LED chip 104 and the bonding layer (solder 103 or conductive colloid 102a).

[0046] The present application provides a display panel and a manufacturing method thereof that can avoid bonding failure between a Micro-LED chip and a bonding layer.

[0047] The technical solutions of the present application will be described clearly and completely below with reference to the drawings. It is obvious that the described embodiments are only some of the embodiments of the present application, but not all of the embodiments. Based on the embodiments of the present application, any other embodiments obtained by those skilled in the art without any creative efforts fall within the scope of protection of the present application.

[0048] It should be understood that in the description of this application, orientations or positional relationships indicated by terms such as "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" are orientations or positional relationships based on the illustrations and are used merely to facilitate or simplify the description of this application, and do not indicate or imply that such devices or elements have a particular orientation or are configured and operated in a particular orientation, and are not intended to limit the present application. Furthermore, it should be understood that the terms "first," "second," and "third" are used merely for descriptive purposes and do not indicate or imply relative importance.

[0049] In the description of this application, unless otherwise clearly specified and limited, the terms "attached," "coupled," and "connected" should be understood in a broad sense, and may refer to, for example, a fixed connection, a detachable connection, or an integral connection, a mechanical connection, or an electrical connection, a direct connection, an indirect connection via an intermediate medium, or internal communication between two elements. Those skilled in the art can understand the specific meanings of the above terms in this application according to specific circumstances.

[0050] Furthermore, the technical features according to the various embodiments of the present application described below can be combined with each other unless they are inconsistent.

[0051] Example 1 One embodiment of the present application is Step S1 of providing a first substrate having a plurality of micro-LED chips spaced apart from one another on one side thereof, the micro-LED chips including a chip body and a P-type electrode and an N-type electrode located on a portion of a surface of the chip body on one side thereof; Step S2 of providing a second substrate having a plurality of conductive layers on one surface thereof; a step S3 of forming an insulating layer on the second substrate, the insulating layer having a plurality of opening groups, each of which includes a first opening and a second opening spaced apart from each other, the first openings and the second openings exposing a surface of the conductive layer, respectively, the width of the first openings being larger than the width of the P-type electrode, and the width of the second openings being larger than the width of the N-type electrode; Step S4: forming a first bonding layer in the first opening and a second bonding layer in the second opening; and step S5 of supporting the chip body with the insulating layer, bonding the P-type electrode to the first bonding layer, and bonding the N-type electrode to the second bonding layer, so that the P-type electrode is embedded in the first bonding layer and the N-type electrode is embedded in the second bonding layer.

[0052] In this embodiment, the P-type electrode is placed in the first opening and the N-type electrode is placed in the second opening. The insulating layer supports the chip body around the P-type electrode, enhancing self-alignment. The lateral offset of the micro-LED chip is limited by the sidewalls of the first opening and the second opening, ensuring bonding stability. The material of the first bonding layer can be confined within the first opening, and the material of the second bonding layer can be confined within the second opening, reducing the lateral offset between the first and second bonding layer materials during bonding and preventing short-circuiting between the first and second bonding layers. This avoids bonding failures between the micro-LED chip and the first and second bonding layers.

[0053] Hereinafter, a detailed description will be given with reference to FIGS.

[0054] Referring to FIG. 5, a first substrate 300 is provided having a plurality of micro-LED chips spaced apart on one side thereof, and the micro-LED chips include a chip body and a P-type electrode 304 and an N-type electrode 305 located on a portion of the surface of one side of the chip body.

[0055] The chip body includes an N-type semiconductor layer 301, an active layer 302 located on a portion of one surface of the N-type semiconductor layer 301, and a P-type semiconductor layer 303 located on the surface of the active layer 302 away from the N-type semiconductor layer 301, the P-type electrode 304 located on a portion of the surface of the P-type semiconductor layer 303 away from the active layer 302, and the N-type electrode 305 located on a portion of one surface of the N-type semiconductor layer 301 on the side of the active layer 302, the P-type semiconductor layer 303, and the P-type electrode 304.

[0056] In this embodiment, the P-type electrode 304 is located on a portion of the surface of the P-type semiconductor layer 303 away from the active layer 302, i.e., a portion of the surface of the P-type semiconductor layer 303 is not covered by the P-type electrode 304.

[0057] In one embodiment, the difference between the total area of ​​the surface of the P-type semiconductor layer 303 away from the active layer 302 and the projected area of ​​the P-type electrode 304 on the surface of the P-type semiconductor layer 303 is 50 μm 2 ~200μm 2 , e.g., 50 μm 2 , 80 μm 2 , 100 μm 2 , 120 μm 2 , 150 μm 2 , 180 μm 2 or 200 μm 2 is.

[0058] In one embodiment, the pitch between the N-type electrode 305 and the P-type electrode 304 in the Micro-LED chip is 5 μm to 6 μm.

[0059] Referring to FIG. 6, a second substrate 201 is provided having a plurality of conductive layers 206 on one surface thereof.

[0060] The second substrate 201 is a driving substrate, and includes a substrate body and a driving circuit located on one surface of the substrate body. A conductive layer is located on the surface of the driving circuit away from the substrate body, and the conductive layer 206 is electrically connected to the driving circuit.

[0061] The conductive layer 206 is a contact electrode, and is formed by film deposition, photoetching, and etching. The material of the conductive layer 206 includes a metal or an alloy, and the metal is, for example, Al, Ti, or Mo.

[0062] Referring to FIG. 7, an insulating layer 207 is formed on the second substrate 201, and the insulating layer 207 has a plurality of opening groups, each of which includes a first opening 2071 and a second opening 2072 spaced apart from each other, and the first opening 2071 and the second opening 2072 expose the surface of the conductive layer 206, respectively, and the width of the first opening 2071 is greater than the width of the P-type electrode 304, and the width of the second opening 2072 is greater than the width of the N-type electrode 305.

[0063] The step of forming the insulating layer 207 includes the steps of forming an initial insulating layer (not shown) on the second substrate 201 to cover the conductive layer 206, patterning the initial insulating layer, and forming the insulating layer 207.

[0064] In one embodiment, the thickness of the insulating layer 207 is 50% or less of the difference in thickness between the N-type electrode 305 and the P-type electrode 304. The thickness of the insulating layer 207 is a dimension in a direction perpendicular to the surface of the second substrate 201, and the thicknesses of the N-type electrode 305 and the P-type electrode 304 are both dimensions in a direction perpendicular to the surface of the first substrate. This configuration has the following advantages: the thickness of the insulating layer 207 is thin, saving costs, and ensuring better contact between the P-type electrode 304 and the material of a later first bonding layer, and between the N-type electrode 305 and the material of a later second bonding layer.

[0065] In one specific embodiment, the thickness of the insulating layer 207 is 500 nm to 1000 nm.

[0066] The material of the insulating layer 207 includes SiO2 or Si3N4.

[0067] The width of the conductive layer 206 at the bottom of the first opening 2071 is equal to or greater than the width of the first opening 2071, and the width of the conductive layer 206 at the bottom of the second opening 2072 is equal to or greater than the width of the second opening 2072. The width of the conductive layer 206 at the bottom of the first opening 2071 is equal to or greater than the sum of the width of the P-type electrode 304 and twice the specific alignment accuracy, and the width of the conductive layer 206 at the bottom of the second opening 2072 is equal to or greater than the sum of the width of the N-type electrode 305 and twice the specific alignment accuracy. The specific alignment accuracy refers to the alignment accuracy of a binding device used in a later process of bonding the P-type electrode 304 to the first bonding layer 2081 and the N-type electrode 305 to the second bonding layer 2082.

[0068] Referring to FIG. 8, a first bonding layer 2081 is formed in the first opening 2071, and a second bonding layer 2082 is formed in the second opening 2072.

[0069] In one embodiment, the material of the first bonding layer 2081 and the second bonding layer 2082 is solder, and the solder includes In solder or tin-containing lead-free solder.

[0070] In another embodiment, the material of the first bonding layer 2081 and the second bonding layer 2082 is a conductive adhesive, and the conductive adhesive is an anisotropic conductive adhesive.

[0071] The melting point of the first bonding layer 2081 is lower than that of the conductive layer 206 and lower than that of the insulating layer 207. The melting point of the second bonding layer 2082 is lower than that of the conductive layer 206 and lower than that of the insulating layer 207.

[0072] In the steps of forming the first bonding layer 2081 in the first opening 2071 and the second bonding layer 2082 in the second opening 2072, the thickness of the first bonding layer 2081 is 80% or more of the depth of the first opening 2071 but not more than the depth of the first opening 2071, and the thickness of the second bonding layer 2082 is 80% or more of the depth of the second opening 2072 but not more than the depth of the second opening 2072. In this way, in the subsequent bonding process, the material of the first bonding layer 2081 can surround the P-type electrode, and the material of the second bonding layer 2082 can surround the N-type electrode, and the materials of the first bonding layer 2081 and the second bonding layer 2082 can be prevented from overflowing and causing a short circuit.

[0073] In one specific embodiment, the thickness of the first bonding layer 2081 is 400 nm to 800 nm, and the thickness of the second bonding layer 2082 is 400 nm to 800 nm.

[0074] Referring to FIG. 9, the insulating layer 207 supports the chip body, and the P-type electrode 304 is bonded to the first bonding layer 2081, and the N-type electrode 305 is bonded to the second bonding layer 2082, so that the P-type electrode 304 is embedded in the first bonding layer 2081 and the N-type electrode 305 is embedded in the second bonding layer 2082.

[0075] During the bonding of the P-type electrode 304 to the first bonding layer 2081 and the bonding of the N-type electrode 305 to the second bonding layer 2082, the insulating layer 207 supports the P-type semiconductor layer 303 around the P-type electrode 304.

[0076] In the process of bonding the P-type electrode 304 to the first bonding layer 2081 and the N-type electrode 305 to the second bonding layer 2082, the binding device employed has a specific alignment accuracy, and the width of the first opening 2071 is equal to or greater than the sum of the width of the P-type electrode 304 and twice the specific alignment accuracy, and the width of the second opening 2072 is equal to or greater than the sum of the width of the N-type electrode 305 and twice the specific alignment accuracy. In one embodiment, the specific alignment accuracy is 0.5 μm to 2 μm.

[0077] When the material of the first bonding layer 2081 and the second bonding layer 2082 is solder, reflow soldering is adopted to bond the P-type electrode 304 to the first bonding layer 2081, and to bond the N-type electrode 305 to the second bonding layer 2082.

[0078] If the material of the first bonding layer 2081 and the second bonding layer 2082 is a conductive adhesive, the P-type electrode 304 and the first bonding layer 2081 are extruded to interconnect the P-type electrode 304 and the conductive particles in the first bonding layer 2081, and the N-type electrode 305 and the second bonding layer 2082 are extruded to interconnect the N-type electrode 305 and the conductive particles in the second bonding layer 2082.

[0079] The first opening 2071 accommodates the P-type electrode 304, the second opening 2072 accommodates the N-type electrode 305, and the insulating layer 207 supports the P-type semiconductor layer 303 around the P-type electrode 304. In this way, not only is the self-alignment function improved, but the flatness of the top surfaces of all the Micro-LED chips facing away from the second substrate is also ensured to a certain extent, the uniformity of the light-emitting angles of the Micro-LED chips is improved, and the effective light-emitting area of ​​the Micro-LED chips is increased.

[0080] Referring to FIG. 10, the Micro-LED chip and the first substrate 300 are peeled off.

[0081] In one specific embodiment, the first substrate 300 and the Micro-LED chip are peeled off by ultraviolet irradiation.

[0082] Example 2 Referring to Figure 11, Figure 11 is a schematic diagram based on Figure 7, in which a first inclined surface A1 is formed near the boundary between the sidewall of the first opening 2071 and the top surface of the insulating layer 207 around the first opening 2071, and a second inclined surface A2 is formed near the boundary between the sidewall of the second opening 2072 and the top surface of the insulating layer 207 around the second opening 2072.

[0083] In one embodiment, there is a first included angle between the top surface of the insulating layer 207 connected to the first inclined surface A1 and the first inclined surface A1, and tan(180°-θ1)>μ1, where θ1 is the first included angle and μ1 is the coefficient of friction of the first inclined surface.

[0084] In one embodiment, there is a second included angle between the top surface of the insulating layer 207 connected to the second inclined surface A2 and the second inclined surface A2, and tan(180°-θ2)>μ2, where θ2 is the second included angle and μ2 is the coefficient of friction of the second inclined surface.

[0085] The advantage of setting the first and second included angles is that it ensures that the P-type electrode 304 of the Micro-LED chip can automatically enter the first opening and the N-type electrode 305 of the Micro-LED chip can automatically enter the second opening, thereby reducing yield loss to a certain extent.

[0086] Referring to FIG. 12, after the first inclined surface A1 is formed, the first bonding layer 2081a is formed in the first opening 2071, and after the second inclined surface A2 is formed, the second bonding layer 2082a is formed in the second opening 2072.

[0087] Referring to FIG. 13, the insulating layer 207 supports the chip body, and the P-type electrode 304 is bonded to the first bonding layer 2081a, and the N-type electrode 305 is bonded to the second bonding layer 2082a, such that the P-type electrode 304 is embedded in the first bonding layer 2081a and the N-type electrode 305 is embedded in the second bonding layer 2082a. Then, the Micro-LED chip and the first substrate 300 are peeled off.

[0088] Example 3 Referring to FIG. 14, FIG. 14 is a schematic diagram based on FIG. 7, in which a barrier layer 211 is formed on the insulating layer 207 around the opening group, and a third opening is formed in the barrier layer 211, and the width of the third opening is greater than the width of the Micro-LED chip.

[0089] In one embodiment, the material of the barrier layer 211 is a light-blocking resin, which is a resin with a light-blocking effect, but the material of the barrier layer 211 is not limited to this material, and the width of the third opening needs to be slightly larger than the width of the Micro-LED chip so that the Micro-LED chip can fall smoothly into the third opening. One third opening corresponds to one Micro-LED chip.

[0090] The function of the barrier layer 211 includes restricting the position of the Micro-LED chip and causing one Micro-LED chip to fall into one third opening.

[0091] In one embodiment, the barrier layer 211 is a light-blocking barrier layer, which is used to prevent crosstalk between lights emitted by adjacent Micro-LED chips. The material of the light-blocking barrier layer may be, for example, a light-blocking resin.

[0092] The barrier layer 211 may further be made of a non-light-blocking material.

[0093] In one embodiment, the width of the third opening is greater than the width of the Micro-LED chip and is not greater than 1.5 times the width of the Micro-LED chip.

[0094] In one embodiment, the barrier layer 211 is a light-blocking barrier layer, and after bonding the P-type electrode to the first bonding layer and the N-type electrode to the second bonding layer, the height of the top surface of the barrier layer 211 away from the second substrate is greater than the height of the top surface of the Micro-LED chip away from the second substrate, which has the advantage of better preventing crosstalk between lights emitted by adjacent Micro-LED chips.

[0095] It should be noted that in another embodiment, after bonding the P-type electrode to the first bonding layer and the N-type electrode to the second bonding layer, the height of the top surface of the barrier layer 211 facing away from the second substrate is equal to or less than the height of the top surface of the Micro-LED chip facing away from the second substrate.

[0096] This embodiment further includes the steps of forming a first inclined surface near the boundary between the sidewall of the first opening 2071 and the top surface of the insulating layer 207 surrounding the first opening 2071, and forming a second inclined surface near the boundary between the sidewall of the second opening 2072 and the top surface of the insulating layer 207 surrounding the second opening 2072. After forming the first and second inclined surfaces, the barrier layer 211 is formed. The first and second inclined surfaces may be described in the above embodiments, and will not be described in detail here.

[0097] It should be noted that in other embodiments, when the barrier layer 211 is formed, the first and second inclined surfaces may not be provided.

[0098] Referring to FIG. 15, a first bonding layer 2081b is formed in the first opening 2071, and a second bonding layer 2082b is formed in the second opening 2072.

[0099] In this embodiment, the first bonding layer 2081b and the second bonding layer 2082b are formed after the barrier layer 211 is formed. In other embodiments, the barrier layer 211 may be formed after the first bonding layer 2081b and the second bonding layer 2082b are formed.

[0100] Referring to FIG. 16, the insulating layer 207 supports the chip body, and the P-type electrode 304 is bonded to the first bonding layer 2081b, and the N-type electrode 305 is bonded to the second bonding layer 2082b, so that the P-type electrode 304 is embedded in the first bonding layer 2081b and the N-type electrode 305 is embedded in the second bonding layer 2082b.

[0101] Example 4 In this embodiment, referring to FIG. A plurality of spaced apart micro-LED chips each including a chip body and a P-type electrode 304 and an N-type electrode 305 located on a portion of one surface of the chip body; a second substrate 201 having a plurality of conductive layers 206 on one surface thereof; an insulating layer 207 located on one side of the second substrate 201, the insulating layer 207 having a plurality of opening groups, each opening group including a first opening and a second opening spaced apart, the first opening and the second opening being located in the conductive layer 206, respectively, the width of the first opening being greater than the width of the P-type electrode 304, and the width of the second opening being greater than the width of the N-type electrode 305; a first bonding layer located in the first opening; a second bonding layer located in the second opening; The P-type electrode 304 is embedded in the first bonding layer, the N-type electrode 305 is embedded in the second bonding layer, and the chip body contacts the top surface of a part of the insulating layer 207, thereby providing a display panel.

[0102] The chip body includes an N-type semiconductor layer 301, an active layer 302 located on a portion of one surface of the N-type semiconductor layer 301, and a P-type semiconductor layer 303 located on a surface of the active layer 302 facing away from the N-type semiconductor layer 301, the P-type electrode 304 located on a portion of the surface of the P-type semiconductor layer 303 facing away from the active layer 302, and the N-type electrode 305 located on a portion of one surface of the N-type semiconductor layer 301 on a side of the active layer 302, the P-type semiconductor layer 303, and the P-type electrode 304. The P-type semiconductor layer 303 around the P-type electrode 304 contacts the top surface of the insulating layer 207 around the first opening.

[0103] In one embodiment, the width of the first opening is greater than or equal to the sum of the width of the P-type electrode 304 and twice the specific alignment accuracy, and the width of the second opening is greater than or equal to the sum of the width of the N-type electrode 305 and twice the specific alignment accuracy, and the specific alignment accuracy is 0.5 μm to 2 μm.

[0104] In one embodiment, the thickness of the first bonding layer is greater than or equal to 80% of the depth of the first opening and less than or equal to the depth of the first opening, and the thickness of the second bonding layer is greater than or equal to 80% of the depth of the second opening and less than or equal to the depth of the second opening.

[0105] In one embodiment, the thickness of the insulating layer 207 is less than or equal to 50% of the difference in thickness between the N-type electrode and the P-type electrode.

[0106] In one embodiment, the thickness of the insulating layer 207 is between 500 nm and 1000 nm.

[0107] The material of the first bonding layer and the second bonding layer is solder, and the material of the first bonding layer and the second bonding layer is a conductive adhesive.

[0108] Example 5 The difference between this embodiment and embodiment 4, as shown in FIG. 13, is that there is a first inclined surface A1 (see FIG. 12) between the sidewall of the first opening and the top surface of the insulating layer 207 around the first opening, and there is a second inclined surface A2 (see FIG. 12) between the sidewall of the second opening and the top surface of the insulating layer 207 around the second opening.

[0109] In one embodiment, there is a first included angle between the top surface of the insulating layer connected to the first inclined surface and the first inclined surface, and tan(180°-θ1)>μ1, where θ1 is the first included angle and μ1 is the coefficient of friction of the first inclined surface.

[0110] In one embodiment, there is a second included angle between the top surface of the insulating layer connected to the second inclined surface and the second inclined surface, and tan(180°-θ2)>μ2, where θ2 is the second included angle and μ2 is the coefficient of friction of the second inclined surface.

[0111] Example 6 The difference between this embodiment and Example 5, as shown in FIG. 16, is that the display panel further includes a barrier layer 211 located on the insulating layer 207 around the opening group, and the barrier layer 211 has a third opening, and the width of the third opening is greater than the width of the Micro-LED chip.

[0112] In one embodiment, the width of the third opening is less than or equal to 1.5 times the width of the Micro-LED chip.

[0113] In one embodiment, the barrier layer 211 is a light-shielding barrier layer. The material of the light-shielding barrier layer is a light-shielding resin. In another embodiment, the material of the barrier layer 211 may also be a non-light-shielding material.

[0114] In one embodiment, the barrier layer 211 is a light-blocking barrier layer, and the height of the top surface of the barrier layer facing away from the second substrate is greater than the height of the top surface of the Micro-LED chip facing away from the second substrate.

[0115] In another embodiment, the height of the top surface of the barrier layer facing away from the second substrate is equal to or less than the height of the top surface of the Micro-LED chip facing away from the second substrate.

[0116] The same contents of this embodiment as those of the fifth embodiment will not be described in detail here.

[0117] Example 7 The difference between this embodiment and the fourth embodiment is that the display panel further includes a barrier layer disposed on the insulating layer surrounding the openings, and the barrier layer includes a third opening, the width of which is greater than the width of the Micro-LED chip. In one embodiment, the width of the third opening is 1.5 times or less than the width of the Micro-LED chip.

[0118] In one embodiment, the barrier layer 211 is a light-shielding barrier layer. The material of the light-shielding barrier layer is a light-shielding resin. In another embodiment, the material of the barrier layer 211 may also be a non-light-shielding material.

[0119] In one embodiment, the barrier layer 211 is a light-blocking barrier layer, and the height of the top surface of the barrier layer facing away from the second substrate is greater than the height of the top surface of the Micro-LED chip facing away from the second substrate. In another embodiment, the height of the top surface of the barrier layer facing away from the second substrate is equal to or less than the height of the top surface of the Micro-LED chip facing away from the second substrate.

[0120] The details of this embodiment that are similar to those of the fourth embodiment will not be described in detail here.

[0121] It is apparent that the above examples are merely illustrative and do not limit the embodiments. Those skilled in the art may make various changes and modifications based on the above description. It is not necessary and cannot cover all embodiments here. Any obvious changes and modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. A method for manufacturing a display panel, comprising: providing a first substrate having a plurality of Micro-LED chips spaced apart from one another on one side thereof, each Micro-LED chip including a chip body and a P-type electrode and an N-type electrode located on a portion of a surface of the chip body; providing a second substrate having a plurality of conductive layers on one surface thereof; forming an insulating layer on the second substrate, the insulating layer having a plurality of opening groups, each opening group including a first opening and a second opening spaced apart from each other, the first openings and the second openings exposing a surface of the conductive layer, respectively, the width of the first openings being greater than the width of the P-type electrode, and the width of the second openings being greater than the width of the N-type electrode; forming a first bonding layer in the first opening and a second bonding layer in the second opening; supporting the chip body with the insulating layer, bonding the P-type electrode to the first bonding layer, and bonding the N-type electrode to the second bonding layer, so that the P-type electrode is embedded in the first bonding layer and the N-type electrode is embedded in the second bonding layer.

2. the chip body includes an N-type semiconductor layer, an active layer located on a portion of one surface of the N-type semiconductor layer, and a P-type semiconductor layer located on a surface of the active layer away from the N-type semiconductor layer, the P-type electrode is located on a portion of a surface of the P-type semiconductor layer away from the active layer, and the N-type electrode is located on a portion of a surface of one side of the N-type semiconductor layer at a side of the active layer, the P-type semiconductor layer, and the P-type electrode; 2. The method for manufacturing a display panel according to claim 1, wherein the insulating layer supports the P-type semiconductor layer around the P-type electrode during the process of bonding the P-type electrode to the first bonding layer and the process of bonding the N-type electrode to the second bonding layer.

3. 2. The method for manufacturing a display panel according to claim 1, further comprising the steps of: forming a first inclined surface near a boundary between a sidewall of the first opening and a top surface of the insulating layer surrounding the first opening before forming a first bonding layer in the first opening; and forming a second inclined surface near a boundary between a sidewall of the second opening and a top surface of the insulating layer surrounding the second opening before forming a second bonding layer in the second opening.

4. There is a first included angle between the top surface of the insulating layer connected to the first inclined surface and the first inclined surface, and tan(180°-θ １ ) > μ １ and θ １ is the first included angle, and μ １ 4. The method for manufacturing a display panel according to claim 3, wherein the coefficient of friction of the first inclined surface is:

5. There is a second included angle between the top surface of the insulating layer connected to the second inclined surface and the second inclined surface, and tan(180°-θ ２ ) > μ ２ and θ ２ is the second included angle, and μ ２ 4. The method for manufacturing a display panel according to claim 3, wherein the coefficient of friction of the second inclined surface is:

6. 6. The method for manufacturing a display panel according to claim 1, further comprising the steps of: forming a barrier layer on the insulating layer around the opening group before bonding the P-type electrode to the first bonding layer and the N-type electrode to the second bonding layer; and forming a third opening in the barrier layer, the width of the third opening being larger than the width of the Micro-LED chip.

7. 7. The method for manufacturing a display panel according to claim 6, wherein the width of the third opening is 1.5 times or less the width of the Micro-LED chip.

8. 7. The method for manufacturing a display panel according to claim 6, wherein the barrier layer is a light-shielding barrier layer.

9. 9. The method for manufacturing a display panel according to claim 8, wherein the material of the light-shielding barrier layer is a light-shielding resin.

10. 7. The method of claim 6, further comprising the step of: bonding the P-type electrode to the first bonding layer and the N-type electrode to the second bonding layer, and then bonding the barrier layer such that the height of the top surface of the barrier layer facing away from the second substrate is greater than the height of the top surface of the Micro-LED chip facing away from the second substrate.

11. In the process of bonding the P-type electrode to the first bonding layer and the N-type electrode to the second bonding layer, a binding device is used that has a specific alignment accuracy; 2. The method for manufacturing a display panel according to claim 1, wherein the width of the first opening is equal to or greater than the sum of the width of the P-type electrode and twice the specific alignment accuracy, and the width of the second opening is equal to or greater than the sum of the width of the N-type electrode and twice the specific alignment accuracy.

12. 2. The display panel manufacturing method of claim 1, wherein in the step of forming a first bonding layer in the first opening and a second bonding layer in the second opening, the thickness of the first bonding layer is 80% or more of the depth of the first opening and less than the depth of the first opening, and the thickness of the second bonding layer is 80% or more of the depth of the second opening and less than the depth of the second opening.

13. 2. The method for manufacturing a display panel according to claim 1, wherein the thickness of the insulating layer is 50% or less of the difference in thickness between the N-type electrode and the P-type electrode.

14. 14. The method for manufacturing a display panel according to claim 13, wherein the insulating layer has a thickness of 500 nm to 1000 nm.

15. 2. The method for manufacturing a display panel according to claim 1, wherein the material of the first bonding layer and the second bonding layer is solder, and the material of the first bonding layer and the second bonding layer is a conductive adhesive.

16. A display panel, a first substrate having a plurality of Micro-LED chips spaced apart from one another on one side thereof, each Micro-LED chip including a chip body and a P-type electrode and an N-type electrode located on a portion of a surface of one side of the chip body; a second substrate having a plurality of conductive layers on one surface thereof; an insulating layer located on one side of the second substrate, the insulating layer having a plurality of opening groups, each opening group including a first opening and a second opening spaced apart, the first openings and the second openings being located in a conductive layer, the width of the first openings being greater than the width of the P-type electrode, and the width of the second openings being greater than the width of the N-type electrode; a first bonding layer located in the first opening; a second bonding layer located in the second opening; a first bonding layer formed on the first substrate and a second bonding layer formed on the second substrate; a first bonding layer formed on the first substrate and a second bonding layer formed on the second substrate; a second bonding layer formed on the second substrate and a second bonding layer;

17. the chip body includes an N-type semiconductor layer, an active layer located on a portion of one surface of the N-type semiconductor layer, and a P-type semiconductor layer located on a surface of the active layer away from the N-type semiconductor layer, 17. The display panel of claim 16, wherein the P-type electrode is located on a portion of a surface of the P-type semiconductor layer away from the active layer, the N-type electrode is located on a portion of a surface of one side of the N-type semiconductor layer on a side of the active layer, the P-type semiconductor layer, and the P-type electrode, and the P-type semiconductor layer around the P-type electrode contacts a top surface of the insulating layer around the first opening.

18. 17. The display panel of claim 16, wherein a first inclined surface is provided between a sidewall of the first opening and a top surface of the insulating layer surrounding the first opening, and a second inclined surface is provided between a sidewall of the second opening and a top surface of the insulating layer surrounding the second opening.

19. There is a first included angle between the top surface of the insulating layer connected to the first inclined surface and the first inclined surface, and tan(180°-θ １ ) > μ １ and θ １ is the first included angle, and μ １ 19. The display panel according to claim 18, wherein the coefficient of friction of the first inclined surface is

20. There is a second included angle between the top surface of the insulating layer connected to the second inclined surface and the second inclined surface, and tan(180°-θ ２ ) > μ ２ and θ ２ is the second included angle, and μ ２ 19. The display panel according to claim 18, wherein the coefficient of friction of the second inclined surface is

21. 21. The display panel of claim 16, further comprising a barrier layer located on the insulating layer around the opening group, wherein the barrier layer has a third opening, and the width of the third opening is larger than the width of the Micro-LED chip.

22. 22. The display panel of claim 21, wherein the width of the third opening is 1.5 times or less the width of the Micro-LED chip.

23. 22. The display panel according to claim 21, wherein the barrier layer is a light-blocking barrier layer.

24. 24. The display panel according to claim 23, wherein the material of the light-shielding barrier layer is a light-shielding resin.

25. 22. The display panel of claim 21, wherein the height of the top surface of the barrier layer on the side away from the second substrate is greater than the height of the top surface of the Micro-LED chip on the side away from the second substrate.

26. The display panel of claim 16, wherein the width of the first opening is equal to or greater than the sum of the width of the P-type electrode and twice the specific alignment accuracy, and the width of the second opening is equal to or greater than the sum of the width of the N-type electrode and twice the specific alignment accuracy, and the specific alignment accuracy is 0.5 μm to 2 μm.

27. 17. The display panel of claim 16, wherein the thickness of the first bonding layer is greater than or equal to 80% of the depth of the first opening and less than or equal to the depth of the first opening, and the thickness of the second bonding layer is greater than or equal to 80% of the depth of the second opening and less than or equal to the depth of the second opening.

28. 17. The display panel according to claim 16, wherein the thickness of the insulating layer is 50% or less of the difference in thickness between the N-type electrode and the P-type electrode.

29. 29. The display panel of claim 28, wherein the insulating layer has a thickness of 500 nm to 1000 nm.

30. 17. The display panel according to claim 16, wherein the material of the first bonding layer and the second bonding layer is solder, and the material of the first bonding layer and the second bonding layer is a conductive adhesive.

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