High aspect ratio etching with non-uniform metal or semi-metal containing masks

Abstract

A method for etching features in a stack is provided. A non-uniform metal- or semi-metal-containing mask is formed on the stack. The stack is etched through the non-uniform metal- or semi-metal-containing mask, and the etching sputters the metal or semi-metal in the non-uniform metal- or semi-metal-containing mask, which physically redeposits the sputtered metal or semi-metal on the sidewalls of the features etched in the stack as a passivation layer containing the sputtered metal or semi-metal.

Description

[Background technology]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims the benefit of priority to U.S. Patent Application No. 63 / 400,828, filed August 25, 2022, which is incorporated herein by reference for all purposes.

[0002] The present disclosure relates to a method for forming semiconductor devices on a semiconductor wafer.

[0003] When forming semiconductor devices, etching layers can be used to form memory holes or lines and other semiconductor features. Some semiconductor devices are formed by etching a single stack of silicon dioxide, also known as silicon oxide (SiO2), to form, for example, capacitors for dynamic access random memory (DRAM). Other semiconductor devices are formed by etching stacks of alternating bilayers of silicon dioxide (oxide) and silicon nitride (nitride) (ONON) or alternating bilayers of silicon dioxide and polysilicon (OPOP). Other stacks of alternating layers can also be etched. In some alternating layer stacks, one of the layers is silicon oxide. Some alternating layers are alternating trilayers. Such stacks can be used for memory applications and three-dimensional "not-and" gates (3D NAND). These stacks tend to require relatively high aspect ratio (HAR) etching of the dielectric. For high aspect ratio etches, desirable etch properties include high etch selectivity to the mask (e.g., amorphous carbon mask), low sidewall etch with a linear profile, and high etch rate at the etch front. High aspect ratio etches can result in tapered features that are much wider at the top than at the bottom. Such features can increase device failure and limit device density, device performance, and device depth.

[0004] In the etching process for OPOP stacks using an amorphous carbon mask, a metal-containing passivant may be used during the etching process. The metal-containing passivant may be applied during the etching process so that passivation and etching occur simultaneously, or the passivation and etching steps may be alternated. When using tungsten (W) passivation, it has been found that tungsten deposits selectively on polysilicon relative to silicon oxide, resulting in less passivation on silicon oxide than on polysilicon. Poor silicon oxide passivation increases defects such as increased CD and notching. The ability of a passivation layer to protect the underlying material is determined by its weakest or thinnest deposition. For example, if a thin deposition on oxide deteriorates during further etching, the oxide may begin to etch, even if tungsten passivation is still present on the silicon. Etching the oxide causes increased CD, as well as further defect formation such as notching and keyholes. Non-uniform passivation can also cause profile twists, kinks, and lateral bowing of the ions.

[0005] The background description provided herein is intended to generally present the contents of the present disclosure. The information described in this Background section, as well as aspects of the description that may not otherwise be considered prior art at the time of filing, are not admitted, expressly or impliedly, as prior art against the present disclosure. Summary of the Invention

[0006] To achieve the above, and in accordance with the objectives of the present disclosure, a method for etching features in a stack is provided, in which a non-uniform metal- or semi-metal-containing mask is formed on the stack, the stack is etched through the non-uniform metal- or semi-metal-containing mask, the etching sputtering the metal or semi-metal in the non-uniform metal- or semi-metal-containing mask, and the sputtered metal or semi-metal physically redepositing the sputtered metal or semi-metal on the sidewalls of the feature etched in the stack as a passivation layer containing the sputtered metal or semi-metal.

[0007] These and other features of the present disclosure are described in more detail below in the detailed description and in conjunction with the following figures. [Brief explanation of the drawings]

[0008] The present disclosure is illustrated by way of example, and not limitation, in the figures of the accompanying drawings, in which like reference numerals refer to similar elements.

[0009] [Figure 1] FIG. 1 is a high-level flow diagram of a process used in some embodiments.

[0010] [Figure 2A] FIG. 2A is a schematic cross-sectional view of a laminate processed according to some embodiments. [Figure 2B] FIG. 2B is a schematic cross-sectional view of a laminate processed according to some embodiments. [Figure 2C] FIG. 2C is a schematic cross-sectional view of a laminate processed according to some embodiments. [Figure 2D] FIG. 2D is a schematic cross-sectional view of a laminate processed according to some embodiments. [Figure 2E] FIG. 2E is a schematic cross-sectional view of a laminate processed according to some embodiments.

[0011] [Figure 3A] FIG. 3A is a schematic cross-sectional view of a laminate according to another embodiment.

[0012] [Figure 3B] FIG. 3B is a schematic cross-sectional view of a laminate according to another embodiment.

[0013] [Figure 4] FIG. 4 is a schematic diagram of an etching chamber that may be used in some embodiments.

[0014] [Figure 5] FIG. 5 is a schematic diagram of a computer system that may be used in implementing some embodiments.

[0015] In the drawings, like reference numbers may be used to designate like structural elements. It should be understood that the depictions in the figures are schematic and not to scale. DETAILED DESCRIPTION OF THE INVENTION

[0016] The present disclosure will be described in detail below with reference to several preferred embodiments as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without some or all of these specific details. In other instances, well-known process steps and / or structures have not been described in detail in order to avoid unnecessarily obscuring the present disclosure.

[0017] Dry development of high-aspect-ratio contacts requires tight control of the sidewall taper angle. Various methods attempt to limit the difference in lateral critical dimension (CD) between the top and bottom of etched structures. The recent development of 3D NAND memory, which employs an increasing number of ONON or OPOP bilayers and thicker structures, places particular demands on tight control of top and bottom geometries. As the profile (the difference between the top and bottom CD) increases, subsequent steps in device fabrication can impact device performance. Current technology relies on sidewall deposition to protect high-aspect-ratio structures from lateral CD erosion. Achieving a delicate balance between etching and sidewall deposition is particularly challenging for high-aspect-ratio features. As a result, high-aspect-ratio dry development is limited to thinner structures, and significantly more complex development is required to enable etching of thicker stacks.

[0018] Additionally, when a feature is etched, the etch near the top of the feature may have different characteristics than the etch near the bottom of the feature. For example, if the feature is shallow, less sidewall passivation may be required. As the feature is etched deeper, more sidewall passivation may be required near the top sidewall of the feature.

[0019] Some embodiments described herein provide for deeper, high-aspect ratio features etched into a stack, where the width of the feature near the top of the feature is approximately equal to the width of the feature near the bottom of the feature. For ease of understanding, FIG. 1 illustrates a high-level flow diagram that may be used in some embodiments. A non-uniform metal- or semi-metal-containing mask is deposited on the stack (step 104). In some embodiments, plasma-enhanced physical vapor deposition (PECVD) is used to deposit a metal-containing dielectric film that may be used as a first mask layer. A method for depositing tungsten carbide films using PECVD is described in U.S. Patent No. 9,875,890, entitled "Deposition of Metal Dielectric Films for Hard Masks," issued January 23, 2018, the contents of which are incorporated by reference for all purposes, and may be used in some embodiments. In some embodiments, the deposited tungsten carbide film is patterned to form a mask. In some embodiments, a metal- and semi-metal-free carbon mask is deposited on the first mask layer to form a second mask layer.

[0020] 2A is a schematic cross-sectional view of a stack 204 that can be etched in some embodiments. In some embodiments, the stack 204 includes a substrate 208 beneath a plurality of bilayer films 212 disposed below a patterned non-uniform mask 216. In some embodiments, the patterned non-uniform mask 216 includes a first mask layer 217 and a second mask layer 219. In some embodiments, the first mask layer 217 is a layer containing a metal or metalloid, and the second mask layer 219 is free of metals and metalloids. In some embodiments, the first mask layer 217 is a tungsten-doped amorphous carbon mask, and the second mask layer 219 is pure amorphous carbon. In some embodiments, one or more layers may be disposed between the substrate 208 and the plurality of bilayer films 212 and / or between the plurality of bilayer films 212 and the patterned non-uniform mask 216. In some embodiments, the patterned non-uniform mask pattern 216 comprises mask features 220 for high aspect ratio contacts. In some embodiments, the mask features 220 are formed before the stack 204 is placed in the etch chamber. In other embodiments, the mask features 220 are formed while the stack 204 is in the etch chamber. In some embodiments, each bilayer 212 includes a layer 224 of silicon oxide and a layer 228 of silicon nitride.

[0021] The stack and non-uniform mask are etched (step 108). In some embodiments, an etching gas is provided. In some embodiments, the etching gas is a metal- and metalloid-free gas. In some embodiments, RF power is provided to convert the etching gas into a plasma containing etching ions. A voltage is applied to accelerate the etching ions from the plasma into the stack. In some embodiments, metal- and metalloid-free etching ions are provided from an ion source and accelerated into the stack. The etching ions etch the stack. Etching the stack may include at least one of chemical etching and physical sputtering of the stack.

[0022] 2B is a schematic cross-sectional view of the stack 204 during etching to form a partially etched feature 240. Etching ions 244 are accelerated toward the stack 204. The etching ions 244 etch the stack 204 to form the partially etched feature 240 and also etch a portion of the second mask layer 219 of the non-uniform mask 216. In the embodiment shown in FIG. 2B, the second mask layer 219 does not provide passivation for the metal or semi-metal, resulting in a significant tapered shape of the partially etched feature 240.

[0023] Etching of the stack 204 continues. The second mask layer 219 of the non-uniform mask 216 is completely etched away, and the first mask layer 217 of the non-uniform mask 216 is exposed to etching ions 244. FIG. 2C is a schematic cross-sectional view of the stack 204 during further etching of the partially etched feature 240. The etching ions 244 are accelerated toward the stack 204. The etching ions 244 etch the stack 204, further etching the partially etched feature 240, and also sputter a portion of the first mask layer 217 of the non-uniform mask 216. In some embodiments, the etching ions 244 result in two separate processes for depositing a metal or semi-metal passivation on the sidewalls of the feature 240. In one process, the etching ions 244 sputter metal or semi-metal atoms from the non-uniform mask 216 into the plasma and generate metal or semi-metal species from the first mask layer 217. Metal or metalloid species in the plasma are chemically deposited on the sidewalls of the feature 240. In a second process, the metal or metalloid is sputtered from the first mask layer 217 of the non-uniform mask 216 and redeposited on the sidewalls of the partially etched feature 240. In some embodiments, the sputtered metal or metalloid-containing passivation layer 248 is formed by both chemical vapor deposition of the metal or metalloid passivation and physical sputtering of the metal or metalloid. This physical sputtering mechanism overcomes the reduction in metal or metalloid-containing deposition resulting from chemical or ion-assisted deposition processes, especially on silicon oxide, and allows for a more uniform passivation layer.

[0024] In some embodiments, the etching of the stack continues until the etching of the stack is complete. Figure 2D is a schematic cross-sectional view of stack 204 after the etching of stack 204 is completed. In some embodiments, feature 240 is etched through the entire depth of stack 204, so that feature 240 reaches conductive contact 258 on substrate 208. A passivation layer 248 containing a sputtered metal or metalloid protects the sidewalls of feature 240 and can further improve the vertical etch rate, thereby reducing the overall process time.

[0025] In some embodiments, the metal- or metalloid-containing passivation layer 248 is removed (step 112). In some embodiments, a wet process is used to remove the sputtered metal- or metalloid-containing passivation layer 248. In some embodiments, a dry process is used. FIG. 2E is a schematic cross-sectional view of the stack 204 after the sputtered metal- or metalloid-containing passivation layer 248 shown in FIG. 2D has been removed. In some embodiments, the first mask layer 217 of the non-uniform mask 216 shown in FIG. 2D is removed using the same process used to remove the sputtered metal- or metalloid-containing passivation layer. In some embodiments, the non-uniform mask is removed using a separate process used to remove the sputtered metal- or metalloid-containing passivation layer.

[0026] One of the major challenges during high aspect ratio (HAR) etching is CD scaling, particularly as desired features are scaled vertically while simultaneously maintaining consistent lateral feature dimensions. In practice, this is extremely difficult to achieve, and many current techniques face trade-offs. In some embodiments, a tungsten-doped carbon hard mask is utilized to not only protect the stack from unwanted etching, but also to provide robust tungsten species that deposit on the sidewalls of the etched features, protecting them from further lateral etching. This robust tungsten-containing passivation on the feature sidewalls enables CD control and prevents other defect formation, such as notching. Furthermore, some embodiments provide more uniform passivation at the top of the features by allowing direct physical sputtering of tungsten-doped carbon, rather than just chemical vapor deposition from the tungsten species. The tungsten in the first mask layer 217 provides tungsten for the tungsten sidewall passivation.

[0027] In some embodiments, tungsten passivation is not required at the beginning of the etch of feature 240. Because second mask layer 219 does not contain tungsten, there is no metal or semi-metal passivation. Etching without metal or semi-metal passivation at the beginning of the etch allows for faster etching. At the beginning of the etch when the feature aspect ratio is low, the strong metal / semi-metal-containing material can hinder the vertical etch rate by excessive deposition at the etch front. Furthermore, excessive initial deposition can cause CD narrowing at the top of the feature. This narrowing can cause ion scattering within the feature, resulting in double-bow formation and increased pillar twisting.

[0028] By providing a non-uniform mask having a first mask layer with a tungsten-containing dopant and a second mask layer that is free of metals and metalloids, the non-uniformity of the mask can be tailored or adjusted to match the non-uniformity of the feature etching process. The non-uniformity of the feature etching process can be caused by different etching conditions due to different etch depths. Furthermore, different etch depths pursue different etching goals. For example, at the beginning of the etch, the etching process may form a tapered feature, as shown in FIG. 2B, but the focus of the etch is to etch downward as quickly as possible. Near the end of the etch process, the rate of downward etching slows, and the sidewalls near the top of the feature are protected by the metal- or metalloid-containing sidewall passivation, eliminating the tapered shape. Thus, in some embodiments, the non-uniform mask has a tailored non-uniformity to provide a desired non-uniform etch process.

[0029] Some embodiments have been found to provide tailored passivation by depositing tailored tungsten-containing species on SiO2, which is not limited by the previous deposition quality / thickness of tungsten on SiO2 provided by previously used processes, resulting in improved lateral etch rates and better prevention of defect formation such as notching. Because the tungsten required to create the protective passivation material is derived from the mask material itself, some embodiments offer improvements in several respects. The improvement provided by some embodiments is due to the passivation deposition mechanism. Sputtering of tungsten from a non-uniform mask not only adds molecular tungsten species as a reactive gas, but also physically sputters and redeposits the tungsten-doped carbon mask material on the sidewalls. Thus, both a chemically assisted deposition process (due to the by-product formation of tungsten) and a physical sputtering process (due to the tungsten-doped carbon) occur, the combination of which allows for highly uniform deposition across different materials in the etched features. Overall, this greatly helps to protect the upper regions of the features from lateral etching and defect formation (notching) in both bare Si and SiO2 materials.

[0030] Some embodiments may be used with oxide / nitride (ONON) multilayer stacks to form features such as contact holes and trenches when fabricating 3D NAND memory devices. Some embodiments may be used to etch dynamic random access memory (DRAM) capacitors. Some embodiments may be used to etch silicon oxide and polysilicon bilayers (OPOPs). Some embodiments provide etch depths greater than 1 micron. In some embodiments, the etch depth is greater than 10 microns.

[0031] An advantage of some embodiments is that device manufacturers have tighter control over the profile of high aspect features. Various embodiments allow for increased bottom CDs to achieve extremely high aspect ratio features. Various embodiments enable next-generation devices that rely on higher aspect ratio and deeper structures. Various embodiments reduce device manufacturing costs by reducing the number of development steps for high aspect ratio contacts. Various embodiments reduce the variation in width of a feature along its depth, reducing the difference in width at any two points along the depth of the feature 240.

[0032] In some embodiments, the heterogeneous mask may have two or more mask layers, at least one of which is a metal- or semi-metal-containing mask. For example, in some embodiments, the heterogeneous mask may include a first mask layer of silicon oxide or carbon, a second mask layer of a carbon-based material containing a metal or semi-metal, and a third mask layer of a carbon-based material that is free of metals and semi-metals. In some embodiments, the first mask layer is free of metals and semi-metals, and the second mask layer is a metal- or semi-metal-containing layer. In some embodiments, the heterogeneous mask includes at least one layer of at least one of carbon, silicon oxide, and tetraethoxysilane (TEOS) in addition to at least one layer of a metal- or semi-metal-containing mask layer.

[0033] In some embodiments, the stack may be etched using multiple etching steps. In some embodiments, the non-uniform mask is adapted to match the different etching steps. For example, the first etching step of the ONON stack is a fast, shallow, vertical etch. Therefore, the top layer of the non-uniform mask may be free of metals and semi-metals. The second etching step may use a more aggressive etch to open the bottom of the deep feature. Therefore, the bottom layer of the non-uniform mask may have a metal- or semi-metal-containing dopant to provide metal- or semi-metal-containing sidewall passivation to protect the top sidewalls of the feature during the more aggressive etch. In some embodiments, different mask layers of the non-uniform mask may have different metal or semi-metal dopants.

[0034] 3A is a schematic cross-sectional view of a stack 304 that can be etched in some embodiments. In some embodiments, the stack 304 includes a substrate 308 beneath a plurality of bilayer films 312 disposed beneath a patterned non-uniform mask 316. In some embodiments, the patterned non-uniform mask 316 includes a mask doped with a metal or semi-metal dopant, where the concentration of the metal or semi-metal dopant forms a gradient in a direction from the top of the non-uniform mask 316 to the bottom of the mask. In this example, the metal or semi-metal dopant concentration increases from the top of the non-uniform mask 316 to the bottom of the non-uniform mask 316, as indicated by the increasing density of the shading. In some embodiments, the pattern of the patterned non-uniform mask comprises mask features 320 for high aspect ratio contacts. In some embodiments, the mask features 320 are formed before the stack 304 is placed in the etch chamber. In other embodiments, the mask features 320 are formed while the stack 304 is in the etch chamber. In some embodiments, each bilayer 312 includes a layer 324 of silicon oxide and a layer 328 of silicon nitride.

[0035] When etching stack 304, a low concentration of metal or semi-metal dopant in non-uniform mask 316 may result in a lower amount of metal or semi-metal passivation and a faster etch early in the etch. Because the concentration of metal or semi-metal dopant increases from the top to the bottom of the mask, as the etch progresses, the etch process may slow and the metal or semi-metal passivation may increase. In some embodiments, if the stack requires more passivation as the feature is etched deeper into the stack, the mask may have a gradient with a higher concentration of metal or semi-metal passivant near the bottom of the non-uniform mask, so that a higher concentration of metal or semi-metal passivant is exposed to the plasma only as more of the mask is removed as the feature is etched deeper.

[0036] In other embodiments, the non-uniform mask may have a gradient where the concentration of the metal or semi-metal dopant is highest near the top of the non-uniform mask. In other embodiments, the non-uniform mask may have a gradient where the concentration of the metal or semi-metal dopant is highest somewhere between the top and bottom of the non-uniform mask. In some embodiments, the non-uniform mask may have at least two layers, at least one of which has a metal or semi-metal dopant gradient. In some embodiments, the metal or semi-metal dopant comprises between 1% and 50% by weight of the mask material of the mask layer.

[0037] 3B is a schematic cross-sectional view of a stack 304 that can be etched in some embodiments. In some embodiments, stack 344 includes a substrate 348 beneath a plurality of bilayers 352 disposed beneath a patterned non-uniform mask 356. In some embodiments, patterned non-uniform mask 356 includes a first mask layer 357, a second mask layer 359, and a third mask layer 361. In some embodiments, each bilayer 352 includes a layer 364 of silicon oxide and a layer 368 of silicon nitride. At least one of first mask layer 357, second mask layer 359, and third mask layer 361 contains a metal or semi-metal. In some embodiments, the profile of non-uniform mask 356 is non-uniform but tailored to the desired etch result. For example, the first mask layer 357 may be TEOS, the second mask layer 359 may be a carbon layer doped with a metal or semimetal, and the third mask layer 361 may be an amorphous carbon layer without metal or semimetal dopants. The first mask layer 357 tapers downward. The third mask layer 361 widens downward. As a result, the second mask layer 359 has the largest CD among the mask features 360 of the non-uniform mask 356. As a result, the non-uniform profile of the mask features 360 can further control the passivation of the metal or semimetal and become another knob for controlling the etch process.

[0038] In some embodiments, the stack may be a silicon-containing monolayer, such as a monolayer of silicon oxide, silicon nitride, or silicon, hi some embodiments, the stack may include a layer or layers of other silicon-containing materials.

[0039] In some embodiments, for etching a stack having a silicon layer, the non-uniform mask may further include oxygen. In some embodiments, for etching a silicon oxide stack, the non-uniform mask may further include silicon. Some embodiments may have other materials in addition to the metal or metalloid dopant. In some embodiments, the metal in the metal or metalloid-containing mask is at least one of tungsten, molybdenum, ruthenium, tantalum, titanium, platinum, and aluminum. In other embodiments, the metalloid is boron. In some embodiments, the metal and metalloid species are provided by sputtering the metal or metalloid-containing mask, so the etching gas does not include metals and metalloids.

[0040] Some embodiments provide novel mask stacks with rational designs that are specifically adapted to provide downstream benefits in high aspect ratio (HAR) etch processes, particularly for improving etch rates and etch feature profiles (i.e., bow CD, bottom CD, taper, twist, defect formation, etc.) that are very difficult to achieve through HAR process tuning alone.

[0041] 4 is a schematic diagram of an etch reactor system 400 that can be used in some embodiments. In some embodiments, the etch reactor system 400 includes a gas distribution plate 406 with gas inlets and an electrostatic chuck (ESC) 408 within an etch chamber 409 surrounded by chamber walls 452. Within the etch chamber 409, a stack 404 is disposed on top of the ESC 408. The ESC 408 may receive a bias from an ESC source 448. An etch gas source 410 is connected to the etch chamber 409 through the gas distribution plate 406. An ESC temperature controller 450 is connected to the ESC 408. A radio frequency (RF) source 430 supplies RF power to the lower electrode and / or the upper electrode. In this embodiment, the lower electrode and the upper electrode are the ESC 408 and the gas distribution plate 406, respectively. In some embodiments, 400 kilohertz (kHz), 60 megahertz (MHz), and optionally 2 MHz and 27 MHz power sources comprise the RF source 430 and the ESC source 448. In some embodiments, the upper electrode is grounded. In some embodiments, one generator is provided for each frequency. In some embodiments, the generators may be on separate RF sources, or separate RF generators may be connected to different electrodes. For example, the upper electrode may have an inner electrode and an outer electrode connected to different RF sources. In other embodiments, other arrangements of RF sources and electrodes may be used. A controller 435 is controllably connected to the RF source 430, the ESC source 448, the exhaust pump 420, and the etching gas source 410. An example of such an etching chamber is the Flex™ Etch System manufactured by Lam Research, Fremont, California. The process chamber may be a CCP (capacitively coupled plasma) reactor or an ICP (inductively coupled plasma) reactor.

[0042] FIG. 5 is a high-level block diagram illustrating a computer system 500 suitable for implementing the controller 435 used in the embodiments. The computer system 500 can take many physical forms, from integrated circuits, printed circuit boards, and small handheld devices to large supercomputers. The computer system 500 includes one or more processors 502 and may further include an electronic display device 504 (for displaying images, text, and other data), main memory 506 (e.g., random access memory (RAM)), storage device 508 (e.g., a hard disk drive), removable storage device 510 (e.g., an optical disk drive), user interface device 512 (e.g., a keyboard, touch screen, keypad, mouse, or other pointing device), and a communications interface 514 (e.g., a wireless network interface). The communications interface 514 allows software and data to be transferred between the computer system 500 and external devices via a link. The system may also include a communications infrastructure 516 (e.g., a communications bus, crossover bar, or network) to which the aforementioned devices / modules are connected.

[0043] Information transferred through communications interface 514 may be in the form of signals, such as electronic, electromagnetic, optical, or other signals, receivable by communications interface 514 over a communications link carrying the signals, which may be implemented using wire or cable, fiber optics, telephone line, cellular phone link, radio frequency link, and / or other communications channel. It is contemplated that such communications interface 514 enables one or more processors 502 to receive information from a network and output information to a network in the course of performing the method steps described above. Furthermore, method embodiments may be performed solely by the processor or may be performed over a network, such as the Internet, in conjunction with a remote processor that shares some of the processing.

[0044] The term "non-transitory computer-readable medium" is used generally to refer to storage devices such as primary memory, secondary memory, removable storage, and storage devices such as hard disks, flash memory, disk drive memory, CD-ROMs, and other forms of persistent storage, and should not be construed to include transient objects such as carrier waves or signals. Examples of computer code include machine code, such as produced by a compiler, and files containing high-level code that are executed by a computer using an interpreter. Computer-readable medium may also be computer code carried by a computer data signal embodied in a carrier wave and representing sequences of instructions executable by a processor.

[0045] In some embodiments, the plasma may be monitored in situ during mask opening or stack etching to adjust the etch or open recipe in real time. Plasma monitoring may be used to detect and measure the concentration of species, such as metals or metalloids, in the plasma, or the relative concentrations of two or more different species. The detected concentrations of the measured species may be used to modify the recipe in real time to provide the desired open or etch.

[0046] While the present disclosure has been described in terms of several preferred embodiments, alterations, modifications, arrangements, and various substitute equivalents exist that fall within the scope of the present disclosure. It should be noted that there are many alternative ways of implementing the methods and apparatuses of the present disclosure. Accordingly, the following appended claims are intended to be construed as including all such alterations, modifications, arrangements, and various substitute equivalents as fall within the true spirit and scope of the present disclosure. As used herein, the phrase "A, B, or C" should be construed to mean a non-exclusive logical "OR" ("A OR B OR C"), and not to mean "only one of A or B or C." Each step within a process is optional and not required. Different embodiments may omit one or more steps or provide steps in a different order. Furthermore, various embodiments may provide different steps simultaneously rather than sequentially.

Claims

1. 1. A method of etching a feature in a laminate, comprising: a) forming a non-uniform metal or metalloid containing mask on the stack; b) etching the stack through the non-uniform metal or metalloid containing mask; The method of claim 1, wherein the etching sputters metal or metalloid in the non-uniform metal or metalloid-containing mask, and the sputtered metal or metalloid physically redeposits on sidewalls of features etched into the stack as a sputtered metal or metalloid-containing passivation layer.

2. 2. The method of claim 1, wherein the step of etching the stack comprises: providing metal- and metalloid-free etching ions; and accelerating the etching ions into the stack; The method wherein the etching ions etch features into the stack and sputter metal or metalloid from the metal or metalloid-containing mask.

3. 3. The method of claim 2, wherein the metal or semi-metal containing passivation layer provides a metal or semi-metal species.

4. 4. The method of claim 3, wherein the metallic or semi-metallic species chemically deposits on the sidewalls of the feature in addition to the sputtered metal or semi-metallic species being physically redeposited on the sidewalls of the feature.

5. 10. The method of claim 1, wherein the metal or metalloid is at least one of tungsten, molybdenum, ruthenium, tantalum, titanium, platinum, aluminum, and boron.

6. The method of claim 1 , wherein the stack is a silicon-containing stack.

7. The method of claim 1 , wherein the laminate is a silicon oxide-containing laminate.

8. 10. The method of claim 1, wherein the stack is a plurality of alternating layers, and at least one layer of the plurality of alternating layers is a layer containing silicon oxide.

9. 10. The method of claim 1, further comprising the step of removing the passivation layer containing the sputtered metal or metalloid.

10. 2. The method of claim 1, wherein forming a non-uniform metal- or semi-metal-containing mask on the stack comprises forming a metal- or semi-metal-containing mask having a gradient that varies the concentration of metal or semi-metal from an upper portion of the non-uniform metal- or semi-metal-containing mask to a lower portion of the non-uniform metal- or semi-metal-containing mask.

11. 10. The method of claim 1, wherein forming a non-uniform metal or semi-metal containing mask on the stack comprises forming a metal or semi-metal containing mask having a first mask layer and a second mask layer, the first mask layer having at least a first concentration of metal or semi-metal, and the second mask layer having a second concentration or less of metal or semi-metal, the first concentration being greater than the second concentration.

12. The method of claim 11 , wherein the second mask layer is between the first mask layer and the stack.

13. 12. The method of claim 11, wherein the first mask layer is between the second mask layer and the stack.

14. 12. The method of claim 11, wherein the second mask layer does not include a metal or a semi-metal.

15. 10. The method of claim 1, further comprising measuring species in a plasma used for etching and adjusting the etching of the stack according to the measured species.

16. The method of claim 1 , wherein the non-uniform metal- or semi-metal-containing mask has a non-uniform profile.

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