Method for manufacturing a structure for transferring a chip

Abstract

The following steps: i) providing an intermediate substrate (110); ii) bonding the chips (121, 122) to a first surface of the intermediate substrate (110), thereby forming an array of chips (121, 122), the chips (121, 122) covering both the central region and the peripheral region of the intermediate substrate (110), and the chips (122) located in the peripheral region protruding from the surface of the intermediate substrate (110); A method for manufacturing a transfer structure (100), comprising: The method also includes, after step ii), a trimming step iii) of removing the ends of the chips (122) protruding from the surface of the intermediate substrate (110), thereby trimming the peripheral chips (122) and obtaining a transfer structure (100) comprising an intermediate substrate (110) covered with a pseudo-donor substrate formed by an arrangement of chips (121, 122), the arrangement of the chips (121, 122) being offset from the crystal plane of the intermediate substrate (110).

Description

[Technical Field]

[0001] The present invention relates to the general field of methods for transferring material from a donor substrate to a receptor substrate, and more particularly to methods for transferring a pseudo-substrate formed by an array of tips to a receptor substrate.

[0002] The present invention relates to a method for producing a structure that allows the transfer of a pseudo-substrate formed by an array of tips to a receptor substrate.

[0003] The present invention also relates to a transfer structure of this kind.

[0004] The invention also relates to a transfer method using this type of structure.

[0005] The invention finds application in many areas of industry, in particular in the manufacture of substrates from materials of interest that are only present in smaller quantities, and is particularly advantageous for the manufacture of substrates of semiconductor materials, for example III-V types, and in particular indium phosphide (InP) substrates.

[0006] The present invention is particularly useful because it allows the fabrication of transfer structures comprising a pseudo-substrate formed by an array of tips, which are mechanically stable and less fragile than those of the prior art. [Background technology]

[0007] The semiconductor materials GaAs and InP are promising materials for many applications, such as photonics and optoelectronics. However, these materials are very fragile, precious, and expensive. Therefore, they are generally produced in the form of small diameter ingots (typically up to 100 mm or 150 mm in diameter), limiting the range of their applications.

[0008] To overcome this drawback, an InP substrate with a diameter of 200 mm can be manufactured by producing an array of InP chips forming a pseudo-substrate, and then transferring a thin layer of this pseudo-substrate onto an SOI substrate, as described in the paper by Ghyselen et al. (Phys. Status Solidi A 2022, 219, 2100543). The method comprises the following steps: - bonding the chips to an intermediate substrate (typically a semiconductor material wafer, for example silicon), thereby obtaining a transfer structure comprising the intermediate substrate covered by an array of chips, the array of chips forming a pseudo donor substrate made of the material of interest (InP); - performing a Smart Cut® process to transfer a thin layer of the pseudo-donor substrate to a receptor substrate; Includes.

[0009] At the end of this process, the pseudo-donor substrate can be reused to retransfer a thin layer of the material of interest to another receptor substrate.

[0010] Generally, the chips have a square shape and the substrate has a circular shape, as shown in Figure 1. Therefore, no chips can be bonded to the edge of the substrate (Figure 1). The chip-free area, known as the exclusion area, has a toothed shape, so that the substrate can be carried in a conventional microelectronic container.

[0011] However, the presence of chips bonded to a substrate causes substrate fragility, which is exacerbated by splitting along the spaces between the chips (inter-chip spaces), compromising many surface preparation processes such as chemical-mechanical polishing (CMP).

[0012] Therefore, there is a need to produce transfer structures that are not fragile. [Prior art documents] [Non-patent literature]

[0013] Ghyselen et al., Phys. Status Solidi A 2022, 219, 2100543 Summary of the Invention [Problem to be solved by the invention]

[0014] One object of the present invention is to overcome the drawbacks of the prior art and to propose a method for manufacturing a structure for transferring chips which overcomes the drawbacks of the prior art and in particular has improved mechanical strength. [Means for solving the problem]

[0015] For this purpose, the present invention comprises the following steps: i) providing an intermediate substrate having a first surface; ii) bonding chips to a first surface of the intermediate substrate, thereby forming an array of chips, the chips covering both the central and peripheral regions of the first surface of the intermediate substrate, and the chips covering the peripheral region protruding from the first surface of the intermediate substrate; The method also includes, after step ii), a trimming step iii) of removing the ends of the chips protruding from the first surface of the intermediate substrate, thereby trimming the peripheral chips and obtaining a chip transfer structure comprising an intermediate substrate covered by a pseudo donor substrate formed by an arrangement of the chips.

[0016] The present invention differs fundamentally from the prior art in that the intermediate substrate is covered with an array of chips both in the central region of its first surface and in the peripheral region of its first surface, resulting in a wafer array forming a pseudo-substrate that can be transferred to a receptor substrate.

[0017] The chip pattern (i.e., the array of chips) formed by all the chips is circular, as is the first surface of the intermediate substrate, which provides a pseudo-substrate with a typical microelectronic shape.

[0018] The chips do not protrude from the intermediate substrate and the structure can be easily transported in conventional containers and handled and used in microelectronic devices.

[0019] The round shape also facilitates drying of the plate using the Marangoni effect or centrifugation, which facilitates all wet process steps that involve rotation of the substrate.

[0020] Furthermore, bonding all the chips to the intermediate substrate and then trimming it maximizes the surface area of ​​the transferred layers, thus increasing the efficiency of the method. For example, the CMP process tends to round the edges of the outermost chips. The rounded edges will now be the edges of the chips that are trimmed. Therefore, the entire chip in the central region will be protected.

[0021] The absence of toothed edges of the array of tips at the edges of the pattern will reduce consumption of consumables, especially in processes such as chemical mechanical polishing (CMP).

[0022] Furthermore, the mechanical strength of the resulting structure is improved compared to substrates from the prior art.

[0023] Advantageously, the trimming step iii) is carried out by trimming and / or grinding.

[0024] Advantageously, after step ii), the method comprises a step iv) in which the chip is thinned. Advantageously, step iii) is carried out after step iv), but it can also be carried out between steps ii) and iii).

[0025] Advantageously, the chip is bonded to the intermediate substrate by direct bonding.

[0026] According to one particularly advantageous embodiment, the arrangement of the chips is offset from the crystal plane of the substrate, in other words, the cutting lines formed by the spaces between the chips are rotated relative to the crystal plane of the substrate to which they are bonded, limiting the splitting and thus the breakage of the structure, so that the resulting structures are less brittle and easier to handle and use in automated equipment.

[0027] This misalignment is never a problem for the final application, since the crystal planes of the material of interest on the final substrate can be realigned when the chip is transferred.

[0028] For example, the chip is made from a semiconductor material, particularly a III-V semiconductor material such as indium phosphide.

[0029] Advantageously, the chips covering the peripheral region are different from the chips covering the central region, for example having a different quality, a different material and / or different dimensions.

[0030] The present invention also relates to a chip transfer structure including an intermediate substrate covered by a pseudo donor substrate formed by an array of chips, chips bonded to a first surface of the intermediate substrate, and chips covering both a central region and a peripheral region of the first surface of the intermediate substrate, the peripherally positioned chips being trimmed so as not to protrude beyond the first surface of the intermediate substrate.

[0031] Advantageously, there can be two populations of chips: "center" chips and edge chips. These two populations can have different qualities (e.g., doping level or crystal defect rate). They can also be of different types to minimize manufacturing costs.

[0032] Advantageously, the arrangement of the chips is offset from the crystal plane of the substrate.

[0033] Advantageously, the intermediate substrate is made from silicon and / or the chip is made from InP.

[0034] The present invention relates to a method for producing a method for manufacturing a semiconductor device comprising the steps of: a) providing a transfer structure as defined above, comprising an intermediate substrate covered by a pseudo donor substrate formed by an array of chips, the chips being bonded to a first surface of the intermediate substrate, the chips covering both a central region and a peripheral region of the first surface of the intermediate substrate, and the chips located on the periphery being trimmed so as not to protrude beyond the first surface of the intermediate substrate; b) transferring the layer of the pseudo-substrate to the receptor substrate, for example with the Smart Cut® process; The present invention also relates to a method for transferring a chip, comprising:

[0035] Other features and advantages of the present invention will become apparent from the following additional description.

[0036] It should be understood that this additional description is provided only as an illustration of the subject matter of the present invention and should not be construed in any way as a limitation of this subject matter.

[0037] The present invention can be better understood on reading the description of exemplary embodiments given for informational purposes only and in no way limited by reference to the accompanying drawings in which: [Brief explanation of the drawings]

[0038] [Figure 1] FIG. 1, mentioned above in the prior art, shows, in plan view, a schematic representation of an intermediate substrate covered by chips to be transferred. [Figure 2] 2A and 2B show schematic diagrams of various steps of a method for manufacturing a chip transfer structure according to a first embodiment of the present invention, the transfer structure being shown in plan view, comprising an intermediate substrate covered with a chip to be transferred. [Figure 3] 3A and 3B show schematic diagrams of various steps of a method for manufacturing a chip transfer structure according to a second embodiment of the present invention, the transfer structure being shown in plan view, comprising an intermediate substrate covered with a chip to be transferred. [Figure 4]Figures 4A, 4B, 4C, 4D, and 4E show schematic diagrams of various steps in a method for manufacturing a chip transfer structure according to a third embodiment of the present invention, the transfer structure being shown in plan view, comprising an intermediate substrate covered with a chip to be transferred. [Figure 5] FIG. 5 shows a schematic diagram of a cross section of the transfer structure shown in FIG. 4E. [Figure 6A] FIG. 6A is a photograph of a chip transfer structure with an array of chips aligned with notches, the structure being made from silicon, according to a specific embodiment of the invention. [Figure 6B] FIG. 6B is a photograph of a chip transfer structure in which the chips are misaligned at a 7° angle relative to the notch, according to a specific embodiment of the present invention, the structure being made from silicon. DETAILED DESCRIPTION OF THE INVENTION

[0039] The different parts shown in the figures are not necessarily drawn to a uniform scale in order to make the figures more legible.

[0040] The various possibilities (alternatives and embodiments) must be understood as not being mutually exclusive and can be combined with one another.

[0041] Furthermore, in the remainder of this specification, orientation-dependent terms such as "top," "bottom," etc. of a structure apply when the structure is considered oriented as illustrated in the drawings.

[0042] We now describe in more detail the fabrication method of the structure 100 used for the transfer of the pseudo-substrate formed by the array of tips 121, 122 made of the material of interest.

[0043] The present invention is particularly useful for the fabrication of large diameter substrates (typically 200 mm or 300 mm in diameter), especially large diameter InP+ substrates, but is not limited to InP and is applicable to many other materials.

[0044] As shown in FIGS. 2A-2B, 3A-3B, or 4D-4E, the method for manufacturing the transfer structure 100 includes the following sequential steps: i) providing an intermediate substrate 110; ii) bonding chips 121, 122 to the first surface of the intermediate substrate, where a first group of chips 121 covers a central region of the first surface of the intermediate substrate 110 and a second group of chips 122 covers a peripheral region of the first surface of the intermediate substrate 110 and protrudes from the first surface of the intermediate substrate 110 (FIGS. 2A, 3A, 4D); iii) performing a trimming step to remove the ends of the chips 122 protruding from the first surface of the intermediate substrate 110, whereby the chips 122 in the peripheral region are trimmed, resulting in a transfer structure 100 comprising an intermediate substrate (110) covered with a pseudo-donor substrate formed by an array of chips (121, 122), the array having the same shape as the intermediate substrate 110 (FIGS. 2B, 3B, 4E); Includes.

[0045] The method may also include step iv) in which the chips 121, 122 are thinned. Step iv) may be performed either between steps ii) and iii) or after step iii). Preferably, it is performed after step iii).

[0046] Preferably, the intermediate substrate 110 provided in step i) is made of a semiconductor material. For example, it is made of silicon. For example, an intermediate silicon substrate 110 with a 100 or 111 crystal orientation is selected. It can also be made of germanium. According to another embodiment, the substrate is made of fused silica (or glass).

[0047] The intermediate substrate 110 is a circular plate or wafer, for example, it can be a plate with a diameter of 200 mm or 300 mm.

[0048] The intermediate substrate 110 includes a first surface (or first main surface) and a second surface (or second main surface) to which the chips 121 and 122 are fixed. The first surface and the second surface are parallel to each other. They are separated by a thickness, which is, for example, between 100 and 2000 μm, more specifically, between 500 and 800 μm.

[0049] The intermediate substrate 110 has an identification notch 130 on its periphery, which is used to identify the orientation of the plate during various steps of the process. This notch 130 is generally semicircular. For example, it can be made into the intermediate substrate 110 by a few millimeters (e.g., 1 mm). The size of the notch is defined in SEMI standards.

[0050] During step ii), the chips 121, 122 are fixed to an intermediate substrate 110 (FIG. 2A or FIG. 3A).

[0051] The first group of chips 121 are located in a central region of the first surface of the intermediate substrate 110. The chips 121 of the first group of chips do not protrude from the first surface of the intermediate substrate 110.

[0052] The second group of chips 122 is located in a peripheral region of the first surface of the intermediate substrate 110. The chips 122 of the second group of chips protrude from the first surface of the intermediate substrate 110.

[0053] The joined chips 121, 122 can be the same or different. They can be made of different materials. For example, the chips 121 in the central region can be made of a first material and the chips 122 in the peripheral region can be made of a second material. In particular, it would be advantageous to choose cheaper chips 122 for the peripheral region, since these chips 122 will be trimmed during step iii).

[0054] One or more of the following materials are selected: InP, AsGa, silicon, germanium, LaNiO3 (LNO), lithium titanate (LTO), SiC, diamond, sapphire, silicon dioxide, glass.

[0055] The chips 121, 122 may include epitaxial layers, metal interconnect layers, and / or stacks such as CMOS.

[0056] On the same intermediate substrate 110 it is possible to integrate chips 121, 122 made from different materials and with different functions.

[0057] The chips 121, 122 can have the same or different surfaces and / or the same or different shapes. For example, in order to optimize the filling of the surfaces, the chips 121 in the central region can have a larger surface than the surface of the chips 122 in the peripheral region. It is advantageous to avoid losing too much material during step iii).

[0058] The chips 121, 122 can have any shape. For example, they can be square or rectangular. Preferably, they are square. For example, the chips have a surface between 0.1 mm x 0.1 mm and 20 x 20 mm, preferably between 1 mm x 1 mm and 10 x 10 mm. Here and hereafter, between X and Y is meant to include the upper and lower limits. For example, the chips 121, 122 can have a surface of 1 cm 2 It is a chip with a surface area of ​​.

[0059] Preferably, the thickness of the chips 121, 122 is several tens to several hundreds of micrometers, for example between 50 μm and 2000 μm, more particularly between 350 μm and 775 μm.

[0060] Advantageously, the tips 121, 122 are equally spaced apart. Very preferably, their position is capable of forming cutting lines. Even more advantageously, the tips 121, 122 are arranged so as to form a cutting grid.

[0061] The space between the chips 121, 122, referred to as the inter-chip space, is for example between 0.01 and 10 mm, more particularly between 0.2 and 1 mm.

[0062] The bonding patterns of the chips 121, 122 can be aligned with the crystal planes of the intermediate substrate 110 to which they are bonded. They are therefore aligned with the notches 130 (FIGS. 2B, 4E). If we consider a line L passing through the notch and through the center of the first circular surface of the intermediate substrate, the cutting lines are parallel or perpendicular to this line L.

[0063] According to one advantageous variant, the patterns of the chips 121, 122 are not aligned with the crystal planes of the intermediate substrate 110 to which they are bonded (FIG. 3B). They are therefore offset from the cuts 130. In other words, the cutting lines are neither parallel nor perpendicular to the above-mentioned line L. This offset limits the splitting and reduces the fragility of the final structure. Advantageously, to enhance this effect, the crystal planes of the chips are also not aligned with the crystal planes of the intermediate substrate.

[0064] The chips 121, 122 can be bonded using different bonding techniques (direct bonding, polymer bonding, eutectic bonding, thermocompression bonding, anodic bonding).

[0065] Preferably, the bonding is a direct bonding.

[0066] As shown in Figures 4A, 4B, 4C, and 4D, step ii) comprises the following substeps: - providing one or more substrates 120 to be cut, the substrates 120 may be of the same material or different materials and / or the substrates 120 may be of the same size or different sizes (a single substrate to be cut is shown in FIG. 4A); - cutting the substrate(s) along cutting lines (indicated by the lines in FIG. 4B) to form chips; - manually or, preferably, automatically (using a pick-and-place device) placing the chips 121, 122 onto the adhesive backing 40 (Fig. 4C); - bonding the chips 121, 122 to the intermediate substrate 110 (Fig. 4D); It is possible to include:

[0067] By way of illustration and without limitation, the substrate to be cut can be a circular InP substrate with a diameter of 50, 75, or 100 mm. For example, for an intermediate substrate 110 that is 200 mm or 300 mm, ten plates of 100 mm diameter can be cut.

[0068] Advantageously, a heat treatment can be carried out after bonding the chips 121 , 122 to increase the adhesive energy between the chips 121 , 122 and the intermediate substrate 110 .

[0069] During step iii), the intermediate substrate 110 is trimmed in order to remove at least the ends of the chips 122 that protrude from the intermediate substrate 110 .

[0070] In one embodiment, only a protruding piece is removed, which causes the formation of truncated chips 122. Therefore, the chips 122 on the periphery of the intermediate substrate 110 partially conform to the shape of the substrate 110. Thus, the array of chips has the same shape and surface area as the first surface of the intermediate substrate 110 (FIGS. 2B and 3B).

[0071] According to another embodiment, a small amount of material can be removed to clean the natural edge ("bevel") of substrate 110, thereby facilitating use of the structure in automated machines set on the natural edge of substrate 110. The array of chips thus has the same shape as the first surface of intermediate substrate 110, but a smaller surface area than the first surface of intermediate substrate 110 (FIG. 4E).

[0072] Advantageously, at least the entire unbonded area of ​​the chip is removed, this area being observable, for example, under an ultrasonic microscope.

[0073] Advantageously, the trimming step is carried out by mechanical means.

[0074] Preferably, this step can be carried out by grinding and / or trimming. Preferably, trimming will be carried out first, followed by grinding.

[0075] By using protruding bonds and performing a trimming step, it is possible to obtain a transfer structure 100 with a circular periphery, in particular one in which the periphery of the pseudo-substrate is circular like the intermediate substrate 110 .

[0076] During step iv), the chips 121, 122 are thinned. They can be thinned by grinding and / or polished by chemical mechanical polishing (CMP). The CMP process gives the chips 121, 122 a mirror-polished appearance. After step iv), the chips 121, 122 have the same thickness. For example, the chips are thinned to have a thickness of around 550 μm. It is also possible to reduce the thickness to a few microns or even tens of microns.

[0077] Advantageously, the remaining thickness is selected to allow successive layer transfer with a single intermediate plate.

[0078] Advantageously, the chip is thinned to at least 15 microns.

[0079] Step iv) comprises the following substeps: - depositing a filler material between the chips 121 and 122 (i.e. in the space between the chips), preferably with a thickness between the chips greater than the final thickness of the chips after thinning, the filler material being able to partially or completely cover the chips 121, 122 as well (i.e. the chips 121, 122 are surrounded by the filler material); - thinning the chips 121, 122; - carrying out a step of planarizing the resulting mixed surface (chips 121, 122 - filling material), for example by chemical mechanical polishing, in order to obtain a flat surface or a surface with filling material slightly recessed, for example by a few nanometers to a few tens of nanometers; It is possible to include:

[0080] After the manufacturing method of the transfer structure 100, a structure 100 is obtained that includes an intermediate substrate 110 covered by an array of chips 121, 122 that form a pseudo-substrate. There are no exclusion areas or limited circular exclusion areas. The presence of limited exclusion areas makes it possible to maintain the outermost edge of the plate ("bevel") without the need for a robot to hold the substrate.

[0081] Both the central and peripheral regions of the intermediate substrate 110 are covered with chips 121, 122. The chip 121 in the central region is complete. The chip 122 in the peripheral region is trimmed so that it does not protrude from the surface of the intermediate substrate 110.

[0082] The array of chips 121, 122 has the same shape as the intermediate substrate 110 (FIGS. 2B, 3B, 4E, 5).

[0083] 6A and 6B are photographs of an aligned transfer structure 100 (i.e., an arrangement of chips aligned with respect to the notches) and an offset transfer structure 100 (i.e., an arrangement of chips offset with respect to the notches; 7° angle), respectively.

[0084] The resulting structure 100 can be used to transfer the pseudo donor substrate to a receptor substrate. Preferably, the receptor substrate is a wafer. Preferably, the receptor substrate is made of a semiconductor material. For example, it can be a silicon oxide substrate or an SOI (silicon on insulator) substrate, i.e., a substrate comprising a silicon layer on an insulator layer, typically a SiO2 layer. Also, SOI substrates are generally oxidized and therefore have an oxide layer on the surface.

[0085] Preferably, the pseudo-donor substrate is transferred to the receptor substrate with the Smart Cut® process.

[0086] The Smart Cut® process - forming an embrittlement zone in the pseudo donor substrate by implantation defining a thin layer intended to be transferred to a receptor substrate; - bonding the transfer structure (i.e., the intermediate substrate and the array of chips) to a receptor substrate by direct bonding, the chips being in contact with the receptor substrate; - dividing the intermediate structure according to the weakened zone in order to transfer the thin layer of the pseudo-donor substrate to the receptor substrate; It is possible to include:

[0087] The embrittlement zone is formed by implantation of chemical species such as hydrogen or helium, the implantation conditions (amount, energy) being determined by the skilled person according to the nature of the substrate and the desired implantation depth.

[0088] Prior to bonding, surface treatments can be performed on the pseudo-substrate and receptor substrate to increase the bonding energy.

[0089] For example, splitting can be initiated by applying a mechanical force to the embrittled region or by heat treatment (annealing).

[0090] After the layer of interest has been transferred to the receptor substrate, the transfer structure 100 can be reused to perform a new transfer of the material of interest. [Example]

[0091] Illustrative and Non-Limiting Example of One Embodiment [Trimming of plates intended to form chips] The InP plate 120 to be trimmed is mounted on a first UV-release adhesive film stretched over a cutting ring. Chips 121, 122 are cut out of the plate using a diamond saw. After trimming, the surface of the chips is cleaned. To reconstruct the surface of a 300 mm wafer 110, it is necessary to cut approximately ten 100 mm diameter InP plates 120.

[0092] [Chip position on adhesive film] To make the chip easier to grip, the adhesive film is exposed to UV lighting.

[0093] The chips 121, 122 are lifted and then placed on a second blank UV-release adhesive film 40 stretched over a cutting ring. This process can be performed automatically with a "pick-and-place" machine. The aim is to reconstruct a plate (i.e., an intermediate substrate) that is larger than the donor plate on this adhesive film 40. Advantageously, the diameter of the reconstructed surface is larger than the diameter of the intermediate substrate 110 that will receive the chips 121, 122, in order to maximize the reconstructed surface after the chips 121, 122 have been trimmed.

[0094] [Cleaning and bonding of chip and intermediate substrate] Once the surfaces are reconstructed on the adhesive film 40, the chips 121, 122 are cleaned together to remove hydrocarbons and debris. Illustratively, an initial UV / ozone clean can be performed to remove hydrocarbons. Then, the chips 121, 122 can be subjected to a megasonic clean.

[0095] The chips 121, 122 are placed face down on the intermediate substrate 110. A slight pressure is applied to the backside of the adhesive film 40 to promote contact between the chips 121, 122 and the intermediate substrate 110. Once the chips 121, 122 are bonded, the adhesive film 40 is exposed and peeled off. Advantageously, this structure with the "protruding" chip 122 is subjected to a heat treatment, for example annealing between 250 and 400°C, to reinforce the bonding interface.

[0096] [Trimming by grinding] The intermediate substrate 110, coated with chips 121, 122 some of which protrude from its surface, can be trimmed by grinding.

[0097] For this purpose, the intermediate substrate 110 to which the chips 121, 122 are bonded is sucked onto a chuck.

[0098] This assembly is transferred under a grinding wheel so that the outer periphery of the wheel's teeth is positioned vertically at the required trimming width. Typically, this width is reduced to a width greater than 1.5 mm relative to the edge of the substrate 110 to make the plate compatible with other microelectronic devices. This frees the natural edges of the plate 110 and its notches 130.

[0099] The grinding wheel and / or chunk on which the intermediate substrate 110 is positioned is then rotated and the grinding wheel is lowered parallel to remove the thickness of the chip bonded to the intermediate substrate 110 .

[0100] The rotation speed (between 100 and 3000 rpm) and the wheel descent speed (between 0.01 and 50 μm / s) are adapted depending on the material and the thickness to be removed. Various descent speeds can be combined during the process. The rotation speed of the chuck is also adapted (its speed is between 100 and 300 rpm).

[0101] [Cutting Trimming] The intermediate substrate 110, coated with chips 121, 122 some of which protrude from its surface, can be trimmed using an abrasive circular blade sawing technique.

[0102] For this purpose, the intermediate substrate 110 to which the chip is to be bonded is held on a chuck.

[0103] The cutting blade is circular. It has an abrasive lining around its periphery, the height of which is at least equal to the working depth. This abrasive lining contains a binder and abrasive particles, such as diamond or corundum, whose size and porosity are adapted to the material to be cut.

[0104] The intermediate substrate 110 is centered by optical alignment modules or mechanical shims defined at the edges of the intermediate substrate.

[0105] The blade is rotated and lowered to a defined height associated with the point of contact of the chuck and the trimming diameter.

[0106] The intermediate substrate 110 undergoes a complete rotational movement which continues the trimming operation.

[0107] Depending on the blade width and the trimming width, various operations may be necessary for trimming the plate.

[0108] The blade can also enter the intermediate substrate 110 via the edge of the plate rather than perpendicularly. In this case, the intermediate substrate 110 first undergoes a translational motion until it reaches the trimming contact point, and then the intermediate substrate performs a complete rotation.

[0109] Typically, to make the substrate compatible with other microelectronic devices, this width is reduced to at least 1.5 mm, corresponding to the trimming value of notch 130 .

[0110] [Thinning of chips placed on trimmed intermediate substrates] The chips 121, 122 can be thinned by grinding. The intermediate substrate 110 is placed on the chuck. The surface of the intermediate substrate 110 opposite the chips 121, 122 is in contact with the chuck.

[0111] The assembly is positioned below the grinding wheel, which is perpendicular to the intermediate substrate 110. The wheel comprises synthetic diamond particles of a size adapted to the material, a resin or other binder, and a set of teeth arranged around the periphery of a metal base with controlled porosity.

[0112] The grindstone and / or chunk are then rotated and the grindstone is lowered to thin the chip bonded to the support substrate to the same thickness.

[0113] The rotation speed (between 100 and 3000 rpm) and the wheel descent speed (between 0.01 and 50 μm / s) are adapted depending on the material and the thickness to be removed. Various descent speeds can be combined during this process. The rotation speed of the chuck can be between 100 and 300 rpm.

[0114] [Chemical Mechanical Polishing (CMP) on Trimmed Intermediate Substrate] The intermediate substrate 110 covered by the array of chips 121, 122 can be subjected to a chemical mechanical polishing (CMP) step.

[0115] This CMP step is used to compensate for the roughness after grinding.

[0116] The intermediate substrate 110 is then subjected to a buffering and then cleaning process so that the surfaces of the chips 121, 122 are compatible with direct bonding.

[0117] [Transfer of chip to receptor substrate] The resulting structure 100 can be used to transfer the chips 121, 122 to a receptor substrate or a final substrate.

[0118] For example, the chips 121, 122 are transferred to a receptor substrate by performing embedding, bonding, and fracturing steps.

[0119] Offset transfer structures (i.e., one in which the alignment is offset from the crystal planes of the intermediate substrate 110) and aligned structures (i.e., one in which the alignment is aligned according to the crystal planes of the intermediate substrate 110) have been fabricated. [Explanation of symbols]

[0120] 40 adhesive film 50 diameter 75 diameter 100 Chip transfer structure 110 Intermediate board 120 boards 121 chips 122 chips

Claims

1. The following steps: i) providing an intermediate substrate (110) having a first surface; ii) bonding chips (121, 122) to the first surface of the intermediate substrate (110), the chips (121, 122) covering both the central region and the peripheral region of the first surface of the intermediate substrate (110), the chip (122) covering the peripheral region protruding from the surface of the intermediate substrate (110); A method for manufacturing a chip transfer structure (100), comprising: The method also comprises, after step ii), a trimming step iii) in which the ends of the chips (122) protruding from the first surface of the intermediate substrate (110) are removed, whereby the chips (122) in the peripheral region are trimmed and a transfer structure (100) is obtained comprising an intermediate substrate (110) covered by a pseudo donor substrate formed by an array of chips (121, 122), The method, characterized in that the arrangement of the chips (121, 122) is offset from the crystal plane of the intermediate substrate (110).

2. 2. The method of claim 1, wherein the crystal planes of the chips (121, 122) are not aligned with the crystal planes of the intermediate substrate (110).

3. 3. A method according to claim 1 or claim 2, characterized in that step iii) is carried out by trimming and / or grinding.

4. Method according to any one of claims 1 to 3, characterized in that the method comprises, after step ii), a step iv) of thinning the chips (121, 122).

5. 5. The method of claim 4, wherein step iii) is performed after step iv).

6. Method according to any one of claims 1 to 5, characterized in that the chips (121, 122) are bonded to the intermediate substrate (110) by direct bonding.

7. The method according to any one of claims 1 to 6, characterized in that the chips (122) covering the peripheral area are different from the chips (121) covering the central area, for example by having a different quality, a different material and / or different dimensions.

8. A chip transfer structure (100) comprising an intermediate substrate (110) covered with a pseudo-donor substrate formed by an array of chips (121, 122), the chips (121, 122) being bonded to a first surface of the intermediate substrate (110); A chip transfer structure, characterized in that the chips (121, 122) cover both the central region and the peripheral region of the first surface of the intermediate substrate (110), the chips (122) positioned in the peripheral region are trimmed so as not to protrude from the first surface of the intermediate substrate (110), and the arrangement of the chips (121, 122) is offset from the crystal plane of the intermediate substrate (110).

9. 9. The structure of claim 8, wherein the crystal planes of the chips (121, 122) are not aligned with the crystal planes of the intermediate substrate (110).

10. 10. A structure according to claim 8 or 9, characterized in that the intermediate substrate (110) is made of silicon and the chips (121, 122) are made of InP.

11. The following steps: a) providing a transfer structure (100) as defined in any one of claims 8 to 10, comprising an intermediate substrate (110) covered by a pseudo donor substrate formed by an array of chips (121, 122), said chips (121, 122) being bonded to a first surface of said intermediate substrate (110); the chips (121, 122) cover both the central region and the peripheral region of the first surface of the intermediate substrate (110), the chips (122) located in the peripheral region are truncated so as not to protrude from the first surface of the intermediate substrate (110), and the arrangement of the chips (121, 122) is offset from the crystal plane of the intermediate substrate (110); b) transferring a layer of said pseudo-donor substrate to a receptor substrate; A method for transferring a chip, comprising:

12. 12. The method of transferring chips according to claim 11, wherein the crystal planes of the chips (121, 122) are not aligned with the crystal planes of the intermediate substrate (110).

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