Solid-state variable impedance devices and systems

Abstract

Embodiments disclosed herein include an impedance matching network. In one embodiment, the impedance matching network includes an input and a first matrix adjustment element on a first branch from the input, the first matrix adjustment element having a variable capacitance. In one embodiment, the impedance matching network further includes a transformer on a second branch from the input, the transformer having at least a first tap, a second matrix adjustment element on the first tap, and the second matrix adjustment element having a variable capacitance. In one embodiment, the impedance matching network further includes a third matrix adjustment element on the second branch after the transformer, the third matrix adjustment element having a variable capacitance. In one embodiment, the impedance matching network further includes an output on the second branch after the third matrix adjustment element.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Patent Application No. 17 / 941,976, filed September 9, 2022, the entire contents of which are incorporated herein by reference.

[0002] Embodiments relate to the field of semiconductor manufacturing, and in particular to solid-state variable impedance matching systems for plasma processing systems. [Background technology]

[0003] In many semiconductor processing tools, such as plasma processing tools, an RF source is used to couple power into a chamber. The RF power can induce a plasma to process a substrate in the chamber. Due to impedance mismatch, a portion of the forward power is reflected back to the RF source. Therefore, many processing tools include an impedance matching network to match the impedance of a load in the chamber.

[0004] Typically, impedance matching networks rely on electromechanical tuning systems, which may include a vacuum variable capacitor driven by a motor, such as a servomotor. Electromechanical tuning systems are popular in high-power applications due to their excellent voltage and current handling attributes. However, electromechanical tuning systems are slow; that is, they can only operate as fast as the motor drive, which is several orders of magnitude slower than the ion transition rate across the plasma sheath.

[0005] Solid-state impedance matching networks have been proposed as an alternative to electromechanical systems. Solid-state solutions have improved speed compared to electromechanical systems. However, existing solid-state impedance matching networks have several drawbacks. For example, the voltage / current handling capability and resolution of solid-state solutions may not be as good as electromechanical systems. Furthermore, solid-state impedance matching systems are significantly more expensive than electromechanical systems. Summary of the Invention

[0006] Embodiments disclosed herein include an impedance matching network. In one embodiment, the impedance matching network includes an input and a first matrix tuning element on a first branch from the input, the first matrix tuning element having a variable capacitance. In one embodiment, the impedance matching network further includes a transformer on a second branch from the input, the transformer having at least a first tap, a second matrix tuning element on the first tap, and the second matrix tuning element having a variable capacitance. In one embodiment, the impedance matching network further includes a third matrix tuning element after the transformer on the second branch, the third matrix tuning element having a variable capacitance. In one embodiment, the impedance matching network further includes an output on the second branch after the third matrix tuning element.

[0007] Embodiments disclosed herein may also include a matrix adjustment element, in one embodiment, comprising one or more cells, each cell comprising an array of diodes coupled to a board, the array comprising one or more columns of diodes, each column comprising four rows of diodes connected in series.

[0008] Embodiments disclosed herein may also include a semiconductor processing tool. In one embodiment, the semiconductor processing tool includes a chamber, an RF source, an electrode coupled to the RF source for inducing RF power in the chamber, and an impedance matching network coupled between the RF source and the electrode. In one embodiment, the impedance matching network includes a first matrix adjustment element on a first branch, the first matrix adjustment element having a variable capacitance, and a transducer on a second branch, the transducer having at least a first tap, a second matrix adjustment element on the first tap, and the second matrix adjustment element having a variable capacitance. In one embodiment, the impedance matching network further includes a third matrix adjustment element on the second branch after the transducer, the third matrix adjustment element having a variable capacitance. [Brief explanation of the drawings]

[0009] [Figure 1A] FIG. 1 is a perspective view of a solid-state impedance-tuning cell, according to one embodiment. [Figure 1B] FIG. 1 is a perspective view of a solid matrix conditioning element, according to one embodiment. [Figure 2A] FIG. 10 is a circuit diagram of a string of diodes in an impedance-tuning cell, according to one embodiment. [Figure 2B] FIG. 1 is a circuit diagram of a matrix adjustment element, according to one embodiment. [Figure 3A] FIG. 1 is a circuit diagram of a solid-state impedance tuning network with multiple variable capacitors, each of which may be a cell or matrix tuning element, according to one embodiment. [Figure 3B] FIG. 1 is a circuit diagram of a converter for a solid-state impedance tuning network including multiple taps, according to one embodiment. [Figure 4A] FIG. 10 is a circuit diagram of a solid-state impedance tuning network with multiple variable capacitors, each of which may be a cell or matrix tuning element, according to an additional embodiment. [Figure 4B]FIG. 10 is a circuit diagram of a solid-state impedance tuning network with multiple variable capacitors, each of which may be a cell or matrix tuning element, according to an additional embodiment. [Figure 5A] 1 is a graph of capacitance versus mechanical displacement for an electromechanical impedance matching network, according to one embodiment. [Figure 5B] 1 is a graph of capacitance versus DC voltage for a solid state impedance matching network, according to one embodiment. [Figure 6] 1 is a cross-sectional view of a semiconductor processing tool including one or more solid state impedance matching networks, according to one embodiment. [Figure 7] FIG. 1 is a block diagram of an exemplary computer system that may be used with a processing tool, according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] The systems described herein include solid-state variable impedance matching systems for plasma processing systems. In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. It will be apparent to those skilled in the art that the embodiments may be practiced without these specific details. In other instances, well-known aspects are not described in detail so as not to unnecessarily obscure the embodiments. Furthermore, it should be understood that the various embodiments shown in the accompanying drawings are illustrative representations and are not necessarily drawn to scale.

[0011] As mentioned above, solid-state impedance matching networks have the advantage of being tuned faster than electromechanical impedance matching networks. For example, the change in capacitance of the solid-state impedance matching networks described herein is controlled by changing the DC bias voltage coupled to the circuit. A limitation on the DC bias voltage used to vary the capacitance of the diode cell configuration is the rise time of the DC power supply. Also, the current draw for the DC power is a function of the rise time. Reverse biasing of diodes, such as those used herein, requires low current, and DC power rise times are expected to be less than 10 μs. Such short rise times are consistent with the RF pulsing requirements of plasma processing tools.

[0012] In addition to improved tuning speed, the embodiments disclosed herein have improved resolution. Resolution is improved by diode cells configured to vary capacitance with a reverse-biased DC voltage. The DC bias voltage resolution is equivalent to a radial electromechanical motor driver. Additionally, voltage and current handling capacity are improved. As used herein, silicon devices are distributed in a cell configuration to achieve higher current applications. The cells can be configured with impedance transformation circuits to reduce voltage stress.

[0013] In one embodiment, the complexity of the solid-state impedance matching network disclosed herein is also minimized. In particular, adjusting the DC bias circuit is similar to the motor drive method in electromechanical systems. Furthermore, the cost of the solid-state impedance matching network disclosed herein is reduced compared to existing solid-state solutions. In particular, common diodes used for impedance matching cells are suitable for this application. This bridges the cost gap between electromechanical and solid-state solutions.

[0014] As described in more detail below, the lowest-level building block of the variable capacitor used in the solid-state impedance matching network is a diode. Specifically, a set of four diodes electrically in series is provided in a column on the board. Multiple columns may be provided electrically in parallel to form an impedance adjustment cell (or simply cell for short). In one embodiment, multiple cells may be coupled to each other to form a matrix adjustment element. As can be appreciated, scaling diodes to multiple columns and / or multiple cells enables improved resolution and dynamic range of the impedance matching network. In one embodiment, multiple variable capacitors may be configured in a circuit to provide the desired adjustment of the impedance matching network. In one embodiment, the variable capacitors may each have a variable capacitance. That is, each variable capacitor may have a capacitance range that can be obtained through control of the variable capacitor (e.g., by a DC bias voltage). In some cases, each variable capacitor may have a different capacitance range, or two or more of the variable capacitors may have the same capacitance range.

[0015] 1A, a perspective view of an impedance matching cell 100 is shown, according to one embodiment. In one embodiment, the impedance matching cell 100 comprises a plurality of diodes 121 coupled to a board 101, such as a printed circuit board (PCB). The diodes 121 may be arranged in an array. For example, the array may include a plurality of columns 120, each column 120 comprising four rows. As described in more detail below, each column 120 of the four rows provides a building block for an impedance matching network. In the illustrated embodiment, eight columns 120 are shown in FIG. 1. However, it should be appreciated that in some embodiments, one or more columns 120 may be used. Increasing the number of columns 120 increases the resolution achievable by the impedance matching cell 100.

[0016] In one embodiment, each of the columns 120 may be electrically coupled to one another in electrical parallel. An input may be provided proximate a top edge of the board 101, and an output may be provided proximate a bottom edge of the board 101. The input may be coupled to an RF power source, and the output may be coupled to a load, such as a plasma load of a semiconductor processing tool. Additionally, as disclosed in more detail below, a first capacitor may be provided between the column 120 and the input, and a second capacitor may be provided between the column 120 and the output.

[0017] In addition to a single impedance matching cell 100, multiple impedance matching cells 100 can be coupled together to provide a matrix adjustment element. That is, a matrix adjustment element can be a construct that includes two or more impedance matching cells 100. For example, a matrix adjustment element can include up to five impedance matching cells 100. However, it should be appreciated that even more impedance matching cells 100 can be included in a matrix adjustment element.

[0018] 1B, a perspective view of a matrix adjustment element 105 is shown, according to one embodiment. The matrix adjustment element 105 comprises multiple impedance matching cells 100 electrically coupled to one another. Thus, impedance adjustment can be scaled to larger matrix adjustment elements 105 to improve the resolution and capacitance range of the system. While four impedance matching cells 100 are shown in FIG. 1B, it should be appreciated that the matrix adjustment element 105 can include two or more impedance matching cells 100.

[0019] 2A, a circuit diagram of a string 220 of an impedance-matching cell 100 is shown, according to one embodiment. In one embodiment, the string 220 may include a set of four diodes 221A and 221B connected in series between a first capacitor 213 and a second capacitor 215. The input 212 may be coupled to the first capacitor 213, and the output 214 may be coupled to the second capacitor 215. In one embodiment, the diodes 221 may be configured as cathodes 221A or anodes 221B. The configuration between the first capacitor 213 and the second capacitor 215 may include a pattern of cathode diodes 221A, anode diodes 221B, cathode diodes 221A, and anode diodes 221B. The diodes 221 may be substantially similar to one another in some embodiments. In other embodiments, the diodes 221 may have different IV characteristics.

[0020] In one embodiment, a ground connection 223 may be provided between the first capacitor 213 and the first cathode diode 221A and between the second anode diode 221B and the second capacitor 215. A resistor 224 may be provided before each ground connection 223. In one embodiment, DC bias inputs 222A and 222B may be provided between the first cathode diode 221A and the first anode diode 221B and between the second cathode diode 221A and the second anode diode 221B. A resistor 224 may be provided before each DC bias input 222A and 222B. Control of the DC bias at the DC bias input 222 allows the value of the capacitance of the string 220 to be adjusted to provide a desired impedance matching value. In the illustrated embodiment, a resistor 224 is provided before each of the DC biases 222A and 222B. However, it should be appreciated that any high-impedance passive device(s) may be provided before the DC biases 222A and 222B. Specifically, the high-impedance passive device prevents RF power from flowing to the DC biases 222A and 222B. In one embodiment, the two DC bias inputs 222A and 222B may have the same DC bias applied to them. In other embodiments, the DC bias of the first DC bias input 222 may be different from the DC bias of the second DC bias input 222. In other embodiments, the bias applied to the DC biases 222A and 222B may be a differential bias, a pulsed bias, or the like. More specifically, the bias to the DC biases 222A and 222B is not limited to a particular waveform. Furthermore, it should be appreciated that each string 120 in the impedance matching cell 100 may be independently controllable to provide the impedance matching cell 100 with a desired value of capacitance.

[0021] 2B, a circuit diagram of a pair of columns 2201 and 2202 is shown, according to one embodiment. As shown, multiple columns 220 may be coupled in parallel between the RF input 212 and the RF output 214. The individual columns 2201 and 2202 may be substantially similar to the columns 220 described in more detail above with respect to FIG. 2A. While two columns 2201 and 2202 are shown, it should be appreciated that any number of columns 220 may be provided in parallel between the RF input 212 and the RF output 214.

[0022] 3A, a circuit diagram of an impedance matching network 350 is shown, according to one embodiment. In one embodiment, the impedance matching network 350 may be a solid-state impedance matching network 350. That is, impedance control is provided by solid-state components such as diodes, as opposed to an electromechanical solution that uses motors to drive different capacitances. The circuit between the input 312 and the output 314 may be considered a conditioning circuit 305.

[0023] In one embodiment, impedance matching network 350 comprises an input 312 and an output 314. Input 312 receives power from an RF source (not shown), and output 314 delivers RF power to a load (not shown), such as a plasma load in a semiconductor processing chamber.

[0024] In one embodiment, the input 312 splits into a first branch 331 and a second branch 332. The first branch 331 includes a first variable capacitor C1, an inductor 335, and a ground 336. The first variable capacitor C1 may be a matrix tuning element. That is, the first variable capacitor C1 may comprise a solid-state impedance tuning cell similar to the impedance tuning cell 100 described in more detail above. Thus, the capacitance of the first variable capacitor C1 is controlled by a pair of DC biases. The first branch 331 may then proceed to an inductor 335, which has an output coupled to the ground 336.

[0025] In one embodiment, the second branch 332 includes a transformer circuit 306. The transformer circuit 306 may include a transformer 337. In one embodiment, the transformer 337 includes a single tap. However, as described in more detail below, the transformer 337 may include multiple taps. In one embodiment, a first end of the tap includes a third variable capacitor C3. The third variable capacitor C3 may be a matrix tuning element. That is, the third variable capacitor C3 may comprise a solid-state impedance tuning cell, similar to the impedance tuning cell 100 described in more detail above. Thus, the capacitance of the third variable capacitor C3 is controlled by a pair of DC biases. An output of the third variable capacitor C3 may be coupled to ground 336. A second, opposite end of the tap may be directly coupled to ground 336.

[0026] In one embodiment, a second variable capacitor C2 may be provided along the second branch 332 between the converter 337 and the output 314. The second variable capacitor C2 may be a matrix tuning element. That is, the second variable capacitor C2 may comprise a solid-state impedance tuning cell, similar to the impedance tuning cell 100 described in more detail above. Thus, the capacitance of the second variable capacitor C2 is controlled by a pair of DC biases.

[0027] It should be appreciated that multiple variable capacitors (e.g., C1, C2, and C3) may be independently controlled. Thus, various capacitance values ​​may be used to set a desired impedance in the impedance matching network. In some embodiments, all three of the variable capacitors C1, C2, and C3 are formed with solid-state impedance tuning cells or matrix tuning elements. In other embodiments, two or one of the variable capacitors C1, C2, and C3 may include solid-state impedance tuning cells or matrix tuning elements. Other variable capacitors may include electromechanical variable capacitors. That is, embodiments may include both solid-state and electromechanical variable capacitors. Furthermore, it should be appreciated that the variable capacitors C1, C2, and C3 need not have the same range of capacitance. That is, the capacitance range of C1 may be different from the capacitance range of C2 and / or C3, the capacitance range of C2 may be different from the capacitance range of C1 and / or C3, and the capacitance range of C3 may be different from the capacitance range of C1 and / or C2.

[0028] Referring now to FIG. 3B, a circuit diagram of transformer circuit 306 is shown according to an additional embodiment. In one embodiment, transformer circuit 306 may be substituted into impedance matching network 350 described above with respect to FIG. 3A. In one embodiment, transformer circuit 306 may include multiple taps. For example, three taps are provided in FIG. 3B, although it should be appreciated that two or more taps may be included in different embodiments. In one embodiment, inductor 337 may be coupled to inductors 341-343. Each of inductors 341-343 may be a different tap.

[0029] In one embodiment, each of the taps includes an inductor 341-343 and a variable capacitor C1-C3. Each of the variable capacitors C1-C3 may be similar to any of the variable capacitors described in more detail above. For example, the variable capacitors C1-C3 may comprise matrix tuning elements. That is, the variable capacitors C1-C2 may comprise solid-state impedance tuning cells similar to the impedance tuning cell 100 described in more detail above. Thus, the capacitance of the variable capacitors C1-C3 is each controlled by a pair of DC biases. In one embodiment, each of the taps may further include a pair of grounds 336 on either side of the inductors 341-343. On one side, the outputs of the inductors 341-343 are directly coupled to the ground 336. The variable capacitors C1-C3 are provided between the inductors 341-343 and the ground 336 on the other side of the inductors 341-343.

[0030] In one embodiment, inductors 341-343 may have non-uniform inductances. In other embodiments, inductors 341-343 may have the same inductance. Similarly, variable capacitors C1-C3 may be uniform, or variable capacitors C1-C3 may have different capacitance ranges.

[0031] 4A, a circuit diagram of an impedance matching network 450 is shown according to an additional embodiment. In one embodiment, the impedance matching network 450 may comprise an input 412 and an output 414. The input 412 may be coupled to an RF source, and the output 414 may be coupled to a load, such as a plasma load in a semiconductor processing tool. In one embodiment, the impedance matching network 450 may comprise a first branch 431 and a second branch 432.

[0032] The first branch 431 may include a first variable capacitor C1. A transformer 437 may then be coupled to the output of the first variable capacitor C1. The transformer 437 may have a single tap coupled to a second variable capacitor C2. The single tap may have two ends coupled to ground 436. In one embodiment, the first branch 431 may also terminate at ground 436. In one embodiment, the second branch 431 may include a third variable capacitor C3. An inductor 438 may be provided after the third variable capacitor C3.

[0033] In one embodiment, variable capacitors C1-C3 may each be a capacitance adjustment cell, or multiple cells to form a matrix adjustment element. Variable capacitors C1-C3 may include different capacitance ranges in some embodiments. In other embodiments, two or more of variable capacitors C1-C3 may have the same capacitance range.

[0034] 4B, a circuit diagram of an impedance matching network 450 is shown according to an additional embodiment. In one embodiment, the impedance matching network 450 may comprise an input 412 and an output 414. The input 412 may be coupled to an RF source, and the output 414 may be coupled to a load, such as a plasma load in a semiconductor processing tool. In one embodiment, the impedance matching network 450 may comprise a first branch 431, a second branch 432, and a third branch 433.

[0035] The first branch 431 may include a first variable capacitor C1. An inductor 439 may then be coupled to the output of the first variable capacitor C1. In one embodiment, the first branch 431 may terminate at ground 436. In one embodiment, the second branch 432 may include a transformer 437. The transformer 437 may have a single tap coupled to the second variable capacitor C2. The single tap may have two ends coupled to ground 436. In one embodiment, the second branch 432 may also terminate at ground 436. In one embodiment, the third branch 433 may include a third variable capacitor C3. An inductor 438 may be provided after the third variable capacitor C3.

[0036] In one embodiment, variable capacitors C1-C3 may each be a capacitance adjustment cell, or multiple cells to form a matrix adjustment element. Variable capacitors C1-C3 may include different capacitance ranges in some embodiments. In other embodiments, two or more of variable capacitors C1-C3 may have the same capacitance range.

[0037] 5A and 5B, graphs of capacitance versus mechanical displacement (FIG. 5A) and capacitance versus DC bias voltage (FIG. 5B) are shown, according to one embodiment. FIG. 5A is a graph for an electromechanical tuning system, and FIG. 5B is a graph for a solid-state tuning system, such as those described herein. As shown in FIG. 5A, the capacitance resolution is high; that is, there is a substantially continuous output. Such a capacitance relationship allows for fine tuning of the impedance. In existing solid-state solutions, the output of the capacitance graph is not continuous, leading to poor resolution.

[0038] However, in the embodiments disclosed herein, the capacitance graph is continuous. An example of capacitance versus DC bias voltage is shown in FIG. 5B. As shown, there is high resolution, allowing for fine tuning of the impedance, similar to the electromechanical solution plotted in FIG. 5A. Furthermore, the curve in FIG. 5B is relatively smooth. Therefore, the performance of the solid-state solutions described herein can substantially match that of electromechanical solutions. However, as explained above, the solid-state solutions described herein have response times that are several orders of magnitude faster than those of electromechanical solutions. Therefore, the embodiments disclosed herein include improved resolution and improved response times compared to existing solutions.

[0039] 6, a cross-sectional view of a semiconductor processing tool 680 is shown, according to one embodiment. In one embodiment, the semiconductor processing tool 680 may include a chamber 681. The chamber 681 may be suitable for supporting a low-pressure environment, such as near-vacuum pressure. In one embodiment, a pump and exhaust system may be included (not shown) to obtain the low-pressure environment. In one embodiment, one or more process gases may be flowed into the chamber. For example, the process gases may be flowed into the chamber 681 through a lid 685. The lid 685 may be a showerhead-type component to more evenly distribute the gases throughout the chamber 681.

[0040] In one embodiment, the chamber 681 may comprise a pedestal 682. The pedestal 682 may be suitable for supporting a substrate 683. The pedestal 682 may include heating and / or cooling features to control the temperature of the substrate 683 during processing. The substrate 683 may be coupled to the pedestal 682 using any suitable chucking mechanism. For example, an electrostatic chuck, a vacuum chuck, or the like may be used to secure the substrate 683. The substrate 683 may be any substrate processed in the semiconductor processing tool 680. For example, the substrate 683 may comprise a semiconductor wafer, such as a silicon wafer. However, other semiconductor materials may also be used. In one embodiment, the wafer has a standard form factor, such as 150 mm, 200 mm, 300 mm, 450 mm, or the like. In one embodiment, other substrates (e.g., glass, sapphire, etc.) may also be processed in the chamber 681.

[0041] In one embodiment, an RF source 686 may be coupled to the chamber 681. Specifically, the RF source 686 may be coupled to the lid 685 or other electrode in the chamber 681. The RF source 686 produces RF power that may be coupled to processing gases in the chamber 681 to form a plasma 684 for processing the substrate 683. An impedance match network 687 may be provided between the RF source 686 and the lid 685 to maximize forward power into the chamber 681 (with minimal reflected power).

[0042] In one embodiment, the impedance matching network 687 may be substantially similar to any of the impedance matching networks described in more detail herein. In particular, the impedance matching network 687 may be a solid-state impedance matching network 687. For example, the impedance matching network 687 may include a variable capacitor formed of an array of diodes. The array of diodes may be configured in four rows with any number of parallel columns on a board to form a cell. Multiple cells may be coupled to each other to form a matrix adjustment element. The capacitance (i.e., the variable capacitance) of the variable capacitor may be controlled by a DC bias voltage. As described above, the rise time of the DC bias voltage may be approximately 10 μs or less. Thus, agile and precise control of the variable capacitance is enabled to control the impedance of the impedance matching network 687. In one embodiment, the variable capacitors may each have a variable capacitance. That is, each variable capacitor may have a capacitance range that can be obtained through control of the variable capacitor (e.g., by a DC bias voltage). In some cases, each variable capacitor may have a different capacitance range, or two or more of the variable capacitors may have the same capacitance range.

[0043] In one embodiment, the semiconductor processing tool 680 may also include a second RF source 688. The second RF source 688 may be coupled to the pedestal 682 and / or the substrate 683. The second RF source 688 may be used in conjunction with the RF source 686. In other embodiments, the second RF source 688 may be used in place of the RF source 686. The second RF source 686 may be coupled to the chamber through a second impedance match network 689.

[0044] In one embodiment, the second impedance matching network 689 may be substantially similar to any of the impedance matching networks described in more detail herein. In particular, the second impedance matching network 689 may be a solid-state impedance matching network 689. For example, the second impedance matching network 689 may include a variable capacitor formed of an array of diodes. The diode array may be configured in four rows with any number of parallel columns on a board to form a cell. Multiple cells may be coupled to each other to form a matrix tuning element. The capacitance of the variable capacitor may be controlled by a DC bias voltage. As described above, the rise time of the DC bias voltage may be approximately 10 μs or less. Thus, agile and precise control of the variable capacitance is enabled to control the impedance of the second impedance matching network 689.

[0045] Referring now to FIG. 7 , a block diagram of an exemplary computer system 700 of a processing tool is shown, according to one embodiment. In one embodiment, the computer system 700 is coupled to the processing tool and controls processing in the processing tool. The computer system 700 may be connected (e.g., networked) to other machines in a local area network (LAN), an intranet, an extranet, or the Internet. The computer system 700 may operate in the capacity of a server machine or a client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The computer system 700 may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a web appliance, a server, a network router, switch, or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by the machine. Furthermore, although only a single machine is shown for computer system 700, the term "machine" is also intended to include any collection of machines (e.g., computers) that individually or together execute a set (or sets) of instructions to perform any one or more of the methodologies described herein.

[0046] Computer system 700 may include a computer program product, or software 722, having a non-transitory machine-readable medium having instructions stored thereon, which can be used to program computer system 700 (or other electronic devices) to perform a process according to an embodiment. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, machine-readable (e.g., computer-readable) media includes machine- (e.g., computer) readable storage media (e.g., read-only memory (“ROM”), random-access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices, etc.), machine- (e.g., computer) readable transmission media (electrical, optical, acoustic, or other forms of propagated signals (e.g., infrared signals, digital signals, etc.)), etc.

[0047] In one embodiment, computer system 700 includes a system processor 702, a main memory 704 (e.g., read only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), a static memory 706 (e.g., flash memory, static random access memory (SRAM)), and a secondary memory 718 (e.g., a data storage device), which communicate with each other via a bus 730.

[0048] The system processor 702 represents one or more general-purpose processing devices, such as a microsystem processor, a central processing unit, etc. More specifically, the system processor may be a complex instruction set computing (CISC) microsystem processor, a reduced instruction set computing (RISC) microsystem processor, a very long instruction word (VLIW) microsystem processor, a system processor implementing other instruction sets, or a system processor implementing a combination of instruction sets. The system processor 702 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal system processor (DSP), a network system processor, etc. The system processor 702 is configured to execute processing logic 726 for performing the operations described herein.

[0049] The computer system 700 may further include a system network interface device 708 for communicating with other devices or machines. The computer system 700 may also include a video display unit 710 (e.g., a liquid crystal display (LCD), a light emitting diode display (LED), or a cathode ray tube (CRT)), an alphanumeric input device 712 (e.g., a keyboard), a cursor control device 714 (e.g., a mouse), and a signal generation device 716 (e.g., a speaker).

[0050] The secondary memory 718 may include a machine-accessible storage medium 732 (or more specifically, a computer-readable storage medium) having stored thereon one or more sets of instructions (e.g., software 722) embodying any one or more of the methodologies or functions described herein. The software 722 may also reside completely or at least partially within the main memory 704 and / or within the system processor 702 during execution of the software 722 by the computer system 700, with the main memory 704 and the system processor 702 also comprising machine-readable storage media. The software 722 may further be transmitted or received over the network 720 via the system network interface device 708. In one embodiment, the network interface device 708 may operate using RF, optical, acoustic, or inductive coupling.

[0051] While machine-accessible storage medium 732 is shown to be a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be interpreted to include a single medium or multiple media (e.g., centralized or distributed databases, and / or associated caches and servers) that store one or more sets of instructions. The term "machine-readable storage medium" should also be interpreted to include any medium that is capable of storing or encoding a set of instructions for execution by a machine, causing the machine to perform any one or more of the methodologies. The term "machine-readable storage medium" should therefore be interpreted to include, but is not limited to, solid-state memories and optical and magnetic media.

[0052] In the foregoing specification, certain exemplary embodiments have been described. It will be apparent that various modifications may be made thereto without departing from the scope of the following claims. The specification and drawings are, therefore, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. An impedance matching network comprising: Input and a first matrix adjustment element on a first branch from the input, the first matrix adjustment element comprising a first variable capacitance; a transducer on a second branch from the input, the transducer having at least a first tap, a second matrix adjustment element on the first tap, the second matrix adjustment element comprising a second variable capacitance; a third matrix adjustment element on the second branch after the converter, the third matrix adjustment element comprising a third variable capacitance; an output after the third matrix adjustment element on the second branch; An impedance matching network comprising:

2. 2. The impedance matching network of claim 1, wherein the first matrix adjustment element, the second matrix adjustment element, and the third matrix adjustment element are identical to each other.

3. 2. The impedance matching network of claim 1, wherein two or more of the first matrix adjustment elements, the second matrix adjustment elements, and the third matrix adjustment elements are different from one another.

4. 2. The impedance matching network of claim 1, wherein the first matrix adjustment element, the second matrix adjustment element, and the third matrix adjustment element each comprise at least four diodes connected in series with each other.

5. 5. The impedance matching network of claim 4, wherein the four diodes include a first cathode diode, a first anode diode, a second cathode diode, and a second anode diode.

6. 6. The impedance matching network of claim 5, wherein a ground connection is provided before the first cathode diode and after the second anode diode.

7. 6. The impedance matching network of claim 5, wherein a first DC bias is connected between the first cathode diode and the first anode diode, and a second DC bias is connected between the second cathode diode and the second anode diode.

8. 8. The impedance matching network of claim 7, wherein the first DC bias and the second DC bias are differential biases or pulse biases.

9. One or more of the first matrix adjustment element, the second matrix adjustment element, and the third matrix adjustment element are An impedance adjustment cell having two or more columns of diodes, each column comprising four rows of said diodes connected in series.

10. The impedance matching network of claim 1, comprising:

10. 9. The impedance matching network of claim 8, wherein two or more strings of diodes are electrically in parallel.

11. The impedance matching network of claim 8 , wherein the matrix tuning elements each comprise a plurality of impedance tuning cells.

12. 10. The impedance matching network of claim 1, wherein the transformer comprises three or more taps, each tap including a matrix tuning element.

13. The impedance matching network of claim 1 , wherein the output is coupled to a plasma processing tool and the input is coupled to an RF power source.

14. 2. The impedance matching network of claim 1, wherein at least one of the first matrix adjustment element, the second matrix adjustment element, and the third matrix adjustment element is a solid-state device, and at least one of the first matrix adjustment element, the second matrix adjustment element, and the third matrix adjustment element is an electromechanical device.

15. A matrix adjustment element, One or more cells each cell comprising: an array of diodes coupled to a board, said array comprising one or more columns of diodes, each column comprising four rows of diodes connected in series; A matrix adjustment element comprising:

16. The four rows of diodes are: a first cathode diode; a first anode diode; a second cathode diode; a second anode diode; The matrix adjustment element of claim 15 comprising:

17. 17. The matrix adjustment element of claim 16, wherein a first DC bias connection is provided between the first cathode diode and the first anode diode, and a second DC bias connection is provided between the second cathode diode and the second anode diode.

18. 1. A semiconductor processing tool comprising: a chamber; an RF source; and an electrode coupled to the RF source for inducing RF power in the chamber; an impedance matching network coupled between the RF source and the electrode, the impedance matching network comprising: a first matrix adjustment element on the first branch, the first matrix adjustment element comprising a first variable capacitance; a transducer on the second branch, the transducer having at least a first tap, a second matrix adjustment element on the first tap, the second matrix adjustment element comprising a second variable capacitance; a third matrix adjustment element on the second branch after the converter, the third matrix adjustment element comprising a third variable capacitance; and an impedance matching network comprising:

1. A semiconductor processing tool comprising:

19. 20. The semiconductor processing tool of claim 18, wherein the first matrix adjustment element, the second matrix adjustment element, and the third matrix adjustment element each comprise a plurality of cells, each cell comprising a plurality of columns of diodes, each column comprising four rows of diodes coupled in series with each other.

20. 20. The semiconductor processing tool of claim 18, wherein the first matrix adjustment element, the second matrix adjustment element, and the third matrix adjustment element have variable capacitance controlled by a DC bias.

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