Semiconductor element manufacturing method

Abstract

The present invention relates to a method for manufacturing a semiconductor device. According to one embodiment, a method for manufacturing a semiconductor device may include forming a thin film structure on a substrate, forming a through hole through the thin film structure, forming a channel layer covering at least a portion of the through hole, performing a high-pressure surface treatment process on the channel layer, and performing an insulating layer formation process on the channel layer. In one embodiment, performing the high-pressure surface treatment process may include performing a high-pressure nitridation (HPN) process.

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] Semiconductor devices are components primarily used in electronic circuits and similar devices that utilize the electrical conductivity properties of semiconductors. Semiconductors can be divided into memory semiconductors and non-memory semiconductors. Memory semiconductors can be divided into volatile memory such as DRAM and SRAM, and non-volatile memory such as Mask ROM, EP ROM, EEP ROM, and flash memory.

[0003] 1 and 2 show a typical manufacturing process for a semiconductor device.

[0004] Referring initially to FIG. 1, insulating layers 110 and gate layers 112 may be alternately and repeatedly deposited on a substrate 100 to form a thin film structure (TS).

[0005] Next, a through-hole (H) can be formed that penetrates the thin film structure (TS) and exposes the substrate 100. The through-hole (H) may be formed two-dimensionally on the upper surface of the thin film structure (TS) from a planar perspective.

[0006] Next, a semiconductor pattern (SP) may be formed to cover at least a portion of the through-hole (H) and expose the substrate 100. The semiconductor pattern (SP) may include a blocking layer 120 that covers at least a portion of the through-hole (H), a charge storage layer 130 formed on the blocking layer 120, and a first insulating layer 140 formed on the charge storage layer 130.

[0007] Once the semiconductor pattern (SP) is formed, a channel layer 150 may be formed covering the semiconductor pattern (SP) and the substrate 100, as shown in FIG. 1. The channel layer 150 may be a semiconductor material formed using one of atomic layer deposition (ALD) and chemical vapor deposition (CVD) techniques. The channel layer 150 may be a polycrystalline silicon film, for example. According to one embodiment, the channel layer 150 is amorphous when deposited, but may be crystallized using an annealing process or the like. According to another embodiment, the channel layer 150 may be formed to expose the substrate 100.

[0008] Thereafter, the channel layer 150 may be patterned to form a trench pattern (T) inside the channel layer 150 .

[0009] 2, an insulating layer forming process is performed on the channel layer 150, so that a second insulating layer 160 can be formed inside the trench pattern (T) of the channel layer 150. However, if the second insulating layer 160 is formed without protecting the channel layer 150 during the process of forming the insulating layer 160, a phenomenon occurs in which a portion of the channel layer 150, i.e., a consumed region 170, is consumed during the process of forming the second insulating layer 160.

[0010] As described above, if the thickness of the channel layer 150 is not formed to a certain level due to the occurrence of the consumed region 170 during the manufacturing process of the semiconductor device, the electrical characteristics (e.g., V T Distribution (V T distribution)) can be low.

[0011] In addition, if the conformality of the channel layer 150 is reduced due to the generation of the wasted region 170 during the manufacturing process of the semiconductor device, the electrical characteristics (e.g., V T distribution) can be low. Summary of the Invention [Problem to be solved by the invention]

[0012] The purpose of this specification is to provide a method for manufacturing a semiconductor device that can improve the electrical characteristics of the semiconductor device by reducing the consumed area of ​​the channel layer and improving the conformality of the channel layer during the process of forming an insulating layer after forming the channel layer.

[0013] The objects of the present specification are not limited to those mentioned above, and other objects and advantages of the present specification not mentioned above can be more clearly understood from the examples of the present specification described below. In addition, the objects and advantages of the present specification can be realized by the elements and combinations thereof described in the claims. [Means for solving the problem]

[0014] A method for manufacturing a semiconductor device according to an embodiment may include forming a thin film structure on a substrate, forming a through hole penetrating the thin film structure, forming a channel layer covering at least a portion of the through hole, performing a high-pressure surface treatment process on the channel layer, and performing an insulating layer formation process on the channel layer.

[0015] In an embodiment, the step of performing the high pressure surface treatment process may include a step of performing a high pressure nitridation (HPN) process or a high pressure fluorination (HPF) process.

[0016] In one embodiment, the high pressure surface treatment process can be performed in a treatment apparatus in which a reactive gas containing nitrogen or fluorine is injected in an inert gas atmosphere.

[0017] In one embodiment, when the high pressure surface treatment process is performed, the concentration of the reactive gas in the treatment device may be 1% or more.

[0018] In one embodiment, when the high-pressure surface treatment process is performed, the internal pressure of the treatment device may be maintained at 2 to 100 atmospheres.

[0019] In one embodiment, the internal temperature of the treatment device may be maintained at 200 to 1000°C when the high pressure surface treatment process is performed.

[0020] In one embodiment, a trench pattern may be formed within the channel layer.

[0021] In one embodiment, a second insulating layer may be formed within the trench pattern by an insulating layer forming process on the channel layer.

[0022] The method for manufacturing a semiconductor device according to an embodiment may further include forming a semiconductor pattern between the through hole and the channel layer.

[0023] In one embodiment, the semiconductor pattern may include a blocking layer covering at least a portion of the through hole, a charge storage layer formed on the blocking layer, and a first insulating layer formed on the charge storage layer. [Effects of the Invention]

[0024] According to the method for manufacturing a semiconductor device according to the embodiment, in the process of manufacturing a semiconductor device, after forming a channel layer, a consumed region of the channel layer is reduced and the conformality of the channel layer is improved during the process of forming an insulating layer, thereby improving the electrical characteristics of the semiconductor device. [Brief explanation of the drawings]

[0025] [Figure 1] 1A to 1C are diagrams illustrating a typical manufacturing process of a semiconductor device. [Figure 2] 1A to 1C are diagrams illustrating a typical manufacturing process of a semiconductor device. [Figure 3] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to an embodiment. [Figure 4]1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to an embodiment. [Figure 5] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to an embodiment. [Figure 6] 4 is a graph showing the thickness of a channel layer of a semiconductor device manufactured according to a conventional semiconductor device manufacturing method and the thickness of a channel layer of a semiconductor device manufactured according to an embodiment of the present invention; [Figure 7] 1 is a graph showing the conformality of a channel layer of a semiconductor device fabricated according to a conventional semiconductor device fabrication method and the conformality of a channel layer of a semiconductor device fabricated according to an embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0026] The above-mentioned objects, features, and advantages will be described in detail below with reference to the accompanying drawings, so that those skilled in the art can easily implement the embodiments of the present specification. In describing the present specification, if a detailed description of known technologies related to the present specification is deemed to obscure the gist of the present specification, the detailed description will be omitted. Hereinafter, preferred embodiments of the present specification will be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings indicate the same or similar components.

[0027] 3 to 5 show a manufacturing process of a semiconductor device according to one embodiment.

[0028] Referring now to FIG. 3, insulating layers 210 and gate layers 212 may be alternately and repeatedly deposited on a substrate 200 to form a thin film structure (TS).

[0029] In one embodiment, the substrate 200 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

[0030] In one embodiment, the insulating layer 210 may be a silicon oxide film formed by a thermal oxidation process or a silicon oxide film formed using a deposition technique. In one embodiment, the insulating layers 210 may have the same thickness. In another embodiment, some of the insulating layers 210 may have different thicknesses.

[0031] In one embodiment, gate layer 212 is a conductive material and may be a polycrystalline silicon film, but in other embodiments, gate layer 212 may include a material such as silicide or polycide. In other embodiments, gate layer 212 may include a metal material such as Al, Cu, or W.

[0032] In one embodiment, the insulating layer 210 and the gate layer 212 may be formed using a thermal chemical vapor deposition (thermal CVD), a plasma enhanced chemical vapor deposition (plasma enhanced CVD), a physical chemical vapor deposition (physical CVD), or an atomic layer deposition (ALD) process.

[0033] Next, through-holes (H) may be formed through the thin film structure (TS) to expose the substrate 200. The through-holes (H) may be formed two-dimensionally on the upper surface of the thin film structure (TS) from a planar perspective. Forming the through-holes (H) may include forming a first mask pattern (not shown) having openings that define areas where the through-holes (H) will be formed on the thin film structure (TS), and anisotropically etching the thin film structure (TS) using the first mask pattern as an etching mask. The first mask pattern may be formed of a material that is selective to the insulating layer 210 and the gate layer 212. The etching process may over-etch the upper surface of the substrate 200, resulting in a recess in the upper portion of the substrate 200.

[0034] Next, a semiconductor pattern (SP) may be formed to cover at least a portion of the through-hole (H) and expose the substrate 100. The semiconductor pattern (SP) may include a blocking layer 220 that covers at least a portion of the through-hole (H), a charge storage layer 230 formed on the blocking layer 220, and a first insulating layer 240 formed on the charge storage layer 230. The semiconductor pattern (SP) may be deposited using, for example, plasma enhanced chemical vapor deposition (PCVD), physical chemical vapor deposition (physical CVD), or atomic layer deposition (ALD) techniques.

[0035] After the semiconductor pattern (SP) is formed, a channel layer 250 may be formed to cover the semiconductor pattern (SP) and the substrate 200, as shown in FIG. 3. The channel layer 250 may be a semiconductor material formed using one of atomic layer deposition (ALD) and chemical vapor deposition (CVD) techniques. The channel layer 250 may be a polycrystalline silicon film, for example. According to one embodiment, the channel layer 250 is amorphous when deposited, but may be crystallized using an annealing process or the like. According to another embodiment, the channel layer 250 may be formed to expose the substrate 200.

[0036] In the above-described embodiment, the semiconductor pattern (SP) is formed inside the through hole (H), and then the channel layer 250 is formed on the semiconductor pattern (SP). However, in other embodiments, the semiconductor pattern (SP) may not be formed inside the through hole (H), and only the channel layer 250 may be formed.

[0037] Once the channel layer 250 is formed, a trench pattern (T) may be formed within the channel layer 250 by patterning.

[0038] Next, as shown in FIG. 4, a high pressure surface treatment process is performed on the channel layer 250, so that a protection layer 255 can be formed inside the trench pattern (T) of the channel layer 250.

[0039] In one embodiment, the high pressure surface treatment process performed on the channel layer 250 may include a high pressure nitridation (HPN) process or a high pressure fluorination (HPF) process.

[0040] In one embodiment, the HPN process can be performed in a processing device (eg, a chamber or furnace) in an inert gas atmosphere where reactive gases including nitrogen are injected.

[0041] Examples of inert gases include N2, Ar, and He, but the type of inert gas is not limited to these.

[0042] Examples of reactive gases containing nitrogen include NH2 and NH3, but the types of reactive gases containing nitrogen are not limited to these.

[0043] In one embodiment, when the HPN process is performed, the concentration of the nitrogen-containing reactive gas in the processing equipment may be 1% or more, for example, when the HPN process is performed, the concentration of the nitrogen-containing reactive gas in the processing equipment may be 1% to 100%.

[0044] In one embodiment, when the HPN process is performed, the internal pressure of the processing apparatus may be maintained at 2 to 100 atmospheres.

[0045] In one embodiment, the internal temperature of the processing apparatus may be maintained at 200 to 1000°C when the HPN process is performed.

[0046] In one embodiment, the HPF process can be performed in a processing system in which a reactive gas containing fluorine is injected in an inert gas atmosphere.

[0047] Examples of inert gases include N2, Ar, and He, but the type of inert gas is not limited to these.

[0048] Examples of reactive gases containing fluorine include CF4, C2F6, C3F8, NF3, SF6, WF6, and HF, but the types of reactive gases containing fluorine are not limited to these.

[0049] In one embodiment, when the HPF process is performed, the concentration of the fluorine-containing reactive gas in the processing apparatus may be 1% or more, for example, when the HPF process is performed, the concentration of the fluorine-containing reactive gas in the processing apparatus may be 1% to 100%.

[0050] In one embodiment, when the HPF process is performed, the internal pressure of the processing apparatus may be maintained at 2 to 100 atmospheres.

[0051] In one embodiment, the internal temperature of the processing apparatus may be maintained at 200 to 1000°C when the HPF process is performed.

[0052] 5, a protective layer 255 is formed inside the trench pattern (T) of the channel layer 250 by a high-pressure surface treatment process on the channel layer 250, and an insulating layer formation process is then performed on the channel layer 250, thereby forming a second insulating layer 260 inside the trench pattern (T) of the channel layer 250. Examples of the insulating layer formation process include a deposition process of an insulating material (e.g., SiOx, SiNy, etc.) or an oxidation process on the channel layer 250, but the type of insulating layer formation process is not limited thereto.

[0053] During the process of forming the second insulating layer 260, a portion of the channel layer 250, i.e., a consumed region 270, is consumed during the process of forming the second insulating layer 260. According to one embodiment, during the process of forming the second insulating layer 260, the second insulating layer 260 is formed on top of the protective layer 255 instead of being formed directly on top of the channel layer 250. Therefore, the thickness or volume of the consumed region 270 shown during the process of forming the second insulating layer 260 according to the embodiment is smaller than the thickness or volume of the consumed region 170 in a typical semiconductor manufacturing process shown in FIG.

[0054] In addition, in the process of forming the second insulating layer 260, instead of forming the second insulating layer 260 directly on top of the channel layer 250, the second insulating layer 260 is formed on top of the protective layer 255, which may improve the conformality of the channel layer 250 compared to the conventional semiconductor manufacturing process shown in FIG.

[0055] As described above, by forming the second insulating layer 260 after the protective layer 255 is formed on the channel layer 250, the thickness of the channel layer 250 may be maintained at a certain level or more, and the conformality of the channel layer 250 may be improved compared to the conventional method, thereby improving the electrical characteristics of the semiconductor device.

[0056] FIG. 6 is a graph showing the thickness of a channel layer of a semiconductor device manufactured according to a conventional semiconductor device manufacturing method and the thickness of a channel layer of a semiconductor device manufactured according to an embodiment of the present invention.

[0057] 6, M1 denotes a channel layer thickness 150 measured before an insulating layer formation process is performed on the channel layer in a typical semiconductor device manufacturing method or a semiconductor device manufacturing method according to an embodiment. M2 denotes a channel layer thickness 112 and a consumed region thickness 38 measured after an insulating layer formation process is performed directly on the channel layer in a typical semiconductor device manufacturing method. M3 denotes a channel layer thickness 135 and a consumed region thickness 15 measured after a high-pressure surface treatment process and an insulating layer formation process are performed sequentially on the channel layer in a semiconductor device manufacturing method according to an embodiment.

[0058] As shown in FIG. 6, in a typical semiconductor device manufacturing method, when an insulating layer formation process is performed on a channel layer, the channel layer is consumed too much, resulting in a thick consumed region 38 and a thin channel layer thickness 112.

[0059] However, in the method for manufacturing a semiconductor device according to one embodiment, a protective layer is formed on the channel layer, and then an insulating layer is formed on the channel layer. As a result, the channel layer is not directly consumed, and therefore the thickness 15 of the consumed region is thinner and the thickness 135 of the channel layer is thicker than in semiconductor devices manufactured by conventional semiconductor device manufacturing methods. Therefore, the thickness of the channel layer can be maintained at a constant level, and the electrical characteristics of the semiconductor device can be improved.

[0060] FIG. 7 is a graph showing the conformality of a channel layer of a semiconductor device manufactured according to a conventional semiconductor device manufacturing method and the conformality of a channel layer of a semiconductor device manufactured according to an embodiment of the semiconductor device manufacturing method.

[0061] N1 in FIG. 7 indicates the conformality 95 of the channel layer measured before the insulating layer formation process is performed on the channel layer in a conventional semiconductor device manufacturing method or a semiconductor device manufacturing method according to an embodiment.

[0062] Also, N2 indicates the conformality 87 of the channel layer measured after a direct insulating layer formation step is performed on the channel layer in a typical semiconductor device manufacturing method.

[0063] Also, N3 represents the conformality 90 of the channel layer measured when the insulating layer formation process is performed after a high-pressure surface treatment process is performed on the channel layer while the internal pressure of the processing apparatus is maintained at 5 atmospheres in a method for manufacturing a semiconductor device according to one embodiment.

[0064] Also, N4 indicates the conformality 93 of the channel layer measured when the insulating layer formation process is performed after the high-pressure surface treatment process is performed on the channel layer while the internal pressure of the processing apparatus is maintained at 10 atmospheres in a method for manufacturing a semiconductor device according to one embodiment.

[0065] Also, N5 indicates the conformality 95 of the channel layer measured when the insulating layer formation process is performed after a high-pressure surface treatment process is performed on the channel layer while the internal pressure of the processing apparatus is maintained at 20 atmospheres in a method for manufacturing a semiconductor device according to one embodiment.

[0066] 7, the conformalities 90, 93, and 95 of the channel layer measured when the insulating layer formation process is performed after the high-pressure surface treatment process on the channel layer according to the semiconductor device manufacturing method of the embodiment are higher than the conformality 87 of the channel layer measured after the insulating layer formation process is performed directly on the channel layer in the conventional semiconductor device manufacturing method. That is, when the insulating layer formation process is performed after the high-pressure surface treatment process on the channel layer, the conformality of the channel layer is improved compared to when the insulating layer formation process is performed directly on the channel layer. This can improve the electrical characteristics of the semiconductor device.

[0067] Also, as shown in FIG. 7, when a high-pressure surface treatment process is performed on a channel layer according to an embodiment of the method for manufacturing a semiconductor device, the conformality of the channel layer can be improved as the pressure inside the treatment apparatus increases.

[0068] Although the present specification has been described with reference to exemplary drawings, the present invention is not limited to the embodiments and drawings disclosed in the specification, and various modifications can be made by those skilled in the art. Note that even if the effects of the configurations of the specification are not explicitly described in the above-described embodiments of the specification, the effects that can be predicted by the configurations should also be recognized.

Claims

1. forming a thin film structure on a substrate; forming a through hole through the thin film structure; forming a channel layer covering at least a portion of the through-hole; performing a high-pressure surface treatment process on the channel layer; and performing an insulating layer forming process on the channel layer; A method for manufacturing semiconductor devices.

2. The step of performing the high pressure surface treatment process includes: The method includes a step of performing a high pressure nitridation (HPN) process or a high pressure fluorination (HPF) process, The method for manufacturing a semiconductor device according to claim 1 .

3. The high-pressure surface treatment process is carried out in a treatment device in which a reactive gas containing nitrogen or fluorine is injected in an inert gas atmosphere. The method for manufacturing a semiconductor device according to claim 1 .

4. When the high-pressure surface treatment process is performed, the concentration of the reactive gas in the treatment device is 1% or more. The method for manufacturing a semiconductor device according to claim 3 .

5. When the high-pressure surface treatment process is performed, the internal pressure of the treatment device is maintained at 2 to 100 atmospheres. The method for manufacturing a semiconductor device according to claim 1 .

6. When the high pressure surface treatment process is performed, the internal temperature of the treatment device is maintained at 200 to 1000°C. The method for manufacturing a semiconductor device according to claim 1 .

7. a trench pattern is formed in the channel layer; a second insulating layer is formed inside the trench pattern by an insulating layer forming process on the channel layer; The method for manufacturing a semiconductor device according to claim 1 .

8. forming a semiconductor pattern between the through hole and the channel layer; The method for manufacturing a semiconductor device according to claim 1 .

9. The semiconductor pattern is a blocking layer covering at least a portion of the through-hole; a charge storage layer formed on the blocking layer; and a first insulating layer formed on the charge storage layer; The method for manufacturing a semiconductor device according to claim 8 .

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