Method for monitoring thermal impedance of power modules

Abstract

1. A method for monitoring thermal impedance of a power module of a power converter used to convert DC current to AC current or vice versa, the power module comprising at least one semiconductor die attached to a material stack of layers for heat dissipation and / or electrical connection thereof, the semiconductor producing asymmetric losses between two half cycles of an AC frequency f of the AC current, the method comprising: sampling and measuring a signal related to a junction temperature Tj of the semiconductor die at a frequency greater than twice the AC frequency of the AC current; calculating a time span Δt=tTjmax-tTjmin between a time point tTjmax at which the junction temperature of the semiconductor die is at its maximum value and a time point tTjmin at which the junction temperature is at its minimum value in one cycle of the AC current; storing the time span Δt in a memory; and measuring the time span Δt at different times t during operation of the power module. x =t0~t m , by repeatedly sampling and measuring the signal and calculating the time widths to obtain a series of time widths Δt t0 ~Δt tm and the time span Δt tm Δt t0 and monitoring the transition of the time width Δt by comparing the time width Δt with the time width Δt, thereby determining the transition of degradation of the thermal impedance of the power module.

Description

[Technical Field]

[0001] The present disclosure relates to the field of protecting power semiconductor modules from failure due to overheating, particularly overheating due to interface degradation, and maintaining equipment that uses such modules. [Background technology]

[0002] Thermal interface degradation in power modules is caused by delamination and voids occurring somewhere in the substructure between the semiconductor die and the heat sink. These degradations cause the temperature of the semiconductor die to rise, leading to an unsafe temperature operating region. High temperatures result in the destruction of the semiconductor and the failure of the power module. Therefore, monitoring the thermal interface is important to maintain the power module within a safe temperature region and to guide the maintenance and replacement stages of the power module.

[0003] The degradation phenomenon is caused by temperature variations and CTE (coefficient of thermal expansion) mismatch between the various materials that make up the power module stack shown in Figure 1. The power module stack includes at least a semiconductor die 3 (e.g., silicon), a die attach 4 (e.g., solder), a conductive layer 6 (e.g., copper), an electrical insulator layer 7, and a heat sink 8 (e.g., aluminum).

[0004] Power module 1 may also include elements such as a thermally conductive layer 9 (e.g., copper), a bonding layer 10 (e.g., solder), a base plate 11 (e.g., copper), and a thermal interface 12 (e.g., graphite or thermal paste). Double-sided cooling is also envisioned with a symmetrical material stack where the aforementioned stack is repeated on top surface 5 of semiconductor die 3.

[0005] Figure 2 shows a crack 2 that can occur in a layer such as layer 4. Such a crack reduces the thermal conductivity of the layer.

[0006] Non-Patent Document 1 discloses a method for extracting the thermal impedance frequency response function of a power module without interrupting normal converter operation. A sinusoidal small-signal loss excitation to the power device extracts the temperature response of such a power device, and by correlating both signals, the thermal impedance at the excitation frequency is estimated. Because this method relies on phase information rather than gain, it is not susceptible to loss and / or temperature measurement errors. This requires a small-signal loss excitation method that affects torque ripple for motor driver applications, for example.

[0007] In Non-Patent Document 2, the spatiotemporal dynamic thermal response of a semiconductor assembly with degradation is measured using heat injection with specific frequency components (sine wave and square wave). The temperature of the semiconductor die is estimated via thermal sensitive electrical parameters (TSEP), a frequency response function (FRF) is calculated for each system identification experiment, the FRF segments are combined, and a functional model is interpreted for thermal interface degradation.

[0008] Non-Patent Document 3 describes a method for monitoring solder fatigue in inverters that use IGBT power modules by detecting changes in output harmonics. It has been shown that low-order harmonics generated by non-ideal switching are affected by the device junction temperature, which depends on the solder condition of the module. Because this method lacks precision, the inverter controller is set to cause harmonic resonance at a given frequency.

[0009] Standard JESD51-14 describes a method for measuring "transient measurements of thermal resistance." This method preferably consists of measuring the junction temperature after the heating power has been switched off (cooling curve). Although not recommended, in principle, a heating curve can also be used if the heating power is constant during the heating pulse time. In the first case, the measurement requires that the power module is switched off after operating in a known thermal steady state. In both cases, the power losses must be known, which is difficult to estimate during online operation (in field applications).

[0010] Thermal impedance measurement is a powerful transient thermal response technique that can provide information about the degradation of various interfaces in a power module. This technique typically consists of: First, semiconductor switches are used as active devices to subject the power module to a starting steady-state thermal condition, which is either a zero power condition or a condition where a known, measured constant power is dissipated in the semiconductors.

[0011] Second, a controlled power step increase (if the starting condition is a zero power condition) or power step decrease (if the starting condition is a constant power condition) is applied, and the semiconductor temperature progression is then recorded until a new steady-state thermal condition is reached.

[0012] Finally, the recorded temperature transient behavior is described by using an equivalent Foster and Cauer network, which represents the thermal structure of the power module by multiple RC elements. By fitting the temperature change using the Foster equation, the resistance and capacitance of the various parts of the power module can be extracted, providing information on the evolution of the thermal resistance and capacitance.

[0013] Lock-in thermography is a well-proven, commercially available technique for detecting damage in materials and systems (e.g., delamination cracks, voids in composites, etc.), as described in Non-Patent Document 4.

[0014] Lock-in thermography techniques use a process in which the material or system being thermally analyzed is excited with a non-steady-state signal (e.g., a pulsed or sinusoidal signal) at a specific frequency (related to the material thickness or damage depth). For example, an infrared radiation source, such as a set of halogen lamps, is used to record images of the system / material's transient temperature response, and specific software and algorithms are used to calculate the phase and amplitude between the response and the excitation, producing phase and amplitude images. These techniques are used under thermal steady-state conditions.

[0015] The problems with state-of-the-art methods for thermal impedance monitoring are as follows: The power dissipation in the semiconductor must be known, i.e., measured or estimated, which can be a difficult task when the semiconductor is integrated into a power conversion device. The thermal measurement techniques described above do not provide information about which layers of the power module stack are degraded (because the measurements are performed at thermal steady state). [Prior art documents] [Non-patent literature]

[0016] [Non-Patent Document 1] Broeck & al., "In situ thermal impedance spectroscopy of Power electronic modules for localized degradation identification", PCIM Europe 2019;International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, 07-09 May 2019 Nuremberg, Germany;VDE ISBN:978-3-8007-4938-6 [Non-patent document 2] Polom & al., "Real-Time, In Situ Degradation Monitoring in Power Semiconductor Converters" 2019 IEEE Applied Power Electronics Conference and Exposition (APEC), 17-21 March 2019, IEEE, DOI:10.1109 / APEC.2019.872182 [Non-patent document 3] Xiang & al., "Condition Monitoring Power Module Solder Fatigue Using Inverter Harmonic Identification", IEEE Transactions on Power Electronics, Volume:27, Issue:1, January 2012 Pages 235-247, DOI:10.1109 / TPEL.2011.2160988 [Non-patent document 4] Gerd Busse "Lockin-Thermography: Principles", NDE-applications and trends, January 2014 Conference: 2014 Quantitative InfraRed Thermography, DOI:10.21611 / qirt.2014.e Summary of the Invention

[0017] This disclosure proposes a measurement method that uses lock-in techniques in transient conditions rather than steady state.

[0018] More precisely, the present disclosure proposes a method for monitoring the thermal impedance of a power module of a power converter used to convert DC current into AC current or vice versa, the power module comprising at least one semiconductor die attached to a material stack for heat dissipation and / or electrical connection, the semiconductor producing asymmetric losses between two half-cycles of an AC frequency f of the AC current. The method comprises: sampling and measuring a signal related to a junction temperature Tj of the semiconductor die at a frequency greater than ten times the AC frequency of the AC current; Calculating a time interval Δt=tTjmax−tTjmin between a time point tTjmax at which the junction temperature of the semiconductor die is at its maximum value and a time point tTjmin at which the junction temperature is at its minimum value in one period of the AC current, and storing the time interval Δt in a memory; During the operation of the power module at different times t x =t0~t p , by repeatedly sampling and measuring the signal and calculating the time widths to obtain a series of time widths Δt t0 ~Δt tp and the time span Δt tp time width Δt t0 By comparing with the time width Δt x and monitoring the change in the thermal impedance of the power module to determine the change in the thermal impedance degradation of the power module. Includes.

[0019] This method involves measuring the AC frequency and the time duration Δt tx and AC frequency f fund and storing the pair with the value.

[0020] The method involves varying the AC frequency during dedicated operation of the converter to provide a plurality of different AC frequencies f at each of which the thermal impedance of a particular layer of the stack can be detected. m = f1, f2, ..., f n and sampling and measuring the time width Δt corresponding to such different AC frequencies. txf1 , Δt txf2, ..., Δt txfn Repeatedly calculating During operation of the power module, the signal is repeatedly sampled and measured, and the time width is calculated to obtain a series of Δt to Δt for each of the different AC frequencies. x and provide AC frequency f m = f1, f2, ..., f n For each of Δt txfm Δt t0fm By comparing with Δt xfm monitoring the progress of the thermal impedance of a particular layer to determine the progress of degradation of the thermal impedance of the particular layer; may include:

[0021] The method may include measuring the time difference Δtmin between two successive minima of the junction temperature and calculating the AC frequency as f=1 / Δtmin.

[0022] The signal related to the junction temperature Tj may be a temperature sensitive electrical parameter of the semiconductor.

[0023] In such cases, the signal may be an uncalibrated temperature sensitive electrical parameter of the semiconductor.

[0024] The AC frequency is f d =D die / l die 2 where l die is the die thickness, D die is the diffusion coefficient of the die.

[0025] The AC frequency may be less than 2 kHz.

[0026] The AC frequency may be less than 1 kHz.

[0027] The AC frequency is the fundamental frequency that powers the converter or the fundamental output frequency of the converter, f fund may be.

[0028] The present disclosure also relates to a converter device comprising, on a power semiconductor switch die of the converter device, sensor means for sensing the temperature of the power semiconductor switch die, analog-to-digital converter means, sampling means, and a processor provided with memory means for storing and executing software configured to perform the thermal impedance monitoring method described above. In particular, the sensor means is designed to sense a temperature-sensitive electrical parameter of the die. The present disclosure also proposes software including instructions for performing the thermal impedance monitoring method disclosed above.

[0029] A detailed description of exemplary embodiments of the present disclosure is discussed below with reference to the accompanying drawings. [Brief explanation of the drawings]

[0030] [Figure 1] 1 is an example of a conventional stack for a power module. [Figure 2] FIG. 1 is a diagram of a solder layer in which a crack has occurred. [Figure 3] FIG. 1 is a prior art diagram of surface temperature response phase shift versus defect depth. [Figure 4] 1 is an example of a Cauer network for a power module stack. [Figure 5] FIG. 1 is a first Bode plot of a first example of a defect layer in a stack. [Figure 6] FIG. 10 is a second Bode plot of a second example of a defect layer in a stack. [Figure 7] FIG. 10 is a third Bode plot of a third example of a defect layer in a stack. [Figure 8] FIG. 6 is an enlarged Bode plot of a first example of a defect layer in the stack of FIG. 5. [Figure 9] 1 is a simplified schematic diagram of an example of a conversion device having a processor. [Figure 10A] FIG. 10 is a graph of bond temperature versus time and loss versus time for an initial laminate and an aged laminate. [Figure 10B]It is a diagram of the joint temperature versus time and loss versus time for the initial laminate and the deteriorated laminate. [Figure 11] It is a diagram showing loss waveforms for different modulation types in a DC / AC conversion device with different controls. [Figure 12] It is a diagram of the equivalent phase shift versus the fundamental frequency for different deteriorations of the layer. [Figure 13A] It is a diagram showing the method steps of this method. [Figure 13B] It is a diagram showing the method steps of this method. [Figure 13C] It is a diagram showing the method steps of this method.

Mode for Carrying Out the Invention

[0031] To characterize the behavior of the power module, in the heat wave theory, it is predicted that the thermal response of the surface of a homogeneous infinite material half-space receiving a thermal excitation P0 = P0(1 + cosθ(ωt)) / 2 is shifted by +π / 4 (+45 degrees). Due to the wave nature of the excitation, the heat propagation in the material can be analyzed from the wave theory. A defect or interface existing at a distance d below the surface of the material can be modeled by the reflection coefficient R (0 < R < 1) of the heat wave, and the phase of the thermal response of the surface changes compared to the case of a semi-infinite body. When voids or defects exist at the interface, the reflection coefficient is a function of the material properties and the contact resistance between different materials. The reflection coefficient also depends on the frequency. The curve in Figure 3 shows the influence of a defect of intensity R located at a depth d on the phase shift of the surface temperature response, as disclosed in the literature Rigert “Induktions-Lockin-Thermografie: ein neues Verfahren zur zerstoerungsfreien Pruefung” http: / / dx.doi.org / 10.18419 / opus-1734. This graph shows the influence of the defect depth d (normalized by μ which is a material parameter) and the reflection coefficient R (R = 0 → no defect (complete transmission), R = 1 → strong defect (complete reflection)). <​​It can be seen that when the defect is located at d<1.55 μm and has a reflection coefficient R>0.4, the surface temperature response phase shift changes from a 45° semi-infinite body value to a lower value that depends on R and the location of the defect.

[0033] Thus, FIG. 3 illustrates the basic principles of lock-in thermography for characterizing defects and interfaces in materials, devices including module stacks.

[0034] Importantly, the value of μ is frequency dependent, and for defects deep inside the material, lowering the excitation frequency increases the sensitivity. Therefore, by varying the excitation frequency, information about the interface (degradation) can be obtained for different stacks or for different interfaces.

[0035] While this simple model provides a good guide to how to use thermal waves to detect damage, a power semiconductor stack cannot be modeled as a semi-infinite body due to the different thermal properties of each layer in the stack. To analyze this system more accurately, a 1D electrical equivalent of the thermal model can be used, one of which can be analyzed as a frequency response function.

[0036] Thermal Impedance: Electrical Equivalent Model: Based on the fact that heat conduction and electron conduction are both physical processes modeled by the same phenomenon (diffusion), the thermal impedance of a semiconductor module can be modeled by analogy with the scaled heat conduction equation and the telegraph equation. Therefore, the equivalent electrical network of the thermal system can be deduced. The resistance and capacitance of the electrical equivalent are defined by analogy with the thermal resistance Rth and capacitance Cth using the following equations:

number

number

[0037] In a simple model of a power module made up of stacks of different materials, each layer exhibits a thermal resistance and a thermal capacitance. Therefore, an electrical network called a Cauer network can represent the thermal system of a five-layer stack as shown in Figure 4. Ploss is the heat flux from the top surface 5 of the semiconductor die in Figure 1, which corresponds to the losses occurring on the semiconductor die (the electrical equivalent is a current source), Cth and Rth are the equivalent capacitance and resistance of each layer starting from the die layer 3 and the heat sink layer 8, and Tamb is the ambient heat sink temperature.

[0038] The total thermal impedance of the network of FIG. 4 can be calculated using the following equation, where s is the Laplace operator:

number

[0039] In the case of a degraded layer, the new (increased) resistance R th,v is calculated using the void fraction f as described in the following equation: The amount of material is not corrected, so the heat capacity C th remains the same.

number

[0040] For example, using the nine layer stack shown in Figure 1 and the material data in Table 1 below. [Table 1]

[0041] The thermal impedance can be plotted in a Bode diagram, with the gain and phase plotted as a function of the excitation frequency of a sinusoidal type. The curves in Figures 5 to 7 compare measurements at increasing frequencies between a pristine, i.e., unaged, module and an aged module according to Figure 1.

[0042] Figure 5 is a Bode plot of the stack according to Figure 1 with 40% voids in layers 4 and 10. Figure 6 is a Bode plot of the stack according to Figure 1 with 40% voids in layer 4. Figure 7 is a Bode plot of the stack according to Figure 1 with 40% voids in layer 10. These figures show that the gain and phase of the thermal impedance change with degradation.

[0043] Curves 32 and 33 in Figure 5, curves 36 and 37 in Figure 6, and curves 40 and 41 in Figure 7 represent the phase difference between the temperature change of the die in the initial layer shown by the dotted line and the degraded layer shown by the solid line. Curves 30 and 31 in Figure 5, curves 34 and 35 in Figure 6, and curves 38 and 39 in Figure 7 represent the gain between the temperature change of the die in the initial layer shown by the dotted line and the degraded layer shown by the solid line.

[0044] The effects of degradation in layer 4, located closer to the excitation source, can be best detected by the phase shift of curve 33 relative to curve 32 at approximately 100 Hz excitation, as shown in Figures 5 and 6. On the other hand, a relatively low excitation frequency of approximately 1 Hz to 10 Hz is required to detect the frequency shift between curves 40 and 41, corresponding to damage in layer 10, located further away from the heat source, as shown in Figure 7. Note that no change in phase shift is observed at 100 Hz when damage is introduced in layer 10. Therefore, by varying the excitation frequency, it is possible to obtain information about which layer is damaged.

[0045] Power Semiconductor Die Losses: In the previous section, we discussed the thermal response of the system to sinusoidal excitation. In real-world applications, power dissipation does not necessarily follow a sinusoidal behavior. The purpose of this section is to explain the necessary conditions for the semiconductor operating point that produces the appropriate thermal response of the system so that information about layer degradation can be obtained. To support the loss profile requirements, the Bode plot in Figure 6 is plotted over a wider frequency range as in Figure 8, where the interval is 1 Hz to 1 MHz.

[0046] In this example, Figure 8 shows the following information: The gain of a Bode plot gives essentially the same information as a thermal impedance plot. The phase information shows that the unimpaired curve 44 and the impaired curve 45 meet at f > 1 kHz, so no impairment information can be obtained by analyzing the phase response of the system above this frequency.

[0047] The reason why the degraded and non-degraded cases cannot be separated at f > 1 kHz is that in the high frequency range, the thermal impedance of the heat source (the silicon die) acts as a filter to the electrical excitation. The thermal response time scale of the die is τ d =Rth d Cth d This is easy once you realize that it is of the order of . Use the following definitions:

number

[0048] In diffusion theory,

number

[0049] Using the values ​​for material 3 in Table 1, D d =4.88 10 -5 m 2 / s and the die thickness l d If we use =0.14mm, τ d =4.01 10 -4 s. Therefore, the thermal system response bandwidth is f d =1 / τ d = 2.5 kHz, which is of the same order as the 1 kHz found by inspection of the Bode plot in Figure 8.

[0050] Therefore, the applicability of the present invention means that the electrical excitation frequency of interest is f d =D si / 1 d 2 , i.e., preferably less than 2 kHz, and more preferably less than 1 kHz.

[0051] Advantageously for the present invention, typical signal modulation strategies, such as PWM modulation in converters, usually operate at frequencies higher than 1 kHz, such as 5 kHz or 10 kHz. As a result, the thermal system response is weak in this frequency range, resulting in weak temperature oscillations due to the PWM frequency, as seen in the gain <-60 dB in the Bode plot of Figure 8. Advantageously, therefore, the thermal system is not affected by the PWM excitation. Using the model described in the previous section, this means that losses are averaged over the PWM period.

[0052] Advantageously for the present invention, typical excitation frequencies may be limited by load impedance, by load requirements, or by external controls of the system, so that the system is typically excited in the frequency range of interest, i.e., at frequencies below 1 kHz, for example, 50 Hz, 60 Hz, 100 Hz, 400 Hz, or 1 Hz.

[0053] Another implication of this analysis is that the low-frequency electrical excitation signal dThis means that the power must not decrease from the maximum power value to the zero power value in a time shorter than the

[0054] Therefore, to summarize the loss requirements of the power semiconductor in the present invention, the loss waveform of the power semiconductor die depends on the application in which the power module or system is installed.

[0055] The present invention relates to the case of DC / AC or AC / DC power converter topologies and when the losses are low frequency periodic pulse waves with the following characteristics: a. The maximum pulse duration corresponds to a half period of the fundamental frequency of the AC current, and there is a zero-loss time. and b. There is at least one maximum within the pulse or asymmetric loss occurrence between the two half cycles. and c. The time difference between the last maximum value and the zero loss time is τ d =l d 2 / D d is greater than l d is the thickness of the semiconductor chip, and D d is the thermal diffusivity of the semiconductor chip. This means that the frequency of the modulated loss is f d =D die / (l die ) 2 means lower than die is the die thickness, and D die is the diffusion coefficient of the die.

[0056] As an example, under condition c, the semiconductor chip has a thickness of l die = 100 μm silicon chip, the thermal diffusivity of silicon is D die =4.89×10 -4 m 2 / s, so f die =4.89kHz, τ die =205μs.

[0057] An example of a DC / AC power topology is shown in Figure 9. Here, a DC power supply 51 functions to create a three-phase AC power supply 52 using a power semiconductor switch 1. The DC / AC power converter has a three-phase configuration supplied by a DC bus voltage. The semiconductor dies can be any IGBT, diode, MOSFET, or MISFET, and can be in any arrangement of the power converter topology. In the following example, the semiconductor dies of interest in the power module are placed in one leg in the high-side position.

[0058] The switching and conduction losses of semiconductor die 50 occur during normal operation of the power module in a motor control application, given the load current and bus voltage during switching and conduction events.

[0059] The occurrence of semiconductor die losses in a power module during DC / AC or AC / DC operation depends on the following variables related to the operating point: I cond The current passing through, the switching current I sw , switching voltage V sw , switching frequency f sw , junction temperature T j , proportional to the duty cycle modulation strategy / PWM technique.

[0060] In such applications, the periodic pulse loss waveform typically occurs at a fundamental frequency, such as a grid frequency of 50 Hz or an electric motor rotation control frequency of 1 Hz to 2 kHz in DC / AC or AC / DC applications. In either case, semiconductor losses occur only during the first half-cycle of the fundamental frequency, and the semiconductor does not experience any losses during the second half-cycle of the fundamental frequency.

[0061] Consider a power converter producing sinusoidal current waveforms at the outputs of phases ABC with a fundamental frequency of 100 Hz and chopped voltage waveforms operating at a switching frequency of 20 kHz.

[0062] 10A and 10B show the junction temperature and losses of a pristine and degraded power module at a fundamental AC frequency of 100 Hz. FIG. 10A is a schematic diagram of the power and junction temperature waveforms versus time. FIG. 10B is a zoomed-in view of one loss period, also including measurements of the die temperature Tj over time. In this example, the loss wave 70 on the semiconductor die in FIG. 10A has only a positive sinusoidal shape. In other words, the losses are proportional to the fundamental frequency f f Within, it follows a sinusoidal shape between 0 and 180 degrees (0 and π) and has a zero value between 180 and 360 degrees (π and 2π).

number

[0063] The die temperature responses Tj 71, 72 in Figure 10A are calculated using the thermal impedance. The temperature waveform has one minimum value 71a, 72a and one maximum value 71b, 72b, respectively, within the fundamental period. Measuring the time between the minimum and maximum temperature points provides an indication of module degradation. In Figure 10B, which shows a single loss period, it can be seen that when a degraded power module with 40% voids in layer 4 of Figure 1 is operated with a 100 Hz AC current, the time span Δt = td is longer than the time span Δt = tp of the initial power module. This can be explained by the Bode plot in Figure 6. Figure 6 shows that at 100 Hz, the absolute value of the phase angle of the degraded thermal impedance is larger than that of the initial thermal impedance.

[0064] Importantly, the sudden power change causes a kink in the temperature response, so that the start of the pulse corresponding to tTjmin can be identified simply by inspecting the temperature response. Thus, the knowledge of Δt=tTjmax-tTjmin is advantageously related to the phase angle between the temperature response and the power excitation.

[0065] Figure 11 shows losses at the fundamental frequency of a DC / AC power converter plotted for various modulation strategies when the converter drives an electric motor: sine wave 60, DPWM1 61, DPWM3 62, and space vector 63. Losses are calculated taking into account both conduction and switching losses in the semiconductor die and are averaged over the modulation period.

[0066] The converter topology is not limited to the example converters, but can be multi-level topologies such as NPC (neutral point clamped) inverter, ANPC (active-neutral-point-clamped) inverter, MMC (modular multilevel converter), FC (flying capacitor), and other state-of-the-art topologies.

[0067] This shows that in an AC / DC or DC / AC power converter having a power module with at least one semiconductor die attached to a material stack for heat dissipation and / or electrical connection, if the semiconductor experiences asymmetric losses between two half-cycles of an AC frequency, then by measuring, during the AC period, a signal related to the temperature of the semiconductor at that frequency, and measuring the time width Δt=tTjmax-tTjmin between the temperature Tjmax at which the junction temperature is maximum and the temperature Tjmin at which it is minimum, and repeating such measurements during operation of the power converter, it is possible to obtain a measure of the degradation of at least one layer in the stack of layers between the die and the heat sink to which it is attached.

[0068] Therefore, because degradation is sensitive to the temperature rise time delay Δt and not to the magnitude of the temperature or the magnitude of the power loss, the estimation of thermal degradation is not sensitive to the accuracy of the measurement of the junction temperature, and any signal related to the temperature of the semiconductor can be used as long as there is a monotonic relationship between the temperature and the signal. Therefore, there is no need to estimate or measure the power loss in the semiconductor, which has the advantages of reducing the number of sensors and calculation time and improving the accuracy of the degradation measurement.

[0069] During operation of the converter, the measurement is repeated and for comparison, the calculation of the temperature rise time delay Δt=tTjmax-tTjmin is stored in memory at each iteration and compared with the initial value and / or previous value to determine the t x =t0~t p Such a time delay Δt x The change in the thermal impedance can be monitored to obtain the degradation state of the thermal impedance.

[0070] In addition to measuring the temperature rise time delay, the fundamental frequency f at which losses are measured fund is measured and stored, and the time width Δt(f fund ) can determine the state of deterioration.

[0071] Therefore, the damage indicator Δt x Since the fluctuation of is sensitive to the fundamental frequency, it has the advantage that degradation information of a specific laminate layer can be obtained.

[0072] For example, the fundamental loss frequency can be measured using an AC load current probe, or specified by a controller standard, or specified by a user's AC frequency requirements.

[0073] As explained below, damage at different heights in the stack causes different phase shifts in the temperature rise curve, resulting in different frequencies f fund,i In the damage indicator Δti(f fund,i) can provide information about the progression of degradation in the various layers of the stack. Higher frequencies are used to monitor the degradation of the stack layers closer to the semiconductor, and lower frequencies are used to monitor the degradation of the stack layers further away from the semiconductor.

[0074] The effect of degradation on the frequency response function of a particular layer of the stack can be determined, for example, by identifying the degradation in a particular layer using equation (4), measuring the phase shift associated with this degradation using the Z(s) estimate in equation (3), and plotting Bode plots such as those in Figures 5-7.

[0075] As an example, one or more frequencies between 20 Hz and 500 Hz are used to monitor the degradation of layer 4 according to FIG. 6, and one or more frequencies between 1 Hz and 10 Hz are used to monitor layer 10 resulting in the curves of FIG. 7.

[0076] In the case of a combination of multiple impairments, monitoring the time delay at multiple frequencies allows the contributions of the multiple impairments to be separated, as in the example of Figure 5.

[0077] To support the relationship between Δt and phase angle, as a first approximation, the change in phase angle Ph in degrees due to degradation, i.e., from Δt=tp to Δt=td, can be approximated by the following equation:

number

[0078] FIG. 12 shows a comparison of a first-order estimate of the phase Ph using Equation (7) with the phase extracted from a calculation using the impedance method for the fundamental frequency. In this figure, curve 80 is the estimated phase curve for degradation layers 4 and 10 of FIG. 1, curve 81 is the theoretical curve for degradation layers 4 and 10, curve 82 is the estimated phase curve for degradation layer 4, curve 83 is the theoretical curve for degradation layer 4, curve 84 is the estimated phase curve for degradation layer 10, and curve 85 is the theoretical curve for degradation layer 10. This shows that at frequencies above about 10 Hz, the first-order estimate shows a similar trend to the more rigorous model, thus demonstrating that the information in Δt is the same as that in the phase of the Bode plots of FIGS. 5-8.

[0079] Then, if the fundamental frequency f of the AC current is changed, the method can monitor the time difference for different fundamental frequencies, which allows an estimation of which layer is the degraded layer.

[0080] By measuring the time difference Δtmin between two successive minimum values ​​of the junction temperature, the fundamental frequency is f fund = 1 / Δtmin.

[0081] This therefore has the advantage that the fundamental frequency can be recorded without using additional sensors or obtaining the fundamental frequency information from a separate algorithm, and therefore the algorithm for degradation analysis can function independently of the converter control algorithm or any other operating conditions of the power module.

[0082] For example, in FIG. 10A, the time interval between two consecutive minima is Δtmin=0.02 s, so the fundamental frequency is f fund =1 / Δtmin=50Hz.

[0083] The signal used to measure the temperature may be any temperature sensitive electrical parameter (TSEP) of the associated semiconductor switch.

[0084] Therefore, the system complexity is reduced since the degradation can be identified and quantified without complex prior calibration of the TSEP.

[0085] For example, if TSEP can have a value X between Xa and Xb corresponding to the temperature range [−20° C.; 200° C.], the relationship between temperature and TSEP is linear as follows:

number

[0086] In this example, only the variable X is measured, so there is no need to calibrate the TSEP, i.e., determine A and B, before implementing the method. In a subexample, A>0, and the times tTjmax and tTjmin when the junction temperature is maximum and minimum correspond to the times when X is at its maximum and minimum values, respectively. In another subexample, A<0, and the times tTjmax and tTjmin when the junction temperature is maximum and minimum correspond to the times when X is at its minimum and maximum values, respectively.

[0087] More generally, it is sufficient that the function T(X) is monotonically increasing or decreasing, e.g., that its first derivative does not change sign in the interval [Xa;Xb]. Therefore, uncalibrated TSEPs with nonlinear temperature characteristics can also be advantageously used within the scope of the present invention.

[0088] FIG. 13A illustrates the method steps of the present disclosure, which include: Sampling and measuring 100 a signal S related to a junction temperature Tj of the semiconductor die at a frequency greater than 10 times the AC frequency of the AC current; a step 110 of calculating a time interval Δt=tTjmax−tTjmin between a time point tTjmax at which the junction temperature of the semiconductor die is at its maximum value and a time point tTjmin at which the junction temperature is at its minimum value in one period of the AC current; and a step 120 of storing the time interval Δt in a memory. The transition of the time width Δt is monitored to determine the transition of the deterioration of the thermal impedance of the power module. p Time span Δt t0 Δt tp a step 130 of comparing Different times tx=t0 to t during operation of the power module p , repeatedly sampling and measuring the signal and calculating the time spans (140, 150) to generate a series of time spans Δt t0 ~Δt tp and Includes.

[0089] Step 100 may also include measuring the AC frequency, and step 120 may include measuring the AC frequency over a time period Δt tx and AC frequency f fund This can include storing pairs of

[0090] The measurements in step 100 can be taken using a variety of means, such as thermocouples, infrared imaging, TSEP, etc.

[0091] Because measurements may be noisy, averaging of Δt may be necessary. The comparison may not be strictly based on the first Δt value measured, but rather on the average of several measurements taken at the beginning of product use. In such cases, averaging may be performed over 2 to 10 measurements.

[0092] The repeated sampling, measurement, and comparison may be performed periodically, daily, weekly, monthly, or every number of AC frequency fluctuations (e.g., every tenth or several hundred hours) corresponding to the use of the converter associated with the estimated rate of deterioration. tx The repetition rate may also be accelerated when the difference between t0 and Δt0 becomes greater than a predetermined warning value.

[0093] The method also modifies the AC frequency during dedicated operation of the converter to provide a plurality of different AC frequencies f, each capable of detecting the thermal impedance of a particular layer of the stack, as shown in FIG. 13B. m = f1, f2, ..., f n and sampling and measuring 200 the TSEP signal S and frequency and the time width Δt corresponding to such different AC frequencies. txf1 , Δt txf2 , ..., Δt txfn one or more steps of repeating 210 calculating The progress of Δt is monitored for each of the AC frequencies to determine the progress of the degradation of the thermal impedance of the particular layer. t0fm Δt tpfm one or more steps 230 of comparing with a value; Δt x To compare the value with the Δt0 value, the different AC frequencies f m For each of the series of Δt x =Δt0~Δt p This may involve repeatedly sampling and measuring the signal and calculating the time duration during operation of the power module to provide the value.

[0094] Here again, the repeated sampling, measurement, and comparison may be performed periodically, such as daily, weekly, monthly, or every number of AC frequency fluctuations (e.g., tenths or hundreds of hours) corresponding to the use of the converter associated with the estimated degradation rate. tx The repetition rate may also be accelerated when the difference between t0 and Δt0 becomes greater than a predetermined warning value.

[0095] Additionally, tests using AC frequency adaptation may be performed in specific situations, such as tests involving grid frequency or motor speed ramping.

[0096] 13C, the method may also include one or more steps 300 of measuring the time difference Δt between two successive minima of the junction temperature, and step 310 of calculating the AC frequency as f=1 / Δt, thereby eliminating the need to measure the frequency using a means separate from the signal S related to the junction temperature T, which may be an uncalibrated temperature-sensitive electrical parameter of the semiconductor.

[0097] To carry out the method, a conversion apparatus as shown in FIG. 9 may comprise, on a power semiconductor switch die of the conversion apparatus, sensor means 53 for sensing the TSEP signal of the power semiconductor switch die, analog-to-digital converter means 54, sampling means 55, and a processor 56 with necessary memory means 57 and calculation means for storing and executing software configured to carry out the thermal impedance monitoring method of the present disclosure.

Claims

1. 1. A thermal impedance monitoring method for a power module of a power converter used to convert DC current to AC current or vice versa, the power module comprising at least one semiconductor die attached to a material stack for heat dissipation and / or electrical connections thereof, the semiconductor producing asymmetric losses between two half-cycles of an AC frequency f of the AC current, the thermal impedance monitoring method comprising: sampling and measuring a signal related to a junction temperature Tj of the semiconductor die at a frequency greater than ten times the AC frequency of the AC current; Calculating a time interval Δt=tTjmax−tTjmin between a time tTjmax at which the junction temperature of the semiconductor die is at its maximum value and a time tTjmin at which the junction temperature is at its minimum value in one period of AC current, and storing the time interval Δt in a memory; At different times t during operation of the power module ｘ = t ０ ~t ｐ by repeating the steps of sampling and measuring the signal and calculating the time spans to obtain a series of time spans Δt ｔ０ ~Δt ｔｐ and providing the time width Δt ｔｐ The time width Δt ｔ０ By comparing with the time width Δt ｘ and determining a change in the thermal impedance of the power module by monitoring the change in the thermal impedance of the power module. A thermal impedance monitoring method comprising:

2. 2. The method of claim 1, further comprising averaging the measurements of said time width Δt over a period of time to reduce noise in the measurements.

3. measuring the AC frequency and the time duration Δt ｔｘ and AC frequency f ｆｕｎｄ and storing the pair of

4. Modifying the AC frequency during dedicated operation of the power converter to provide a plurality of different AC frequencies f each capable of detecting the thermal impedance of a particular layer of the material stack. ｍ = f １ , f ２ ,... ,f ｎ and providing a time width Δt corresponding to the sampling and measuring and the different AC frequencies. ｔｘｆｍ =Δt ｔｘｆ１ , Δt ｔｘｆ２ , . . . , Δt ｔｘｆｎ Repeatedly calculating During operation of the power module, the sampling and measuring of the signal and the calculation of the time duration are repeated to obtain a series of Δt for each of the different AC frequencies. ０ｆｍ ~Δt ｘｆｍ and providing the AC frequency f ｍ = f １ , f ２ ,... ,f ｎ For each of Δt ｔｍ Δt ｔ０ monitoring the progress of Δt by comparing it with the thermal impedance of the specific layer to determine the progress of degradation of the thermal impedance of the specific layer; 4. The thermal impedance monitoring method of claim 3, comprising:

5. 4. The method of claim 3, further comprising measuring a time difference Δt min between two successive minima of the junction temperature and calculating the AC frequency as f=1 / Δt min.

6. 3. A method for monitoring thermal impedance according to claim 1 or 2, wherein the signal related to the junction temperature Tj is a temperature-sensitive electrical parameter of the semiconductor.

7. 7. The thermal impedance monitoring method of claim 6, wherein the signal related to the junction temperature Tj is an uncalibrated temperature sensitive electrical parameter of the semiconductor.

8. The AC frequency is f ｄ =D ｄｉｅ / l ｄｉｅ ２ is lower than ｄｉｅ is the thickness of the die, and D ｄｉｅ 3. The thermal impedance monitoring method of claim 1, wherein: is the diffusion coefficient of the die.

9. 3. The thermal impedance monitoring method of claim 1, wherein the AC frequency is less than 2 kHz.

10. The thermal impedance monitoring method of claim 1 or 2, wherein the AC frequency is less than 1 kHz.

11. The AC frequency is a fundamental frequency for supplying power to the power conversion device or a fundamental output frequency f ｆｕｎｄ 3. The thermal impedance monitoring method of claim 1, wherein:

12. 3. A conversion device comprising: sensor means on a power semiconductor switch die of the conversion device for sensing a temperature of the power semiconductor switch die; analog-to-digital converter means; sampling means; and a processor provided with memory means for storing and executing software configured to perform the thermal impedance monitoring method of claim 1 or 2.

13. 13. The converter of claim 12, wherein the sensor means is designed to sense a temperature-sensitive electrical parameter of the power semiconductor switch die.

14. Permanent memory means including software containing instructions which, when executed by a processor, carry out the thermal impedance monitoring method of claim 1 or 2.

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