Stacked FET with contact placeholder structure

Abstract

A semiconductor structure is provided that includes a first FET device region including a plurality of first FETs, each of which includes a first source / drain region located on either side of a functional gate structure. A second FET device region is stacked above the first FET device region and includes a plurality of second FETs, each of which includes a second source / drain region located on either side of the functional gate structure. The structure further includes at least one first front-side contact placeholder structure disposed adjacent to one of the first source / drain regions of the at least one first FET and at least one second front-side contact placeholder structure disposed adjacent to at least one of the second source / drain regions of the at least one second FET.

Description

[Technical Field]

[0001] This application relates to semiconductor technology, and more particularly to semiconductor structures including stacked field effect transistors (FETs) with flexible signal and power wiring. [Background technology]

[0002] Integrated circuits continue to shrink and transistor densities increase. Three-dimensional (3D) integration improves transistor density by utilizing the Z dimension and building not only laterally outward in the X and Y dimensions, but also upward. Another development that can be used for increasingly dense semiconductor devices is the use of both front-side and back-side interconnects to establish electrical connections between semiconductor devices. Whether an integrated circuit contains one device layer (or equivalently, a "device region") or multiple device layers, the use of back-side interconnects can improve various aspects of the construction and performance of semiconductor devices, particularly with respect to density constraints. Summary of the Invention

[0003] The present application provides a semiconductor structure having flexible signal and power wiring. The semiconductor structure includes a second FET device stacked above a first FET device, wherein the source / drain regions of the second FET device are misaligned with respect to the source / drain regions of the first FET device, and a front-side contact placeholder structure is located in the device region including the first and second FET devices. It should be noted that the misalignment of the first and second source / drain regions is not 100% misaligned, and some overlap (in the vertical plane from the first and second source / drain regions) of these stacked source / drain regions may occur.

[0004] In one aspect of the present application, a semiconductor structure is provided. In one embodiment, the semiconductor structure includes a first FET device region including a plurality of first FETs, each of which includes a first source / drain region located on either side of a functional gate structure. A second FET device region is stacked above the first FET device region and includes a plurality of second FETs, each of which includes a second source / drain region located on either side of the functional gate structure. The structure further includes at least one first front-side contact placeholder structure disposed adjacent to one of the first source / drain regions of the at least one first FET and at least one second front-side contact placeholder structure disposed adjacent to at least one of the second source / drain regions of the at least one second FET. The presence of the first and second front-side contact placeholder structures provides design flexibility to the structure.

[0005] In embodiments of the present application, the center of each first source / drain region is offset relative to the center of each second source / drain region. In such embodiments, the edge of each first source / drain region can overlap the edge of each second source / drain region, which helps reduce cell height. In such embodiments, at least one first front-side contact placeholder structure is offset relative to at least one second front-side contact placeholder structure, with the at least one first front-side contact placeholder structure located below one of the second source / drain regions of one of the second FETs and the at least one second front-side contact placeholder structure located above one of the first source / drain regions of one of the first FETs. These embodiments enable flexible signal and back-side power routing.

[0006] In some embodiments of the present application, the structure further comprises a stacked FET device isolation layer separating the first FET device region from the second FET device region, the stacked FET device isolation layer providing device isolation between the first and second FET device regions.

[0007] In some embodiments of the present application, the structure further comprises a bottom dielectric insulating layer located below each of the first source / drain regions and present in the first FET device region, the bottom dielectric insulating layer providing electrical isolation to the structure and preventing the formation of unwanted parasitic capacitance.

[0008] In some embodiments of the present application, at least one first front-side contact placeholder structure contacts a VSS power source, which is connected to a back-side power distribution network, which allows connection to the back-side of the structure.

[0009] In some embodiments of the present application, the structure further comprises a signal line located above the second FET device region, where the signal line contacts additional interconnect line (BEOL) structures, which allow connection to the front side of the structure.

[0010] In some embodiments of the present application, the carrier wafer is located above additional BEOL structures.

[0011] In some embodiments of the present application, another of the second source / drain regions is wired to a V power supply by a backside source / drain contact structure that extends from the second FET device region completely through the first FET device region.

[0012] In some embodiments of the present application, another of the first source / drain regions is wired to a VSS power supply by a backside source / drain contact structure that extends to the first FET device region.

[0013] In some embodiments of the present application, another of the first source / drain regions and another of the second source / drain regions are electrically connected by a shared source / drain contact structure.

[0014] In some embodiments of the present application, both the at least one first front-side contact placeholder structure and the at least one second front-side contact placeholder structure include a placeholder dielectric material that can be designed to impart stress to nearby structures.

[0015] In some embodiments of the present application, at least one of the source / drain regions is interconnected to a signal line located above the second FET device region by a first source / drain region front side contact structure and a metal via.

[0016] In some embodiments of the present application, at least one of the second source / drain regions is interconnected to a signal line located above the second FET device region by a second source / drain region front side contact structure and a metal via.

[0017] In some embodiments of the present application, each of the first source / drain regions is located on a surface of a bottom dielectric insulating layer, and each of the second source / drain regions is located on a surface of a stacked FET device isolation layer disposed between the first FET device region and the second FET device region.

[0018] In some embodiments of the present application, at least one first contact placeholder structure extends through the shallow trench isolation region and the first interlayer dielectric material layer, the first interlayer dielectric material layer being laterally adjacent to and located above each first source / drain region, and at least one second front-side contact placeholder structure extends through the second interlayer dielectric material layer, the second interlayer dielectric material layer being laterally adjacent to and located above each second source / drain region.

[0019] In some embodiments of the present application, the first FET and the second FET are FET-containing nanosheets, where a functional gate structure is wrapped around a nanosheet of semiconducting channel material present in each of the first FET device region and the second FET device region.

[0020] In some embodiments of the present application, the first FET is of a first conductivity type and the second FET is of a second conductivity type, where the second conductivity type is different from the first conductivity type.

[0021] In some embodiments of the present application, the first FET is of a first conductivity type and the second FET is of a second conductivity type, where the second conductivity type is the same conductivity type as the first conductivity type.

[0022] In another aspect of the present application, there is provided a method of forming a semiconductor structure, the method of the present application becoming more apparent with reference to the drawings and detailed description of the present application that follow. [Brief explanation of the drawings]

[0023] [Figure 1] FIG. 1 is a top-down view illustrating a possible device layout according to an embodiment of the present application.

[0024] [Figure 2A] 2 is a cross-sectional view of an exemplary semiconductor structure taken through XX shown in FIG. 1 that may be employed in the present application, the exemplary semiconductor structure including a semiconductor substrate, a bottom dielectric insulating layer located on the semiconductor substrate, a plurality of first-nanosheet-containing stacks of alternating first sacrificial semiconductor material nanosheets and first semiconductor channel material nanosheets located on the bottom dielectric insulating layer, a first sacrificial gate structure spanning each first-nanosheet-containing stack, first source / drain regions extending outward from each first semiconductor channel material nanosheet, and a first front-side interlayer dielectric (ILD) material layer located on the first source / drain regions. [Figure 2B]2 is a cross-sectional view of an exemplary semiconductor structure taken through YY shown in FIG. 1 that may be employed in the present application, the exemplary semiconductor structure including a semiconductor substrate, a bottom dielectric insulating layer located on the semiconductor substrate, a plurality of first-nanosheet-containing stacks of alternating first sacrificial semiconductor material nanosheets and first semiconductor channel material nanosheets located on the bottom dielectric insulating layer, a first sacrificial gate structure spanning each first-nanosheet-containing stack, first source / drain regions extending outward from each first semiconductor channel material nanosheet, and a first front-side interlayer dielectric (ILD) material layer located on the first source / drain regions.

[0025] [Figure 3A] 2B is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 2A after forming a plurality of first front-side contact placeholder structures. [Figure 3B] 2C is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 2B after forming a plurality of first front-side contact placeholder structures.

[0026] [Figure 4A] 3B is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 3A after forming a stacked FET device isolation layer and forming a material stack of alternating second sacrificial semiconductor material layers and second semiconductor channel material layers on the stacked FET device isolation layer. [Figure 4B] 3C is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 3B after forming a stacked FET device isolation layer and forming a material stack of alternating second sacrificial semiconductor material layers and second semiconductor channel material layers on the stacked FET device isolation layer.

[0027] [Figure 5A]4B is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 4A after forming a plurality of second sacrificial gate structures spanning different portions of the material stack, patterning the material stack utilizing at least the second sacrificial gate structures as a pattern mask to provide a plurality of second-nanosheet-containing stacks of alternating second sacrificial semiconductor material nanosheets and second semiconductor channel material nanosheets, forming second source / drain regions extending outward from each second semiconductor channel material nanosheet, and forming a second front-side ILD material layer. [Figure 5B] 4B after forming a plurality of second sacrificial gate structures spanning different portions of the material stack, patterning the material stack utilizing at least the second sacrificial gate structures as a pattern mask to provide a plurality of second-nanosheet-containing stacks of alternating second sacrificial semiconductor material nanosheets and second semiconductor channel material nanosheets, forming second source / drain regions extending outward from each second semiconductor channel material nanosheet, and forming a second front-side ILD material layer.

[0028] [Figure 6A] FIG. 5B is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 5A after removing each second sacrificial gate structure and each first sacrificial gate structure, removing each second sacrificial semiconductor material nanosheet and each first sacrificial semiconductor material nanosheet to leave each second semiconductor channel material nanosheet and each first semiconductor channel material nanosheet suspended, and forming a functional gate structure including a first functional gate structure portion wrapped around the suspended first semiconductor channel material nanosheet and a second functional gate structure portion wrapped around the suspended second semiconductor channel material nanosheet. [Figure 6B]FIG. 5C is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 5B after removing each second sacrificial gate structure and each first sacrificial gate structure, removing each second sacrificial semiconductor material nanosheet and each first sacrificial semiconductor material nanosheet to leave each second semiconductor channel material nanosheet and each first semiconductor channel material nanosheet suspended, and forming a functional gate structure including a first functional gate structure portion wrapped around the suspended first semiconductor channel material nanosheet and a second functional gate structure portion wrapped around the suspended second semiconductor channel material nanosheet.

[0029] [Figure 7A] FIG. 6B is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 6A after forming a plurality of second front-side contact placeholder structures, wherein the plurality of second front-side contact placeholder structures are offset relative to the plurality of first front-side contact placeholder structures, each first front-side contact placeholder structure being located below one of the second source / drain regions, and each second front-side contact placeholder structure being located above one of the first source / drain regions. [Figure 7B] FIG. 6C is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 6B after forming a plurality of second front-side contact placeholder structures, wherein the plurality of second front-side contact placeholder structures are offset relative to the plurality of first front-side contact placeholder structures, each first front-side contact placeholder structure being located below one of the second source / drain regions, and each second front-side contact placeholder structure being located above one of the first source / drain regions.

[0030] [Figure 8A] FIG. 7B is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 7A after forming a middle-of-the-line (MOL) dielectric material layer having contact openings that physically expose a first set of second front-side contact placeholder structures. [Figure 8B]FIG. 7C is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 7B after forming a middle-of-the-line (MOL) dielectric material layer having contact openings that physically expose a first set of second front-side contact placeholder structures.

[0031] [Figure 9A] 8B is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 8A after removing, via etching, a first set of physically exposed second front-side contact placeholder structures and continuing the etching to physically expose a first set of first source / drain regions disposed beneath the removed first set of second front-side contact placeholder structures. [Figure 9B] 8B after removing, via etching, a first set of physically exposed second front-side contact placeholder structures and continuing the etching to physically expose a first set of first source / drain regions disposed beneath the removed first set of second front-side contact placeholder structures.

[0032] [Figure 10A] 9B is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 9A after forming source / drain contact openings that physically expose a first set of second source / drain regions. [Figure 10B] 9C is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 9B after forming source / drain contact openings that physically expose the first set of second source / drain regions.

[0033] [Figure 11A] 10B is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 10A after forming front-side source / drain containing structures in various contact openings similar to the openings provided by the etching of FIG. 8A. [Figure 11B]10B after forming front-side source / drain containing structures in various contact openings similar to the openings provided by the etching of FIG. 8B.

[0034] [Figure 12A] 11B is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 11A after forming a back-end of line (BEOL) dielectric material layer and an M1 signal line. [Figure 12B] 11C is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 11B after forming a back-end of line (BEOL) dielectric material layer and an M1 signal line.

[0035] [Figure 13A] 12B is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 12A and a carrier wafer after forming additional BEOL structures. [Figure 13B] FIG. 12C is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 12B and carrier wafer after forming additional BEOL structures.

[0036] [Figure 14A] 13B is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 13A after the wafer has been flipped to allow for backside processing of the structure. [Figure 14B] FIG. 13C is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 13B after the wafer has been flipped to allow for backside processing of the structure.

[0037] [Figure 15A] 14B is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 14A after removing a first layer of semiconductor material of the semiconductor substrate to physically expose an etch stop layer of the semiconductor substrate. [Figure 15B] 14C is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 14B after removing the first semiconductor material layer of the semiconductor substrate to physically expose an etch stop layer of the semiconductor substrate.

[0038] [Figure 16A]15B is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 15A after removing the etch stop layer and the second layer of semiconductor material of the semiconductor substrate. [Figure 16B] 15C is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 15B after removing the etch stop layer and the second layer of semiconductor material of the semiconductor substrate.

[0039] [Figure 17A] 16B is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 16A after forming a backside ILD material layer. [Figure 17B] 16C is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 16B after forming a backside ILD material layer.

[0040] [Figure 18A] FIG. 17B is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 17A after forming a patterned mask on the backside ILD material layer, where the patterned mask has an opening that physically exposes one of the first front-side contact placeholder structures. [Figure 18B] FIG. 17C is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 17B after forming a patterned mask on the backside ILD material layer, where the patterned mask has an opening that physically exposes one of the first frontside contact placeholder structures.

[0041] [Figure 19A] 18B is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 18A after etching through the structure utilizing a patterned mask as an etching mask to physically expose one surface of the second source / drain region. [Figure 19B] FIG. 18C is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 18B after etching through the structure utilizing a patterned mask as an etching mask to physically expose one surface of the second source / drain region.

[0042] [Figure 20A]19B is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 19A after forming a backside first source / drain contact opening in one of the first source / drain regions. [Figure 20B] 19C is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 19B after forming a backside first source / drain contact opening in one of the first source / drain regions.

[0043] [Figure 21A] 20A after forming backside source / drain contact structures in the first source / drain contact openings similar to the openings provided by the etching performed in FIG. 19A. [Figure 21B] 20B after forming backside source / drain contact structures in the first source / drain contact openings similar to the openings provided by the etching performed in FIG. 19B.

[0044] [Figure 22A] 21B is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 21A after forming a backside power supply rail and a backside power distribution network. [Figure 22B] 21C is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 21B after forming a backside power supply rail and a backside power distribution network. DETAILED DESCRIPTION OF THE INVENTION

[0045] The present application will now be described in more detail by reference to the following discussion and the drawings that accompany this application. It should be noted that the drawings of the present application are provided for illustrative purposes only, and therefore the drawings are not drawn to scale. It should also be noted that like and corresponding elements are referred to by like reference numerals.

[0046] In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps, and techniques, to provide an understanding of various embodiments of the present application. However, it will be understood by those skilled in the art that various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail to avoid obscuring the present application.

[0047] When an element, such as a layer, region, or substrate, is referred to as being "on" or "over" another element, it will be understood that the element can be directly on the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. When an element is referred to as being "beneath" or "under" another element, it will be understood that the element can be directly below or directly underneath the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly beneath" or "directly under" another element, there are no intervening elements present.

[0048] Referring first to FIG. 1 , a top-down view of an exemplary semiconductor device layout that may be employed in accordance with one embodiment of the present application is shown. The illustrated semiconductor device layout includes various active device regions AA spaced apart from one another by inactive device regions (not specifically labeled in the drawing). Within each active device region AA are multiple gate structures GS oriented parallel to one another. The semiconductor device layout shown in FIG. 1 will be used to describe a stacked nanosheet FET device in accordance with one embodiment of the present application. While a stacked nanosheet device is described and illustrated, the present application also works for other stacked FET devices, including, for example, stacked planar FET devices, stacked FinFET devices, or stacked nanowire devices. Mixed stacked devices, such as FinFET and nanosheet devices, are also contemplated.

[0049] Figure 1 includes a section line XX that passes through the central active device area AA shown in Figure 1. Figure 1 also includes a section line YY that is perpendicular to XX and passes through the source / drain regions present in each active device area AA shown in Figure 1. The section line YY is between a pair of adjacent gate structures present in each active device area AA. In the present application, Figures 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, 21A, and 22A illustrate an exemplary semiconductor structure through section line XX shown in Figure 1 and through various processing steps of the present application, and Figures 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16B, 17B, 18B, 19B, 20B, 21B, and 22B illustrate an exemplary semiconductor structure through section line YY shown in Figure 1 and through various processing steps of the present application.

[0050] 2A-2B, which illustrate exemplary semiconductor structures employable in the present application, each of which is labeled XX and YY as shown in FIG. 1. The exemplary semiconductor structure includes a semiconductor substrate 10 / 12 / 14, a bottom dielectric insulating layer 16 disposed on the semiconductor substrate 10 / 12 / 14, a plurality of first nanosheet-containing stacks (by way of example, FIG. 2A illustrates three first nanosheet-containing stacks) of alternating first sacrificial semiconductor material nanosheets 18 and first semiconductor channel material nanosheets 20 disposed on the bottom dielectric insulating layer 16, a first sacrificial gate structure 22 spanning each of the first nanosheet-containing stacks 18 / 20, first source / drain regions 28 extending outward from each first semiconductor channel material nanosheet 20, and a first front-side interlayer dielectric (ILD) material layer 30 disposed on the first source / drain regions 28. The semiconductor substrate includes a first layer of semiconductor material 10, an etch stop layer 12, and a second layer of semiconductor material 14.

[0051] The exemplary structure also includes shallow trench isolation regions 15 located laterally adjacent to the unetched portions of the second semiconductor material layer 14 of the semiconductor substrate, first gate spacers 24 located laterally adjacent to each sacrificial gate structure 22, and first interior spacers 26 located laterally adjacent to an end wall of each first sacrificial semiconductor material nanosheet 18. The first interior spacers 26 are located below each first semiconductor channel material nanosheet 20.

[0052] The first semiconductor material layer 10 of the semiconductor substrate is composed of a first semiconductor material having semiconducting properties. Examples of first semiconductor materials that can be used to provide the first semiconductor material layer 10 include, but are not limited to, silicon (Si), silicon germanium (SiGe) alloy, silicon germanium carbide (SiGeC) alloy, germanium (Ge), a III / V compound semiconductor, or a II / VI compound semiconductor. The second semiconductor material layer 14 is composed of a second semiconductor material. The second semiconductor material providing the second semiconductor material layer 14 can be compositionally the same as or different from the first semiconductor material providing the first semiconductor material layer 10. In some embodiments of the present application, the etch stop layer 12 can be composed of a dielectric material such as, for example, silicon dioxide and / or boron nitride. In other embodiments of the present application, the etch stop layer 12 is composed of a semiconductor material that is compositionally different from the semiconductor materials providing both the first semiconductor material layer 10 and the second semiconductor material layer 14.

[0053] In one example, the first semiconductor material layer 10 is composed of silicon, the etch stop layer 12 is composed of silicon dioxide, and the second semiconductor material layer 14 is composed of silicon. Such a semiconductor substrate including silicon / silicon dioxide / silicon can be referred to as a silicon-on-insulator (SOI) substrate. In another example, the first semiconductor material layer 10 is composed of silicon, the etch stop layer 12 is composed of silicon germanium, and the second semiconductor material layer 14 is composed of silicon. Such a semiconductor substrate including silicon / silicon germanium / silicon can be referred to as a bulk semiconductor substrate.

[0054] Shallow trench isolation region 15 may be comprised of any trench dielectric material, such as, for example, silicon oxide. In some embodiments, trench dielectric material, such as, for example, SiN, may be present along the sidewalls and bottom wall of the trench dielectric material. Shallow trench isolation region 15 may have a top surface that is coplanar with the top surface of the unetched portion of second semiconductor material layer 14.

[0055] As described above, each first-nanosheet-containing stack (each stack is a vertical stack of nanosheets) includes alternating, one-on-one stacked first sacrificial semiconductor material nanosheets 18 and second semiconductor channel material nanosheets 20. Within each first-nanosheet-containing stack, there may be "n" first semiconductor channel material nanosheets 20 and "n or n+1" first sacrificial semiconductor material nanosheets 18; an "n+1" embodiment is not shown, where n is an integer starting from 1. In the illustrated embodiment, each vertical nanosheet-containing stack includes "n" first sacrificial semiconductor material nanosheets 18 and "n" first semiconductor channel material nanosheets 20. As an example, each first-nanosheet-containing stack includes two first semiconductor channel material nanosheets 20 and two first sacrificial semiconductor material nanosheets 18.

[0056] Each first sacrificial semiconductor material nanosheet 18 is composed of a third semiconductor material, while each first semiconductor channel material nanosheet 20 is composed of a fourth semiconductor material that is compositionally different from the third semiconductor material. The third and fourth semiconductor materials include any of the semiconductor materials described above for first semiconductor material layer 10. In some embodiments, first semiconductor channel material nanosheet 20 is composed of a fourth semiconductor material that can provide high channel mobility for NFET devices. In other embodiments, first semiconductor channel material nanosheet 20 is composed of a fourth semiconductor material that can provide high channel mobility for PFET devices.

[0057] Each first sacrificial semiconductor material nanosheet 18 has a first width, and each first semiconductor channel material nanosheet 20 has a second width greater than the first width. In one example, the first width is 10 nm to 100 nm, and the second width is 20 nm to 130 nm. Each first sacrificial semiconductor material nanosheet 18 and each first semiconductor channel material nanosheet 20 have the same length. In one example, the length of each first sacrificial semiconductor material nanosheet 18 and each first semiconductor channel material nanosheet 20 is 10 nm to 130 nm. The vertical height of each first sacrificial semiconductor material nanosheet 18 and each first semiconductor channel material nanosheet 20 is within the range of 4 nm to 20 nm. The vertical height of each first sacrificial semiconductor material nanosheet 18 can be equal to, greater than, or less than the vertical height of each first semiconductor channel material nanosheet 20.

[0058] The first sacrificial gate structure 22 includes at least a sacrificial gate material. In some embodiments, the first sacrificial gate structure 22 may include a sacrificial gate dielectric material. The sacrificial gate dielectric material may be composed of a dielectric material such as, for example, silicon dioxide. The sacrificial gate material may include, but is not limited to, polysilicon, amorphous silicon, amorphous silicon germanium, tungsten, titanium, tantalum, aluminum, nickel, ruthenium, palladium, platinum, or alloys of these metals.

[0059] The first gate spacers 24 are composed of a gate spacer dielectric material. Examples of gate spacer dielectric materials that can be used in providing the first gate spacers 24 include, but are not limited to, SiN, SiBCN, SiOCN, or SiOC. The bottom dielectric insulating layer 16 is composed of one of the gate spacer dielectric materials described above for the first gate spacers 24.

[0060] The bottom dielectric insulating layer 16 and the first gate spacer 24 are formed simultaneously and are therefore composed of the same compositional gate spacer dielectric material. The bottom dielectric insulating layer 16 may have a thickness of 5 nm to 50 nm, although other thicknesses are contemplated and may be employed for the bottom dielectric insulating layer 16.

[0061] The first inner spacer 26 is composed of one of the gate spacer dielectric materials described above for the first gate spacer 24. The gate spacer dielectric material that provides the first inner spacer 26 can be compositionally the same as or compositionally different from the gate spacer dielectric material that provides the first gate spacer 24.

[0062] The first source / drain regions 28 are composed of a semiconductor material and a first dopant. As used herein, a "source / drain" or "S / D" region can be either a source region or a drain region depending on subsequent wiring and application of voltage during operation of a field effect transistor (FET). As is well known, a source / drain region is located on each side of a gate structure. The semiconductor material providing the first source / drain regions 28 can include one of the semiconductor materials described above for the first semiconductor material layer 10 of the semiconductor substrate. The semiconductor material providing the first source / drain regions 28 can be compositionally the same as or different from each first semiconductor channel material nanosheet 20. The first dopant present in the first source / drain regions 28 can be either a p-type dopant or an n-type dopant. The term "p-type" refers to the addition of an impurity to an intrinsic semiconductor that creates a deficiency of valence electrons. In silicon-containing semiconductor materials, examples of p-type dopants, or impurities, include, but are not limited to, boron, aluminum, gallium, and indium. "N-type" refers to the addition of an impurity that contributes free electrons to an intrinsic semiconductor. In silicon-containing semiconductor materials, examples of n-type dopants, or impurities, include, but are not limited to, antimony, arsenic, and phosphorus. In one example, first source / drain region 28 has a 4×10 20 atoms / cm 3 ~3×10 21 atoms / cm 3 As shown, the first source / drain regions 28 contact the bottom dielectric insulating layer 16 (see, eg, Figures 2A-2B).

[0063] The first front-side ILD material layer 30 can be composed of a dielectric material including, for example, silicon oxide, silicon nitride, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. As used throughout this application, the term "low-k" refers to a dielectric material having a dielectric constant less than 4.0. All dielectric constants referred to herein are measured relative to a vacuum unless otherwise specified.

[0064] The exemplary structure shown in Figures 2A-2B can be formed using conventional nanosheet stack formation processes well known to those skilled in the art. In one example, the exemplary structure shown in Figures 2A-2B can be formed by first forming a sacrificial placeholder material layer (not shown) on the surface of the second semiconductor material layer 14. The sacrificial placeholder material layer can include a semiconductor material that is compositionally different from the second semiconductor material that provides the second semiconductor material layer 14, the third semiconductor material that provides each of the first sacrificial semiconductor material nanosheets 18, and the fourth semiconductor material that provides each of the first semiconductor channel material nanosheets 20. Formation of the placeholder material layer can include an epitaxial growth process or any other deposition process, such as, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or evaporation. After forming the placeholder material layer, a material stack of alternating layers of third and fourth semiconductor materials is formed by epitaxial growth or using any of the deposition processes described above for forming the placeholder material layer, and then lithography and etching can be used to pattern the material stack and the placeholder material layer into a multilayer material structure that includes remaining portions of the placeholder material layer and remaining portions of the material stack.

[0065] The terms "epitaxial growth" or "epitaxially growing" refer to the growth of a second semiconductor material on the growth surface of a first semiconductor material, where the grown second semiconductor material has the same crystalline properties as the first semiconductor material. In an epitaxial deposition process, chemical reactants provided by source gases are controlled, and system parameters are set so that the depositing atoms arrive at the growth surface of the first semiconductor material with sufficient energy to move around on the growth surface and orient themselves into the crystalline arrangement of the atoms on the growth surface. Examples of various epitaxial growth process equipment that can be utilized in this application include, for example, rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). Epitaxial deposition temperatures typically range from 550°C to 900°C. Higher temperatures usually result in faster deposition, but faster deposition can result in crystalline defects and film cracking.

[0066] A first sacrificial gate structure 22 is then formed on this multi-layer material stack by depositing a sacrificial gate dielectric material (if present) and a blanket layer of sacrificial gate material. Deposition of the sacrificial gate material and, if present, the blanket layer of sacrificial gate dielectric material may include, but is not limited to, CVD, PECVD, PVD, ALD, or any combination of such deposition processes. After forming these blanket layers, a patterning process (including lithography and etching) is used to convert the sacrificial gate dielectric material (if present) and the blanket layer of sacrificial gate dielectric material into the sacrificial gate structure 22. The etching may include dry etching and / or wet chemical etching. The dry etching may include reactive ion etching (RIE), plasma etching, or ion beam etching (IBE). During this etching, the second semiconductor material layer 14 may be etched, and shallow trench isolation regions 15 may be formed using techniques known to those skilled in the art. Next, the placeholder material layer present in the multi-layer material stack is removed using an etching process that selectively removes the placeholder material layer. A space (or gap) is formed between the bottom sacrificial semiconductor material layer of the multi-layer material stack and the second semiconductor material layer 14. This structure is not free-floating but is supported by the first sacrificial gate structure 22. Next, the first gate spacer 24 and the bottom dielectric insulating layer 16 are simultaneously formed. Specifically, the first gate spacer 24 and the bottom dielectric insulating layer 16 are formed by depositing a gate spacer dielectric material and subsequently etching the spacer. The deposition fills the gap, forming the bottom dielectric insulating layer 16. In an embodiment, the first gate spacer 24 can be I-shaped and have a top surface that is coplanar with the top surface of the first sacrificial gate structure 22.

[0067] After forming the first gate spacers 24 and the bottom dielectric insulating layer 16, the multilayer material stack, including alternating layers of third and fourth semiconductor materials, is etched, with the first sacrificial gate structure 22 and the first gate spacers 24 acting as an etch mask. The etching stops on the bottom dielectric insulating layer 16. In this application, the unetched (i.e., remaining) portions of each layer of the third semiconductor material are referred to as first sacrificial semiconductor material nanosheets 18, and the unetched (i.e., remaining) portions of each layer of the fourth semiconductor material are referred to as first semiconductor channel material nanosheets 20. Next, first interior spacers 26 are formed. The first interior spacers 26 are formed by first recessing each sacrificial semiconductor material nanosheet 18 to form interior spacer gaps adjacent the ends of each first sacrificial semiconductor material nanosheet 18. After this recessing step, the remaining (i.e., recessed) first sacrificial semiconductor material nanosheets 18 have a reduced lateral width compared to the width of the original sacrificial semiconductor material nanosheets. The recessing includes a lateral etching process that is selective in removing the sacrificial semiconductor material nanosheet relative to the first semiconductor channel material nanosheet 20. First interior spacers 26 are then formed in the interior spacer gaps by conformal deposition of a spacer dielectric material, followed by isotropic etching. First source / drain regions 28 are then formed by epitaxial growth, as defined above, followed by deposition of a first front-side ILD material layer 30 over the source / drain regions, followed by a planarization process.

[0068] 3A-3B, the exemplary semiconductor structure shown in FIGS. 2A-2B, respectively, is illustrated after forming a plurality of first front-side contact placeholder structures 32. The first front-side contact placeholder structures 32 are formed laterally adjacent to each first source / drain region 28, with each first front-side contact placeholder structure 32 extending through the first ILD material layer 30, the shallow trench isolation region 15, and into a portion of the second semiconductor material layer 14. In this manner, each first front-side contact placeholder structure 32 contacts a sub-surface of the second semiconductor material layer 14. The term "sub-surface" is used throughout this application to refer to a surface of a material located between the top surface of the material and the bottom surface of the material.

[0069] The first front side contact placeholder structure 32 is composed of any suitable placeholder dielectric material such as, for example, SiC, SiCO, and combinations thereof. The placeholder dielectric material that provides the front side contact placeholder structure 32 can be designed to exert stress on nearby structures.

[0070] Each first front-side contact placeholder structure 32 can be formed by first forming an opening in the exemplary structure through the first ILD material layer 30 and the shallow trench isolation region 15, physically exposing a sub-surface of the second semiconductor material layer 14. The opening can be formed by lithography and etching (e.g., RIE, etc.). After forming the opening, a deposition process is utilized to fill the opening with a placeholder dielectric material and / or metal. For example, a planarization process, such as chemical mechanical polishing (CMP), can follow the deposition of the placeholder dielectric material and / or metal. Each first front-side contact placeholder structure 32 has a top surface that is coplanar with the top surface of the first ILD material layer 30. The number of first front-side contact placeholder structures 32 is not limited to four, as shown in FIGS. 3A-3B .

[0071] 4A-4B, cross-sectional views of the exemplary semiconductor structure shown in FIGS. 3A-3B, respectively, are shown after forming a stacked FET device isolation layer 34 and forming a material stack 36L / 38L of alternating second sacrificial semiconductor material layers 36L and second semiconductor channel material layers 38L on the stacked FET device isolation layer 34. The stacked FET device isolation layer 34 includes a layer of dielectric material such as, for example, silicon dioxide, tetraethylorthosilicate (TEOS), fluorinated tetraethylorthosilicate (FTEOS), and combinations thereof. The stacked FET device isolation layer 34 is typically deposited on the exemplary structure shown in FIGS. 3A-3B.

[0072] The material stacks 36L / 38L are formed by an epitaxial process as defined above, followed by lithographic patterning. Each second sacrificial semiconductor material layer 36L is composed of a fifth semiconductor material, and each second semiconductor channel material layer 38L is composed of a sixth semiconductor material, which is compositionally different from the fifth semiconductor material layer. The fifth semiconductor material is typically compositionally the same as the third semiconductor material used in providing each first sacrificial semiconductor material nanosheet 18, while the sixth semiconductor material can be compositionally the same as or different from the fourth semiconductor material used in providing each first semiconductor channel material nanosheet 20. In one example, each first semiconductor channel material nanosheet 20 is composed of a fourth semiconductor material suitable for use in an NFET, while each second semiconductor channel material layer 38L is composed of a sixth semiconductor material suitable for use in a PFET device. The material stack 36L / 38L may include "m" second semiconductor channel material layers 38L and "m or m+1" second sacrificial semiconductor material layers 36L, with "m+1" embodiments not shown, where m is an integer starting from 1. In the illustrated embodiment, each material stack 36L / 38L includes "m" second sacrificial semiconductor material layers 36L and "m" second semiconductor channel material layers 38L. As an example, each material stack 36L / 38L includes two second semiconductor channel material layers 38L and two second sacrificial semiconductor material layers 36L.

[0073] 5A-5B, there are illustrated cross-sectional views of the exemplary semiconductor structure shown in FIGS. 4A-4B, respectively, after forming a plurality of second sacrificial gate structures 40 spanning different portions of the material stack 36L / 38L, patterning the material stack 36L / 38L using at least the second sacrificial gate structures 40 as a pattern mask to provide a plurality of second nanosheet-containing stacks of alternating second sacrificial semiconductor material nanosheets 36 and second semiconductor channel material nanosheets 38, forming second source / drain regions 46 extending outward from each second semiconductor channel material nanosheet 38, and forming a second front-side ILD material layer 48. In the present application, a second gate spacer 42 is formed after forming the second sacrificial gate structure 40, and the second sacrificial gate structure 40 and the second gate spacer 42 are employed as a combined etch mask. In this embodiment, after forming the second nanosheet-containing laminate, second internal spacers 44 are formed on the end walls of each second sacrificial semiconductor material nanosheet 36L.

[0074] The second sacrificial gate structure 40 comprises the materials described above for the first sacrificial gate structure 22. The second gate spacers 42 and the second inner dielectric spacers 44 comprise the materials described above for the first gate spacers 24 and the first inner spacers 26, respectively. The second source / drain regions 46 comprise a semiconductor material and a second dopant. The semiconductor material providing the second source / drain regions 46 can be compositionally the same as or different from the semiconductor material providing the first source / drain regions 28. The second dopant can be the same conductivity type as the first dopant described above in providing the first source / drain regions 28, or a different conductivity type. The second ILD material layer 40 comprises one of the dielectric materials described above for the first ILD material layer 30.

[0075] The nanosheet processing described above in forming the exemplary structure shown in Figures 2A-2B can be adapted and used here in providing the exemplary structure shown in Figures 5A-5B. In this embodiment, the remaining (unetched) portions of each second sacrificial semiconductor material layer 36L form second sacrificial semiconductor material nanosheets 36 of the second nanosheet-containing laminate, and the remaining (unetched) portions of each second semiconductor channel material layer 38L form second semiconductor channel material nanosheets 38 of the second nanosheet-containing laminate. The length, width, and height of the second sacrificial semiconductor material nanosheets 36 and the second semiconductor channel material nanosheets 38 are within the ranges described above for the first sacrificial semiconductor material nanosheets 18 and the first semiconductor channel material nanosheets 20, respectively.

[0076] As shown in FIG. 5A, each second nanosheet-containing laminate 36 / 38 is positioned vertically above and aligned with the first nanosheet-containing laminate 18 / 20. As shown in FIG. 5B, the second source / drain region 46 is offset above the first source / drain region 28. It should be noted that in the present application, there may be some overlap between the first source / drain region 28 and the second source / drain region 46. However, the central (or center) portions of each of the first and second source / drain regions 28 and 46 are offset. This overlap helps reduce the cell height.

[0077] 6A-6B, there are shown cross-sectional views of the exemplary semiconductor structure shown in FIGS. 5A-5B, respectively, after removing each second sacrificial gate structure 40 and each first sacrificial gate structure 22, removing each second sacrificial semiconductor material nanosheet 38 and each first sacrificial semiconductor material nanosheet 20 to leave each second semiconductor channel material nanosheet 36 and each first semiconductor channel material nanosheet 18 suspended, and forming functional gate structures including a first functional gate structure portion 50B wrapped around the suspended first semiconductor channel material nanosheet 36 and a second functional gate structure portion 50A wrapped around the suspended second semiconductor channel material nanosheet 20. As shown, now, a first FET device region D1 and a second FET device region D2 have each been formed to include a functional gate structure wrapped around the semiconductor channel material nanosheets present in the respective FET device regions.

[0078] The removal of each second sacrificial gate structure 40 and each first sacrificial gate structure 22 involves an etching process that selectively removes the material providing the second sacrificial gate structure 40 and the first sacrificial gate structure 22, respectively. Typically, a single etch is used, but multiple etches can be used if different materials are used in providing the second sacrificial gate structure 40 and the first sacrificial gate structure 22.

[0079] The removal of each of the second sacrificial semiconductor material nanosheet 36 and the first sacrificial semiconductor material nanosheet 18 may include an etching process that selectively removes the second sacrificial semiconductor material nanosheet 36 and the first sacrificial semiconductor material nanosheet 18 relative to the second semiconductor channel material nanosheet 38 and the first semiconductor material nanosheet 20. Typically, a single etch is used, but multiple etches can be used if different materials are used in providing the second sacrificial semiconductor material nanosheet 36 and the first sacrificial semiconductor material nanosheet 18.

[0080] A functional gate structure including a first functional gate structure portion 50B and a second functional gate structure portion 50A includes at least a gate dielectric material layer and a gate electrode, which are not separately illustrated in the drawings of the present application. It should be noted that the first functional gate structure portion 50B is typically compositionally identical to the second functional gate structure portion 50A of the functional gate structure. As is well known, the gate dielectric material layer of the functional gate structure directly contacts the physically exposed portion of each semiconductor channel material nanosheet, and the gate electrode is located on the gate dielectric material layer. In some embodiments, the gate structure includes a work function metal (WFM) layer (not shown) located between the gate dielectric material layer and the gate electrode. In other embodiments, the WFM layer is used only as the gate electrode.

[0081] The gate dielectric material layer of the functional gate structure is comprised of a gate dielectric material such as silicon oxide, or a dielectric material having a dielectric constant greater than 4.0 (such dielectric materials can be referred to as high-k gate dielectric materials). Illustrative examples of high-k gate dielectric materials include, for example, hafnium dioxide (HfO), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiO), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium dioxide (ZrO), zirconium silicon oxide (ZrSiO), zirconium silicon oxynitride (ZrSiO). x N y ), tantalum oxide (TaO x High-k gate dielectric materials may further include dopants such as lanthanum (La), aluminum (Al), and / or magnesium (Mg).

[0082] The gate electrode material of the functional gate structure may be, but is not limited to, tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), zirconium (Zr), cobalt (Co), copper (Cu), aluminum (Al), lead (Pb), platinum (Pt), tin (Sn), silver (Ag), or gold (Au), tantalum nitride (TaN), titanium nitride (TiN), tantalum carbide (TaC), or the like. X ), titanium carbide (TiC), titanium aluminum carbide, tungsten silicide (WSi2), tungsten nitride (WN), ruthenium oxide (RuO2), cobalt silicide, or nickel silicide.

[0083] In some embodiments, the WFM layer can be employed as a conductive metal-containing material that provides the gate electrode, or as a separate layer located between the gate electrode and the preceding layer of gate dielectric material. The WFM layer can be used to set the threshold voltage of the FET to a desired value. In some embodiments, the WFM layer can be selected to produce an n-type threshold voltage shift. "N-type threshold voltage shift," as used herein, refers to a shift in the effective work function of a work function metal-containing material toward the conduction band of silicon in a silicon-containing material. In one embodiment, the work function of the n-type work function metal is in the range of 4.1 eV to 4.3 eV. Examples of such materials that can produce an n-type threshold voltage shift include, but are not limited to, titanium aluminum, titanium aluminum carbide, tantalum nitride, titanium nitride, hafnium nitride, hafnium silicon, or combinations thereof. In other embodiments, the WFM layer can be selected to produce a p-type threshold voltage shift. In one embodiment, the work function of the p-type work function metal is in the range of 4.9 eV to 5.2 eV. As used herein, "threshold voltage" refers to the lowest achievable gate voltage that turns on a semiconductor device, e.g., a transistor, by making the device's channel conductive. The term "p-type threshold voltage shift" refers to a shift in the effective work function of a metal-containing material toward the valence band of silicon in a silicon-containing material. Examples of such materials that can exert a p-type threshold voltage shift effect include, but are not limited to, titanium nitride, tantalum carbide, hafnium carbide, and combinations thereof.

[0084] A functional gate structure including a first functional gate structure portion 50B and a second functional gate structure portion 50A is formed by depositing a gate dielectric material layer, an optional WFM layer and a gate electrode layer, or a gate dielectric material layer and a WFM layer, followed by a planarization process. The deposition of the gate dielectric material layer may include CVD, PECVD, or ALD, while the deposition of the WFM layer and / or the gate electrode layer may include CVD, PECVD, PVD, ALD, or sputtering. Block mask techniques may be used when the materials providing the first functional gate structure portion 50B and the second functional gate structure portion 50A of the functional gate structure are different. Note that the FET present in the first FET device region may be of the same conductivity type as the FET present in the second FET device region, or a different conductivity type.

[0085] 7A-7B, which are cross-sectional views of the exemplary semiconductor structure shown in FIGS. 6A-6B, respectively, after forming a plurality of second front-side contact placeholder structures 52, where the plurality of second front-side contact placeholder structures 52 are shown offset relative to the plurality of first front-side contact placeholder structures 32, with each first front-side contact placeholder structure 32 located below one of the second source / drain regions 46 and each second front-side contact placeholder structure 52 located above one of the first source / drain regions 28. Each second front-side contact placeholder structure 52 includes a placeholder dielectric material (a dielectric material that can be designed to impart stress to adjacent structures) as described above. Each second front-side contact placeholder structure 52 is formed by forming openings through the second ILD material layer by lithography and etching. The openings are located between the second source / drain regions 46, as shown in FIG. 7B. 7B , the number of second front-side contact placeholder structures 52 formed is not limited to three. The etching stops on the top surface of the stacked FET device isolation layer 34. Any placeholder dielectric material for the first front-side contact placeholder structures 32 described above is then deposited, after which a planarization process is used to remove any placeholder material formed outside the openings and on top of the second ILD material layer 48. The second front-side contact placeholder structures 52 have a top surface that is coplanar with the top surface of the second ILD material layer 48. The number of second front-side contact placeholder structures 52 formed is not limited to three, as shown in FIG.

[0086] 8A-8B, cross-sectional views of the exemplary semiconductor structure shown in FIGS. 7A-7B, respectively, are illustrated after forming a middle-of-the-line (MOL) dielectric material layer 54 having contact openings 58 that physically expose the first set of second front-side contact placeholder structures 52. The MOL dielectric material layer 54 may be composed of one of the dielectric materials described above for the first ILD material layer 30. The MOL dielectric material layer 54 may be formed by a deposition process such as, for example, CVD, PECVD, or spin-on coating. Forming the contact openings 58 includes depositing a masking material layer 56, such as an organic planarization film (OPL), on the MOL dielectric material layer 54. Deposition of the masking material layer 56 includes, but is not limited to, CVD, PECVD, or spin-on coating. The deposited masking material layer 56 is then patterned by lithography and etching to have pre-contact openings. The pre-contact openings are then transferred into the MOL dielectric material layer 54 using a transfer etch. In some embodiments, the pre-contact opening and the contact opening 58 are formed using the same etch.

[0087] 9A-9B, cross-sectional views of the exemplary semiconductor structure shown in FIGS. 8A-8B, respectively, are illustrated after etching to remove the first set of physically exposed second front-side contact placeholder structures 52 and continuing to physically expose the first set of first source / drain regions 28 located beneath the removed first set of second front-side contact placeholder structures 52. This provides the extended contact openings 58E shown in FIG. 9B. The etch used to remove the first set of physically exposed second front-side contact placeholder structures 52 is selective in removing the placeholder material providing the second front-side contact placeholder structures 52. The subsequent etch includes another etch that removes the second ILD material layer 48, the stacked FET device isolation layer 34, and the first ILD material layer 30, but stops on the surfaces of the underlying first source / drain regions 28. This subsequent etch can be different from the etch used to remove the first set of physically exposed second front-side contact placeholder structures 52. After formation of the structure shown in Figures 9A-9B, masking material layer 56 can be removed from over MOL dielectric material layer 54 utilizing a material removal process that is selective in removing the masking material that provides masking material layer 56.

[0088] 10A-10B, cross-sectional views of the exemplary semiconductor structure shown in FIGS. 9A-9B, respectively, are illustrated after forming source / drain contact openings 60 that physically expose the first set of second source / drain regions 46. As shown in FIG. 10B, at least one of the second source / drain contact openings 60 may merge with one of the extended contact openings 58E. The source / drain contact openings 60 may be formed by lithography and etching.

[0089] 11A-11B, cross-sectional views of the exemplary semiconductor structure shown in Figures 10A-10B, respectively, are illustrated after forming front-side source / drain-containing structures 61, 62, 63 in various contact openings 60, as well as the extended opening 58E provided by etching in Figures 8A-8B. In the present application, a front-side source / drain contact structure in contact with only one of the first source / drain regions 28 may be referred to as a first source / drain region front-side contact structure 61, a front-side source / drain contact structure in contact with only one of the second source / drain regions 46 may be referred to as a second source / drain region front-side contact structure 62, and a front-side source / drain contact structure in contact with both the first source / drain region 28 and the second source / drain region 46 may be referred to as a shared source / drain contact structure 63.

[0090] The front-side source / drain-containing structures 61, 62, 63 may be formed using any known metallization process. The front-side source / drain-containing structures 61, 62, 63 include at least a contact conductor material, such as W, Cu, Al, Co, Ru, Mo, Os, Ir, Rh, or alloys thereof. In embodiments, each front-side source / drain-containing structure 61, 62, 63 may also include a silicide liner, such as TiSi, NiSi, NiPtSi, or a deposited metal liner, such as TiN. The contact conductor material may be formed by any suitable deposition method, such as ALD, CVD, PVD, or plating. In some embodiments (not shown), a metal semiconductor alloy region may be formed in each of the contact opening 62 and the extension opening 58 before forming the contact conductor material. The metal semiconductor alloy region may be composed of a silicide or a germicide. In one or more embodiments of the present application, the metal semiconductor alloy region may be formed by first depositing a metal layer (not shown) in the trench. The metal layer can include metals such as Ni, Co, Pt, W, Ti, Ta, rare earth metals (e.g., Er, Yt, La), alloys thereof, or any combination thereof. The metal layer can be deposited by ALD, CVD, PVD, or ALD. The thickness of the metal layer can be 2 nm to 10 nm, although smaller or larger thicknesses can also be employed. Next, a diffusion barrier (not shown), such as TiN or TaN, can be formed on the metal layer. Subsequently, an annealing process can be performed at high temperature to induce reaction of the semiconductor material in the source / drain regions to provide metal-semiconductor alloy regions. Thereafter, the unreacted portions of the metal layer and, if present, the diffusion barrier, are removed, for example, by an etching process (or multiple etching processes). In one embodiment, the etching process can be a wet etch that removes the metal of the metal layer selective to the metal-semiconductor alloy in the metal-semiconductor alloy regions.

[0091] Each front-side source / drain-containing structure 61, 62, 63 may have one or more source / drain contact liners (not shown). In one or more embodiments, the contact liners (not shown) may include a diffusion barrier material. Exemplary diffusion barrier materials include, but are not limited to, Ti, Ta, Ni, Co, Pt, W, Ru, TiN, TaN, WN, WC, alloys thereof, or stacks thereof, such as Ti / TiN and Ti / WC. The contact liners may be formed using a conformal deposition process, including CVD or ALD. The formed contact liners may have a thickness in the range of 1 nm to 5 nm, although smaller and larger thicknesses may also be employed.

[0092] In any of the above-described embodiments, a block mask technique can be employed to vary the compositional makeup of the front-side source / drain containing structures 61, 62, 63.

[0093] 12A-12B, cross-sectional views of the exemplary semiconductor structure shown in FIGS. 11A-11B, respectively, are illustrated after forming a back-end (BEOL) dielectric material layer 64 and an M1 signal line 66L. Some of the signal lines 66L include metal vias that connect to one of the front-side source / drain-containing structures 61, 62, and 63. In particular, metal via 66B is used to connect one of the signal lines 66L to the first source / drain region front-side contact structure 61, metal via 66C is used to connect one of the signal lines 66L to the second source / drain region front-side contact structure 62, and metal via 66D is used to connect one of the signal lines 66L to the shared source / drain contact structure. Also, metal via 66A is used to connect one of the signal lines 66L to the second portion 50A of the functional gate structure, as shown in FIG. 12A.

[0094] The BEOL dielectric material layer 64 may comprise any interconnect dielectric material, similar to the dielectric materials described above in providing the first ILD material layer 30. The BEOL dielectric material layer 64 may be formed by a deposition process, including, for example, CVD, PECVD, ALD, or spin-on coating. The signal line 66L, including the metal vias 66A, 66B, 66C, and 66D, may be formed using any known metallization process. The signal line 66L, including the metal vias 66A, 66B, 66C, and 66D, is composed of a conductive material, such as Cu, Co, W, or Ru, and has a thin metal deposition liner.

[0095] 13A-13B, there are illustrated cross-sectional views of the exemplary semiconductor structure shown in FIGS. 12A-12B and a carrier wafer 70, respectively, after forming additional BEOL structures 68. The additional BEOL structures 68 include one or more interconnect dielectric material layers with one or more wiring / via regions embedded therein. The additional BEOL structures 68 can be formed using BEOL processing techniques well known to those skilled in the art. The carrier wafer 70 can include one of the semiconductor materials described above for the first semiconductor material layer 10. In the present application, the carrier wafer 70 is bonded to the additional BEOL structures 68. This includes processing of the front side of the wafer, i.e., the portions of the structures that are located above the semiconductor substrate.

[0096] 14A-14B, cross-sectional views of the exemplary semiconductor structure shown in FIGS. 13A-13B, respectively, are illustrated after the wafer has been flipped (180°) to allow for backside processing of the structure. The flipping of the structure can be performed manually or by utilizing mechanical means such as a robotic arm. Here, after flipping, the first layer of semiconductor material 10 is physically exposed.

[0097] 15A-15B, cross-sectional views of the exemplary semiconductor structure shown in Figures 14A-14B, respectively, are illustrated after removing first semiconductor material layer 10 of the semiconductor substrate to physically expose semiconductor substrate etch stop layer 12. Removal of first semiconductor material layer 10 can be performed utilizing a material removal process that selectively removes the semiconductor material that provides first semiconductor material layer 10.

[0098] 16A-16B, cross-sectional views of the exemplary semiconductor structure shown in FIGS. 15A-15B, respectively, are illustrated after removing the etch stop layer 12 and the second semiconductor material layer 14 of the semiconductor substrate. After these removal steps, the bottom dielectric insulating layer 16, the shallow trench isolation regions 15, and the first front-side contact placeholder structures 32 are physically exposed. Removal of the etch stop layer 12 comprises a material removal process that is selective to removing the etch stop layer 12. Removal of the second semiconductor material layer 14 comprises a material removal process that is selective to removing the second semiconductor material layer 14. In some embodiments, a single material removal process may be utilized to remove the first semiconductor material layer 10, the etch stop layer 12, and the second semiconductor material layer 14.

[0099] 17A-17B, there are shown cross-sectional views of the exemplary semiconductor structure shown in Figures 16A-16B, respectively, after forming a backside ILD material layer 72. Backside ILD material layer 72 includes one of the dielectric materials described above for first ILD material layer 30. Backside ILD material layer 72 may be formed utilizing a deposition process such as, for example, CVD, PECVD, PVD, or ALD.

[0100] 18A-18B, which are cross-sectional views of the exemplary semiconductor structure shown in FIGS. 17A-17B, respectively, after forming a patterned mask 74 on a backside ILD material layer 72, where the patterned mask 74 is shown having an opening 76 that physically exposes one of the first front-side contact placeholder structures 32. The patterned mask 74 may comprise any masking material, such as, for example, OPL. The patterned mask 74 may be formed by deposition of a masking material, followed by lithographic patterning.

[0101] 19A-19B, there are illustrated cross-sectional views of each of the exemplary semiconductor structures shown in FIGS. 18A-18B after etching through the structure utilizing a patterned mask 74 as an etch mask to physically expose one surface of the second source / drain region 46. The physically exposed second source / drain region 46 need not include any front-side source / drain-containing structures 61, 62, 63 in contact therewith. This etch includes one or more etching processes capable of removing the physically exposed first front-side contact placeholder structure 32 and the underlying stacked FET device isolation layer 34. A backside contact opening 76E is formed by this stage of the application. After forming the backside contact opening 76E, the patterned mask 74 can be removed utilizing any material removal process that selectively removes the masking material that provided the patterned mask 74.

[0102] 20A-20B, cross-sectional views of the exemplary semiconductor structure shown in FIGS. 19A-19B, respectively, are shown after forming a backside first source / drain contact opening 78 to physically expose one of the first source / drain regions 28. The backside first source / drain contact opening 78 physically exposes the first source / drain region 28 without any frontside source / drain-containing structures 61, 62, 63 in contact therewith. The backside first source / drain contact opening 78 may be formed by lithography and etching, which removes a portion of the backside ILD material layer 72 and the bottom dielectric insulating layer 16.

[0103] 21A-21B, illustrated are cross-sectional views of each of the exemplary semiconductor structures shown in FIGS. 20A-20B after forming backside source / drain contact structures 80, 81 in contact openings 78, similar to the openings (i.e., 76E) provided by the etching performed in FIGS. 19A-19B. The backside source / drain contact structure in contact with the first source / drain region 28 may be referred to as the first backside source / drain contact structure 80, while the backside source / drain contact structure in contact with the second source / drain region 46 may be referred to as the second backside source / drain contact structure 81. The backside source / drain contact structures 80, 81 may have materials such as those described above for the frontside source / drain-containing structures 61, 62, 63. The backside source / drain contact structures 80, 81 may be formed utilizing any well-known metallization process.

[0104] 22A-22B, there are illustrated cross-sectional views of the exemplary semiconductor structure shown in FIGS. 21A-21B, respectively, after forming backside power rails 82, 83 and backside power distribution network 84. Backside power rail 82 is a VDD power supply, while backside power rail 83 is a VSS power supply. This stage of the application begins with first forming additional backside ILD material on top of previously formed backside ILD material layer 72. Backside ILD material layer 72 and the additional backside ILD material are collectively referred to in the drawings as element 73. Next, a metallization process is utilized to form backside power rails 82, 83. The backside power rails 82, 83 include a conductive power rail material, including but not limited to tungsten (W), cobalt (Co), ruthenium (Ru), aluminum (Al), copper (Cu), platinum (Pt), rhodium (Rh), or palladium (Pd), and a thin metal adhesion layer, such as TiN, TaN, etc.

[0105] As shown, two of the backside power supply rails 83, which function as VSS power sources, are connected to the first frontside contact placeholder structure, while the other backside power supply rail 83, which functions as VSS power source, is connected to the second backside source / drain contact structure 81. Also as shown, two of the backside power supply rails 82, which function as VDD power sources, are embedded in the backside ILD material multi-layer structure 73, while the other backside power supply rail 82, which functions as VDD power source, is connected to the backside source / drain contact structure 80.

[0106] After forming the backside conductive structures 82, 83, a backside power distribution network 84 is formed. The backside power distribution network 84 includes elements / components configured to distribute power to the stacked FETs.

[0107] 22A and 22B (flipped 180° from what is shown) illustrate an exemplary semiconductor structure of the present application, including a first FET device region D1 that includes a plurality of first FETs, each first FET of the plurality of first FETs including a first source / drain region 28 located on either side of a functional gate structure (i.e., first portion 50B of the functional gate structure defined above). A second FET device region, D2, is stacked above the first FET device region, D1, and includes a plurality of second FETs, each second FET of the plurality of second FETs including a second source / drain region 46 located on either side of the functional gate structure (i.e., second portion 50B of the functional gate structure defined above). The structure further includes at least one first front-side contact placeholder structure 32 disposed adjacent to one of the first source / drain regions 28 of the at least one first FET and at least one second front-side contact placeholder structure 52 disposed adjacent to at least one of the second source / drain regions 46 of the one second FET. As described above, the first source / drain region 28 is offset relative to the second source / drain region 46, and the at least one first front-side contact placeholder structure 32 is offset relative to the at least one first front-side contact placeholder structure 32. In the present application, the at least one first front-side contact placeholder structure 32 is located below one of the second source / drain regions 46, and the at least one second front-side contact placeholder structure 52 is located above one of the first source / drain regions 28.

[0108] While the present application has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and detail may be made therein without departing from the spirit and scope of the present application. It is therefore intended that the present application not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.

Claims

1. a first field effect transistor (FET) device region including a plurality of first FETs, each first FET of the plurality of first FETs including a first source / drain region located on each side of a functional gate structure; a second FET device region stacked above the first FET device region and including a plurality of second FETs, each second FET of the plurality of second FETs including a second source / drain region located on each side of a functional gate structure; at least one first front-side contact placeholder structure located adjacent one of the first source / drain regions of at least one of the first FETs; and at least one second front-side contact placeholder structure located adjacent to at least one of the second source / drain regions of at least one of the second FETs; 1. A semiconductor structure comprising:

2. 10. The semiconductor structure of claim 1, wherein a center of each first source / drain region is offset relative to a center of each second source / drain region.

3. 3. The semiconductor structure of claim 2 wherein an edge of each first source / drain region overlaps an edge of each second source / drain region.

4. 4. The semiconductor structure of claim 2 or 3, wherein the at least one first front side contact placeholder structure is misaligned with respect to the second front side contact placeholder structure, the at least one first front side contact placeholder structure being located below one of the second source / drain regions of one of the second FETs and the at least one second front side contact placeholder structure being located above one of the first source / drain regions of one of the first FETs.

5. 5. The semiconductor structure of claim 1 further comprising a stacked FET device isolation layer separating said first FET device region from said second FET device region.

6. 6. The semiconductor structure of claim 1 further comprising a bottom dielectric insulating layer underlying each first source / drain region and present in said first FET device region.

7. 7. The semiconductor structure of claim 1, wherein said at least one first front-side contact placeholder structure contacts a VSS power source, said VSS power source being connected to a back-side power distribution network.

8. 8. The semiconductor structure of claim 1 further comprising a signal line located over said second FET device region, said signal line contacting a back-end-of-line (BEOL) structure.

9. 10. The semiconductor structure of claim 8 wherein a carrier wafer overlies said additional BEOL structure.

10. 10. The semiconductor structure of claim 1, wherein another of the second source / drain regions is wired to a VDD power source by a backside source / drain contact structure that extends from the second FET device region completely through the first FET device region.

11. 11. The semiconductor structure of claim 1, wherein another of said first source / drain regions is wired to a VSS power source by a backside source / drain contact structure extending to said first FET device region.

12. 12. The semiconductor structure of claim 1, wherein another of the first source / drain regions and another of the second source / drain regions are electrically connected by a shared source / drain contact structure.

13. 13. The semiconductor structure of any one of claims 1 to 12, wherein both said at least one first front side contact placeholder structure and said at least one second front side contact placeholder structure comprise a placeholder dielectric material.

14. 14. The semiconductor structure of any one of claims 1 to 13, wherein at least one of said first source / drain regions is wired to a signal line overlying said second FET device region by a first source / drain region front side contact structure and a metal via.

15. 15. The semiconductor structure of any one of claims 1 to 14, wherein at least one of said second source / drain regions is wired to a signal line overlying said second FET device region by a second source / drain region front side contact structure and a metal via.

16. 16. The semiconductor structure of claim 1, wherein each of said first source / drain regions is located on a surface of a bottom dielectric insulating layer and each of said second source / drain regions is located on a surface of a stacked FET device isolation layer disposed between said first FET device region and said second FET device region.

17. 17. The semiconductor structure of claim 1, wherein the at least one first contact placeholder structure extends through the shallow trench isolation region and the first interlayer dielectric material layer, the first interlayer dielectric material layer being laterally adjacent to and located above each first source / drain region, and the at least one second front-side contact placeholder structure extends through the second interlayer dielectric material layer, the second interlayer dielectric material layer being laterally adjacent to and located above each second source / drain region.

18. 18. The semiconductor structure of any one of claims 1 to 17, wherein said first FET and said second FET are FET-containing nanosheets, and said functional gate structure is wrapped around a nanosheet of semiconducting channel material present in each of said first FET device region and said second FET device region.

19. 19. The semiconductor structure of any one of claims 1 to 18, wherein said first FET is of a first conductivity type and said second FET is of a second conductivity type, said second conductivity type being different from said first conductivity type.

20. 20. The semiconductor structure of any one of claims 1 to 19, wherein said first FET is of a first conductivity type and said second FET is of a second conductivity type, said second conductivity type being the same conductivity type as said first conductivity type.

21. 21. A method of forming the semiconductor structure of any one of claims 1 to 20.

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