Quantum Information Processing System
The quantum information processing system employs superconducting electrodes with high current capabilities to address power dissipation and fabrication challenges, enabling efficient and low-error quantum gate operations.
Patent Information
- Application Number
- JP2025514444
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2022-09-09
- Filing Date
- 2023-09-08
- Publication Date
- 2025-09-17
AI Technical Summary
Existing quantum gate technologies in trapped-ion systems face challenges with high power dissipation and fabrication difficulties of superconducting materials, particularly in generating strong magnetic fields and gradients for low-error operations.
A quantum information processing system using superconducting electrodes with current-carrying pathways formed from materials like niobium or rare earth barium copper oxide (ReBCO) to trap charged particles, allowing high currents (≥1 A) at low frequencies (≤1 GHz) for reduced power consumption and improved gate operations.
The system reduces power consumption and enhances the efficiency of quantum logic gates by utilizing superconducting materials that support high currents without significant power dissipation, facilitating low-error quantum operations.
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Abstract
Description
[Technical Field]
[0001] The present invention relates to quantum information processing systems. [Background technology]
[0002] Low-error quantum gates in trapped-ion systems can be implemented using magnetic fields, as described, for example, in T. P. Harty et al., "High-fidelity preparation, gates, memory and readout of a trapped-ion quantum bit," https: / / arxiv.org / abs / 1403.1524 (2014), and R. Srinivas et al., "High-fidelity laser-free universal control of two trapped ion qubits," https: / / arxiv.org / pdf / 2102.12533.pdf (2021). [Prior art documents] [Patent documents]
[0003] [Patent Document 1] International Application Publication No. 2021 / 205145A1 [Non-patent literature]
[0004] [Non-Patent Document 1] TP Harty et al., “High-fidelity preparation, gates, memory and readout of a trapped-ion quantum bit,” https: / / arxiv.org / abs / 1403.1524 (2014) [Non-patent document 2] R. Srinivas et al., “High-fidelity laser-free universal control of two trapped ion qubits,” https: / / arxiv.org / pdf / 2102.12533.pdf (2021) [Non-patent document 3] Shannon X. Wang et al., “Superconducting microfabricated ion traps,” https: / / arxiv.org / pdf / 1010.6108.pdf (2010) [Non-patent document 4] PC Holz et al., “Electric field noise in a high-temperature superconducting surface ion trap,” https: / / arxiv.org / pdf / 2106.03945.pdf (2021) [Non-Patent Document 5] J. Chiaverini and JM Sage, “Insensitivity of the rate of ion motional heating to trap-electrode material over a large temperature range”, Physical Review A, volume 89, page 012317 (2014) [Non-patent document 6] SL Todaro et al., “State Readout of a Trapped Ion Qubit Using a Trap-Integrated Superconducting Photon Detector,” Physical Review Letters, volume 126, 010501 (2021) [Non-Patent Document 7] H. Haffner, C. Roos and R. Blatt, “Quantum computing with trapped ions,” https: / / arxiv.org / pdf / 0809.4368.pdf (2008) Summary of the Invention [Means for solving the problem]
[0005] According to a first aspect of the present invention, there is provided a quantum information processing system comprising: a charged particle trap comprising a substrate and a set of electrodes supported on the substrate; and a control system for controlling the charged particle trap, applying a bias to the set of electrodes to trap at least one charged particle, and implementing at least one quantum logic gate for the at least one charged particle, wherein the electrodes include at least one current-carrying electrode formed of a superconducting material, and the control system is configured to apply a current having a peak current of at least 1 A to the at least one current-carrying electrode.
[0006] This can be useful for reducing power consumption when trapping charged particles and performing quantum information processing on them, such as quantum logic gates.
[0007] The at least one current-carrying electrode may have a first end and a second end. The at least one current-carrying electrode is preferably elongated. The first end of the current-carrying wire may be connected to a bias source. The second end of the current-carrying wire may be connected to a bias source, ground, or a terminal load.
[0008] The control system may be configured to apply a current to the at least one current-carrying electrode having a frequency of 1 GHz or less.
[0009] The at least one current carrying electrode may have a thickness t of at least 0.3 μm.
[0010] The charged particles are calcium ions ( 40 Ca + or 43 Ca + The charged particle can be an atom or molecule with a net charge, or an elementary charged particle such as an electron or positron.
[0011] The thickness t may be at least 0.5 μm, or may be at least 1 μm.
[0012] The superconducting material may be rare earth barium copper oxide (ReBCO), niobium, or an alloy containing niobium. The at least one current-carrying electrode may have a width w (which is transverse to the current flow) between 5 μm and 500 μm.
[0013] The electrodes may include at least one electrode formed of a common metal.
[0014] There may be at least two current-carrying electrodes, for example, three current-carrying electrodes. The at least two current-carrying electrodes may have different widths. The control system may be configured to drive respective currents through each current-carrying electrode. The at least two currents may have different frequencies and / or different phases. The at least two currents may have different current values.
[0015] The charged particle trap can include a first layer of coplanar electrodes and a second layer of coplanar electrodes, the first layer of coplanar electrodes can be interposed between the substrate and the second layer of coplanar electrodes.
[0016] The first layer of the coplanar electrodes may include at least one current carrying electrode, and the second layer of the coplanar electrodes may include an electrode formed of a common metal.
[0017] The charged particle trap may further comprise a layer of dielectric material, such as silicon dioxide, interposed between the first layer of coplanar electrodes and the second layer of coplanar electrodes.
[0018] The electrode set has a shielding effect of S=20log 10The trap may include a set of surface electrodes having [B0' / B1']≦20 dB or <1 dB, where B0' is the magnetic field gradient at the charged particle when trapped by the charged particle trap without the set of surface electrodes and B1' is the magnetic field gradient at the charged particle when trapped by the charged particle trap with the set of surface electrodes.
[0019] According to a second aspect of the present invention, there is provided a method of operating a quantum information processing system, the method comprising the steps of trapping at least one charged particle in a trap, each charged particle providing a respective qubit, providing an initial qubit state, and applying one or more sequences of gates to the qubit, wherein applying the one or more sequences of gates to the qubit includes driving a current through the or each current-carrying electrode of at least one current-carrying electrode, the or each respective current having a frequency of less than or equal to 1 GHz and a peak current of at least 1 A.
[0020] The method may further comprise reading the qubit state.
[0021] Some embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which: [Brief explanation of the drawings]
[0022] [Figure 1] FIG. 1 is a schematic diagram of a quantum information processing system including a first surface electrode trap and a control system. [Figure 2] 2 is a schematic cross-sectional view of the first surface electrode trap shown in FIG. 1 taken along line AA'. [Figure 3] FIG. 10 is a schematic cross-sectional view of a second surface electrode trap. [Figure 4] FIG. 10 is a schematic cross-sectional view of a third surface electrode trap. [Figure 5] 2 is a process flow diagram of a method of operating the quantum information processing system shown in FIG. 1. [Figure 6] FIG. 1 shows the current carrying electrodes and control system in more detail. DETAILED DESCRIPTION OF THE INVENTION
[0023] introduction T.P. Harty, supra, and R. Srinivas, supra, utilize configurations in which ions are trapped on the major surface of a chip that supports conductive wiring, and high currents (>1 A) are passed through the wiring to generate strong near-field magnetic fields and magnetic field gradients. These configurations have been used to implement ultra-low error one-qubit and two-qubit gates, but power dissipation remains a challenge.
[0024] Superconducting materials can be used in ion traps, but only in the electrodes that generate the electric field. Shannon X. Wang et al., "Superconducting microfabricated ion traps," https: / / arxiv.org / pdf / 1010.6108.pdf (2010), P.C. Holz et al., "Electric field noise in a high-temperature superconducting surface ion trap," https: / / arxiv.org / pdf / 2106.03945.pdf (2021), and J. Chiaverini and J.M. Sage, "Insensitivity of the rate of ion motional heating to trap-electrode material over a large temperature range," Physical Review A, volume 89, page 012317 (2014), describe superconducting ion traps.
[0025] Superconducting materials have also been used in single-photon detectors fabricated together with surface-electrode ion traps. SL Todaro et al., "State Readout of a Trapped Ion Qubit Using a Trap-Integrated Superconducting Photon Detector," Physical Review Letters, volume 126, 010501 (2021), describe a trap-integrated photon detector using superconducting nanowire single-photon detectors. The trap electrodes are made of electroplated gold on an underlying silicon substrate.
[0026] Some superconductors have a DC critical current density that can allow high currents (>1 A) to flow through them while remaining superconducting, but this ability decreases with increasing frequency. Moreover, while superconductors that exhibit high critical current densities exist, they tend to be difficult to deposit and pattern, especially in thick layers (>300 nm), which can lead to a mismatch between the fabrication requirements for trapping layers and high critical current superconductors.
[0027] Quantum Information Processing System 1 1, there is shown a quantum information processing system 1 including a first surface electrode trap 2. The surface electrode trap 2 comprises a substrate 3, e.g., comprising silicon dioxide, having a top surface 4 (or "major surface") supporting an arrangement of electrodes 5, 6, 7 that can be used to trap and control one or more charged particles 8 that provide respective qubits.
[0028] The charged particles 8 are calcium ions (e.g., 40 Ca + or 43 Ca + ), however, they may also take the form of atoms or molecules with a net electric charge, or elementary charged particles such as electrons or positrons.
[0029] The surface electrode trap 2 is housed in a cryogenic freezer (not shown) for cooling the surface electrode trap 2 to a suitable low temperature T (e.g., less than 77 K or 4.2 K). The surface electrode trap 2 may be housed in a vacuum chamber (not shown), which provides an ultra-high vacuum environment that allows individual charged particles to be isolated. The system 1 also includes a control system 10 for applying DC and AC biases to the electrodes 5, 6, 7, including the central electrode 5 through which a current can be passed to generate a magnetic field gradient. The current-carrying electrodes are preferably elongated (i.e., longer than they are wide) and have first and second ends. The current-carrying electrodes may be referred to as "conductive pathways," "conductive wiring," or simply "wires." If the current-carrying electrodes are formed of a superconducting material, they may also be referred to as "superconducting pathways," "superconducting wiring," or simply "superconducting wires." The first end may have or provide a first terminal (not shown) that is connected to a bias source (not shown), such as a current or voltage source in the control system 10, and the second end may have or provide a second terminal (not shown) that is connected to a bias source, ground, or a terminal load, allowing current to flow from the source through the wire. Examples of quantum information processing systems and surface electrode traps can be found in International Application Publication No. WO 2021 / 205145 A1, which is incorporated herein by reference.
[0030] Still referring to FIG. 2, the center electrode 5, and optionally some or all of the other electrodes 6, 7, are formed of a suitable superconducting material, such as niobium or rare earth barium copper oxide (ReBCO), and have a critical current density j c The electrode 5 has a thickness t and width w sufficient to accommodate a DC or low-frequency AC current (0≦f≦1 GHz) having a peak magnitude of at least 1 A without exceeding 1 Ω. For example, ReBCO can be YBCO. The center electrode 5, and optionally the other electrodes 6, 7, have a thickness t of at least 0.3 μm, preferably at least 0.5 μm, and more preferably at least 1 μm. The center electrode 5, and optionally the RF electrode 6, have a width w, transverse to the longitudinal axis 9, between 5 μm and 500 μm, preferably between 10 μm and 100 μm.
[0031] One or more layers of material, such as a metal, may be included under or over the layer of superconducting material to provide a better surface for wirebonding, promote adhesion, provide a diffusion barrier, and / or provide a protective barrier layer. Examples of metals include gold, aluminum, and chromium. For example, a layer of gold (e.g., 200 nm thick) may be over the layer of superconducting material to aid in wirebond adhesion. A bilayer of aluminum and chromium may be over the layer of niobium to provide a protective barrier against oxidation.
[0032] Other electrode configurations Referring to Figure 3, a second surface electrode trap 2' is shown.
[0033] The surface electrode trap 2' comprises a substrate 13, for example formed of magnesium oxide, having a top surface 14 supporting a central superconducting strip 15, for example formed of ReBCO, and side layers 16 of a dielectric material such as silicon dioxide.
[0034] The superconducting strips 15 and dielectric layer 16 are covered by a further layer 19 of dielectric material, such as silicon dioxide, having an upper surface 20. The upper surface 20 of the dielectric material supports an arrangement of electrodes 25, 26, 27, which have the same configuration as the electrodes of the previously described first surface electrode trap 2 (FIG. 1), but which are formed of a common metal such as gold, silver, or aluminum (in its normal state, above its critical temperature). The superconducting strips 15 pass under the center electrode 25 and an inner portion of the RF electrode 26. In other words, the superconducting strips 15 are wider than the center electrode 25.
[0035] Referring to FIG. 4, a third surface electrode trap 2'' is shown.
[0036] The third surface electrode trap 2'' is identical to the second surface electrode trap 2', except that the single wide superconducting strip 15 (Figure 3) is replaced by three narrower superconducting strips 15', 16 that are substantially adjacent (when viewed from above) to the center electrode 25 and the RF electrode 26.
[0037] Shielding of surface electrodes The surface electrode traps described above may include one or more antennas (not shown) disposed below the surface electrode, i.e., inserted between the substrate and the surface electrode. The antennas may take the form of electrically conductive paths (or "wires") carrying current that generate a magnetic field that can act on the trapped charged particles. To electrically insulate the antenna and the surface electrode, a dielectric layer, such as silicon dioxide having a thickness between 1 μm and 10 μm, may be deposited over the antenna, thereby inserting a dielectric layer between the antenna and the surface electrode.
[0038] The shielding effectiveness S in dB is S=20log 10 (B0' / B1') (1) where B0' is the magnetic field gradient for a charged particle without a shielding structure, and B1' is the magnetic field gradient for a charged particle with a shielding structure.
[0039] The shielding effect can be in three forms, namely: - "Low shielding": S<1dB (i.e. B1'>0.9B0') - "Medium shielding": 20dB≧S≧1dB (i.e., 0.1B0'≦B1'≦0.9B0') - "High Shielding": S>20dB (i.e., B1'<0.1B0') It can be divided into:
[0040] The surface electrodes are preferably positioned so as not to shield charged particles from the antenna, in other words to provide low shielding, although moderate shielding may also be acceptable.
[0041] Low shielding can be achieved by (a) choosing an appropriate material for the electrodes and an electrode thickness that is much smaller than the skin depth δ of the material (i.e., t<<δ), and (b) configuring the electrode layout to have, for example, slots and / or spacing.
[0042] The shielding effectiveness can be estimated by modeling the layer above the antenna as a solid ground plane of thickness t and conductivity σ. For example, for a 500 nm thick copper layer (t = 500 nm and σ = 5.96 × 10) at room temperature, 7 S / m) is considered a poor shielding layer at frequency f = 10 MHz because S < 1 dB. A 5 μm thick copper layer (t = 5 μm and σ = 5.96 × 10 7 S / m) is a high shielding layer at frequency f = 300 MHz, since S>20 dB.
[0043] The shielding effectiveness S is altered by the electrode geometry, especially the presence of slots and notches. However, the shielding effectiveness of a sheet without slots or notches can be used as an approximation.
[0044] operation Referring to FIG. 5, a method of operating a quantum information processing system will now be described.
[0045] One or more charged particles 8 are confined in the trap 2 (step S1) and an initial qubit state is prepared (step S2). A sequence of one or more gates, for example in the form of Pauli gates followed by Clifford gates, is applied to the qubit (step S3) and the final state is measured (step S4).
[0046] Examples of suitable operations can be found in T. P. Harty, supra, and R. Srinivas, supra, which are incorporated herein by reference. See also H. Haffner, C. Roos, and R. Blatt, "Quantum computing with trapped ions," https: / / arxiv.org / pdf / 0809.4368.pdf (2008), which is incorporated herein by reference.
[0047] During trapping, initialization and / or gating operations, a current I of at least 1 A is passed through one or more of the electrodes 5, 6.
[0048] 3 and 4, when implementing a quantum gate (step S3), a high current (>1 A) oscillating at a low frequency (<1 GHz) is applied to one or more of the three superconducting electrodes 15, 15′, 16. At the same time, a low current (<1 A) may be applied to one or more of the regular electrodes 25, 26 and / or one or more of the superconducting electrodes 15, 15′, 16.
[0049] Electrode that passes current 6, there is shown in more detail the current-carrying electrodes 5, 6 and the control system 10. Although the current-carrying electrodes 5, 6 are shown as being straight, this need not be the case and may, for example, include bent or curved portions.
[0050] As previously described, the current-carrying electrodes 5, 6 (which may be referred to as "wires" or "wiring") are formed from a superconducting material such as rare earth barium copper oxide and have a first end 8 and a second end 9.
[0051] First ends 8 of the wires 5, 6 are connected to a bias source 11, such as a current or voltage source, in a control system 10. Second ends 9 of the wires 5, 6 are connected to ground GND, a terminal load 12, or the bias source 11 to allow a current I to flow through the wires 5, 6. The connection is an ohmic connection.
[0052] The control system 10 is configured to drive current through the wires 5, 6 between the first and second ends 8, 9 of the wires such that the peak current during trapping, initialization, and / or gating operations is at least 1 A. The current in the current-carrying electrodes generates the magnetic fields used to implement the quantum gates.
[0053] The current I has a waveform 30 that is controlled over time by the control circuit 10 .
[0054] The configuration of the current carrying electrodes 5, 6 differs from the non-current carrying electrodes 7. For non-current carrying electrodes 7, such as DC electrodes used to generate an electric field, there is only one input / output connection and therefore the control system 10 does not drive a current through the electrode.
[0055] If the current-carrying electrodes 5, 6 are sufficiently short, the current is generally constant across the electrode. However, the voltage at one end of a current-carrying electrode may differ from the other (dV=IZ, where Z is the impedance of the electrode). This is in contrast to a non-current-carrying electrode 7, where the voltage is generally constant but the current may vary across the electrode.
[0056] An electrode can be considered sufficiently short if it can be accurately modeled by an RLC circuit (when the electrode length L is much smaller than the wavelength). If the current-carrying electrodes 5, 6 are long enough to be considered transmission lines (i.e., the electrode length L is equal to or greater than the wavelength), the current-carrying electrodes 5, 6 can be viewed as transmission lines. Thus, the transmission line has a first end and a second end (or "end point"), with the second end terminated with a very low load (in other words, essentially short-circuited). Thus, applying power to the first end (or "input") can generally produce voltage nodes and current antinodes in the ion trap. In contrast, in a long, narrow, non-current-carrying electrode, the end point is essentially open. Thus, applying power at the input generally produces voltage antinodes and current nodes in the ion trap.
[0057] Modification It will be understood that various modifications may be made to the previously described embodiments. Such modifications may involve equivalent and other features which are already known in the design, manufacture, and use of charged particle traps and their components, and which may be used instead of, or in addition to, features already described herein. Features of one embodiment may be replaced by, or supplemented by, features of another embodiment.
[0058] The traps described herein have one layer of electrodes or two layers of electrodes (in which case one of the layers of electrodes is buried). Traps with three or more layers (which include at least two buried layers of electrodes) may also be used.
[0059] Although claims in this application are formulated to particular combinations of features, the scope of the present disclosure should be understood to include any novel feature or any novel combination of features explicitly or implicitly disclosed herein, or any generalization thereof, regardless of whether it relates to the same invention as presently asserted in any claim and regardless of whether it alleviates any or all of the same technical problems as the present invention. Applicants hereby give notice that new claims may be formulated to such features and / or combinations of features during prosecution of this application or any further application derived therefrom. [Explanation of symbols]
[0060] 1. Quantum information processing system 2 surface electrode trap, first surface electrode trap 2' Second surface electrode trap 2'' Third Surface Electrode Trap 3. Circuit Board 4 Top side 5. Electrode, center electrode, current-carrying electrode 6 Electrodes, current-carrying electrodes, RF electrodes 7 electrode, electrode 8 first end, charged particle 9 Second End, Longitudinal Axis 10. Control System 11 Bias Source 12 Terminal Load 13 PCB 14 Top side 15 Superconducting strips, superconducting electrodes Superconducting strips narrower than 15', superconducting electrodes 16 Dielectric layer, side layer, narrower superconducting strips, superconducting electrodes 19 layers 20 Top side 25 electrodes, center electrode 26 electrodes, RF electrodes 27 electrodes 30 waveforms
Claims
1. a charged particle trap comprising a substrate and a set of electrodes supported on the substrate; a control system for controlling the charged particle trap, applying a bias to the set of electrodes to trap at least one charged particle, and implementing at least one quantum logic gate on the at least one charged particle; Equipped with 1. A quantum information processing system, wherein the electrodes include at least one current-carrying electrode formed of a superconducting material, and wherein the control system is configured to apply a current having a peak current of at least 1 A to the at least one current-carrying electrode.
2. 10. The quantum information processing system of claim 1, wherein the control system is configured to apply the current having a frequency of 1 GHz or less.
3. 3. The quantum information processing system of claim 1, wherein the at least one current-carrying electrode has a thickness t of at least 0.3 μm.
4. 4. The quantum information processing system according to claim 1, wherein the superconducting material is rare earth barium copper oxide (ReBCO).
5. 5. The quantum information processing system of claim 1, wherein the at least one current-carrying electrode has a width w between 5 μm and 500 μm.
6. 6. The quantum information processing system of claim 1, wherein the charged particle trap comprises a first layer of coplanar electrodes and a second layer of coplanar electrodes, the first layer of coplanar electrodes being interposed between the substrate and the second layer of coplanar electrodes.
7. 7. The quantum information processing system of claim 6, wherein the first layer of coplanar electrodes comprises the at least one current-carrying electrode.
8. 8. The quantum information processing system of claim 6 or 7, wherein the second layer of coplanar electrodes comprises electrodes formed of a common material.
9. 9. The quantum information processing system of claim 6, wherein the charged particle trap further comprises a layer of dielectric material interposed between the first layer of coplanar electrodes and the second layer of coplanar electrodes.
10. The set of electrodes has a shielding effect S=20log 10 10. The quantum information processing system of claim 1, comprising a set of surface electrodes having [B0' / B1']≦20 dB, where B0' is the magnetic field gradient at a charged particle when trapped by the charged particle trap in the absence of the set of surface electrodes and B1' is the magnetic field gradient at a charged particle when trapped by the charged particle trap in the presence of the set of surface electrodes.
11. 11. The quantum information processing system of claim 1, wherein a current-carrying electrode has a first end and a second end, the first end connected to a bias source and the second end connected to the bias source, ground, or a terminal load, and the control system is configured to cause the current having a peak current of at least 1 A to flow through the at least one current-carrying electrode wire during trapping, initialization, and / or gating operations.
12. A method of operating a quantum information processing system according to any one of claims 1 to 11, comprising the steps of: Trapping at least one charged particle in the trap, each charged particle providing a respective quantum bit; providing an initial qubit state; applying a sequence of one or more gates to the qubit; Equipped with 10. The method of claim 9, wherein applying the sequence of one or more gates to the qubit comprises driving a current through the or each of the at least one current-carrying electrodes, the or each current having a peak current of at least 1 A.
13. 13. The method of claim 12, wherein the or each current has a frequency of 1 GHz or less.
14. applying said sequence of one or more gates 14. The method of claim 12 or 13, comprising operating the qubit using low frequency radiation.
15. applying said sequence of one or more gates 15. The method of any one of claims 12 to 14, comprising implementing a ZZ gate.
16. applying said sequence of one or more gates 16. The method of any one of claims 12 to 15, comprising performing MS gating.
17. 17. The method of claim 12, further comprising reading out the qubit state.
Citation Information
Patent Citations
A method for manipulating charged particles
WO2021205145A1